Дисертації з теми "Reconfiguration Time"
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1
Thompson, Dean (Dean Barrie) 1974. "Dynamic reconfiguration under real-time constraints." Monash University, School of Computer Science and Software Engineering, 2002. http://arrow.monash.edu.au/hdl/1959.1/7991.
Повний текст джерела
2
Parrott, Curtis Alan. "Real-time reconfiguration of programmable logic controller communication paths." Diss., Rolla, Mo. : Missouri University of Science and Technology, 2009. http://scholarsmine.mst.edu/thesis/pdf/Parrott_09007dcc806c2c91.pdf.
Повний текст джерелаАнотація:
Thesis (M.S.)--Missouri University of Science and Technology, 2009.Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed November 17, 2009) Includes bibliographical references (p. 53).
3
Bowen, John Kipp. "Dynamic Module Library Generation for FPGA-based Run-Time Reconfigurable Systems." Thesis, Virginia Tech, 2008. http://hdl.handle.net/10919/31088.
Повний текст джерелаАнотація:
Modern Field Programmable Gate Arrays (FPGAs) can implement entire run-time reconfigurable systems using partial reconfiguration. Module-based run-time reconfiguration permits the construction of custom applications at run-time using pre-compiled Intellectual Property (IP) from a module library. The need for both flexible module placement and custom inter-module communication is mostly ignored by existing modular run-time reconfiguration approaches and few existing tool flows for module generation address the need for automation. This thesis introduces an automated compile-time tool flow for generating dynamic modules that allow flexible run-time placement and communication synthesis.Master of Science
4
Hansen, Sindre. "Self Reconfiguration of Clock Networks on FPGA : Methodology for partial reconfiguration of synchronous modules at run-time." Thesis, Norges teknisk-naturvitenskapelige universitet, Institutt for elektronikk og telekommunikasjon, 2011. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-13641.
Повний текст джерелаАнотація:
In this thesis, methodology for partial self-reconfiguration of synchronous modules has been developed. A simple software-based scheduler has been built for scheduling synchronous modules on the FPGA. The motivation behind this was that partial reconfiguration of synchronous modules at run-time had not been performed earlier in the AHEAD-project. Also, the project report written by the same author as this thesis has shown that a synchronous module can be replaced in a bitfile. However, the project report did not perform this reconfiguration at run-time.Based on the project report, the problem has been decomposed and simple tests using clocked flip-flop designs have been performed on the FPGA. These tests forms a proof-of-concept for partial self-reconfiguration of synchronous modules on the Virtex-4 FPGA. However, the tests also showed that the reconfiguration time was quite high. It took several seconds to write one partial bitstream to the configuration memory.Vegard Endresen has previously made a backend module for data transfer between the HWOS and a reconfigurable module. Experiments were performed in this thesis to see if the clocking methodology could be integrated into this backend module. The module could be built with the methodology, but a running solution on the FPGA was not shown.The software part of the HWOS was rewritten from scratch as the previous version was not thoroughly analyzed. A round-robin scheduler using priority queues has been implemented. A test-driven development technique has been used for development, hopefully making the system more robust. The scheduler is a part of a daemon running on the embedded system, where a message server handles requests for new processes and a placer places new tasks on the FPGA. The complete system was initially based on ideas and code developed by Sverre Hamre and Vegard Endresen in previous AHEAD-projects.
5
Guo, Guanghao. "Evaluation of FPGA Partial Reconfiguration : for real-time Vision applications." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-279957.
Повний текст джерелаАнотація:
The usage of programmable logic resources in Field Programmable Gate Arrays, also known as FPGAs, has increased a lot recently due to the complexity of the algorithms, especially for some computer vision algorithms. Due to this reason, sometimes the hardware resources in the FPGA are not sufficient. Partial reconfiguration provides us with the possibility to solve this problem. Partial reconfiguration is a technique that can be used to reconfigure specific parts of the FPGA during run-time. By using this technique, we can reduce the need for programmable logic resources. This master thesis project aims to design a software framework for partial reconfiguration that can load a set of processing components/algorithms (e.g. object detection, optical flow, Harris-Corner detection etc) in the FPGA area without affecting real-time static components such as camera capture, basic image filtering and colour conversion which are continuously running. Partial reconfiguration has been applied to two different video processing pipelines, a direct streaming architecture and a frame buffer streaming architecture respectively. The result shows that reconfiguration time is predictable which depends on the partial bitstream size, and that partial reconfiguration can be used in real-time applications taking the partial bitstream size and the frequency to switch the partial bitstreams into account.Användningen av programmerbara logiska resurser i Field Programmable Gate Arrayer, även känd som FPGA:er, har ökat mycket nyligen på grund av komplexiteten hos algoritmerna, speciellt för vissa datorvisningsalgoritmer. På grund av detta är det ibland inte tillräckligt med hårdvaruresurser i FPGA:n. Partiell omkonfiguration ger oss möjlighet att lösa detta problem. Partiell omkonfigurering är en teknik som kan användas för att omkonfigurera specifika delar av FPGA:n under körtid. Genom att använda denna teknik kan vi minska behovet av programmerbara logiska resurser. Det här mastersprojektet syftar till att utforma ett programvaru-ramverk för partiell omkonfiguration som kan ladda en uppsättning processkomponenter / algoritmer (t.ex. objektdetektering, optiskt flöde, Harris-Corner detection etc) i FPGA- området utan att påverka statiska realtids-komponenter såsom kamerafångst, grundläggande bildfiltrering och färgkonvertering som körs kontinuerligt. Partiell omkonfiguration har tillämpats på två olika videoprocessnings-pipelines, en direkt-strömmande respektive en rambuffert-strömmande arkitektur. Resultatet visar att omkonfigurationstiden är förutsägbar och att partiell omkonfiguration kan användas i realtids-tillämpningar.
6
Khan, Asif H. "Analysis of time varying load for minimum loss distribution reconfiguration." Diss., This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-06062008-171313/.
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7
Heron, Jean-Paul Stephen. "Design and implementation of reconfigurable DSP circuit architectures on FPGA." Thesis, Queen's University Belfast, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.266712.
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8
Puett, Ronnie Douglas. "Reconfiguration in robust distributed real-time systems based on global checkpoints." Thesis, Monterey, California. Naval Postgraduate School, 1991. http://hdl.handle.net/10945/26720.
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9
Mahmood, Waqar. "Intelligent modeling for control, reconfiguration and optimization of discrete event systems." Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/15014.
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10
Ballagh, Jonathan Bartlett. "An FPGA-based Run-time Reconfigurable 2-D Discrete Wavelet Transform Core." Thesis, Virginia Tech, 2001. http://hdl.handle.net/10919/33649.
Повний текст джерелаАнотація:
FPGAs provide an ideal template for run-time reconfigurable (RTR) designs. Only recently have RTR enabling design tools that bypass the traditional synthesis and bitstream
generation process for FPGAs become available. The JBits tool suite is an environment that provides support for RTR designs on Xilinx Virtex and 4K devices. This research
provides a comprehensive design process description of a two-dimensional discrete wavelet transform (DWT) core using the JBits run-time reconfigurable FPGA design tool
suite. Several aspects of the design process are discussed, including implementation, simulation, debugging, and hardware interfacing to a reconfigurable computing platform.
The DWT lends itself to a straightforward implementation in hardware, requiring relatively simple logic for control and address generation circuitry. Through the application
of RTR techniques to the DWT, this research attempts to exploit certain advantages that are unobtainable with static implementations. Performance results of the DWT core are
presented, including speed of operation, resource consumption, and reconfiguration overhead times.Master of Science
11
Courtney, T. E. G. "Exploring run-time reconfiguration on programmable logic for DSP and telecommunications applications." Thesis, Queen's University Belfast, 2003. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.273222.
Повний текст джерела
12
Celik, Guner Dincer. "Scheduling algorithms for throughput maximization in time-varying networks with reconfiguration delays." Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/78442.
Повний текст джерелаАнотація:
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 247-258).
We consider the control of possibly time-varying wireless networks under reconfiguration delays. Reconfiguration delay is the time it takes to switch network resources from one subset of nodes to another and it is a widespread phenomenon observed in many practical systems. Optimal control of networks has been studied to a great extent in the literature, however, the significant effects of reconfiguration delays received limited attention. Moreover, simultaneous presence of time-varying channels and reconfiguration delays has never been considered and we show that it impacts the system fundamentally. We first consider a Delay Tolerant Network model where data messages arriving randomly in time and space are collected by mobile collectors. In this setting reconfiguration delays correspond to travel times of collectors. We utilize a combination of wireless transmission and controlled mobility to improve the system delay scaling with load [rho] from [theta](1/(1-[rho])²) to [theta](1/1-[rho]), where the former is the delay for the corresponding system without wireless transmission. We propose control algorithms that stabilize the system whenever possible and have optimal delay scaling. Next, we consider a general queuing network model under reconfiguration delays and interference constraints which includes wireless, satellite and optical networks as special cases. We characterize the impacts of reconfiguration delays on system stability and delay, and propose scheduling algorithms that persist with service schedules for durations of time based on queue lengths to minimize negative impacts of reconfiguration delays. These algorithms provide throughput-optimality without requiring knowledge of arrival rates since they dynamically adapt inter-switching durations to stochastic arrivals. Finally, we present optimal scheduling under time-varying channels and reconfiguration delays, which is the main contribution of this thesis. We show that under the simultaneous presence of these two phenomenon network stability region shrinks, previously suggested policies are unstable, and new algorithmic approaches are necessary. We propose techniques based on state-action frequencies of Markov Decision Process theory to characterize the network stability region and propose throughput-optimal algorithms. The state-action frequency technique is applicable to a broad class of systems with or without reconfiguration delays, and provides a new framework for characterizing network stability region and developing throughput-optimal scheduling policies.
by Güner Dinc̦er C̦elik.
Ph.D.
13
Belaggoun, Amel. "Adaptability and reconfiguration of automotive embedded systems." Thesis, Paris 6, 2017. http://www.theses.fr/2017PA066252/document.
Повний текст джерелаАнотація:
Les véhicules modernes sont de plus en plus informatisés pour satisfaire les exigences de sureté les plus strictes et pour fournir de meilleures expériences de conduite. Par conséquent, le nombre d'unités de contrôle électronique (ECU) dans les véhicules modernes a augmenté de façon continue au cours des dernières années. En outre, les applications à calcul complexe offrent une demande de calcul plus élevée sur les ECU et ont des contraintes de temps-réel dures et souples, d'où le besoin d’une approche unifiée traitant les deux types de contraintes. Les architectures multi-cœur permettent d'intégrer plusieurs niveaux de criticité de sureté sur la même plate-forme. De telles applications ont été conçues à l'aide d'approches statiques; cependant, les approches dites statiques ne sont plus réalisables dans des environnements très dynamiques en raison de la complexité croissante et les contraintes de coûts strictes, d’où la nécessite des solutions plus souples. Cela signifie que, pour faire face aux environnements dynamiques, un système automobile doit être adaptatif; c'est-à-dire qu'il doit pouvoir adapter sa structure et / ou son comportement à l'exécution en réponse à des changements fréquents dans son environnement. Ces nouvelles exigences ne peuvent être confrontées aux approches actuelles des systèmes et logiciels automobiles. Ainsi, une nouvelle conception de l'architecture électrique / électronique (E / E) d'un véhicule doit être développé. Récemment, l'industrie automobile a convenu de changer la plate-forme AUTOSAR actuelle en "AUTOSAR Adaptive Platform". Cette plate-forme est développée par le consortium AUTOSAR en tant que couche supplémentaire de la plate-forme classique. Il s'agit d'une étude de faisabilité continue basée sur le système d'exploitation POSIX qui utilise une communication orientée service pour intégrer les applications dans le système à tout moment. L'idée principale de cette thèse est de développer de nouveaux concepts d'architecture basés sur l'adaptation pour répondre aux besoins d'une nouvelle architecture E / E pour les véhicules entièrement électriques (VEF) concernant la sureté, la fiabilité et la rentabilité, et les intégrer à AUTOSAR. Nous définissons l'architecture ASLA (Adaptive System Level in AUTOSAR), qui est un cadre qui fournit une solution adaptative pour AUTOSAR. ASLA intègre des fonctions de reconfiguration au niveau des tâches telles que l'addition, la suppression et la migration des tâches dans AUTOSAR. La principale différence entre ASLA et la plate-forme Adaptive AUTOSAR est que ASLA permet d'attribuer des fonctions à criticité mixtes sur le même ECU ainsi que des adaptations bornées temps-réel, tant dis que Adaptive AUTOSAR sépare les fonctions temps réel critiques (fonctionnant sur la plate-forme classique) des fonctions temps réel non critiques (fonctionnant sur la plate-forme adaptative). Pour évaluer la validité de notre architecture proposée, nous fournissons une implémentation prototype de notre architecture ASLA et nous évaluons sa performance à travers des expériencesModern vehicles have become increasingly computerized to satisfy the more strict safety requirements and to provide better driving experiences. Therefore, the number of electronic control units (ECUs) in modern vehicles has continuously increased in the last few decades. In addition, advanced applications put higher computational demand on ECUs and have both hard and soft timing constraints, hence a unified approach handling both constraints is required. Moreover, economic pressures and multi-core architectures are driving the integration of several levels of safety-criticality onto the same platform. Such applications have been traditionally designed using static approaches; however, static approaches are no longer feasible in highly dynamic environments due to increasing complexity and tight cost constraints, and more flexible solutions are required. This means that, to cope with dynamic environments, an automotive system must be adaptive; that is, it must be able to adapt its structure and/or behaviour at runtime in response to frequent changes in its environment. These new requirements cannot be faced by the current state-of-the-art approaches of automotive software systems. Instead, a new design of the overall Electric/Electronic (E/E) architecture of a vehicle needs to be developed. Recently, the automotive industry agreed upon changing the current AUTOSAR platform to the “AUTOSAR Adaptive Platform”. This platform is being developed by the AUTOSAR consortium as an additional product to the current AUTOSAR classic platform. This is an ongoing feasibility study based on the POSIX operating system and uses service-oriented communication to integrate applications into the system at any desired time. The main idea of this thesis is to develop novel architecture concepts based on adaptation to address the needs of a new E/E architecture for Fully Electric Vehicles (FEVs) regarding safety, reliability and cost-efficiency, and integrate these in AUTOSAR. We define the ASLA (Adaptive System Level in AUTOSAR) architecture, which is a framework that provides an adaptive solution for AUTOSAR. ASLA incorporates tasks-level reconfiguration features such as addition, deletion and migration of tasks in AUTOSAR. The main difference between ASLA and the Adaptive AUTOSAR platform is that ASLA enables the allocation of mixed critical functions on the same ECU as well as time-bound adaptations while adaptive AUTOSAR separates critical, hard real-time functions (running on the classic platform) from non-critical/soft-real-time functions (running on the adaptive platform). To assess the validity of our proposed architecture, we provide an early prototype implementation of ASLA and evaluate its performance through experiments
14
Liu, Ming. "Adaptive Computing based on FPGA Run-time Reconfigurability." Doctoral thesis, KTH, Elektroniksystem, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-33866.
Повний текст джерелаАнотація:
In the past two decades, FPGA has been witnessed from its restricted use as glue logic towards real System-on-Chip (SoC) platforms. Profiting from the great development on semiconductor and IC technologies, the programmability of FPGAs enables themselves wide adoption in all kinds of aspects of embedded designs. Modern FPGAs provide the additional capability of being dynamically and partially reconfigured during the system run-time. The run-time reconfigurability enhances FPGA designs from the sole spatial to both spatial and temporal parallelism, providing more design flexibility for advanced system features. Adaptive computing delegates an advanced computing paradigm in which computation tasks and resources are intelligently managed in correspondence with conditional requirements. In this thesis, we investigate adaptive designs on FPGA platforms: We present a comprehensive and practical design framework for adaptive computing based on the FPGA run-time reconfigurability. It concerns several design key issues in different hardware/software layers, specifically hardware architecture, run-time reconfiguration technical support, OS and device drivers, hardware process scheduler, context switching as well as Inter-Process Communications (IPC). Targeting a special application of data acquisition (DAQ) and trigger systems in nuclear and particle physics experiments, we set up the data streaming model and conduct theoretical analysis on the adaptive system. Three application studies are employed to verify the proposed adaptive design framework: The first application demonstrates a peripheral controller adaptable system aiming at general embedded designs. Through dynamically loading/unloading a NOR flash memory controller and an SRAM controller, both flash memory and SRAM accesses may be accomplished with less resource consumption than in traditional static designs. In the second case, two real algorithm processing engines are adaptively time-multiplexed in the same reconfigurable slot for particle recognition computation. Experimental results reveal the reduced on-chip resource requirements, as well as an approximate processing capability of the peer static design. Taking advantage of the FPGA dynamic reconfigurability, we present in the third application a novel on-FPGA interconnection microarchitecture named RouterLess NoC (RL-NoC). RL-NoC employs the novel design concept of Move Logic Not Data (MLND), and significantly distinguishes itself from the existing interconnection architectures such as buses, crossbars or NoCs. It does not rely on routers to deliver packets hop by hop as canonical NoCs do, but buffers data packets in virtual channels and brings various nodes using run-time reconfiguration to produce or consume them. In comparison with canonical packet-switching NoCs, the routerless architecture features lower design complexity, less resource consumption, higher work frequency, more efficient power dissipation as well as comparable or even higher packet delivery efficiency. It is regarded as a promising interconnection approach in some design scenarios on FPGAs, especially for light-weight applications.QC 20110531
15
Schneider, Etienne. "A middleware approach for dynamic real-time software : reconfiguration on distributed embedded systems." Université Louis Pasteur (Strasbourg) (1971-2008), 2004. https://publication-theses.unistra.fr/public/theses_doctorat/2004/SCHNEIDER_Etienne_2004.pdf.
Повний текст джерелаАнотація:
La reconfiguration dynamique d'un logiciel peut être un auxiliaire utile pour adapter et maintenir des systèmes informatiques. Dans la plupart des approches, le système doit être interrompu pour que la reconfiguration puisse être exécutée. Cette interruption ne peut convenir aux systèmes temps-réel : il est nécessaires que les contraintes temporelles soient respectées, même lorsque le système est en train d'être reconfiguré. Notre approche se base sur OSA+, un middleware temps-réel. Notre objectif principal est d'être capable de reconfigurer un (ou plusieurs) service lorsque le système est en fonction, avec un temps de non-réponse prévisible et prédéfini, c'est-à-dire un temps pendant lequel le système ne réagit pas à cause de la reconfiguration. Trois approches différentes concernant le blocage ou le non-blocage d'un service sont présentées. Ces approches peuvent être utilisées pour réaliser un compromis entre le temps de reconfiguration et le temps de non-réponseDynamic software reconfiguration is a useful tool to adapt and maintain software systems. In most approaches, the system has to be stopped while the reconfiguration is in progress. This is not suitable for real-time systems. Timing constraints must be met even while the system is reconfiguring. Our approach is based on the real-time middleware OSA+. Our main objective is to be able to reconfigure one (or more) service during the run-time, with a predictable and predefined blackout time (the time the systems does not react due to the reconfiguration). Three different approaches concerning the blocking or non-blocking state of a service are presented. These approaches can be used to realize a tradeoff between the reconfiguration time and the blackout time
16
Bittner, Ray Albert Jr. "Wormhole Run-Time Reconfiguration: Conceptualization and VLSI Design of a High Performance Computing System." Diss., Virginia Tech, 1997. http://hdl.handle.net/10919/30499.
Повний текст джерелаАнотація:
In the past, various approaches to the high performance numerical computing problem have been explored. Recently, researchers have begun to explore the possibilities of using Field Programmable Gate Arrays (FPGAs) to solve numerically intensive problems. FPGAs offer the possibility of customization to any given application, while not sacrificing applicability to a wide problem domain. Further, the implementation of data flow graphs directly in silicon makes FPGAs very attractive for these types of problems. Unfortunately, current FPGAs suffer from a number of inadequacies with respect to the task. They have lower transistor densities than ASIC solutions, and hence less potential computational power per unit area. Routing overhead generally makes an FPGA solution slower than an ASIC design.
Bit-oriented computational units make them unnecessarily inefficient for implementing tasks that are generally word-oriented. And finally, in large volumes, FPGAs tend to be more expensive per unit due to their lower transistor density. To combat these problems, researchers are now exploiting the unique advantage that FPGAs exhibit over ASICs: reconfigurability. By customizing the FPGA to the task at hand, as the application executes, it is hoped that the cost-performance product of an FPGA system can be shown to be a better solution than a system implemented by a collection of custom ASICs. Such a system is called a Configurable Computing Machine (CCM). Many aspects of the design of the FPGAs available today hinder the exploration of this field.
This thesis addresses many of these problems and presents the embodiment of those solutions in the Colt CCM. By offering word grain reconfiguration and the ability to partially reconfigure at computational element resolution, the Colt can offer higher effective utilization over traditional FPGAs. Further, the majority of the pins of the Colt can be used for both normal I/O and for chip reconfiguration. This provides higher reconfiguration bandwidth contrasted with the low percentage of pins used for reconfiguration of FPGAs. Finally, Colt uses a distributed reconfiguration mechanism called Wormhole Run-Time Reconfiguration (RTR) that allows multiple data ports to simultaneously program different sections of the chip independently. Used as the primary example of Wormhole RTR in the patent application, Colt is the first system to employ this computing paradigm.Ph. D.
17
Lehn, David Ilan. "Framework for a Context-Switching Run-Time Reconfigurable System." Thesis, Virginia Tech, 2002. http://hdl.handle.net/10919/32300.
Повний текст джерелаАнотація:
The reprogrammable nature of configurable computing machines has led to a wealth of research in run-time reconfigurable systems and applications. A limitation often encountered in this research is the slow configuration time with respect to the system clock speed. One technique to deal with these configuration delays has been to develop devices that can hold multiple rapidly interchangeable configurations. This technique is known as context-switching.
This thesis discusses the development of a framework to support applications which execute on a run-time reconfigurable system containing context-switching devices. The framework is divided into a number of layers: hardware, middleware, software, and applications. The design, implementation, and details of each layer are presented.
Master of Science
18
Templin, Joshua R. "Design of an Adaptable Run-Time Reconfigurable Software-Defined Radio Processing Architecture." DigitalCommons@USU, 2010. https://digitalcommons.usu.edu/etd/810.
Повний текст джерелаАнотація:
Processing power is a key technical challenge holding back the development of a high-performance software defined radio (SDR). Traditionally, SDR has utilized digital signal processors (DSPs), but increasingly complex algorithms, higher data rates, and multi-tasking needs have exceed the processing capabilities of modern DSPs. Reconfigurable computers, such as field-programmable gate arrays (FPGAs), are popular alternatives because of their performance gains over software for streaming data applications like SDR. However, FPGAs have not yet realized the ideal SDR because architectures have not fully utilized their partial reconfiguration (PR) capabilities to bring needed flexibility. A reconfigurable processor architecture is proposed that utilizes PR in reconfigurable computers to achieve a more sophisticated SDR. The proposed processor contains run-time swappable blocks whose parameters and interconnects are programmable. The architecture is analyzed for performance and flexibility and compared with available alternate technologies. For a sample QPSK algorithm, hardware performance gains of at least 44x are seen over modern desktop processors and DSPs while most of their flexibility and extensibility is maintained.
19
Zhu, Dan. "Electric Distribution Reliability Analysis Considering Time-varying Load, Weather Conditions and Reconfiguration with Distributed Generation." Diss., Virginia Tech, 2007. http://hdl.handle.net/10919/26557.
Повний текст джерелаАнотація:
This dissertation is a systematic study of electric power distribution system
reliability evaluation and improvement. Reliability evaluation of electric power systems
has traditionally been an integral part of planning and operation. Changes in the electric
utility coupled with aging electric apparatus create a need for more realistic techniques
for power system reliability modeling.
This work presents a reliability evaluation technique that combines set theory and
Graph Trace Analysis (GTA). Unlike the traditional Markov approach, this technique
provides a fast solution for large system reliability evaluation by managing computer
memory efficiently with iterators, assuming a single failure at a time. A reconfiguration
for restoration algorithm is also created to enhance the accuracy of the reliability
evaluation, considering multiple concurrent failures. As opposed to most restoration
simulation methods used in reliability analysis, which convert restoration problems into
mathematical models and only can solve radial systems, this new algorithm seeks the
reconfiguration solution from topology characteristics of the network itself. As a result
the new reconfiguration algorithm can handle systems with loops.
In analyzing system reliability, this research takes into account time-varying load
patterns, and seeks approaches that are financially justified. An exhaustive search scheme
is used to calculate optimal locations for Distributed Generators (DG) from the reliability
point of view. A Discrete Ascent Optimal Programming (DAOP) load shifting approach
is proposed to provide low cost, reliability improvement solutions.
As weather conditions have an important effect on distribution component failure
rates, the influence of different types of storms has been incorporated into this study.
Storm outage models are created based on ten yearsâ worth of weather and power outage
data. An observer is designed to predict the number of outages for an approaching or on
going storm. A circuit corridor model is applied to investigate the relationship between
power outages and lightning activity.Ph. D.
20
Iskander, Yousef Shafik. "Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug." Diss., Virginia Tech, 2012. http://hdl.handle.net/10919/28716.
Повний текст джерелаАнотація:
Design validation is the most time-consuming task in the FPGA design cycle. Although manufacturers and third-party vendors offer a range of tools that provide different perspectives of a design, many require that the design be fully re-implemented for even simple parameter modifications or do not allow the design to be run at full speed. Designs are typically first modeled using a high-level language then later rewritten in a hardware description language, first for simulation and then later modified for synthesis. IP and third-party cores may differ during these final two stages complicating development and validation. The developed approach provides two means of directly validating synthesized hardware designs. The first allows the original high-level model written in C or C++ to be directly coupled to the synthesized hardware, abstracting away the traditional gate-level view of designs. A high-level programmatic interface allows the synthesized design to be validated with the same arbitrary test data on the same framework as the hardware. The second approach provides an alternative view to FPGAs within the scope of a traditional software debugger. This debug framework leverages partially reconfigurable regions to accelerate the modification of dynamic, software-like breakpoints for low-level analysis and provides a automatable, scriptable, command-line interface directly to a running design on an FPGA.Ph. D.
21
Scalera, Kevin R. "A Comparison of Control Allocation Methods for the F-15 ACTIVE Research Aircraft Utilizing Real-Time Piloted Simulations." Thesis, Virginia Tech, 1999. http://hdl.handle.net/10919/34113.
Повний текст джерелаАнотація:
A comparison of two control allocation methods is performed utilizing the F-15 ACTIVE research vehicle. The control allocator currently implemented on the aircraft is replaced in the simulation with a control allocator that accounts for both control effector positions and rates. Validation of the performance of this Moment Rate Allocation scheme through real-time piloted simulations is desired for an aircraft with a high fidelity control law and a larger control effector suite.
A more computationally efficient search algorithm that alleviates the timing concerns associated with the early work in Direct Allocation is presented. This new search algorithm, deemed the Bisecting, Edge-Search Algorithm, utilizes concepts derived from pure geometry to efficiently determine the intersection of a line with a convex faceted surface.
Control restoring methods, designed to drive control effectors towards a ``desired" configuration with the control power that remains after the satisfaction of the desired moments, are discussed. Minimum-sideforce restoring is presented. In addition, the concept of variable step size restoring algorithms is introduced and shown to yield the best tradeoff between restoring convergence speed and control chatter reduction.
Representative maneuvers are flown to evaluate the control allocator's ability to perform during realistic tasks. An investigation is performed into the capability of the control allocators to reconfigure the control effectors in the event of an identified control failure. More specifically, once the control allocator has been forced to reconfigure the controls, an investigation is undertaken into possible performance degradation to determine whether or not the aircraft will still demonstrate acceptable flying qualities.
A direct comparison of the performance of each of the two control allocators in a reduced global position limits configuration is investigated. Due to the highly redundant control effector suite of the F-15 ACTIVE, the aircraft, utilizing Moment Rate Allocation, still exhibits satisfactory performance in this configuration. The ability of Moment Rate Allocation to utilize the full moment generating capabilities of a suite of controls is demonstrated.
NOTE: (02/2011) An updated copy of this ETD was added after there were patron reports of problems with the file.Master of Science
22
Rubattu, Claudio. "Response time analysis of parameterized dataflow applications on heterogeneous SW/HW systems." Thesis, Rennes, INSA, 2020. http://www.theses.fr/2020ISAR0005.
Повний текст джерелаАнотація:
Les fortes contraintes de réactivité et de consommation énergétique des systèmes embarqués et cyber-physiques nécessitent l’utilisation croissante de systèmes de calculs parallèles et fortement hétérogènes. La nature de ces systèmes parallèles implique une énorme complexité dans la compréhension et la prévision des performances en termes de temps de réponse. En effet, le temps de réponse dépend de nombreux facteurs associés aux caractéristiques à la fois de la fonctionnalité implémentée et de l’architecture cible. Les méthodes d’optimisation système actuelles dérivent le temps de réponse du système en examinant les opérations requises par chaque tâche, tant pour le traitement que pour l’accès aux ressources partagées. Cette procédure est souvent suivie par l’ajout ou l’élimination des interférences potentielles dues à la concurrence entre tâches. Cependant, de telles approches nécessitent une connaissance avancée des détails du logiciel et du matériel, rarement disponible en pratique lors du dimensionnement du système. Cette thèse propose une stratégie alternative "top-down" visant à étendre les cas dans lesquels le temps de réponse matériel et logiciel peut être analysé et prédit. La stratégie proposée s’appuie sur des représentations d’applications par des modèles flux de données et se concentre sur l’estimation du temps de réponse d’applications reconfigurables exécutées par des unités de calcul à la fois générales et spécialiséesIn contexts such as embedded and cyber-physical systems, the design of a desired functionality under constraints increasingly requires a parallel execution of different tasks on heterogeneous architectures. The nature of such parallel systems implies a huge complexity in understanding and predicting performance in terms of response time. Indeed, response time depends on many factors associated with the characteristics of both the functionality and the target architecture. State-of-the art strategies derive response time by examining the operations required by each task for both processing and accessing shared resources. This procedure is often followed by the addition or elimination of potential interferences due to task concurrency. However, such approaches require an advanced knowledge of the software and hardware details, rarely available in practice. This thesis provides an alternative "topdown" strategy aimed at extending the cases in which hardware and software response times can be analyzed and predicted. The proposed strategy leverages on dataflow-based application representations and focuses on the response time estimation of reconfigurable applications mapped on both general-purpose and specialized processing elements
23
Mégel, Thomas. "Placement, ordonnancement et mécanismes de migration de tâches temps-réel pour des architectures distribuées multicoeurs." Thesis, Toulouse, INPT, 2012. http://www.theses.fr/2012INPT0027/document.
Повний текст джерелаАнотація:
Les systèmes temps-réel embarqués critiques intègrent un nombre croissant de fonctionnalités comme le montrent les domaines de l'automobile ou de l'aéronautique. Ces systèmes doivent offrir un niveau maximal de sûreté de fonctionnement en disposant des mécanismes pour traiter les défaillances éventuelles et doivent être également performants, avec le respect de contraintes temps-réel strictes. Ces systèmes sont en outre contraints par leur nature embarquée : les ressources sont limitées, tels que par exemple leur espace mémoire et leur capacité de calcul. Dans cette thèse, nous traitons deux problématiques principales de ce type de systèmes. La première porte sur la manière d'apporter une meilleure tolérance aux fautes dans les systèmes temps-réel distribués subissant des défaillances matérielles multiples et permanentes. Ces systèmes sont souvent conçus avec une allocation statique des tâches. Une approche plus flexible effectuant des reconfigurations est utile si elle permet d'optimiser l'allocation à chaque défaillance rencontrée, pour les ressources restantes. Nous proposons une telle approche hors-ligne assurant un dimensionnement adapté pour prendre en compte les ressources nécessaires à l'exécution de ces actions. Ces reconfigurations peuvent demander une réallocation des tâches ou répliques si l'espace mémoire local est limité. Dans un contexte temps-réel strict, nous définissons notamment des mécanismes et des techniques de migration garantissant l'ordonnançabilité globale du système. La deuxième problématique se focalise sur l'optimisation de l'exécution des tâches au niveau local dans un contexte multicoeurs préemptif. Nous proposons une méthode d'ordonnancement optimal disposant d'une meilleure extensibilité que les approches existantes en minimisant les surcoûts : le nombre de changements de contexte préemptions et migrations locales) et la complexité de l'ordonnanceurCritical real-time embedded systems are integrating an increasing number of functionalities, as shown in automotive domain or aeronautics. These systems require high dependability including mechanisms to handle possible failures and have to be effective, meeting hard real-time constraints. These systems are also constrained by their embedded nature : resources are limited, such as their memory and their computing capacities. In this thesis, we focus on two main problems for this type of systems. The first one is about a way to bring a better fault-tolerance in distributed real-time systems when multiple and permanent hardware failures can occur. In classical systems, the design is limited to a static task assignment. A more flexible approach exploiting reconfigurations is useful if it allows to optimize assignment at each failure for the remaining resources. We propose an off-line approach to obtain an adapted sizing taking into account necessary resources to execute these actions. These reconfigurations may require to reallocate tasks or replicas if memory capacities are limited. In a hard real-time context, we define mechanisms and migration techniques to guarantee global schedulability of the system. The second problem focus on optimizing performance to run tasks at a local level in a multicore preemptive context. We propose an optimal scheduling method allowing a better scalability than existing approaches by minimizing overheads : the number of context switches (local preemptions and migrations) and the scheduler complexity
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Boukhanoufa, Mohamed-Lamine. "Adaptabilité et reconfiguration des systèmes temps-réel embarqués." Phd thesis, Université Paris Sud - Paris XI, 2012. http://tel.archives-ouvertes.fr/tel-00758807.
Повний текст джерелаАнотація:
Les systèmes temps réel peuvent être grands, distribués et avoir un environnement dynamique. Cela exige la mise en place de différents modes de fonctionnement et techniques de fiabilité. Par ailleurs, ces différents changements dynamiques d'architecture et de comportement ont un impact sur les caractéristiques temporelles des systèmes qui nécessitent une étude particulière de la capacité des comportements d'adaptation à garantir les contraintes fixées aux systèmes. Le travail présenté dans cette thèse est focalisé sur la spécification de l'adaptabilité d'un système temps réel et l'étude sur de jeux de configurations prédéfinis de l'impact temporel des actions d'adaptation dynamique. Pour cela, nous présentons une méthodologie outillée basée sur la notion de Mode du profil MARTE. Chaque mode représente un comportement possible du système pour un environnement bien déterminé associé à une configuration logicielle. L'approche développée propose de modéliser le comportement adaptatif à travers la définition du contexte, de la variabilité, des opérations de reconfigurations et de la configuration de base. L'analyse d'ordonnançabilité est ensuite effectuée au niveau du modèle en intégrant l'impact des comportements d'adaptation. Deux paradigmes de modélisation peuvent alors être exploités pour effectuer cette analyse : les requêtes et les flots de données. Cela permet de vérifier que les contraintes temporelles de notre système resteront satisfaites en intégrant les opérations de reconfiguration issues du comportement adaptatif. Enfin, l'approche permet de générer des implantations des comportements adaptatifs à partir des modèles afin d'automatiser l'intégration des mécanismes d'adaptation dans les systèmes temps réel.
25
Kidane, Hiliwi Leake. "Run-time scalable NoC for virtualized FPGA based accelerators as cloud services." Thesis, Bourgogne Franche-Comté, 2018. http://www.theses.fr/2018UBFCK032.
Повний текст джерелаАнотація:
Ces dernières années, les fournisseurs de cloud et les centres de données ont intégrés les FPGA dans leur environnement à des fins d'accélération. Cela est dû au fait que les accélérateurs à base de FPGA sont connus pour leur faible puissance et leurs bonnes performances par watt. En outre, l'introduction de la capacité de reconfiguration partielle dynamique (DPR) de certains FPGA incite les chercheurs de l'industrie et des universitaires à proposer des services de cloud FPGA virtualisés baser sur DPR. Dans la plupart des travaux existants, l'interconnexion entre les vFPGA repose soit sur les réseaux BUS ou OpenFlow. Cependant le bus et OpenFlow ne sont pas des solutions optimales pour la virtualisation.Dans cette thèse, nous avons proposé un NoC évolutif à l'exécution pour les accélérateurs basés sur FPGA virtualisés dans un cloud computing. Les composants NoC s'adapteront dynamiquement aux nombres d'accélérateurs virtualisés actifs en ajoutant et en supprimant des sous-noC. Pour minimiser la complexité de la conception de l'architecture NoC à un niveau inférieur (implémentation HDL), nous avons proposé un langage de modélisation unifié de haut niveau (UML) basé sur une ingénierie dirigée par les modèles. Une approche basée sur UML / MARTE et IP-XACT est utilisée pour définir les composants de la topologie NoC de haut niveau et générer les fichiers HDL requis. Les résultats des expériences montrent que le NoC évolutif à l'exécution peut réduire la consommation d'énergie de 17%. La caractérisation NoC sur la modélisation de haut niveau basée sur MDE réduit également le temps de conception de 25%In the last few years, cloud providers and data centers have been integrating FPGAs in their environment for acceleration purpose. This is due to the fact that FPGA based accelerator are known for their lower power and good performance per watt. Moreover, the introduction of the ability for dynamic partial reconfiguration (DPR) of some FPGAs trigger researchers in both industry and academics to propose DPR based virtualized FPGA (vFPGA) cloud services. In most of the existing works, the interconnection between the vFPGAs relies either on BUS or OpenFlow networks. However, both the bus and OpenFlow are not virtualization-aware and optimal solutions. In this thesis, we have proposed a virtualization-aware dynamically scalable NoC for virtualized FPGA accelerators in cloud computing. The NoC components will adapt to the number of active virtualized accelerator dynamically by adding and removing sub-NoCs. To minimize the complexity of NoC architecture design at a low level (HDL implementation), we have proposed a Model-Driven Engineering (MDE) based high-level unified modeling language (UML). A UML/MARTE and IP-XACT based approach are used to define the NoC Topology components at a high-level and generate the required HDL files. Experiment results show that the dynamically scalable NoC can reduce the power consumption by 17%. The MDE based high-level modeling based NoC characterization also reduce the design time by 25%
26
Hendry, James Hugh. "The Effects of Caching on Reconfigurable Adaptive Computing Systems." Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/9682.
Повний текст джерелаАнотація:
Adaptive computing systems have proven useful for implementing a wide range of algorithms. A limitation of current systems is the relatively small amount of reconfigurable hardware resources. Many algorithms require more hardware resources than are available. One solution to this problem is runtime reconfiguration (RTR). Using RTR techniques, a large algorithm is implemented as a collection of configurations for the reconfigurable hardware. These configurations are loaded onto the reconfigurable hardware as necessary to implement the algorithm. A primary limitation of RTR is that the reconfiguration process is slow. Therefore, methods of decreasing reconfiguration time are desirable.
Another method of implementing large algorithms on small hardware is to use multiple configurable computing platforms connected via a communication network. RTR techniques can be used in conjunction with this method to further increase hardware availability. In this case reconfiguration time is increased by the overhead of transmitting data across the communication network. Methods of decreasing network overhead are desirable.
This thesis discusses the use of caching techniques to decrease reconfiguration time. An architecture for caching configurations is implemented on a configurable computing system platform. The use of caching to decrease network overhead is discussed and exhibited. An example application is implemented and used to evaluate the effects of caching on reconfiguration time and algorithm performance.Master of Science
27
Puttegowda, Kiran. "Context Switching Strategies in a Run-Time Reconfigurable system." Thesis, Virginia Tech, 2002. http://hdl.handle.net/10919/32043.
Повний текст джерелаАнотація:
A distinctive feature of run-time reconfigurable systems is the ability to change the configuration of programmable resources during execution. This opens a number of possibilities such as virtualisation of computational resources, simplified routing and in certain applications lower power. Seamless run-time reconfiguration requires rapid configuration. Commodity programmable devices have relatively long configuration time, which makes them poor candidates for run-time reconfigurable systems. Reducing this reconfiguration time to the order of nano seconds will enable rapid run-time reconfiguration. Having multiple configuration planes and switching between them while processing data is one approach towards achieving rapid reconfiguration. An experimental context switching programmable device, called the Context Switching Reconfigurable Computer (CSRC), has been created by BAE Systems, which provided opportunities to explore context-switching strategies for run-time reconfigurable systems. The work presented here studies this approach for run-time reconfiguration, by applying the concepts to develop applications on a context switching reconfigurable system. The work also discusses the advantages and disadvantages of such an approach and ways of leveraging the concept for efficient computing.Master of Science
28
Wilson, Andrew Elbert. "Dynamic Reconfigurable Real-Time Video Processing Pipelines on SRAM-based FPGAs." BYU ScholarsArchive, 2020. https://scholarsarchive.byu.edu/etd/8620.
Повний текст джерелаАнотація:
For applications such as live video processing, there is a high demand for high performance and low latency solutions. The configurable logic in FPGAs allows for custom hardware to be tailored to a specific video application. These FPGA designs require technical expertise and lengthy implementation times by vendor tools for each unique solution. This thesis presents a dynamically configurable topology as an FPGA overlay to deploy custom hardware processing pipelines during run-time by utilizing dynamic partial reconfiguration. Within the FPGA overlay, a configurable topology with a routable switch allows video streams to be copied and mixed to create complex data paths. This work demonstrates a dynamic video processing pipeline with 11 reconfigurable regions and 16 unique processing cores, allowing for billions of custom run-time configurations.
29
Zhou, Ruoxing. "Dynamic Partial Reconfigurable FPGA." Thesis, Linköpings universitet, Datorteknik, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-74486.
Повний текст джерелаАнотація:
Partial Reconfigurable FPGA provides ability of reconfigure the FPGA duringrun-time. But the reconfigurable part is disabled while performing reconfiguration. In order to maintain the functionality of system, data stream should be hold for RP during that time. Due to this feature, the reconfiguration time becomes critical to designed system. Therefore this thesis aims to build a functional partial reconfigurable system and figure out how much time the reconfiguration takes. A XILINX ML605 evaluation board is used for implementing the system, which has one static part and two partial reconfigurable modules, ICMP and HTTP. A Web Client sends different packets to the system requesting different services. These packets’ type information are analyzed and the requests are held by a MicroBlaze core, which also triggers the system’s self-reconfiguration. The reconfiguration swaps the system between ICMP and HTTP modules to handle the requests. Therefore, the reconfiguration time is defined between detection of packet type and completion of reconfiguration. A counter is built in SP for measuring the reconfiguration time. Verification shows that this system works correctly. Analyze of test results indicates that reconfiguration takes 231ms and consumes 9274KB of storage, which saves 93% of time and 50% of storage compared with static FPGA configuration.
30
Kahne, Brian C. "A Genetic Algorithm-Based Place-and-Route Compiler For A Run-time Reconfigurable Computing System." Thesis, Virginia Tech, 1997. http://hdl.handle.net/10919/36521.
Повний текст джерелаАнотація:
Configurable Computing is a technology which attempts to increase computational power by customizing the computational platform to the specific problem at hand. An experimental computing model known as wormhole run-time reconfiguration allows for partial reconfiguration and is highly scalable. In this approach, configuration information and data are grouped together in a computing unit called a stream, which can tunnel through the chip creating a series of interconnected pipelines.
The Colt/Stallion project at Virginia Tech implements this computing model into integrated circuits. In order to create applications for this platform, a compiler is needed which can convert a human readable description of an algorithm into the sequences of configuration information understood by the chip itself. This thesis covers two compilers which perform this task. The first compiler, Tier1, requires a programmer to explicitly describe placement and routing inside of the chip. This could be considered equivalent to an assembler for a traditional microprocessor. The second compiler, Tier2, allows the user to express a problem as a dataflow graph. Actual placing and routing of this graph onto the physical hardware is taken care of through the use of a genetic algorithm.
A description of the two languages is presented, followed by example applications. In addition, experimental results are included which examine the behavior of the genetic algorithm and how alterations to various genetic operator probabilities affects performance.Master of Science
31
Naz, André. "Algorithmique distribuée pour grands ensembles de robots : centralité, synchronisation et auto-reconfiguration." Thesis, Bourgogne Franche-Comté, 2017. http://www.theses.fr/2017UBFCD027/document.
Повний текст джерелаАнотація:
Les récentes avancées technologiques en particulier dans le domaine de la miniaturisation de dispositifs robotiques laissent présager l'émergence de grands ensembles distribués de petits robots qui coopéreront en vue d'accomplir des tâches complexes (e.g., robotique modulaire, robots en essaims, microsystèmes électromécaniques distribués). Ces grands ensembles seront composés d'entités indépendantes, intelligentes et communicantes qui agiront comme un ensemble à part entière. Pour cela, elles s'auto-organiseront et collaboreront en vue d'accomplir des tâches complexes. Ces systèmes présenteront les avantages d'être plus polyvalents et plus robustes que les systèmes robotiques conventionnels tout en affichant un prix réduit. Ces ensembles formeront des systèmes distribués complexes dans lequel chaque entité sera un système embarqué à part entière avec ses propres capacités et ressources toute fois limitées. Coordonner de tels systèmes posent des défis majeurs et ouvrent de nouvelles opportunités dans l'algorithmique distribuée. Je défends la thèse qu'il faut d'ores et déjà identifier et implémenter des algorithmes distribués servant de primitives de base à la coordination de ces ensembles. Dans ce travail, nous nous focalisons sur une classe particulière de robots, à savoir les robots modulaires distribués formant de grands ensembles de modules fortement contraints en ressources (mémoire, calculs, etc.), placés dans une grille régulière et capables de communiquer entre voisins connexes uniquement. J'ai identifié et implémente trois primitives servant à la coordination de ces systèmes, à savoir l'élection d'un nœud central au réseau, la synchronisation temporelle ainsi que l'auto-reconfiguration. Dans ce manuscrit, je propose un ensemble d'algorithmes distribués réalisant ces primitives. J'ai évalué mes algorithmes en utilisant des expériences sur des modules matériels et en simulation sur des systèmes, composés de quelques dizaines à plus d'une dizaine de milliers de modules. Ces expériences montrent que nos algorithmes passent à l'échelle et sont adaptés aux grands ensembles distribués de systèmes embarqués avec des ressources fortement limités à la fois en mémoire et en calculTechnological advances especially in the miniaturization of robotic devices foreshadow the emergence of large-scale ensembles of small-size resource-constrained robots that distributively cooperate to achieve complex tasks (e.g., modular self-reconfigurable robots, swarm robotic systems, distributed microelectromechanical systems, etc.). These ensembles are formed from independent, intelligent and communicating units which act as a whole ensemble. These units cooperatively self-organize themselves to achieve common goals. These systems are tought to be more versatile and more robust than conventional robotic systems while having at the same time a lower cost.These ensembles form complex asynchronous distributed systems in which every unit is an embedded system with its own but limited capabilities. Coordination of such large-scale distributed embedded systems poses significant algorithmic issues and open for new opportunities in distributed algorithms. In my thesis, I defend the idea that distributed algorithmic primitives suitable for the coordination of these ensembles should be both identified and designed.In this work, we focus on a specific class of modular robotics systems, namely large-scale distributed modular robotic ensembles composed of resource-constrained modules that are organized in a lattice structure and which can only communicate with neighboring modules. We identified and implemented three building blocks, namely centrality-based leader election, time synchronization and self-reconfiguration.We propose a collection of distributed algorithms to realize these primitives. We evaluate them using both hardware experiments and simulations on systems ranging from a dozen of modules to more than a dozen of thousands of modules. We show that our algorithms scale well and are suitable for large-scale embedded distributed systems with scarce memory and computing resources
32
Fazzoletto, Emilio. "Characterization of Partial and Run-Time Reconfigurable FPGAs." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-202724.
Повний текст джерелаАнотація:
FPGA based systems have been heavily used to prototype and test Application Specic Integrated Circuit (ASIC) designs with much lower costs and development time compared to hardwired prototypes. In recentyears, thanks to both the latest technology nodes and a change in the architecture of reconfigurable integrated circuits (from traditional Complex Programmable Logic Device (CPLD) to full-CMOS FPGA), FPGAs have become more popular in embedded systems, both as main computation resources and as hardware accelerators. A new era is beginning for FPGA based systems: the partial run-time reconguration of a FPGA is a feature now available in products already on the market and hardware designers and software developers have to exploit this capability. Previous works show that, when designed properly, a system can improve both its power efficiency and its performance taking advantage of a partial run-time reconfigurable architecture. Unfortunately, taking advantage of run-time reconfigurable hardware is very challenging and there are several problems to face: the reconfiguration overhead is not negligible compared to nowadays CPUs performance,the reconfiguration time is not easily predictable, and the software has to be re-though to work with a time-evolving platform. This thesis project aims to investigate the performance of a modern run-time reconfigurable SoC (a Xilinx Zynq 7020), focusing on the reconfiguration overhead and its predictability, on the achievable speedup, and the trade-off and limits of this kind of platform. Since it is not always obvious when an application (especially a real-time one) is really able to use at its own advantage a partial run-time reconfigurable platform, the data collected during this project could be a valid help for hardware designers that use reconfigurable computing.FPGA-baserade system har tidigare främst använts för snabb och kostnadseffektiv konstruktion av prototyper vid framtagandet av applikationsspecika integrerade kretsar (ASIC). På senare år har användandet av FPGA:er i inbyggda system för implementation av hårdvaruacceleratorers såväl som huvudsaklig beräkningsenhet ökat. Denna ökning har möjliggjorts mycket tack vare den utveckling som har skett av rekonfigurerbara integrerade kretsar: från de mer traditionella Complex Programmable Logic Devices (CPLD) till helt CMOS-baserade FPGA:er. Nu inleds en ny era för FPGA-baserade system tack vare möjligheten att under körning rekonfigurera delar av FPGA:n genom så kallad partial run-time reconguration(RTR) - en teknik som redan idag finns tillgänglig i produkter på marknaden. Tidigare forskning visar att användandet av en RTR-baserad hårdvaruarkitektur kan ha en positiv effekt med avseende på prestanda såväl som strömförbrukning. Att använda RTR-baserad hårdvara innebär dock flera utmaningar: En ej försumbar rekonfigurationstid måste tas i beaktning, så även den icke-deterministiska exekveringstiden som en rekonfiguration kan innebära. Vidare måste anpassningar av mjukvaran göras för att fungera med en hårdvaruplattform som förändras över tid. Denna uppsats syftar till att undersöka prestandan hos ett modernt RTRbaserat SoC (Xilinx Zynq 7020) med fokus på rekonfigurationstider och dess förutsägbarhet, prestanda ökning, begränsningar samt nödvändiga kompromisser som denna arkitektur innebär. Huruvida en applikation kan dra nytta av en RTR-baserad arkitektur eller inte kan vara svårt att avgöra. Den insamlade datan som presenteras i denna rapport kan dock fungera som stöd för hårdvarukonstruktörer som önskar använda en RTR-baserad plattform.
33
Nilsson, Daniel, and Henrik Norin. "Adaptive QoS Management in Dynamically Reconfigurable Real-Time Databases." Thesis, Linköping University, Department of Computer and Information Science, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2800.
Повний текст джерелаАнотація:
During the last years the need for real-time database services has increased due to the growing number of data-intensive applications needing to enforce real-time constraints. The COMponent-based Embedded real-Time database (COMET) is a real-time database developed to meet these demands. COMET is developed using the AspeCtual COmponent-based Real-time system Development (ACCORD) design method, and consists of a number of components and aspects, which can be composed into a number of different configurations depending on system demands, e.g., Quality of Service (QoS) management can be used in unpredictable environments.
In embedded systems with requirementson high up-time it may not be possible to temporarily shut down the system for reconfiguration. Instead it is desirable to enable dynamic reconfiguration of the system, exchanging components during run-time. This in turn sets demands on the feedback control of the system to adjust to these new conditions, since a new time variant system has been created.
This thesis project implements improvements in COMET to create a more stable database suitable for further development. A mechanism for dynamic reconfiguration of COMET is implemented, thus, enabling components and aspects to be swapped during run-time. Adaptive feedback control algorithms are also implemented in order to better adjust to workload variations and database reconfiguration.
34
Gammoudi, Aymen. "Stratégie de placement et d'ordonnancement de taches logicielles pour architectures reconfigurables sous contrainte énergétique." Thesis, Rennes 1, 2018. http://www.theses.fr/2018REN1S030/document.
Повний текст джерелаАнотація:
La conception de systèmes temps-réel embarqués se développe de plus en plus avec l’intégration croissante de fonctionnalités critiques pour les applications de surveillance, notamment dans le domaine biomédical, environnemental, domotique, etc. Le développement de ces systèmes doit relever divers défis en termes de minimisation de la consommation énergétique. Gérer de tels dispositifs embarqués, entièrement autonomes, nécessite cependant de résoudre différents problèmes liés à la quantité d’énergie disponible dans la batterie, à l’ordonnancement temps-réel des tâches qui doivent être exécutées avant leurs échéances, aux scénarios de reconfiguration, particulièrement dans le cas d’ajout de tâches, et à la contrainte de communication pour pouvoir assurer l’échange des messages entre les processeurs, de façon à assurer une autonomie durable jusqu’à la prochaine recharge et ce, tout en maintenant un niveau de qualité de service acceptable du système de traitement. Pour traiter cette problématique, nous proposons dans ces travaux une stratégie de placement et d’ordonnancement de tâches permettant d’exécuter des applications temps-réel sur une architecture contenant des cœurs hétérogènes. Dans cette thèse, nous avons choisi d’aborder cette problématique de façon incrémentale pour traiter progressivement les problèmes liés aux contraintes temps-réel, énergétique et de communications. Tout d’abord, nous nous intéressons particulièrement à l’ordonnancement des tâches sur une architecture mono-cœur. Nous proposons une stratégie d’ordonnancement basée sur le regroupement des tâches dans des packs pour pouvoir calculer facilement les nouveaux paramètres des tâches afin de réobtenir la faisabilité du système. Puis, nous l’avons étendu pour traiter le cas de l’ordonnancement sur une architecture multi-cœurs homogènes. Finalement, une extension de ce dernier sera réalisée afin d’arriver à l’objectif principal qui est l’ordonnancement des tâches pour les architectures hétérogènes. L’idée est de prendre progressivement en compte des contraintes d’exécution de plus en plus complexes. Nous formalisons tous les problèmes en utilisant la formulation ILP afin de pouvoir produire des résultats optimaux. L’idée est de pouvoir situer nos solutions proposées par rapport aux solutions optimales produites par un solveur et par rapport aux autres algorithmes de l’état de l’art. Par ailleurs, la validation par simulation des stratégies proposées montre qu’elles engendrent un gain appréciable vis-à-vis des critères considérés importants dans les systèmes embarqués, notamment le coût de la communication entre cœurs et le taux de rejet des tâchesThe design of embedded real-time systems is developing more and more with the increasing integration of critical functionalities for monitoring applications, particularly in the biomedical, environmental, home automation, etc. The developement of these systems faces various challenges particularly in terms of minimizing energy consumption. Managing such autonomous embedded devices, requires solving various problems related to the amount of energy available in the battery and the real-time scheduling of tasks that must be executed before their deadlines, to the reconfiguration scenarios, especially in the case of adding tasks, and to the communication constraint to be able to ensure messages exchange between cores, so as to ensure a lasting autonomy until the next recharge, while maintaining an acceptable level of quality of services for the processing system. To address this problem, we propose in this work a new strategy of placement and scheduling of tasks to execute real-time applications on an architecture containing heterogeneous cores. In this thesis, we have chosen to tackle this problem in an incremental manner in order to deal progressively with problems related to real-time, energy and communication constraints. First of all, we are particularly interested in the scheduling of tasks for single-core architecture. We propose a new scheduling strategy based on grouping tasks in packs to calculate the new task parameters in order to re-obtain the system feasibility. Then we have extended it to address the scheduling tasks on an homogeneous multi-core architecture. Finally, an extension of the latter will be achieved in order to realize the main objective, which is the scheduling of tasks for the heterogeneous architectures. The idea is to gradually take into account the constraints that are more and more complex. We formalize the proposed strategy as an optimization problem by using integer linear programming (ILP) and we compare the proposed solutions with the optimal results provided by the CPLEX solver. Inaddition, the validation by simulation of the proposed strategies shows that they generate a respectable gain compared with the criteria considered important in embedded systems, in particular the cost of communication between cores and the rate of new tasks rejection
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Iturbe, Xabier. "Design and implementation of a reliable reconfigurable real-time operating system (R3TOS)." Thesis, University of Edinburgh, 2013. http://hdl.handle.net/1842/9413.
Повний текст джерелаАнотація:
Twenty-first century Field-Programmable Gate Arrays (FPGAs) are no longer used for implementing simple “glue logic” functions. They have become complex arrays of reconfigurable logic resources and memories as well as highly optimised functional blocks, capable of implementing large systems on a single chip. Moreover, Dynamic Partial Reconfiguration (DPR) capability permits to adjust some logic resources on the chip at runtime, whilst the rest are still performing active computations. During the last few years, DPR has become a hot research topic with the objective of building more reliable, efficient and powerful electronic systems. For instance, DPR can be used to mitigate spontaneously occurring bit upsets provoked by radiation, or to jiggle around the FPGA resources which progressively get damaged as the silicon ages. Moreover, DPR is the enabling technology for a new computing paradigm which combines computation in time and space. In Reconfigurable Computing (RC), a battery of computation-specific circuits (“hardware tasks”) are swapped in and out of the FPGA on demand to hold a continuous stream of input operands, computation and output results. Multitasking, adaptation and specialisation are key properties in RC, as multiple swappable tasks can run concurrently at different positions on chip, each with custom data-paths for efficient execution of specific computations. As a result, considerable computational throughput can be achieved even at low clock frequencies. However, DPR penetration in the commercial market is still testimonial, mainly due to the lack of suitable high-level design tools to exploit this technology. Indeed, currently, special skills are required to successfully develop a dynamically reconfigurable application. In light of the above, this thesis aims at bridging the gap between high-level application and low-level DPR technology. Its main objective is to develop Operating System (OS)-like support for high-level software-centric application developers in order to exploit the benefits brought about by DPR technology, without having to deal with the complex low-level hardware details. The developed solution in this thesis is named as R3TOS, which stands for Reliable Reconfigurable Real-Time Operating System. R3TOS defines a flexible infrastructure for reliably executing reconfigurable hardware-based applications under real-time constraints. In R3TOS, the hardware tasks are scheduled in order to meet their computation deadlines and allocated to non-damaged resources, keeping the system fault-free at all times. In addition, R3TOS envisages a computing framework whereby both hardware and software tasks coexist in a seamless manner, allowing the user to access the advanced computation capabilities of modern reconfigurable hardware from a software “look and feel” environment. This thesis covers all of the design and implementation aspects of R3TOS. The thesis proposes a novel EDF-based scheduling algorithm, two novel task allocation heuristics (EAC and EVC) and a novel task allocation strategy (called Snake), addressing many RC-related particularities as well as technological constraints imposed by current FPGA technology. Empirical results show that these approaches improve on the state of the art. Besides, the thesis describes a novel way to harness the internal reconfiguration mechanism of modern FPGAs to performinter-task communications and synchronisation regardless of the physical location of tasks on-chip. This paves the way for implementing more sophisticated RC solutions which were only possible in theory in the past. The thesis illustrates R3TOS through a proof-of-concept prototype with two demonstrator applications: (1) dependability oriented control of the power chain of a railway traction vehicle, and (2) datastreaming oriented Software Defined Radio (SDR).
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Xia, Tian. "Research on virtualisation technlogy for real-time reconfigurable systems." Thesis, Rennes, INSA, 2016. http://www.theses.fr/2016ISAR0009/document.
Повний текст джерелаАнотація:
Cette thèse porte sur l'élaboration d'un micro-noyau original de type hyperviseur, appelé Ker-ONE, permettant de gérer la virtualisation pour des systèmes embarqués sur des plateformes de type SoC et fournissant un environnement pour les machines virtuelles en temps réel. Nous avons simplifié l'architecture du micro-noyau en ne gardant que les caractéristiques essentielles requises pour la virtualisation, et fortement réduit la complexité de la conception du noyau. Sur cette base, nous avons mis en place un mécanisme capable de gérer des ressources reconfigurables dans un système supportant des machines virtuelles. Les accélérateurs matériels reconfigurables sont mappés en tant que dispositifs classiques dans chaque machine. Grâce à une gestion efficace de la mémoire dédiée, nous détectons automatiquement le besoins de ressources et permettons une allocation dynamique des ressources sur FPGA. Suite à diverses expériences et évaluations sur la plateforme Zynq-7000, combinant ARM et ressources FPGA, nous avons montré que Ker-ONE ne dégrade que très peu les performances en termes de temps d'exécution. Les surcoûts engendrés peuvent généralement être ignorés dans les applications réelles. Nous avons également étudié l'ordonnançabilité temps réel dans les machines virtuelles. Les résultats montrent que le respect de l'échéance des tâches temps réel est garanti. Nous avons également démontré que le noyau proposé est capable d'allouer des accélérateurs matériels très rapidementThis thesis describes an original micro-kernel that manages virtualization and that provides an environment for real-time virtual machines. We have simplified the micro-kernel architecture by only keeping critical features required for virtualization, and massively reduced the kernel design complexity. Based on this micro-kernel, we have introduced a framework capable of DPR resource management in a virtual machine system. DPR accelerators are mapped as ordinary devices in each VM. Through dedicated memory management, our framework automatically detects the request for DPR resources and allocates them dynamically. According to various experiments and evaluations on the Zynq-7000 platform we have shown that Ker-ONE causes very low virtualization overheads, which can generally be ignored in real applications. We have also studied the real-time schedulability in virtual machines. The results show that RTOS tasks are guaranteed to be scheduled while meeting their intra-VM timing constraints. We have also demonstrated that the proposed framework is capable of virtual machine DPR allocation with low overhead
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Blumer, Aric David. "Register Transfer Level Simulation Acceleration via Hardware/Software Process Migration." Diss., Virginia Tech, 2007. http://hdl.handle.net/10919/29380.
Повний текст джерелаАнотація:
The run-time reconfiguration of Field Programmable Gate Arrays (FPGAs) opens new
avenues to hardware reuse. Through the use of process migration between hardware and
software, an FPGA provides a parallel execution cache. Busy processes can be migrated into
hardware-based, parallel processors, and idle processes can be migrated out increasing the
utilization of the hardware. The application of hardware/software process migration to the
acceleration of Register Transfer Level (RTL) circuit simulation is developed and analyzed.
RTL code can exhibit a form of locality of reference such that executing processes tend to be
executed again. This property is termed executive temporal locality, and it can be exploited by
migration systems to accelerate RTL simulation.
In this dissertation, process migration is first formally modeled using Finite State Machines
(FSMs). Upon FSMs are built programs, processes, migration realms, and the migration
of process state within a realm. From this model, a taxonomy of migration realms is
developed. Second, process migration is applied to the RTL simulation of digital circuits. The
canonical form of an RTL process is defined, and transformations of HDL code are justified
and demonstrated. These transformations allow a simulator to identify basic active units within
the simulation and combine them to balance the load across a set of processors. Through the
use of input monitors, executive locality of reference is identified and demonstrated on a set
of six RTL designs. Finally, the implementation of a migration system is described which
utilizes Virtual Machines (VMs) and Real Machines (RMs) in existing FPGAs. Empirical and
algorithmic models are developed from the data collected from the implementation to evaluate
the effect of optimizations and migration algorithms.Ph. D.
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Kojima, Leandro. "Metodologia de projeto de sistemas dinamicamente reconfiguráveis." Universidade de São Paulo, 2007. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-01082007-174443/.
Повний текст джерелаАнотація:
FPGAs (Field Programmable Gate Arrays) dinamicamente reconfiguráveis (DR-FPGAs) são soluções promissoras para muitos sistemas embarcados devido a potencial redução de área de silício. Metodologias de projeto e ferramentas CAD relacionadas são ainda muito limitadas para auxiliarem os projetistas a encontrarem soluções dinamicamente reconfiguráveis para diferentes aplicações. Este trabalho propõe uma metodologia de projeto que combina modelos de alto nível em SystemC, técnicas de projeto de baixo nível e a metodologia de projeto modular da XILINX. SystemC foi utilizada para representar o comportamento de alto nível não temporizado e não-RTL, bem como o baixo nível RTL-DCS (Chaveamento Dinâmico de Circuitos). Um estudo de caso da Banda Base de um Controlador Bluetooth foi desenvolvido. Duas partições temporais foram testadas em nove diferentes DR-FPGAs. A exploração espacial mostrou que 33% das soluções investigadas atenderam a restrição da especificação de 625µs de tempo do quadro do pacote Bluetooth, deixando diferentes parcelas de recursos livres que podem ser explorados para acomodar outros módulos IP de sistemas mais complexos no mesmo dispositivo.Dynamically Reconfigurable Field Programmable Gate Arrays (DR-FPGAs) are promising solutions for many embedded systems due to the potential silicon area reduction. Design methodologies and related CAD tools are still very limited to assist designers to encounter dynamically reconfigurable solutions for different applications. This work proposes a design methodology that combines high level SystemC models and design techniques with the low level modular design proposed by Xilinx. SystemC has been used to represent the high level untimed non-RTL behavior as well as the low level RTL-DCS (Dynamic Circuit Switching). A Bluetooth Baseband unit case study was performed. Two temporal-functional partitions were evaluated on nine different target DR-FPGAs. The design space exploration showed that 33% of the investigated solutions complied with the 625µs Bluetooth packet time frame specification leaving different amounts if free resources that may be explored to accommodate other IP modules of more complex systems on the same device.
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Zhao, Yue. "Automatic Prevention and Recovery of Aircraft Loss-of-Control by a Hybrid Control Approach." Ohio University / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1458728101.
Повний текст джерела
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Marques, Sampaio Daniel. "Space and time in the making : urban reconfigurations of South and Southeast London." Thesis, Brunel University, 2003. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.249732.
Повний текст джерела
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Pabit, Sersita Suzette Atienza. "Fast dynamics in protein folding time-resolved fluorescence and absorbance studies of polypeptide reconfigurations /." [Gainesville, Fla.] : University of Florida, 2004. http://purl.fcla.edu/fcla/etd/UFE0004296.
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Jara, Mario Andrés Raffo. "Desenvolvimento de um sistema dinamicamente reconfigurável baseado em redes intra-chip e ferramenta para posicionamento de módulos." Universidade de São Paulo, 2010. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-11082010-100838/.
Повний текст джерелаАнотація:
Os sistemas dinamicamente reconfiguráveis (SDRs) são uma alternativa para o desenvolvimento de sistemas sobre silício baseados em circuitos programáveis (SoPC), cujo principal beneficio é o bom aproveitamento da área do dispositivo. Sendo neles implementados circuitos que representam as tarefas que devem operar numa etapa específica do tempo de operação do sistema, permitem um menor consumo de área e de energia, parâmetros importantes nos sistemas portáveis. Isto tem gerado muito interesse no que se refere às metodologias de projeto utilizando FPGAs (Field Programmable Gate Arrays) dinamicamente reconfiguráveis (DRFPGAs) e à definição de um meio de comunicação estruturado para tratar da transferência de dados entre as partes reconfiguráveis e as fixas, mas estas tarefas, assim como a concretização de sua comunicação, seguem sendo ainda essencialmente manuais, devido à falta de metodologias de projeto e ferramentas de CAD que simplifiquem o projeto de SDRs. Este trabalho foca uma das limitações mais efetivas para a adoção da reconfiguração dinâmica: a falta de ferramentas de CAD que suportem o projeto de SDRs, inclusive os baseados em redes intra-chip (NoCs), em particular, no posicionamento dos módulos. Neste trabalho, uma arquitetura para SDRs baseado em NoCs é proposta e um algoritmo de posicionamento dos módulos de um SDR baseado em aspectos reais da família do DRFPGAs é desenvolvido, dentro de uma ferramenta denominada DynoPlace. Desenvolveu-se também um modelo de validação e simulação de SDRs, em tempo de operação, utilizando-se a técnica de chaveamento dinâmico de circuitos. Para o estudo do caso, de validação da arquitetura e metodologia, propõe-se uma aplicação teste baseada em computação de operações aritméticas. A metodologia de simulação permite determinar o tempo da reconfiguração e verificar o comportamento do SDR no momento da reconfiguração. A ferramenta DynoPlace permite gerar os arquivos de restrição de usuário (UCF) de posicionamento dos módulos do SDR no DRFPGA Virtex-4LX25. Este contém informações do posicionamento dos módulos do sistema, dos dispositivos usados para as entradas e saídas do sistema além do posicionamento dos bus-macros. Com os arquivos gerados pela metodologia e ferramenta DynoPlace, pode-se executar com sucesso os scripts da metodologia Early Access da Xilinx para gerar o SDR de forma automática.Dynamically Reconfigurable Systems (DRSs) are an alternative for developing Systems on a Programmable Chip (SoPC), being the efficient use of device\'s area one of its main advantages. Circuits implemented as DRSs represent tasks which must be active in specific times into the system operation, allowing area and energy saving, which is an important goal for portable systems. This has generated interests on the design methodology using Dynamically Reconfigurable Field Programmable Gate Arrays (DRFPGAs) and on the definition of communication systems for handling data transfer between static and reconfigurable partitions. However, these tasks, as well as the communication structure, are still carried out manually due to lack of design methodologies and CAD tools applied to DRSs design. This work focuses on the one of main drawbacks to the adoption of dynamic reconfiguration methods: the absence of CAD tools which support DRS designs, specifically, in the module positioning task, included, for those based on Network-on-Chip (NoCs). In this work, an architecture for DRSs based on NoCs is presented and an algorithm for module positioning is developed in a tool called DynoPlace as well, based on real specifications of DRFPGAs families. It is also developed a run-time simulation and validation model for DRSs, through a dynamic circuit switching technique. For the validation of architecture and methodology study case, an application test based on arithmetic operations has been proposed. The simulations methodology allows to determine the reconfiguration time and verify the DRS behavior at the moment of reconfiguration. The DynoPlace tool allows to generate User Constraint File (UCF) of DRS\'s modules positioning for the DRFPGA Virtex-4LX25. This file contains information of modules positioning in the system, of the devices used for inputs and outputs of the system, and the positioning of bus-macros. After the files generation by the methodology, and the DynoPlace tool, it is possible to successfully execute the Early Access scripts for generating the DRS automatically.
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Coqblin, Mathias. "Optimisation du débit pour des applications linéaires multi-tâches sur plateformes distribuées incluant des temps de reconfiguration." Thesis, Besançon, 2015. http://www.theses.fr/2015BESA2059/document.
Повний текст джерелаАнотація:
Les travaux présentés dans cette thèse portent sur l’ordonnancement d’applications multi-tâches linéaires de type workflow sur des plateformes distribuées. La particularité du système étudié est que le nombre de machines composant la plateforme est plus petit que le nombre de tâches à effectuer. Dans ce cas les machines sont supposées être capables d’effectuer toutes les tâches de l’application moyennant une reconfiguration, sachant que toute reconfiguration demande un temps donné dépendant ou non des tâches. Le problème posé est de maximiser le débit de l’application,c’est à dire le nombre moyen de sorties par unité de temps, ou de minimiser la période, c’est à dire le temps moyen entre deux sorties. Par conséquent le problème se décompose en deux sous problèmes: l’assignation des tâches sur les machines de la plateforme (une ou plusieurs tâches par machine), et l’ordonnancement de ces tâches au sein d’une même machine étant donné les temps de reconfiguration. Pour ce faire la plateforme dispose d’espaces appelés buffers, allouables ou imposés, pour stocker des résultats de production temporaires et ainsi éviter d’avoir à reconfigurer les machines après chaque tâche. Si les buffers ne sont pas pré-affectés nous devons également résoudre le problème de l’allocation de l’espace disponible en buffers afin d’optimiser l’exécution de l’ordonnancement au sein de chaque machine. Ce document est une étude exhaustive des différents problèmes associés à l’hétérogénéité de l’application ; en effet si la résolution des problèmes est triviale avec des temps de reconfiguration et des buffers homogènes, elle devient bien plus complexe si ceux-ci sont hétérogènes. Nous proposons ainsi d’étudier nos trois problèmes majeurs pour différents degrés d’hétérogénéité de l’application. Nous proposons des heuristiques pour traiter ces problèmes lorsqu’il n’est pas possible de trouver une solution algorithmique optimaleIn this document we tackle scheduling problems of multitask linear workflow applications ondistributed platforms. In our particular problem the number of available machines on the platformis lower than the number of stages within the pipeline. The machines are then assumed to be able toperform any kind of task on the application given the appropriate reconfiguration (or setup), the catchbeing that any reconfiguration is time consuming. The problem that we try to solve is to maximizethe throughput of such applications, i.e., the mean amount of outputs per unit of time, or to minimizeits period, i.e., the average time between two outputs. As a result this problem is split into two subproblems:mapping tasks onto different machines of the platform (most machines will likely handleseveral tasks), and find an optimal schedule within a machine while taking setup times into account.To solve this we introduce buffers, which are spaces available for each machine to store temporaryproduction results and avoid reconfiguring after each task execution, and which may or may notbe already allocated for each stage. If those buffers are not already allocated to each task then athird problem must be solved to properly allocate the available space onto each buffer, as differentbuffer configurations have a huge impact on the scheduling of a machine. This document presentsan exhaustive coverage of the different problems that are associated with the heterogeneity of theapplication; the problems with homogeneous buffer capacities and setup times are rather simple tosolve, but they get a lot more complex as heterogeneity increases. We study the three main subproblemsfor each heterogeneity combination, and offer heuristic solution to solve them when anoptimal solution cannot be reasonably found
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Andrés, Martínez David de. "Speeding-up model-based fault injection of deep-submicron CMOS fault models through dynamic and partially reconfigurable FPGAS." Doctoral thesis, Universitat Politècnica de València, 2008. http://hdl.handle.net/10251/1943.
Повний текст джерелаАнотація:
Actualmente, las tecnologías CMOS submicrónicas son básicas para el desarrollo de los modernos sistemas basados en computadores, cuyo uso simplifica enormemente nuestra vida diaria en una gran variedad de entornos, como el gobierno, comercio y banca electrónicos, y el transporte terrestre y aeroespacial. La continua reducción del tamaño de los transistores ha permitido reducir su consumo y aumentar su frecuencia de funcionamiento, obteniendo por ello un mayor rendimiento global. Sin embargo, estas mismas características que mejoran el rendimiento del sistema, afectan negativamente a su confiabilidad. El uso de transistores de tamaño reducido, bajo consumo y alta velocidad, está incrementando la diversidad de fallos que pueden afectar al sistema y su probabilidad de aparición. Por lo tanto, existe un gran interés en desarrollar nuevas y eficientes técnicas para evaluar la confiabilidad, en presencia de fallos, de sistemas fabricados mediante tecnologías submicrónicas.
Este problema puede abordarse por medio de la introducción deliberada de fallos en el sistema, técnica conocida como inyección de fallos. En este contexto, la inyección basada en modelos resulta muy interesante, ya que permite evaluar la confiabilidad del sistema en las primeras etapas de su ciclo de desarrollo, reduciendo por tanto el coste asociado a la corrección de errores. Sin embargo, el tiempo de simulación de modelos grandes y complejos imposibilita su aplicación en un gran número de ocasiones.
Esta tesis se centra en el uso de dispositivos lógicos programables de tipo FPGA (Field-Programmable Gate Arrays) para acelerar los experimentos de inyección de fallos basados en simulación por medio de su implementación en hardware reconfigurable.
Para ello, se extiende la investigación existente en inyección de fallos basada en FPGA en dos direcciones distintas: i) se realiza un estudio de las tecnologías submicrónicas existentes para obtener un conjunto representativo de modelos de fallos transitoriosAndrés Martínez, DD. (2007). Speeding-up model-based fault injection of deep-submicron CMOS fault models through dynamic and partially reconfigurable FPGAS [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/1943
Palancia
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Huang, Yongliang. "Une approche incrémentale pour l’extraction de séquences de franchissement dans un Réseau de Petri Temporisé : application à la reconfiguration des systèmes de production flexibles." Thesis, Ecole centrale de Lille, 2013. http://www.theses.fr/2013ECLI0018/document.
Повний текст джерелаАнотація:
Cette thèse a pour objectif la génération de séquences de franchissement dans les Réseaux de Petri Temporisés (RdPT) en utilisant une approche incrémentale. Le verrou principal auquel est confronté ce travail est l’explosion combinatoire qui résulte de la construction classique du graphe d’accessibilité du RdPT. Nous proposons d’utiliser la notion de séquence de steps temporisés, afin d’exprimer progressivement l’ensemble des séquences de franchissements permettant de passer d’un état courant à un état cible. La notion de step temporisé correspond à une abstraction logique du comportement du système considéré. Le caractère incrémental de l’approche a pour objectif de gagner en efficacité. En effet, il consiste à exprimer tout nouvel état de la résolution par rapport à une profondeur K+1, en fonction d’un état atteint à la profondeur K. Ainsi, nous proposons plusieurs algorithmes de recherche incrémentale permettant d'améliorer l'efficacité de la résolution des problèmes d'accessibilité. Nous utilisons ensuite la programmation par contraintes pour modéliser le problème de recherche d’accessibilité dans un RdPT et mettre en œuvre notre approche incrémentale. Notre approche permet également d’ajouter des contraintes spécifiques à un contexte de résolution. Nous avons notamment utilisé cette possibilité pour proposer des techniques d'identification des jetons dans un RdPT borné, dans le cadre de la reconfiguration des systèmes manufacturiers. Nous concluons par l’évaluation de différentes applications constituant des « benchmarks » permettant d’illustrer l'efficacité des approches proposéesThis PhD thesis is dedicated to the generation of firing sequences in Timed Petri Net (TPN) using an incremental approach. To reduce the influence of the well-known combinatorial explosion issue, a unique sequence of timed steps is introduced to represent implicitly the underlying reachability graph of the TPN, without needing its whole construction. This sequence of timed steps is developed based on the logical abstraction technique. The advantage of the incremental approach is that it can express any state just from the last step information, instead of representing all states before.Several incremental search algorithms are introduced to improve the efficiency of our methodology. Constraint programming techniques are used to model and solve our incremental model, in which search strategies are developed that can search for solutions more efficiently. Our methodology can be used to add specific constraints to model realistic systems. Token identification techniques are developed to handle token confusion issues that appear when addressing the reconfiguration of manufacturing systems. Experimental benchmarks illustrate the effectiveness of approaches proposed in this thesis
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Gicquel, Céline. "MIP models and exact methods for the Discrete Lot-sizing and Scheduling Problem with sequence-dependent changeover costs and times." Phd thesis, Ecole Centrale Paris, 2008. http://tel.archives-ouvertes.fr/tel-00375964.
Повний текст джерелаАнотація:
Le dimensionnement des lots de production est une des nombreuses activités survenant dans le cadre de la planification de production. Il a pour objet de déterminer quand et combien produire de façon à réaliser le meilleur compromis possible entre la minimisation des coûts liés à la production (coûts fixes de reconfiguration de la ressource, coûts de stockage...) et la satisfaction de la demande des clients Nous nous intéressons ici un problème de planification de production par lots connu sous le nom de "Discrete Lot-sizing and Scheduling Problem" ou "DLSP". Plus précisément, nous étudions plusieurs variantes de ce problème dans lesquelles les coûts et/ou les temps de changement de produits sur la ressource sont dépendant de la séquence et nous proposons diverses extensions d'une méthode disponible dans la littérature pour la résolution exacte du problème mono-niveau, mono-ressource. Nos contributions portent à la fois sur la modélisation du problème et sur l'implémentation de méthodes efficaces de résolution. En ce qui concerne la modélisation, nous étudions l'intégration de divers aspects opérationnels dans le modèle de base afin d'en améliorer la pertinence industrielle. Ainsi nous considérons les extensions suivantes : la prise en compte d'une structure de produits "multi-attributs" qui permet de diminuer la taille du problème d'optimisation à résoudre, l'intégration de temps de changement positifs afin de mieux modéliser la perte de production causée par une reconfiguration de la ressource et la présence de plusieurs ressources parallèles dont la production doit être planifiée simultanément. En ce qui concerne la résolution du problème, nous présentons pour chacune des extensions du modèle de base une approche de résolution visant à fournir des solutions optimales exactes. En général, les résultats de nos expériences numériques montrent l'utilité pratique de ces algorithmes pour la résolution d'instances de moyenne et grande taille en des temps de calcul compatibles avec une application industrielle
47
Lange, Sebastian, and Martin Middendorf. "Hyperreconfigurable architectures for fast run time reconfiguration." 2004. https://ul.qucosa.de/id/qucosa%3A32843.
Повний текст джерелаАнотація:
Dynamically reconfigurable architectures or systems are able to reconfigure their function and/or structure to suit changing needs of a computation during run time. The increasing flexibility of modern dynamically reconfigurable systems improves their adaptability but also makes fast reconfiguration difficult because of the large amount of necessary reconfiguration information. However, even when a computation uses this flexibility it is not use it all the time. Therefore, we propose to make the potential for reconfiguration itself reconfigurable. This allows for speeding up reconfiguration operations during phases where only parts of the total flexibility are required. Such architectures are called hyperreconfigurable and uses two types of reconfiguration operations: hyperreconfigurations for changing the reconfiguration potential and ordinary reconfigurations for actually configuring a new context for a computation.
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SELVI, DANIELA. "Real-Time Control Reconfiguration for Active Disturbance Attenuation." Doctoral thesis, 2015. http://hdl.handle.net/2158/1003142.
Повний текст джерелаАнотація:
In this work, the problem of active attenuation of disturbances with uncertain and possibly time-varying characteristics is addressed. The focus is on situations in which the uncertainty set is large, that is, the possible operating conditions of the system subject to disturbances can be different so that a single robust controller cannot ensure satisfactory performance levels. These situations underline the importance of control solutions able to reconfigure their action in real-time. The first part of this work is focused on the description of two different case studies, namely an active suspension system and an adaptive optics system, as well as on an overview of relevant contributions within the literature related to this subject. The solution that we propose is described in the second part; this method relies on the Adaptive Switching Control (ASC) paradigm, which has emerged as an alternative to classical Adaptive Control. In ASC, a finite family of candidate controllers is pre-synthesized off-line, and a supervisory logic has to select the potentially best one to be put in feedback with the plant. Particular attention is devoted to both performance and stability of the overall switching system. Finally, as an extension of the solution based on ASC, in the third part of this work an algorithm is proposed which combines both switching and tuning, aiming at preserving the beneficial features of the two different approaches, while possibly overcoming their drawbacks. The effectiveness of the proposed solutions is validated by means of simulation tests performed in the context of the two considered case studies.
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Tseng, Chi-Hua, and 曾啟華. "Reconfiguration Overhead Reduction and Hiding of Run-Time Reconfigurable System." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/72639710189266801319.
Повний текст джерелаАнотація:
碩士國立交通大學
資訊工程系
92
In run-time reconfigurable system, the whole partial reconfigurable hardware is viewed as a reconfiguration and execution unit traditionally. Therefore, execution cannot start until the finish reconfiguration of the whole partial reconfigurable hardware. We virtually divide the partial reconfigurable hardware into several equal-size blocks. The reconfiguration and execution unit is smaller. This can make reconfiguration of one block overlap with execution of other blocks. And this can hide some reconfiguration overhead. Doing so will bring a new problem which is partitions-to-blocks scheduling. We design a two phases scheduler. Phase I will generate one highest priority partition from un-scheduled partitions. There are three considerations of the partition’s priority. One is the partition is on current critical path or not. Another is the number of outgoing edges and released partitions of the partition. The other is the execution time of the partition. We have two partition selection policies including of critical first and utilization first. Phase II will assign one block to the highest priority partition generated from Phase I. If the partition is the latest partition, we will assign one block to the partition so that the partition can finish execution earliest. If the partition is not the latest partition, we will look ahead one next future partition into consideration together. Choose one block to the primary partition so that these two partitions can release maximal resource with time. The result shows that utilization first is better than critical first. And view a part of the whole partial reconfigurable hardware as a reconfiguration and execution unit can improve completion time of run-time reconfigurable system.
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Lo, Hsin-I., and 羅信易. "Real-Time Dynamic Partial Reconfiguration Platform For Implementation Digital Image Processing Application." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/70588048564477845138.
Повний текст джерелаАнотація:
碩士元智大學
資訊工程學系
98
This paper raises an image processing application which utilizes a platform of dynamic real-time partial reconfiguration. Initially, design a platform of dynamic real-time partial reconfiguration platform and hereby use it to conduct image processing of dilation and erosion as exemplifications here[1].In the algorithm of image processing, morphing of dilation and erosion would be functions of Maximum Filter and Minimum Filter respectively. The platform of real-time partial reconfiguration is composed of a Microprocessor (MicroBlaze)[2] as the core of this system and of both Maximum and Minimum Filters, formed with two modules which are respectively built according to the differences of them executing comparator and are switched to the region based on the concept of partial reconfiguration. On the side of implementation, the Microprocessor (MicroBlaze) is designed in Xilinx XPS 9.2[3] and functions of two filters are programmed by Verilog in Xilinx ISE 9.2i. Eventually, implement the function of system onto Xilinx Virtex-5 ML-506[4] as verification.