Статті в журналах з теми "Reconfiguration overhead"
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Hoffman, John C., and Marios S. Pattichis. "A High-Speed Dynamic Partial Reconfiguration Controller Using Direct Memory Access Through a Multiport Memory Controller and Overclocking with Active Feedback." International Journal of Reconfigurable Computing 2011 (2011): 1–10. http://dx.doi.org/10.1155/2011/439072.
Повний текст джерелаJUNG, S., and T. G. KIM. "Configuration Sharing to Reduce Reconfiguration Overhead Using Static Partial Reconfiguration." IEICE Transactions on Information and Systems E91-D, no. 11 (November 1, 2008): 2675–84. http://dx.doi.org/10.1093/ietisy/e91-d.11.2675.
Повний текст джерелаSungjoon Jung and Tag Gon Kim. "An Operation and Interconnection Sharing Algorithm for Reconfiguration Overhead Reduction Using Static Partial Reconfiguration." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16, no. 12 (December 2008): 1589–95. http://dx.doi.org/10.1109/tvlsi.2008.2000973.
Повний текст джерелаCHOU, Kuan-Hung, and Woei LIN. "Performance Analysis of Optical Packet Switches with Reconfiguration Overhead." IEICE Transactions on Communications E94-B, no. 6 (2011): 1640–47. http://dx.doi.org/10.1587/transcom.e94.b.1640.
Повний текст джерелаKIM, J., J. CHO, and T. G. KIM. "Temporal Partitioning to Amortize Reconfiguration Overhead for Dynamically Reconfigurable Architectures." IEICE Transactions on Information and Systems E90-D, no. 12 (December 1, 2007): 1977–85. http://dx.doi.org/10.1093/ietisy/e90-d.12.1977.
Повний текст джерелаBELAID, IKBEL, BASSEM OUNI, FABRICE MULLER, and MAHER BENJEMAA. "COMPLETE AND APPROXIMATE METHODS FOR OFF-LINE PLACEMENT OF HARDWARE TASKS ON RECONFIGURABLE DEVICES." Journal of Circuits, Systems and Computers 22, no. 02 (February 2013): 1250080. http://dx.doi.org/10.1142/s0218126612500806.
Повний текст джерелаKoch, Dirk, Christian Beckhoff, and Jim Torresen. "Efficient Interfacing of Partially Reconfigurable Instruction Set Extensions for Softcore CPUs on FPGAs." Journal of Integrated Circuits and Systems 6, no. 1 (December 27, 2011): 35–42. http://dx.doi.org/10.29292/jics.v6i1.336.
Повний текст джерелаKIM, YOONJIN. "POWER-EFFICIENT CONFIGURATION CACHE STRUCTURE FOR COARSE-GRAINED RECONFIGURABLE ARCHITECTURE." Journal of Circuits, Systems and Computers 22, no. 03 (March 2013): 1350001. http://dx.doi.org/10.1142/s0218126613500011.
Повний текст джерелаFeng, Xiao Jing, Xi Li, Wang Chao, Xue Hai Zhou, and Jun Neng Zhang. "A Hardware/Software Co-Design Flow for Dynamic Partial Reconfiguration." Advanced Materials Research 433-440 (January 2012): 5172–77. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.5172.
Повний текст джерелаLallet, Julien, Sébastien Pillement, and Olivier Sentieys. "Efficient and Flexible Dynamic Reconfiguration for Multi Context Architectures." Journal of Integrated Circuits and Systems 4, no. 1 (November 21, 2009): 36–44. http://dx.doi.org/10.29292/jics.v4i1.295.
Повний текст джерелаJamali, Vahid, George C. Alexandropoulos, Robert Schober, and H. Vincent Poor. "Low-to-Zero-Overhead IRS Reconfiguration: Decoupling Illumination and Channel Estimation." IEEE Communications Letters 26, no. 4 (April 2022): 932–36. http://dx.doi.org/10.1109/lcomm.2022.3141206.
Повний текст джерелаHe, Xiangyue, Haiyang Li, Luyi Yang, and Jian Zhao. "Reconfigurable Satellite Constellation Design for Disaster Monitoring Using Physical Programming." International Journal of Aerospace Engineering 2020 (September 1, 2020): 1–15. http://dx.doi.org/10.1155/2020/8813685.
Повний текст джерелаChou, Kuan-Hung, and Woei Lin. "An analytical model for input-buffered optical packet switches with reconfiguration overhead." Photonic Network Communications 22, no. 3 (July 7, 2011): 209–20. http://dx.doi.org/10.1007/s11107-011-0320-4.
Повний текст джерелаTomovic, Slavica, and Igor Radusinovic. "Dynamic optimization of load-balancing and reconfiguration overhead in SD-ISP networks." Telfor Journal 11, no. 1 (2019): 8–13. http://dx.doi.org/10.5937/telfor1901008t.
Повний текст джерелаTomovic, Slavica, and Igor Radusinovic. "RO-RO: Routing Optimality - Reconfiguration Overhead Balance in Software-Defined ISP Networks." IEEE Journal on Selected Areas in Communications 37, no. 5 (May 2019): 997–1011. http://dx.doi.org/10.1109/jsac.2019.2906762.
Повний текст джерелаDuhem, F., F. Muller, and P. Lorenzini. "Reconfiguration time overhead on field programmable gate arrays: reduction and cost model." IET Computers & Digital Techniques 6, no. 2 (2012): 105. http://dx.doi.org/10.1049/iet-cdt.2011.0033.
Повний текст джерелаHe, Pan, Gang Liu, and Yue Yuan. "An Adaptive Reconfiguration Mechanism for Periodic Software Rejuvenation based on Transient Reliability Analysis." MATEC Web of Conferences 232 (2018): 03045. http://dx.doi.org/10.1051/matecconf/201823203045.
Повний текст джерелаSoumya, J., K. Niranjan Babu, and Santanu Chattopadhyay. "Multi-Application Mapping onto a Switch-Based Reconfigurable Network-on-Chip Architecture." Journal of Circuits, Systems and Computers 26, no. 11 (April 27, 2017): 1750174. http://dx.doi.org/10.1142/s0218126617501742.
Повний текст джерелаMunaf, S., Dr A. Bharathi, and Dr A. N. Jayanthi. "Double Pumping Low Power Technique for Coarse - Grained Reconfigurable Architecture." International Journal of Electrical and Electronics Research 4, no. 1 (March 31, 2016): 10–15. http://dx.doi.org/10.37391/ijeer.040103.
Повний текст джерелаSchuck, Christian, Bastian Haetzer, and Jürgen Becker. "Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs." International Journal of Reconfigurable Computing 2011 (2011): 1–12. http://dx.doi.org/10.1155/2011/671546.
Повний текст джерелаVADHIYAR, SATHISH S., and JACK J. DONGARRA. "SRS: A FRAMEWORK FOR DEVELOPING MALLEABLE AND MIGRATABLE PARALLEL APPLICATIONS FOR DISTRIBUTED SYSTEMS." Parallel Processing Letters 13, no. 02 (June 2003): 291–312. http://dx.doi.org/10.1142/s0129626403001288.
Повний текст джерелаRantala, Ville, Teijo Lehtonen, Pasi Liljeberg, and Juha Plosila. "Analysis of Monitoring Structures for Network-on-Chip." International Journal of Embedded and Real-Time Communication Systems 2, no. 1 (January 2011): 49–67. http://dx.doi.org/10.4018/jertcs.2011010103.
Повний текст джерелаAnwer, Jahanzeb, Sebastian Meisner, and Marco Platzner. "Dynamic Reliability Management for FPGA-Based Systems." International Journal of Reconfigurable Computing 2020 (June 13, 2020): 1–19. http://dx.doi.org/10.1155/2020/2808710.
Повний текст джерелаHaller, Stefan, Muhammad Farhan Alam, and Kent Bertilsson. "Reconfigurable Battery for Charging 48 V EVs in High-Voltage Infrastructure." Electronics 11, no. 3 (January 24, 2022): 353. http://dx.doi.org/10.3390/electronics11030353.
Повний текст джерелаFarshadjam, Farshid, Mehdi Dehghan, Mahmood Fathy, and Majid Ahmadi. "A new compression based approach for reconfiguration overhead reduction in virtex based RTR systems." Computers & Electrical Engineering 32, no. 4 (July 2006): 322–47. http://dx.doi.org/10.1016/j.compeleceng.2005.09.007.
Повний текст джерелаFu, Shu, Bin Wu, Xiaohong Jiang, Achille Pattavina, Hong Wen, and Hongfang Yu. "Switch cost and packet delay tradeoff in data center networks with switch reconfiguration overhead." Computer Networks 87 (July 2015): 33–43. http://dx.doi.org/10.1016/j.comnet.2015.05.010.
Повний текст джерелаAgrawal, Praveen, Neeraj Kanwar, Nikhil Gupta, Khaleequr Rehman Niazi, Anil Swarnkar, Nand K. Meena, and Jin Yang. "Reliability and Network Performance Enhancement by Reconfiguring Underground Distribution Systems." Energies 13, no. 18 (September 10, 2020): 4719. http://dx.doi.org/10.3390/en13184719.
Повний текст джерелаSaeed, Ahmed, Ali Ahmadinia, and Mike Just. "Secure On-Chip Communication Architecture for Reconfigurable Multi-Core Systems." Journal of Circuits, Systems and Computers 25, no. 08 (May 17, 2016): 1650089. http://dx.doi.org/10.1142/s0218126616500894.
Повний текст джерелаDeng, Li, Yang Li, Li Yao, Yu Jin, and Jinguang Gu. "Power-Aware Resource Reconfiguration Using Genetic Algorithm in Cloud Computing." Mobile Information Systems 2016 (2016): 1–9. http://dx.doi.org/10.1155/2016/4859862.
Повний текст джерелаMon Myint, Su, and Soe Win Naing. "Network Reconfiguration for Loss Reduction and Voltage Profile Improvement of 110-Bus Radial Distribution System Using Exhaustive Search Techniques." International Journal of Electrical and Computer Engineering (IJECE) 5, no. 4 (August 1, 2015): 788. http://dx.doi.org/10.11591/ijece.v5i4.pp788-797.
Повний текст джерелаKamran, Arezoo, and Zainalabedin Navabi. "Self-Healing Many-Core Architecture: Analysis and Evaluation." VLSI Design 2016 (July 25, 2016): 1–17. http://dx.doi.org/10.1155/2016/9767139.
Повний текст джерелаResano, Javier, Diederik Verkest, Daniel Mozos, Serge Vernalde, and Francky Catthoor. "A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs." Microprocessors and Microsystems 28, no. 5-6 (August 2004): 291–301. http://dx.doi.org/10.1016/j.micpro.2004.03.015.
Повний текст джерелаYoshitomi, Hiroyuki. "OrientalHydrocyphon(Coleoptera: Scirtidae: Scirtinae): Seven New Species from Indonesia, Thailand, Malaysia, and India." Psyche: A Journal of Entomology 2012 (2012): 1–16. http://dx.doi.org/10.1155/2012/603875.
Повний текст джерелаMeloni, Paolo, Sebastiano Pomata, Giuseppe Tuveri, Simone Secchi, Luigi Raffo, and Menno Lindwer. "Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper." VLSI Design 2012 (March 29, 2012): 1–16. http://dx.doi.org/10.1155/2012/580584.
Повний текст джерелаPrasad Acharya, G., and M. Asha Rani. "Online Self-testable Multi-core System using Dynamic Partial Reconfiguration of FPGA." International Journal of Reconfigurable and Embedded Systems (IJRES) 6, no. 3 (May 28, 2018): 160. http://dx.doi.org/10.11591/ijres.v6.i3.pp160-168.
Повний текст джерелаKIA, REZA, NIKBAKHSH JAVADIAN, MOHAMMAD MAHDI PAYDAR, and MOHAMMAD SAIDI-MEHRABAD. "A SIMULATED ANNEALING FOR INTRA-CELL LAYOUT DESIGN OF DYNAMIC CELLULAR MANUFACTURING SYSTEMS WITH ROUTE SELECTION, PURCHASING MACHINES AND CELL RECONFIGURATION." Asia-Pacific Journal of Operational Research 30, no. 04 (August 2013): 1350004. http://dx.doi.org/10.1142/s0217595913500048.
Повний текст джерелаLopes Ferreira, Mário, and João Canas Ferreira. "An FPGA-Oriented Baseband Modulator Architecture for 4G/5G Communication Scenarios." Electronics 8, no. 1 (December 20, 2018): 2. http://dx.doi.org/10.3390/electronics8010002.
Повний текст джерелаPortilla, J., A. Otero, E. de la Torre, T. Riesgo, O. Stecklina, S. Peter, and P. Langendörfer. "Adaptable Security in Wireless Sensor Networks by Using Reconfigurable ECC Hardware Coprocessors." International Journal of Distributed Sensor Networks 6, no. 1 (January 1, 2010): 740823. http://dx.doi.org/10.1155/2010/740823.
Повний текст джерелаZhang, Xueji, Goele Pipeleers, Kristian Hengster-Movrić, and Cassio Faria. "Vibration reduction for structures: distributed schemes over directed graphs." Journal of Vibration and Control 25, no. 14 (May 13, 2019): 2025–42. http://dx.doi.org/10.1177/1077546319844856.
Повний текст джерелаGUPTA, VIPUL, and EUGEN SCHENFELD. "TASK GRAPH PARTITIONING AND MAPPING IN A RECONFIGURABLE PARALLEL ARCHITECTURE." Parallel Processing Letters 05, no. 04 (December 1995): 563–74. http://dx.doi.org/10.1142/s0129626495000503.
Повний текст джерелаDo Nascimento, Paulo Sérgio Brandão, Stelita M. Da Silva, Jordana L. Seixas, Remy E. Sant’Anna, and Manoel E. De Lima. "Mapping of Massive Data Processing Systems to FPGA Computers Based on Temporal Partitioning and Design Space Exploration." Journal of Integrated Circuits and Systems 2, no. 1 (September 9, 2007): 45–54. http://dx.doi.org/10.29292/jics.v2i1.235.
Повний текст джерелаAziz, Israa, Hai Jin, Ihsan Abdulqadder, Zaid Hussien, Zaid Abduljabbar, and Firas Flaih. "A Lightweight Scheme to Authenticate and Secure the Communication in Smart Grids." Applied Sciences 8, no. 9 (September 1, 2018): 1508. http://dx.doi.org/10.3390/app8091508.
Повний текст джерелаZhang, Dan, Rong Cai Zhao, Lin Han, and Jin Qu. "A Parallelization Cost Model for FPGA." Advanced Materials Research 181-182 (January 2011): 623–28. http://dx.doi.org/10.4028/www.scientific.net/amr.181-182.623.
Повний текст джерелаMahesh, R., and A. P. Vinod. "An Area-efficient Non-uniform Filter Bank for Low Overhead Reconfiguration of Multi-standard Software Radio Channelizers." Journal of Signal Processing Systems 64, no. 3 (June 22, 2010): 413–28. http://dx.doi.org/10.1007/s11265-010-0502-9.
Повний текст джерелаZeng, Shulin, Guohao Dai, Hanbo Sun, Jun Liu, Shiyao Li, Guangjun Ge, Kai Zhong, Kaiyuan Guo, Yu Wang, and Huazhong Yang. "A Unified FPGA Virtualization Framework for General-Purpose Deep Neural Networks in the Cloud." ACM Transactions on Reconfigurable Technology and Systems 15, no. 3 (September 30, 2022): 1–31. http://dx.doi.org/10.1145/3480170.
Повний текст джерелаSaldaña, Manuel, Arun Patel, Hao Jun Liu, and Paul Chow. "Using Partial Reconfiguration and Message Passing to Enable FPGA-Based Generic Computing Platforms." International Journal of Reconfigurable Computing 2012 (2012): 1–10. http://dx.doi.org/10.1155/2012/127302.
Повний текст джерелаFujioka, Yoshichika, and Nobuhiro Tomabechi. "Design of a Parallel Processor for Visual Feedback Control Based on the Reconfiguration of Word Length." Journal of Robotics and Mechatronics 8, no. 6 (December 20, 1996): 524–30. http://dx.doi.org/10.20965/jrm.1996.p0524.
Повний текст джерелаMoon, Hyeongyun, and Daejin Park. "An Efficient On-Demand Hardware Replacement Platform for Metamorphic Functional Processing in Edge-Centric IoT Applications." Electronics 10, no. 17 (August 28, 2021): 2088. http://dx.doi.org/10.3390/electronics10172088.
Повний текст джерелаJozwik, Krzysztof, Shinya Honda, Masato Edahiro, Hiroyuki Tomiyama, and Hiroaki Takada. "Rainbow: An Operating System for Software-Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs." International Journal of Reconfigurable Computing 2013 (2013): 1–40. http://dx.doi.org/10.1155/2013/789134.
Повний текст джерелаKWON, YOUNG-SU, and NAK-WOONG EUM. "APPLICATION-ADAPTIVE RECONFIGURATION OF MEMORY ADDRESS SHUFFLER FOR FPGA-EMBEDDED INSTRUCTION-SET PROCESSOR." Journal of Circuits, Systems and Computers 19, no. 07 (November 2010): 1435–47. http://dx.doi.org/10.1142/s0218126610006748.
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