Статті в журналах: "Read-Out Circuits"

1

Safari, Leila, Gianluca Barile, Vincenzo Stornelli, and Giuseppe Ferri. "A Review on VCII Applications in Signal Conditioning for Sensors and Bioelectrical Signals: New Opportunities." Sensors 22, no. 9 (May 8, 2022): 3578. http://dx.doi.org/10.3390/s22093578.

Повний текст джерела

Анотація:

This study reviews second-generation voltage conveyor (VCII)-based read-out circuits for sensors and bioelectrical signal conditioning from existing literature. VCII is the dual circuit of a second-generation current conveyor (CCII), which provides the possibility of processing signals in the current domain while providing output signals in the voltage form. The scope of this paper is to discuss the benefits and opportunities of new VCII-based read-out circuits over traditional ones and bioelectrical signals. The achieved main benefits compared to conventional circuits are the simpler read-out circuits, producing an output signal in a voltage form that can be directly used, improved accuracy, possibility of gain adjustment using a single grounded resistor, and the possibility of connecting several SiPM sensors to the readout circuit. The circuits studied in this paper include VCII- based read-out circuits suitable for all types of sensors configured in the current-mode Wheatstone bridge (CMWB) topology, the VCII-based read-out circuits solutions reported for silicon photomultiplier, spiral-shaped ultrasonic PVDF and differential capacitive sensors, and, finally, a simple readout circuitry for sensing bioelectrical signals. There are still not many VCII-based readout circuits, and we hope that the outcome of this study will enhance this area of research and inspire new ideas.

Стилі APA, Harvard, Vancouver, ISO та ін.

2

Im, Saemin, Na-Hoo Lee, Kyoungho Baik, and Sang-Gyu Park. "An Automatic Gain Control Circuits for the Microphone Read-out Integrated Circuit." JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 20, no. 5 (October 31, 2020): 447–55. http://dx.doi.org/10.5573/jsts.2020.20.5.447.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

3

Zhou, Xin Jie, Jing He Wei, and Lei Lei Li. "A SEE Hardened Read-Out Circuit of EEPROM for Space Application." Applied Mechanics and Materials 198-199 (September 2012): 1105–9. http://dx.doi.org/10.4028/www.scientific.net/amm.198-199.1105.

Повний текст джерела

Анотація:

As wide application of EEPROM devices in space and military field, more and more researches focus on its radiation hardened characteristics in international. To improve the single-event effect (SEE) tolerant ability of read-out circuits in the memory, a radiation hardened circuit is designed. The design kernels of radiation hardened latch-flip are given and designed to resist the single-event upset (SEU) effect. A correction circuit is proposed to resist the single-event transient (SET) effect. The performances of this design are: SEU (LET)th ≥ 27 MeV•cm2/mg, SEL(LET)th ≥ 75 MeV•cm2/mg , read out time ≤200 ns. The new design not only satisfied the needs of present work, but supplies a worthful reference for radiation hardened circuit design in future.

Стилі APA, Harvard, Vancouver, ISO та ін.

4

Galeazzi, M., D. F. Bogorin, F. Gatti, and L. Parodi. "RLC Resonant Circuits to Read Out Transition Edge Sensors." IEEE Transactions on Applied Superconductivity 19, no. 3 (June 2009): 514–16. http://dx.doi.org/10.1109/tasc.2009.2017853.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

5

Lu, Weijun, Ning Bao, Tangren Zheng, Xiaorui Zhang, and Yutong Song. "Memristor-Based Read/Write Circuit with Stable Continuous Read Operation." Electronics 11, no. 13 (June 27, 2022): 2018. http://dx.doi.org/10.3390/electronics11132018.

Повний текст джерела

Анотація:

In recent years, computation-intensive applications, such as artificial intelligence, video processing and encryption, have been developing rapidly. On the other hand, the problems of “storage wall” and “power consumption wall” for the traditional storage and computing separated architectures limit the computing performance. The computational circuits and memory cells based on nonvolatile memristors are unified and become a competitive solution to this problem. However, there are various problems that prevent memristor-based circuits from entering practical applications, one of which is the memristor state deviation problem caused by continuous reading. In this paper, we study some circuits studied by predecessors on read/write circuit, compare the experimental results, analyze the reason for the resistance state deviation of memristor, and put forward a new parallel structure of memristor based on opposite polarity. The logic “1” and logic “0” are represented by the positive and negative voltage difference of two memristors with opposite polarity, which can effectively alleviate the problem of the resistance state deviation caused by continuous reading. A reading voltage of 2 V is applied to the four circuits at the same time, and continuous reading is carried out until the output voltage becomes stable. The voltage offset of the optimized circuit when reading logic “0” is reduced to 78 mV, which is significantly smaller than that of other circuits. In addition, when reading logic “1”, it has the effect of enhancing the information stored in the memristor.

Стилі APA, Harvard, Vancouver, ISO та ін.

6

Gottardi, L., J. van de Kuur, S. Bandler, M. Bruijn, P. de Korte, J. R. Gao, R. den Hartog, et al. "AC Read-Out Circuits for Single Pixel Characterization of TES Microcalorimeters and Bolometers." IEEE Transactions on Applied Superconductivity 21, no. 3 (June 2011): 272–75. http://dx.doi.org/10.1109/tasc.2010.2100090.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

7

Zaraee, Negin, Boyou Zhou, Kyle Vigil, Mohammad M. Shahjamali, Ajay Joshi, and M. Selim Unlu. "Gate-Level Validation of Integrated Circuits With Structured-Illumination Read-Out of Embedded Optical Signatures." IEEE Access 8 (2020): 70900–70912. http://dx.doi.org/10.1109/access.2020.2987088.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

8

Nowack, K. C., M. Shafiei, M. Laforest, G. E. D. K. Prawiroatmodjo, L. R. Schreiber, C. Reichl, W. Wegscheider, and L. M. K. Vandersypen. "Single-Shot Correlations and Two-Qubit Gate of Solid-State Spins." Science 333, no. 6047 (August 4, 2011): 1269–72. http://dx.doi.org/10.1126/science.1209524.

Повний текст джерела

Анотація:

Measurement of coupled quantum systems plays a central role in quantum information processing. We have realized independent single-shot read-out of two electron spins in a double quantum dot. The read-out method is all-electrical, cross-talk between the two measurements is negligible, and read-out fidelities are ~86% on average. This allows us to directly probe the anticorrelations between two spins prepared in a singlet state and to demonstrate the operation of the two-qubit exchange gate on a complete set of basis states. The results provide a possible route to the realization and efficient characterization of multiqubit quantum circuits based on single quantum dot spins.

Стилі APA, Harvard, Vancouver, ISO та ін.

9

Borgarino, Mattia. "Circuit-Based Compact Model of Electron Spin Qubit." Electronics 11, no. 4 (February 10, 2022): 526. http://dx.doi.org/10.3390/electronics11040526.

Повний текст джерела

Анотація:

Today, an electron spin qubit on silicon appears to be a very promising physical platform for the fabrication of future quantum microprocessors. Thousands of these qubits should be packed together into one single silicon die in order to break the quantum supremacy barrier. Microelectronics engineers are currently leveraging on the current CMOS technology to design the manipulation and read-out electronics as cryogenic integrated circuits. Several of these circuits are RFICs, as VCO, LNA, and mixers. Therefore, the availability of a qubit CAD model plays a central role in the proper design of these cryogenic RFICs. The present paper reports on a circuit-based compact model of an electron spin qubit for CAD applications. The proposed model is described and tested, and the limitations faced are highlighted and discussed.

Стилі APA, Harvard, Vancouver, ISO та ін.

10

Kim, Younghee, Hongzhou Jin, Dohoon Kim, Panbong Ha, Min-Kyu Park, Joon Hwang, Jongho Lee, et al. "Design of Synaptic Driving Circuit for TFT eFlash-Based Processing-In-Memory Hardware Using Hybrid Bonding." Electronics 12, no. 3 (January 29, 2023): 678. http://dx.doi.org/10.3390/electronics12030678.

Повний текст джерела

Анотація:

This paper presents a synaptic driving circuit design for processing in-memory (PIM) hardware with a thin-film transistor (TFT) embedded flash (eFlash) for a binary/ternary-weight neural network (NN). An eFlash-based synaptic cell capable of programming negative weight values to store binary/ternary weight values (i.e., ±1, 0) and synaptic driving circuits for erase, program, and read operations of synaptic arrays have been proposed. The proposed synaptic driving circuits improve the calculation accuracy of PIM operation by precisely programming the sensing current of the eFlash synaptic cell to the target current (50 nA ± 0.5 nA) using a pulse train. In addition, during PIM operation, the pulse-width modulation (PWM) conversion circuit converts 8-bit input data into one continuous PWM pulse to minimize non-linearity in the synaptic sensing current integration step of the neuron circuit. The prototype chip, including the proposed synaptic driving circuit, PWM conversion circuit, neuron circuit, and digital blocks, is designed and laid out as the accelerator for binary/ternary weighted NN with a size of 324 × 80 × 10 using a 0.35 μm CMOS process. Hybrid bonding technology using bump bonding and wire bonding is used to package the designed CMOS accelerator die and TFT eFlash-based synapse array dies into a single chip package.

Стилі APA, Harvard, Vancouver, ISO та ін.

11

Coccia, Giulio, Argyro N. Giakoumaki, Vibhav Bharadwaj, Ottavia Jedrkiewicz, Roberta Ramponi, and Shane M. Eaton. "Femtosecond laser writing of integrated photonic circuits in diamond." EPJ Web of Conferences 255 (2021): 12006. http://dx.doi.org/10.1051/epjconf/202125512006.

Повний текст джерела

Анотація:

Integrated photonic circuits pave the way for next generation technologies for quantum information and sensing applications. Femtosecond laser writing has emerged as a valuable technique for fabricating such devices when combined with diamond’s properties and its nitrogen vacancy color center. Such color centers are fundamental for sensing applications, being possible to excite them and read them out optically through the fabrication of optical waveguides in the bulk of diamond. We show how to integrate these building blocks in diamond, to develop proof-of-concept devices with unprecedented electric and magnetic field sensitivities.

Стилі APA, Harvard, Vancouver, ISO та ін.

12

Mansore, S. R., and Amit Naik. "Design of a Single-Ended-Write Schmitt-Trigger Based 10T SRAM Cell." Journal of VLSI Design and Signal Processing 8, no. 3 (November 16, 2022): 18–22. http://dx.doi.org/10.46610/jovdsp.2022.v08i03.003.

Повний текст джерела

Анотація:

Technology scaling is done in order to accommodate more and more transistors in today’s high performance VLSI circuits. These high-performance digital circuits demand large capacity of memory to accomplish faithful operations. However, at scaled technology, SRAM-cell stability is a major issue of concern. Also, increased integration density of these VLSI circuits causes increased power consumption. Leakage power in today’s VLSI circuits has become comparable to dynamic power consumption which also needs to be addressed. In this work, a Schmitt-trigger (ST) based 10T SRAM cell with single-ended-writing and differentially-read feature is proposed. The proposed cell offers enhanced stability and dissipates lower leakage power. Due to separate ports for writing and reading in the proposed cell, the conflict design requirement (which is a condition in conventional 6T cell) is eliminated. Schmitt-trigger based inverters in the proposed cell causes increased threshold voltage of the inverters resulting in enhanced cell stability during read operation. Simulation is carried out on TSPICE using a 65nm Predictive Technology Model (PTM). Results show that the proposed 10T cell provides a 1.7x larger Read static noise margin (RSNM) than the conventional 6T cell. Proposed 10T cell provides Write static noise margin (WSNM) of 155mV during write ‘0’ while 150mV during write ‘1’ operation, respectively, at 0.4V. At a supply voltage of 0.4V, the proposed 10T cell consumes 0.71x lesser static power as compared to that of a conventional 6T cell. However, proposed cell uses more transistors (10 transistors) as compared to that of the conventional 6T cell, therefore, our cell occupies large chip-area as compared to the conventional 6T cell.

Стилі APA, Harvard, Vancouver, ISO та ін.

13

GOOBAR, EDGARD, ANDERS KARLSSON, GUNNAR BJÖRK, OLLE NILSSON, and PIERRE-JEAN RIGOLE. "LOW NOISE PHOTON NUMBER MANIPULATION USING SEMICONDUCTOR LIGHT EMITTERS AND RECEIVERS." International Journal of Modern Physics B 09, no. 26 (November 30, 1995): 3355–85. http://dx.doi.org/10.1142/s0217979295001324.

Повний текст джерела

Анотація:

The photon number (intensity) of a light beam can be read out and amplified essentially without adding any noise. In this article we will describe recent proof-of-principle experiments using simple optoelectronic circuits. We also discuss the significance of these results with respects to applications in communication and quantum optics. The relation to quantum non-demolition measurement (QND) strategies is also discussed.

Стилі APA, Harvard, Vancouver, ISO та ін.

14

Mboti, Nyasha. "Circuits of Apartheid." Glimpse 20 (2019): 15–70. http://dx.doi.org/10.5840/glimpse2019202.

Повний текст джерела

Анотація:

This keynote address is about the supply, maintenance and allocation of fungible, vulnerable human bodies—what American President Donald Trump would categorize as the shitholes of the world. Underlying our modern times is a large, unsolved problem about what is really going on in the world. I use the novel theoretical lens of Apartheid Studies to appreciate how we have neglected to read, recognize and call out the persistent circuits of apartheid that are at the heart of global capitalist modernity. Our contemporary age, built on interoperable digital networks, tends to reinforce global forms of apartheid. Apartheid Studies is a new field of studies that makes it possible to expose these circuits. Whereas human beings are human because we all possess a kind of strongly encrypted password which we reserve to give or not to give—so that we feel relatively protected and free to be what we want—this password protection has been eroded by institutions and powerful elites. Modernity itself, by its very nature, emerges when we start to share our passwords with strangers. Passing on the control of the passwords of our being to strangers causes global apartheid. Global capitalist modernity, expressed in invasive technology, generally undermines human beings’ sense of self, immunity, inviolability, indivisibility, and replaces it with social media and an internet of things which are predicated on sharing our privacy with strangers. I propose new emphases on restorative forensics and literacies that are appropriate to the task of generating a scholarship of the future that is ethical and opposed to systemic injustice, that exposes global exploitation, racism, deception, and corruption, and that promotes just worlds.

Стилі APA, Harvard, Vancouver, ISO та ін.

15

Meyyappan, S., and V. Alamelumangai. "Black Box Model based Self Healing Solution for Stuck at Faults in Digital Circuits." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 5 (October 1, 2017): 2451. http://dx.doi.org/10.11591/ijece.v7i5.pp2451-2458.

Повний текст джерела

Анотація:

The paper proposes a design strategy to retain the true nature of the output in the event of occurrence of stuck at faults at the interconnect levels of digital circuits. The procedure endeavours to design a combinational architecture which includes attributes to identify stuck at faults present in the intermediate lines and involves a healing mechanism to redress the same. The simulated fault injection procedure introduces both single as well as multiple stuck-at faults at the interconnect levels of a two level combinational circuit in accordance with the directives of a control signal. The inherent heal facility attached to the formulation enables to reach out the fault free output even in the presence of faults. The Modelsim based simulation results obtained for the Circuit Under Test [CUT] implemented using a Read Only Memory [ROM], proclaim the ability of the system to survive itself from the influence of faults. The comparison made with the traditional Triple Modular Redundancy [TMR] exhibits the superiority of the scheme in terms of fault coverage and area overhead.

Стилі APA, Harvard, Vancouver, ISO та ін.

16

Zhang, L. X., and J. P. Leburton. "Electrostatic cross-talk between quantum dot and quantum point contact charge read-out in few-electron quantum dot circuits." Journal of Applied Physics 96, no. 12 (December 15, 2004): 7352–56. http://dx.doi.org/10.1063/1.1814811.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

17

Gao, R. X., and W. Thelen. "Sensor-Integrated Grinding Balls for on-Line Load Distribution Measurement in Ball Mills." Proceedings of the Institution of Mechanical Engineers, Part B: Journal of Engineering Manufacture 208, no. 3 (August 1994): 183–90. http://dx.doi.org/10.1243/pime_proc_1994_208_077_02.

Повний текст джерела

Анотація:

For the on-line measurement of stress and energy distributions inside ball mills, two types of self-contained, autonomous grinding balls with fully integrated piezo-electric sensors and data-processing electronics are developed and fabricated. The basic model is designed for batchwise experiments on ball mills, where data registered in electronic memories are read out through cable connections to a processing circuit. The improved model contains additional data modulation circuits with a VHF microtransmitter, allowing on-line data retrieval. For the purpose of circuit miniaturization, hybrid and surface mount techniques (SMT) have been utilized. The instrumented balls are identical in size, mass and surface characteristics to the normal grinding balls, with the minimum outer diameter being 40 mm. Systematic experiments have shown that they are fully applicable in a realistic grinding environment where grinding media are presented. In addition to ball mill applications, the developed integration and measuring technique is generally suited for on-line data registration on free-moving objects or other industrial applications where accessibility of the measurand is insufficient.

Стилі APA, Harvard, Vancouver, ISO та ін.

18

Kwon, Dae Woong, Ryoongbin Lee, Sihyun Kim, Hyun-Sun Mo, Dae Hwan Kim, and Byung-Gook Park. "A novel fabrication method for co-integrating ISFET with damage-free sensing oxide and threshold voltage-tunable CMOS read-out circuits." Sensors and Actuators B: Chemical 260 (May 2018): 627–34. http://dx.doi.org/10.1016/j.snb.2017.12.193.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

19

Elangovan, M., and K. Gunavathi. "High Stable and Low Power 8T CNTFET SRAM Cell." Journal of Circuits, Systems and Computers 29, no. 05 (August 2, 2019): 2050080. http://dx.doi.org/10.1142/s0218126620500802.

Повний текст джерела

Анотація:

Designing of Complementary Metal Oxide Semiconductor (CMOS) technology based VLSI circuits in deep submicron range includes many challenges like tremendous increase of leakage power. Design is also easily affected by process variation. The Carbon NanoTube Field Effect Transistor (CNTFET) is an alternative for Metal Oxide Semiconductor Field Effect Transistor (MOSFET) for nanoscale range VLSI circuits design. CNTFET offers best performance than MOSFET. It has high stability and consumes least power. Static Random Access Memory (SRAM) cells play a vital role in cache memory in most of the electronic circuits. In this paper, we have proposed a high stable and low power CNTFET based 8Transistor (8T) SRAM cell. The performance of proposed 8T SRAM cells for nominal chiral value (all CNTFET with [Formula: see text], [Formula: see text]) and Dual chiral value (NCNTFET with [Formula: see text], [Formula: see text] and PCNTFET [Formula: see text], [Formula: see text]) is compared with that of conventional 6T and 8T cells. From the simulation results, it is noted that the proposed structure consumes less power than conventional 6T and 8T cells during read/write operations and gives higher stability during write and hold modes. It consumes higher power than conventional 6T and 8T cells during hold mode and provides lower stability in read mode due to direct contact of bit lines with storage nodes. A comparative analysis of proposed and conventional 8T MOSFET SRAM has been done and the SRAM parameters are tabulated. The simulation is carried out using Stanford University 32[Formula: see text]nm CNTFET model in HSPICE simulation tool.

Стилі APA, Harvard, Vancouver, ISO та ін.

20

Renukarani, S., Bhavana Godavarthi, SK Bia Roshini, and Mohammad Khadir. "A Novel concept on 8-Transistor Dynamic Feedback Control on Static RAM Cell Array." International Journal of Engineering & Technology 7, no. 2.20 (April 18, 2018): 109. http://dx.doi.org/10.14419/ijet.v7i2.20.12185.

Повний текст джерела

Анотація:

A novel idea of 8-Transistor (8T) static random access memory cell with enhanced information stability, sub threshold operation may be outlined. Those prescribed novel built single-ended for dynamic control 8 transistors static RAM (SRAM) cell enhances the static noise margin (SNM) to grater low energy supply. The suggested 8T takes less read and write power supply compared to 6T. Those suggested 8T need higher static noise margin than that from 6T. The portable microprocessor chips need ultralow energy consuming circuits on use battery to more drawn out span. The power utilization might be minimized utilizing non-conventional gadget structures, new circuit topologies, and upgrading the architecture. Although, voltage scaling require of the operation completed over sub threshold for low power consumption, and there will be an inconvenience from exponential decrease in execution. However, to sub threshold regime, that data stability of SRAM cell might a chance to be a amazing issue and worsens for those scaling from claming MOSFET ought to sub-nanometer engineering technology.

Стилі APA, Harvard, Vancouver, ISO та ін.

21

Callegaro, Vinicius, Mayler G. A. Martins, Renato P. Ribas, and André I. Reis. "A Domain-Transformation Approach to Synthesize Read-Polarity-Once Boolean Functions." Journal of Integrated Circuits and Systems 9, no. 1 (December 28, 2014): 60–69. http://dx.doi.org/10.29292/jics.v9i1.389.

Повний текст джерела

Анотація:

Efficient exact factoring algorithms are limited to read-once (RO) functions, where each variable appears exactly once at the final Boolean expression. However, these algorithms present two important constraints: (1) they do not consider incompletely specified Boolean functions (ISFs), and (2) they are not suitable for binate functions. To overcome the first drawback, an algorithm that finds RO expressions for ISF, whenever possible, is proposed. In respect to the second limitation, we propose a domain transformation that splits existing binate variables into two independent unate variables. Such a domain transformation leads to ISFs, which can be efficiently factored by applying the proposed algorithm. The combination of both contributions gives optimal results for a recently proposed broader class of Boolean functions called read-polarity-once (RPO) functions, where each polarity (positive and negative) of a variable appears at most once in the factored form. Experimental results carried out over ISCAS’85 benchmark circuits have shown that RPO functions are significantly more frequent than RO functions.

Стилі APA, Harvard, Vancouver, ISO та ін.

22

Pal, Srijani, Divya S. Salimath, Banusha Chandran, A. Anita Angeline, and V. S. Kanchana Bhaaskaran. "Low Power Memory System Design Using Power Gated SRAM Cell." IOP Conference Series: Materials Science and Engineering 1187, no. 1 (September 1, 2021): 012008. http://dx.doi.org/10.1088/1757-899x/1187/1/012008.

Повний текст джерела

Анотація:

Abstract Static Random-Access Memory (SRAM) is widely used in cache memory, microprocessors, general computing applications and electronic circuits involving ASIC, FPGA and CPLD. The most commonly used SRAM is the 6T SRAM. However, it incurs higher power consumption and degraded signal to noise margin (SNM) during write and read operations. To overcome these shortcomings, a single ended power gated 11T SRAM for low power operation is proposed. The power consumption reduction is achieved using power gating through virtual VSS (VVSS) signal and transmission gates. Due to the introduction of transmission gates, memory cells realize enhanced write margin characteristics as compared to existing technologies. The proposed cell realizes 33.33% lower power consumption and 50% improvement in read SNM as compared to existing SRAM technologies. To study the impact of technology scaling on our proposed design, the work is carried out in Cadence Virtuoso® tool using both 180nm CMOS technology and BPTM 32nm FinFET technology.

Стилі APA, Harvard, Vancouver, ISO та ін.

23

Osouli Tabrizi, Hamed, Abbas Panahi, Saghi Forouhi, Deniz Sadighbayan, Fatemeh Soheili, Mohammad Reza Haji Hosseini Khani, Sebastian Magierowski, and Ebrahim Ghafar-Zadeh. "Oral Cells-On-Chip: Design, Modeling and Experimental Results." Bioengineering 9, no. 5 (May 19, 2022): 218. http://dx.doi.org/10.3390/bioengineering9050218.

Повний текст джерела

Анотація:

Recent advances in periodontal studies have attracted the attention of researchers to the relation between oral cells and gum diseases, which is a real threat to overall human health. Among various microfabrication technologies, Complementary Metal Oxide Semiconductors (CMOSs) enable the development of low-cost integrated sensors and circuits for rapid and accurate assessment of living cells that can be employed for the early detection and control of periodontal diseases. This paper presents a CMOS capacitive sensing platform that can be considered as an alternative for the analysis of salivatory cells such as oral neutrophils. This platform consists of two sensing electrodes connected to a read-out capacitive circuitry designed and fabricated on the same chip using Austria Mikro Systeme (AMS) 0.35 µm CMOS process. A graphical user interface (GUI) was also developed to interact with the capacitive read-out system and the computer to monitor the capacitance changes due to the presence of saliva cells on top of the chip. Thanks to the wide input dynamic range (IDR) of more than 400 femto farad (fF) and high resolution of 416 atto farad (aF), the experimental and simulation results demonstrate the functionality and applicability of the proposed sensor for monitoring cells in a small volume of 1 µL saliva samples. As per these results, the hydrophilic adhesion of oral cells on the chip varies the capacitance of interdigitated electrodes (IDEs). These capacitance changes then give an assessment of the oral cells existing in the sample. In this paper, the simulation and experimental results set a new stage for emerging sensing platforms for testing oral samples.

Стилі APA, Harvard, Vancouver, ISO та ін.

24

Kim, Kyeong-Ah, Chun-Won Byun, Jong-Heon Yang, Kyoung-Ik Cho, Chi-Sun Hwang, and Sung-Min Yoon. "Read-Out Modulation Scheme for the Display Driving Circuits Composed of Nonvolatile Ferroelectric Memory and Oxide–Semiconductor Thin-Film Transistors for Low-Power Consumption." IEEE Transactions on Electron Devices 63, no. 1 (January 2016): 394–401. http://dx.doi.org/10.1109/ted.2015.2501018.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

25

Liza, Nishattasnim, Dylan Murphey, Peizhong Cong, David W. Beggs, Yuihui Lu, and Enrique P. Blair. "Asymmetric, mixed-valence molecules for spectroscopic readout of quantum-dot cellular automata." Nanotechnology 33, no. 11 (December 21, 2021): 115201. http://dx.doi.org/10.1088/1361-6528/ac40c0.

Повний текст джерела

Анотація:

Abstract Mixed-valence compounds may provide molecular devices for an energy-efficient, low-power, general-purpose computing paradigm known as quantum-dot cellular automata (QCA). Multiple redox centers on mixed-valence molecules provide a system of coupled quantum dots. The configuration of mobile charge on a double-quantum-dot (DQD) molecule encodes a bit of classical information robust at room temperature. When arranged in non-homogeneous patterns (circuits) on a substrate, local Coulomb coupling between molecules enables information processing. While single-electron transistors and single-electron boxes could provide low-temperature solutions for reading the state of a ∼1 nm scale molecule, we propose a room-temperature read-out scheme. Here, DQD molecules are designed with slightly dissimilar quantum dots. Ab initio calculations show that the binary device states of an asymmetric molecule have distinct Raman spectra. Additionally, the dots are similar enough that mobile charge is not trapped on either dot, allowing device switching driven by the charge configuration of a neighbor molecule. A technique such as tip-enhanced Raman spectroscopy could be used to detect the state of a circuit comprised of several QCA molecules.

Стилі APA, Harvard, Vancouver, ISO та ін.

26

Ni, Haiyan, Jianping Hu, Huishan Yang, and Haotian Zhu. "Comprehensive Optimization of Dual Threshold Independent-Gate FinFET and SRAM Cells." Active and Passive Electronic Components 2018 (September 19, 2018): 1–10. http://dx.doi.org/10.1155/2018/4512924.

Повний текст джерела

Анотація:

Independent-Gate (IG) FinFET is a promising device in circuit applications due to its two separated gates, which can be used independently. In this paper, we proposed a comprehensive method to optimize the Dual Threshold (DT) IG FinFET devices by carrying out modulations for the gate electrode work function, oxide thickness, and silicon body thickness. Titanium nitride (TiNx) is used as the tunable work function gate electrode for good performances. The thicknesses of the gate oxide and silicon body are swept by TCAD simulations to obtain the appropriate values. The verification simulation of the optimized transistors shows that the DT IG FinFETs can realize merging parallel and series transistors, respectively, and the current characteristics of the transistors are improved significantly. By extracting the BSIM-IMG model parameters, we can simulate the circuits composed of the proposed DT IG FinFET by using HSPICE with BSIM-IMG model. As practical examples, we optimized two novel 7T SRAM cells using DT IG FinFETs. HSPICE simulation results indicate that the new SRAM cells obtain higher write margin and read static noise margin with lower leakage power consumption than the other implementations.

Стилі APA, Harvard, Vancouver, ISO та ін.

27

Lachance-Quirion, Dany, Samuel Piotr Wolski, Yutaka Tabuchi, Shingo Kono, Koji Usami, and Yasunobu Nakamura. "Entanglement-based single-shot detection of a single magnon with a superconducting qubit." Science 367, no. 6476 (January 23, 2020): 425–28. http://dx.doi.org/10.1126/science.aaz9236.

Повний текст джерела

Анотація:

The recent development of hybrid systems based on superconducting circuits provides the possibility of engineering quantum sensors that exploit different degrees of freedom. Quantum magnonics, which aims to control and read out quanta of collective spin excitations in magnetically ordered systems, provides opportunities for advances in both the study of magnetism and the development of quantum technologies. Using a superconducting qubit as a quantum sensor, we report the detection of a single magnon in a millimeter-sized ferrimagnetic crystal with a quantum efficiency of up to 0.71. The detection is based on the entanglement between a magnetostatic mode and the qubit, followed by a single-shot measurement of the qubit state. This proof-of-principle experiment establishes the single-photon detector counterpart for magnonics.

Стилі APA, Harvard, Vancouver, ISO та ін.

28

Gabrielli, A. "Fast Readout Architectures for Large Arrays of Digital Pixels: Examples and Applications." Scientific World Journal 2014 (2014): 1–25. http://dx.doi.org/10.1155/2014/523429.

Повний текст джерела

Анотація:

Modern pixel detectors, particularly those designed and constructed for applications and experiments for high-energy physics, are commonly built implementing general readout architectures, not specifically optimized in terms of speed. High-energy physics experiments use bidimensional matrices of sensitive elements located on a silicon die. Sensors are read out via other integrated circuits bump bonded over the sensor dies. The speed of the readout electronics can significantly increase the overall performance of the system, and so here novel forms of readout architectures are studied and described. These circuits have been investigated in terms of speed and are particularly suited for large monolithic, low-pitch pixel detectors. The idea is to have a small simple structure that may be expanded to fit large matrices without affecting the layout complexity of the chip, while maintaining a reasonably high readout speed. The solutions might be applied to devices for applications not only in physics but also to general-purpose pixel detectors whenever online fast data sparsification is required. The paper presents also simulations on the efficiencies of the systems as proof of concept for the proposed ideas.

Стилі APA, Harvard, Vancouver, ISO та ін.

29

Lee, Bong Wan, Min Seong Seo, Ho Guen Oh, and Chan Yik Park. "High-Speed Wavelength Interrogator of Fiber Bragg Gratings for Capturing Impulsive Strain Waveforms." Advanced Materials Research 123-125 (August 2010): 867–70. http://dx.doi.org/10.4028/www.scientific.net/amr.123-125.867.

Повний текст джерела

Анотація:

It is highly desirable to increase the sampling rate of a fiber Bragg grating (FBG) interrogator in other to sense dynamic strains caused by impulsive acoustic wave. We have developed a wavelength interrogator featuring 100k samplings per second that consists of a solid-state spectrometer, a photodiode array and fully parallel read-out circuits. Central wavelengths on the reflected partial spectra corresponding to FBGs are calculated by the centroid method with the selected groups of the consecutive photodiodes at which each FBG spectrum is imaged. The centroid calculation is simple to be implemented in a field-programmable gate array (FPGA) and fast enough to capture impulsive strain waveforms in real time. Short-term noise on the interrogated wavelengths is estimated to be around 0.5 in terms of stain within the sampling bandwidth.

Стилі APA, Harvard, Vancouver, ISO та ін.

30

Maier, Benjamin D., Luis U. Aguilera, Sven Sahle, Pascal Mutz, Priyata Kalra, Christopher Dächert, Ralf Bartenschlager, Marco Binder, and Ursula Kummer. "Stochastic dynamics of Type-I interferon responses." PLOS Computational Biology 18, no. 10 (October 21, 2022): e1010623. http://dx.doi.org/10.1371/journal.pcbi.1010623.

Повний текст джерела

Анотація:

Interferon (IFN) activates the transcription of several hundred of IFN stimulated genes (ISGs) that constitute a highly effective antiviral defense program. Cell-to-cell variability in the induction of ISGs is well documented, but its source and effects are not completely understood. The molecular mechanisms behind this heterogeneity have been related to randomness in molecular events taking place during the JAK-STAT signaling pathway. Here, we study the sources of variability in the induction of the IFN-alpha response by using MxA and IFIT1 activation as read-out. To this end, we integrate time-resolved flow cytometry data and stochastic modeling of the JAK-STAT signaling pathway. The complexity of the IFN response was matched by fitting probability distributions to time-course flow cytometry snapshots. Both, experimental data and simulations confirmed that the MxA and IFIT1 induction circuits generate graded responses rather than all-or-none responses. Subsequently, we quantify the size of the intrinsic variability at different steps in the pathway. We found that stochastic effects are transiently strong during the ligand-receptor activation steps and the formation of the ISGF3 complex, but negligible for the final induction of the studied ISGs. We conclude that the JAK-STAT signaling pathway is a robust biological circuit that efficiently transmits information under stochastic environments.

Стилі APA, Harvard, Vancouver, ISO та ін.

31

FITRIO, DAVID, SUHARDI TJOA, ANAND MOHAN, RONNY VELJANOVSKI, ANDREW BERRY, and GORAN PANJKOVIC. "A CMOS ANALOG INTEGRATED CIRCUIT FOR PIXEL X-RAY DETECTOR." Journal of Circuits, Systems and Computers 20, no. 01 (February 2011): 71–87. http://dx.doi.org/10.1142/s0218126611007086.

Повний текст джерела

Анотація:

A front-end read-out application specific integrated circuit (ASIC) for a multichannel pixel X-Ray detector system has been fabricated and tested. The chip provides signal amplification for pixelated compound semiconductors such as Cadmium Telluride ( CdTe ) and Cadmium Zinc Telluride ( CZT ) with either 1 mm or 200 μm pitch. Both the detector (compound semiconductor) and ASIC are combined to target future research applicable to spectroscopic imaging in high intensity X-Ray biomedical detector systems. The ASIC was fabricated in a 0.35 μm process by Austria Microsystems and consists of 32 channels, where each channel contains a charge-sensitive amplifier, a pulse shaper and two further stages of amplification providing an overall gain of 1 mV per kilo electron volt (keV) for photons within the energy range of 30–120 keV. The preamplifier and shaper circuits are designed for both positive and negative charge collection (electrons and holes) produced by the CdTe or CZT detectors. The ASIC's shaper has been designed with a time constant of 100 ns to allow operation at photon rate events above 1 Million photons per pixel per second. The design and characterization of the readout chip will be discussed in this paper presenting results from both the simulated and the fabricated chip.

Стилі APA, Harvard, Vancouver, ISO та ін.

32

Joo, Shin, Jung, Cha, Nam, and Kwon. "Oxide Thin-Film Transistor-Based Vertically Stacked Complementary Inverter for Logic and Photo-Sensor Operations." Materials 12, no. 23 (November 20, 2019): 3815. http://dx.doi.org/10.3390/ma12233815.

Повний текст джерела

Анотація:

Numerous studies have addressed the utilization of oxide thin-film transistor (TFT)-based complementary logic circuits that are based on two-dimensional (2D) planar structures. However, there are fundamental limits to the 2D planar structured complementary logic circuits, such as a large dimension and a large parasitic resistance. This work demonstrated a vertically stacked three-dimensional complementary inverter composed of a p-channel tin monoxide (SnO) TFT and an n-channel indium-gallium-zinc oxide (IGZO) TFT. A bottom-gate p-channel SnO TFT was formed on the top-gate n-channel IGZO TFT with a shared common gate electrode. The fabricated vertically stacked complementary inverter exhibited full swing characteristics with a voltage gain of ~33.6, a high noise margin of 3.13 V, and a low noise margin of 3.16 V at a supplied voltage of 10 V. The achieved voltage gain of the fabricated complementary inverter was higher than that of the vertically stacked complementary inverters composed of other oxide TFTs in previous works. In addition, we showed that the vertically stacked complementary inverter exhibited excellent visible-light photoresponse. This indicates that the oxide TFT-based vertically stacked complementary inverter can be used as a sensitive photo-sensor operating in the visible spectral range with the voltage read-out scheme.

Стилі APA, Harvard, Vancouver, ISO та ін.

33

Strube-Bloss, Martin F., Martin P. Nawrot, and Randolf Menzel. "Neural correlates of side-specific odour memory in mushroom body output neurons." Proceedings of the Royal Society B: Biological Sciences 283, no. 1844 (December 14, 2016): 20161270. http://dx.doi.org/10.1098/rspb.2016.1270.

Повний текст джерела

Анотація:

Humans and other mammals as well as honeybees learn a unilateral association between an olfactory stimulus presented to one side and a reward. In all of them, the learned association can be behaviourally retrieved via contralateral stimulation, suggesting inter-hemispheric communication. However, the underlying neuronal circuits are largely unknown and neural correlates of across-brain-side plasticity have yet not been demonstrated. We report neural plasticity that reflects lateral integration after side-specific odour reward conditioning. Mushroom body output neurons that did not respond initially to contralateral olfactory stimulation developed a unique and stable representation of the rewarded compound stimulus (side and odour) predicting its value during memory retention. The encoding of the reward-associated compound stimulus is delayed by about 40 ms compared with unrewarded neural activity, indicating an increased computation time for the read-out after lateral integration.

Стилі APA, Harvard, Vancouver, ISO та ін.

34

Karami Horestani, Fatemeh, Zahra Karami Horastani, and Niclas Björsell. "A Band-Pass Instrumentation Amplifier Based on a Differential Voltage Current Conveyor for Biomedical Signal Recording Applications." Electronics 11, no. 7 (March 30, 2022): 1087. http://dx.doi.org/10.3390/electronics11071087.

Повний текст джерела

Анотація:

Recently, due to their abundant benefits, current-mode instrumentation amplifiers have received considerable attention in medical instrumentation and read-out circuit for biosensors. This paper is focused on the design of current-mode instrumentation amplifiers for portable, implantable, and wearable electrocardiography and electroencephalography applications. To this end, a CMOS differential voltage second-generation current conveyor (DVCCII) based on a linear transconductor is presented. A new band-pass instrumentation amplifier, based on the designed DVCCII, is also implemented in this paper. The concept of the proposed differential voltage current conveyor and instrumentation amplifier is validated numerically and their predicted performance is presented. The simulation results of the presented circuits were tested for 0.18 μm TSMC CMOS technology in a post layout simulation level using the Cadence Virtuoso tool with a ±0.9 V power supply, and demonstrated that the designed DVCCII has a wide dynamic range of ±400 mV and ±0.85 mA and a power consumption of 148 μW. The layout of the DVCCII circuit occupies a total area of 0.378 μm2. It is shown that the designed DVCCII benefits from good linearity over a wide range of input signals and provides a low input impedance at terminal X. Two versions of the proposed band-pass instrumentation amplifier using pseudo resistances were designed with different specifications for two different applications, namely for EEG and ECG signals. Numerical analyses of both designs show proper outputs and frequency responses by eliminating the undesired artifact and DC component of the EEG and ECG input signals.

Стилі APA, Harvard, Vancouver, ISO та ін.

35

Ye, Jing, Menno P. Witter, May-Britt Moser, and Edvard I. Moser. "Entorhinal fast-spiking speed cells project to the hippocampus." Proceedings of the National Academy of Sciences 115, no. 7 (January 31, 2018): E1627—E1636. http://dx.doi.org/10.1073/pnas.1720855115.

Повний текст джерела

Анотація:

The mammalian positioning system contains a variety of functionally specialized cells in the medial entorhinal cortex (MEC) and the hippocampus. In order for cells in these systems to dynamically update representations in a way that reflects ongoing movement in the environment, they must be able to read out the current speed of the animal. Speed is encoded by speed-responsive cells in both MEC and hippocampus, but the relationship between the two populations has not been determined. We show here that many entorhinal speed cells are fast-spiking putative GABAergic neurons. Using retrograde viral labeling from the hippocampus, we find that a subset of these fast-spiking MEC speed cells project directly to hippocampal areas. This projection contains parvalbumin (PV) but not somatostatin (SOM)-immunopositive cells. The data point to PV-expressing GABAergic projection neurons in MEC as a source for widespread speed modulation and temporal synchronization in entorhinal–hippocampal circuits for place representation.

Стилі APA, Harvard, Vancouver, ISO та ін.

36

Li, Lunfu. "The Promotion of Rural Lodging Development by a Comprehensive Evaluation Model of Artificial Intelligence Based on Wireless Network." Mobile Information Systems 2022 (March 16, 2022): 1–10. http://dx.doi.org/10.1155/2022/7157775.

Повний текст джерела

Анотація:

Intelligent scenic planning and management attempt to take advantage of the discipline in the field of artificial intelligence, to explore new roles and models for planning and decision making with the help of machine learning in academic research and to build a complete scenic intelligent management system. Labour costs and energy costs account for a large share of the operating costs of B&Bs. In order to increase revenue while reducing costs and energy losses, this paper designs an unattended intelligent management system for B&Bs. Based on data mining technology, a large amount of B&B operation data is obtained using a crawler program to provide reference to assist B&B business owners in decision making; using wireless RFID technology, the RSSI value of the corresponding tag is read by a reader to detect changes in the location of the human body, making check-in and check-out management more efficient; the driving circuits of lighting, curtains, and air conditioners are controlled by an STM32 control module.

Стилі APA, Harvard, Vancouver, ISO та ін.

37

Elangovan, M., and K. Gunavathi. "High Stable and Low Power 10T CNTFET SRAM Cell." Journal of Circuits, Systems and Computers 29, no. 10 (December 19, 2019): 2050158. http://dx.doi.org/10.1142/s0218126620501583.

Повний текст джерела

Анотація:

The ultimate aim of a memory designer is to design a memory cell which could consume low power with high data stability in the deep nanoscale range. The implementation of Very Large-Scale Integration (VLSI) circuits using MOSFETs in nanoscale range faces many issues such as increasing of leakage power and second-order effects that are easily affected by the PVT variation. Hence, it is essential to find the best alternative of MOSFET for deep submicron design. The Carbon Nanotube Field Effect Transistor (CNTFET) can eradicate all the demerits of MOSFET and be the best replacement of MOSFET for nanoscale range design. In this paper, a 10T CNTFET Static Random Access Memory (SRAM) cell is proposed. The power consumption and Static Noise Margin (SNM) are analyzed. The power consumption and stable performance of the proposed 10T CNTFET SRAM cell are compared with that of conventional 10T CNTFET SRAM cell. The power and stability analyses of the proposed 10T and conventional 10T CNTFET SRAM cells are carried out for the CNTFET parameters such as pitch and chiral vector ([Formula: see text]). The power and SNM analyses are carried out for [Formula: see text]20% variation of oxide thickness (Hox), different dielectric constant (Kox). The supply voltage varies from 0.9[Formula: see text]V to 0.6[Formula: see text]V and temperature varies from 27∘C to 125∘C. The simulation results show that the proposed 10T CNTFET SRAM cell consumes lesser power than conventional 10T CNTFET SRAM cell during the write, hold and read modes. The write, hold and read stability of the proposed 10T CNTFET SRAM cell are higher as compared with that of conventional 10T CNTFET SRAM. The conventional and proposed 10T SRAM cells are also implemented using MOSFET. The stability and power performance of proposed 10T SRAM cell is also as good as conventional 10T SRAM for MOSFET implementation. The proposed 10T SRAM cell consumes lesser power and gives higher stability than conventional 10T SRAM cell in both CNTFET and MOSFET implementation. The simulation is carried out using Stanford University 32[Formula: see text]nm CNTFET model in HSPICE simulation tool.

Стилі APA, Harvard, Vancouver, ISO та ін.

38

Abdul Aziz, 'Umar, Siti Fauziah Toha, Rabiatuladawiah Abu Hanifah, and Nurul Fadzlin Hasbullah. "Intelligent read-out circuit for space radiation detection." Indonesian Journal of Electrical Engineering and Computer Science 22, no. 3 (June 1, 2021): 1411. http://dx.doi.org/10.11591/ijeecs.v22.i3.pp1411-1418.

Повний текст джерела

Анотація:

In the design of the satellite system, space radiation is among the important factors that need to be taken care of as it may contribute to system failure. This research aims to design and implement an intelligent read-out circuit to detect the level of radiation. It has the capability to measure the level of radiation. The capability of the designed device to measure the level of radiation and also the type of radiation exposure are the key components to be considered in the design of the system. In this research, the intelligent read-out circuit has been successfully designed and tested to detect the level of radiation. The results show the capability of the system to measure the level of radiation and determine the status of radiation level using both visual and sound indicators. The designed system is able to determine the level of radiation in a short time and strengthen by the danger-alert mechanism present in the system.

Стилі APA, Harvard, Vancouver, ISO та ін.

39

Carminati, M., G. Ferrari, F. Guagliardo, and M. Sampietro. "ZeptoFarad resolution CMOS read-out circuit for nanosensors." Procedia Engineering 5 (2010): 1123–26. http://dx.doi.org/10.1016/j.proeng.2010.09.308.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

40

Zhu, Kaiqiang, Qingfeng Ding, Tong Mao, Xiuming Tang, Yu Xiao, Hua Qin, and Houjun Sun. "Experimental Realization of 16-Pixel Terahertz Receiver Front-End Based on Bulk Silicon MEMS Power Divider and AlGaN/GaN HEMT Linear Detector Array." Electronics 11, no. 15 (July 23, 2022): 2305. http://dx.doi.org/10.3390/electronics11152305.

Повний текст джерела

Анотація:

A 16-pixel terahertz (THz) receiver front-end working at room temperature was designed, built, and measured in this paper. The designed receiver front-end is based on the antenna-coupled AlGaN/GaN high-electron-mobility transistor (HEMT) THz linear detector array (TeraLDA) and a 16-way THz power divider. The local oscillator (LO) signal is divided by the power divider into 16 ways and transmits to the TeraLDA. Each detector contains a planar unified antenna printed on a 150 μm-thick sapphire substrate and a transistor fabricated on AlGaN/GaN heterostructure. There are 16 silicon hemispheric lenses located on the TeraLDA to increase the responsivity of the TeraLDA. The focus of each lens is aligned in the center of the TeraLDA pixels. Depending on different read out circuits, the receiver front-end could work in homodyne and heterodyne modes. The 16-way power divider is a four-stage power divider that consists of fifteen same 2-way dividers, and was fabricated by bulk silicon microelectromechanical systems (MEMS) technology to achieve low insertion loss (IL). This designed receiver front-end could be a key component of a THz coherent focal plane imaging radar system, that may play a crucial role in nondestructive 3D imaging application.

Стилі APA, Harvard, Vancouver, ISO та ін.

41

DIOSZEGI, ISTVAN, GRAHAM C. SMITH, NEIL A. SCHAKNOWSKI, BO YU, JACK FRIED, CYNTHIA SALWEN, PETER E. VANIER, and LEON FORMAN. "CODED APERTURE THERMAL NEUTRON CAMERA WITH ASIC-BASED PAD READOUT." International Journal of Modern Physics: Conference Series 27 (January 2014): 1460139. http://dx.doi.org/10.1142/s2010194514601392.

Повний текст джерела

Анотація:

A new generation of coded aperture neutron imagers is being developed at Brookhaven National Laboratory. The detector of the camera is a position sensitive thermal neutron chamber. The new device is a 3 He -filled ionization chamber, which uses only anode and cathode planes. The anode is composed of an array of individual pads. The charge is collected on each of the individual 5 × 5 mm2 anode pads, (48 × 48 in total corresponding to a 24 × 24 cm2 sensitive area) and read out by application specific integrated circuits. The new design has several advantages for the field of coded aperture applications compared to the previous generation of wire-grid based neutron detectors. Among these are the rugged design, lighter weight and use of non-flammable stopping gas. The pad-based readout is event by event, thus capable of high count rates, and can perform data analysis and imaging on an event by event basis. The spatial resolution of the detector can be better than the pixel size by using charge sharing between adjacent pads. In this paper, we will report on the development and performance of the new, prototype pad-based neutron camera and present the first pad-based coded aperture images of thermalized neutron sources.

Стилі APA, Harvard, Vancouver, ISO та ін.

42

Ferreira, Pietro M., José Gabriel R. C. Gomes, and Antonio Petraglia. "Current mode read-out circuit for InGaAs photodiode applications." Microelectronics Journal 41, no. 7 (July 2010): 388–94. http://dx.doi.org/10.1016/j.mejo.2010.04.010.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

43

Ravezzi, L., and P. Conci. "ISFET sensor coupled with CMOS read-out circuit microsystem." Electronics Letters 34, no. 23 (1998): 2234. http://dx.doi.org/10.1049/el:19981532.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

44

Ngo, Nguyen Hoai, Kazuhiro Shimonomura, Taeko Ando, Takayoshi Shimura, Heiji Watanabe, Kohsei Takehara, Anh Quang Nguyen, Edoardo Charbon, and Takeharu Goji Etoh. "A Pixel Design of a Branching Ultra-Highspeed Image Sensor." Sensors 21, no. 7 (April 3, 2021): 2506. http://dx.doi.org/10.3390/s21072506.

Повний текст джерела

Анотація:

A burst image sensor named Hanabi, meaning fireworks in Japanese, includes a branching CCD and multiple CMOS readout circuits. The sensor is backside-illuminated with a light/charge guide pipe to minimize the temporal resolution by suppressing the horizontal motion of signal carriers. On the front side, the pixel has a guide gate at the center, branching to six first-branching gates, each bifurcating to second-branching gates, and finally connected to 12 (=6×2) floating diffusions. The signals are either read out after an image capture operation to replay 12 to 48 consecutive images, or continuously transferred to a memory chip stacked on the front side of the sensor chip and converted to digital signals. A CCD burst image sensor enables a noiseless signal transfer from a photodiode to the in-situ storage even at very high frame rates. However, the pixel count conflicts with the frame count due to the large pixel size for the relatively large in-pixel CCD memory elements. A CMOS burst image sensor can use small trench-type capacitors for memory elements, instead of CCD channels. However, the transfer noise from a floating diffusion to the memory element increases in proportion to the square root of the frame rate. The Hanabi chip overcomes the compromise between these pros and cons.

Стилі APA, Harvard, Vancouver, ISO та ін.

45

Tawfik, Hani H., Karim Allidina, Frederic Nabki, and Mourad N. El-Gamal. "Dual-Level Capacitive Micromachined Uncooled Thermal Detector." Sensors 19, no. 24 (December 10, 2019): 5434. http://dx.doi.org/10.3390/s19245434.

Повний текст джерела

Анотація:

This paper presents a novel dual-level capacitive microcantilever-based thermal detector that is implemented in the commercial surface micromachined PolyMUMPs technology. The proposed design is implemented side-by-side with four different single-level designs to enable a design-to-design performance comparison. The dual-level design exhibits a rate of capacitance change per degree Celsius that is over three times higher than that of the single-level designs and has a base capacitance that is more than twice as large. These improvements are achieved because the dual-level architecture allows a 100% electrode-to-detector area, while single-level designs are shown to suffer from an inherent trade-off between sensitivity and base capacitance. In single-level designs, either the number of the bimorph beams or the capacitance electrode can be increased for a given sensor area. The former is needed for a longer effective length of the bimorph for higher thermomechanical sensitivity (i.e., larger tilting angels per degree Celsius), while the latter is desired to relax the read-out integrated-circuits requirements. This thermomechanical response-to-initial capacitance trade-off is mitigated by the dual-level design, which dedicates one structural layer to serve as the upper electrode of the detector, while the other layer contains as many bimorph beams as desired, independently of the former’s area.

Стилі APA, Harvard, Vancouver, ISO та ін.

46

Yildirim, Omer, Ibrahim Bozyel, Kubra Saka, Temel Kayikcioglu, and Dincer Gokcen. "Polydimethylsiloxane‐based capacitive motion sensor and its read‐out circuit." International Journal of Circuit Theory and Applications 49, no. 7 (April 5, 2021): 2147–57. http://dx.doi.org/10.1002/cta.3009.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

47

Huang, Gongxing, Rongshan Wei, Wanjin Wang, and Qunchao Chen. "A low power read-out integrated circuit for multiple sensors." IEICE Electronics Express 17, no. 17 (September 10, 2020): 20200199. http://dx.doi.org/10.1587/elex.17.20200199.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

48

Strache, S., R. Wunderlich, D. Droste, and S. Heinen. "MATLAB/simulink model of a MEMS accelerometer read-out circuit." Procedia Engineering 5 (2010): 508–11. http://dx.doi.org/10.1016/j.proeng.2010.09.158.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

49

Raith, B. "A self-adjusting delay circuit for pixel read-out chips." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 395, no. 3 (August 1997): 324–27. http://dx.doi.org/10.1016/s0168-9002(97)00614-1.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

50

Kurtz, N., and O. Rolland. "An analog low noise read-out circuit for semiconductor detectors." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 313, no. 1-2 (March 1992): 303–7. http://dx.doi.org/10.1016/0168-9002(92)90110-p.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Статті в журналах з теми "Read-Out Circuits"

Оформте джерело за APA, MLA, Chicago, Harvard та іншими стилями