Дисертації з теми "Programmable logic integrated circuits"
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1
Hadjinicolaou, M. G. "Synthesis of programmable logic arrays." Thesis, Brunel University, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.371168.
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2
Davis, Justin S. "An FPGA-based digital logic core for ATE support and embedded test applications." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/15639.
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3
Moon, Gyo Sik. "An Algorithm for the PLA Equivalence Problem." Thesis, University of North Texas, 1995. https://digital.library.unt.edu/ark:/67531/metadc278922/.
Повний текст джерелаАнотація:
The Programmable Logic Array (PLA) has been widely used in the design of VLSI circuits and systems because of its regularity, flexibility, and simplicity. The equivalence problem is typically to verify that the final description of a circuit is functionally equivalent to its initial description. Verifying the functional equivalence of two descriptions is equivalent to proving their logical equivalence. This problem of pure logic is essential to circuit design. The most widely used technique to solve the problem is based on Binary Decision Diagram or BDD, proposed by Bryant in 1986. Unfortunately, BDD requires too much time and space to represent moderately large circuits for equivalence testing. We design and implement a new algorithm called the Cover-Merge Algorithm for the equivalence problem based on a divide-and-conquer strategy using the concept of cover and a derivational method. We prove that the algorithm is sound and complete. Because of the NP-completeness of the problem, we emphasize simplifications to reduce the search space or to avoid redundant computations. Simplification techniques are incorporated into the algorithm as an essential part to speed up the the derivation process. Two different sets of heuristics are developed for two opposite goals: one for the proof of equivalence and the other for its disproof. Experiments on a large scale of data have shown that big speed-ups can be achieved by prioritizing the heuristics and by choosing the most favorable one at each iteration of the Algorithm. Results are compared with those for BDD on standard benchmark problems as well as on random PLAs to perform an unbiased way of testing algorithms. It has been shown that the Cover-Merge Algorithm outperforms BDD in nearly all problem instances in terms of time and space. The algorithm has demonstrated fairly stabilized and practical performances especially for big PLAs under a wide range of conditions, while BDD shows poor performance because of its memory greedy representation scheme without adequate simplification.
4
Tan, Chong Guan. "Another approach to PLA folding." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=66054.
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5
Воргуль, О. В., І. В. Свид, О. В. Зубков, and В. В. Семенець. "Teaching microcontrollers and FPGAs in Quarantine from Coronavirus: Challenges and Prospects." Thesis, MC&FPGA, 2020. https://mcfpga.nure.ua/conf/2020-mcfpga/10-35598-mcfpga-2020-005.
Повний текст джерелаАнотація:
Modern equipment is becoming more and more complex and education establishment must keep up with it and offer its contribution to the overall progress. The goal of this work is to find the way how to survive on self-isolation and teach microcontrollers and FPGAs. What challenges need to be overcome and what prospects may open up.
6
Chadha, Vishal. "Design and Implementation of a Second Generation Logic Cluster for Multi-Technology Field Programmable Gate Arrays." University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1126539992.
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7
Draier, Benny. "Test vector generation and compaction for easily testable PLAs." Thesis, McGill University, 1988. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63970.
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8
Wan, Wei. "A New Approach to the Decomposition of Incompletely Specified Functions Based on Graph Coloring and Local Transformation and Its Application to FPGA Mapping." PDXScholar, 1992. https://pdxscholar.library.pdx.edu/open_access_etds/4698.
Повний текст джерелаАнотація:
The thesis presents a new approach to the decomposition of incompletely specified functions and its application to FPGA (Field Programmable Gate Array) mapping. Five methods: Variable Partitioning, Graph Coloring, Bond Set Encoding, CLB Reusing and Local Transformation are developed in order to efficiently perform decomposition and FPGA (Lookup-Table based FPGA) mapping. 1) Variable Partitioning is a high quality hemistic method used to find the "best" partitions, avoiding the very time consuming testing of all possible decomposition charts, which is impractical when there are many input variables in the input function. 2) Graph Coloring is another high quality heuristic\ used to perform the quasi-optimum don't care assignment, making the program possible to accept incompletely specified function and perform a quasi-optimum assignment to the unspecified part of the function. 3) Bond Set Encoding algorithm is used to simplify the decomposed blocks during the process of decomposition. 4) CLB Reusing algorithm is used to reduce the number of CLBs used in the final mapped circuit. 5) Local Transformation concept is introduced to transform nondecomposable functions into decomposable ones, thus making it possible to apply decomposition method to FPGA mapping. All the above developed methods are incorporated into a program named TRADE, which performs global optimization over the input functions. While most of the existing methods recursively perform local optimization over some kinds of network-like graphs, and few of them can handle incompletely specified functions. Cube calculus is used in the TRADE program, the operations are global and very fast. A short description of the TRADE program and the evaluation of the results are provided at the_ end of the thesis. For many benchmarks the TRADE program gives better results than any program published in the literature.
9
Perez, Segovia Tomás. "Paola : un système d'optimisation topologique de PLA." Grenoble INPG, 1985. http://tel.archives-ouvertes.fr/tel-00316330.
Повний текст джерелаАнотація:
Lors de la conception des circuits intégrés VLSI, les Réseaux Logiques Programmables (P. L. A. ) permettent le dessin automatique des masques à partir d'une description logique. La surface occupée par ces PLAs peut, dans certains cas, s'avérer prohibitive; d'où l'intérêt des méthodes d'optimisation topologique de ceux-ci. Après avoir défini les différentes représentations possibles des PLAs, on présente l'état en ce qui concerne l'optimisation topologique des PLAs. La méthode des «Lignes Brisées» est ensuite détaillée en insistant sur les heuristiques choisies ainsi que sur les interactions qui existent entre l'étape d'optimisation et l'étape de tracé des connexions internes. On termine par une présentation globale du système PAOLA d'optimisation topologique et dessin de PLAs
10
Nguyen, Loc Bao. "Logic design using programmable logic devices." PDXScholar, 1988. https://pdxscholar.library.pdx.edu/open_access_etds/4103.
Повний текст джерелаАнотація:
The Programmable Logic Devices, PLO, have caused a major impact in logic design of digital systems in this decade. For instance, a twenty pin PLO device can replace from three hundreds to six hundreds Transistor Transistor Logic gates, which people have designed with since the 60s. Therefore, by using PLD devices, designers can squeeze more features, reduce chip counts, reduce power consumption, and enhance the reliability of the digital systems.
This thesis covers the most important aspects of logic design using PLD devices. They are Logic Minimization and State Assignment. In addition, the thesis also covers a seldomly used but very useful design style, Self-Synchronized Circuits.
The thesis introduces a new method to minimize Two-Level Boolean Functions using Graph Coloring Algorithms and the result is very encouraging. The raw speed of the coloring algorithms is as fast as the Espresso, the industry standard minimizer from Berkeley, and the solution is equally good.
The thesis also introduces a rule-based state assignment method which gives equal or better solutions than STASH (an Intel Automatic CAD tool) by as much as twenty percent.
One of the problems with Self-Synchronized circuits is that it takes many extra components to implement the circuit. The thesis shows how it can be designed using PLD devices and also suggests the idea of a Clock Chip to reduce the chip count to make the design style more attractive.
11
Dandache, Abbas. "Conception de PLA CMOS." Phd thesis, Grenoble 2 : ANRT, 1986. http://catalogue.bnf.fr/ark:/12148/cb37596962j.
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Williams, Ryan Daniel. "Photonic integrated circuits for optical logic applications." Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/42025.
Повний текст джерелаАнотація:
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2007.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Includes bibliographical references.
The optical logic unit cell is the photonic analog to transistor-transistor logic in electronic devices. Active devices such as InP-based semiconductor optical amplifiers (SOA) emitting at 1550 nm are vertically integrated with passive waveguides using the asymmetric twin waveguide technique and the SOAs are placed in a Mach-Zehnder interferometer (MZI) configuration. By sending in high-intensity pulses, the gain characteristics, phase-shifting, and refractive indices of the SOA can be altered, creating constructive or deconstructive interference at the MZI output. Boolean logic and wavelength conversion can be achieved using this technique, building blocks for optical switching and signal regeneration. The fabrication of these devices is complex and the fabrication of two generations of devices is described in this thesis, including optimization of the mask design, photolithography, etching, and backside processing techniques. Testing and characterization of the active and passive components is also reported, confirming gain and emission at 1550 nm for the SOAs, as well as verifying evanescent coupling between the active and passive waveguides. In addition to the vertical integration of photonic waveguides, Esaki tunnel junctions are investigated for vertical electronic integration. Quantum dot formation and growth via molecular beam epitaxy is investigated for emission at the technologically important wavelength of 1310 nm. The effect of indium incorporation on tunnel junctions is investigated. The tunnel junctions are used to epitaxially link multiple quantum dot active regions in series and lasers are designed, fabricated, and tested.
by Ryan Daniel Williams.
Ph.D.
13
Belhadj, Mohamed Hichem. "Spécification et synthèse de systèmes à controle intensif." Grenoble INPG, 1996. http://www.theses.fr/1996INPG0084.
Повний текст джерелаАнотація:
La realisation avec succes de nouveaux produits fiables, performants et peu couteux est le resume des defis actuels du marche de l'electronique. Relever ces defis passe par un bon choix des moyens de modelisation et de specification et par l'utilisation d'outils specifiques aux applications visees et aux technologies cibles. Cette these propose quelques elements de reponse pour la specification et la synthese des systemes a controle intensif sur les technologies programmables du type fpga et cpld. Les aspects de specification etudies sont relatifs aux modeles abstraits, aux langages de description et aux outils graphiques. Outre l'introduction d'un nouveau modele de description des controleurs communicants, des comparaisons fondees sur les concepts fondamentaux de la modelisation, i. E. La hierarchie, la modularite, la concurrence, la synchronisation etc. , sont suggerees. Des flots de synthese orientes applications dominees par le controle et specifiques aux technologies ciblees sont introduits. Une des contributions de cette these est la recherche systematique de moyens efficaces pour faciliter l'exploration de l'espace des solutions. Dans le cadre de la synthese des controleurs une strategie de choix du codage des etats est presentee. Elle est fondee sur une caracterisation originale des codages, des technologies cibles et de la complexite des controleurs consideres. Enfin, des problemes ouverts sont soulignes et des axes de recherche fondamentale et appliquee a explorer sont proposes.
14
Ben, Dhia Arwa. "Durcissement de circuits logiques reconfigurables." Thesis, Paris, ENST, 2014. http://www.theses.fr/2014ENST0068/document.
Повний текст джерелаАнотація:
Avec les réductions d'échelle, les circuits électroniques deviennent de plus en plus petits, plus performants, consommant moins de puissance, mais aussi moins fiables. En effet, la fiabilité s'est récemment érigée en défi majeur dans l'industrie micro-électronique, devenant un critère de conception important, au même titre que la surface, la consommation de puissance et la vitesse. Par exemple, les défauts physiques dus aux imperfections dans le procédé de fabrication ont été observés plus fréquemment, affectant ainsi le rendement des circuits. Par ailleurs, les circuits nano-métriques deviennent pendant leur durée de vie plus vulnérables aux rayonnements ionisants, ce qui cause des fautes transitoires. Les défauts de fabrication, aussi bien que les fautes transitoires, diminuent la fiabilité des circuits intégrés. En avançant dans les nœuds technologiques, les circuits logiques programmables de type FPGA sont les premiers à entrer sur le marché, grâce à leur faible coût de développement et leur flexibilité qui leur permet d'être utilisés pour n'importe quelle application. Les FPGA possèdent des caractéristiques attrayantes, notamment pour les applications spatiales et aéronautiques, où la reconfigurabilité, les hautes performances et la faible consommation de puissance peuvent être exploitées pour développer des systèmes innovants. Néanmoins, les missions ont lieu dans un environnement rude, riche en radiations pouvant produire des erreurs soft dans les circuits électroniques. Ceci montre l'importance de la fiabilité des FPGA en tant que critère de conception dans les applications critiques. La plupart des FPGA commerciaux ont une architecture matricielle et leurs blocs logiques sont regroupés en clusters. Ainsi, cette thèse s'intéresse à la tolérance aux fautes des blocs de base ( blocs logiques élémentaires (BLE) et boîtes d'interconnexion ) dans un FPGA de type « matrice de clusters ». Dans le but d'améliorer la fiabilité de ces blocs, il est impératif de pouvoir d'abord l'évaluer, pour ensuite sélectionner la bonne technique de durcissement selon le budget mis à disposition. C'est bien le plan principal de cette thèse. Elle a essentiellement deux objectifs : (a) analyser la tolérance aux fautes des blocs de base dans un FPGA de type « matrice de clusters », et identifier les composants les plus vulnérables. (b) proposer des méthodes de durcissement à différents niveaux de granularité, en fonction du budget de durcissement. En ce qui concerne le premier objectif, une méthodologie pour évaluer la fiabilité du cluster a été proposée. Cette méthodologie emploie une méthode analytique déjà existante pour évaluer la fiabilité des circuits logiques combinatoires. La même méthode est utilisée pour identifier les blocs les plus éligibles au durcissement. Quant au deuxième objectif, des techniques de durcissement ont été proposées aux niveaux multiplexeur et transistor. Au niveau multiplexeur, deux solutions de durcissement ont été présentées. La première solution a recours à la redondance spatiale et concerne la structure du bloc logique. Une nouvelle architecture de BLE baptisée « Butterfly » est introduite. Elle a été comparée avec d'autres architectures de BLE en termes de fiabilité et de surcoût. La deuxième solution de durcissement est une technique dite « sans redondance ». Elle est basée sur une synthèse intelligente qui consiste à chercher la structure la plus fiable parmi toutes celles proposées dans la librairie du fondeur, avant d'utiliser directement de la redondance. Ensuite, au niveau transistor, de nouvelles architectures de multiplexeur, à sortie unique ou différentielles, ont été proposées. Elles ont été comparées à d'autres assemblages différents de transistors, selon des métriques de conception appropriéesAs feature sizes scale down to nano-design level, electronic devices have become smaller, more performant, less power-onsuming, but also less reliable. Indeed, reliability has arisen as a serious challenge in nowadays’ microelectronics industry and as an important design criterion, along with area, performance and power consumption. For instance, physical defects due to imperfections in the manufacturing process have been observed more frequently, impacting the yield. Besides, nanometric circuits have become more vulnerable during their lifetime to ionizing radiation which causes transient faults. Both manufacturing defects and transient faults contribute to decreasing reliability of integrated circuits. When moving to a new technology node, Field Programmable Gate Arrays (FPGAs) are the first coming into the market, thanks to their low development and Non-Recurring Engineering (NRE) costs and their flexibility to be used for any application. FPGAs have especially attractive characteristics for space and avionic applications, where reconfigurability, high performance and low-power consumption can be fruitfully used to develop innovative systems. However, missions take place in a harsh environment, rich in radiation, which can induce soft errors within electronic devices. This shows the importance of FPGA reliability as a design criterion in safety and critical applications. Most of commercial FPGAs have a mesh architecture and their logic blocks are gathered into clusters. Therefore, this thesis deals with the fault tolerance of basic blocks (clusters and switch boxes) in a mesh of clusters FPGA. These blocks are mainly made up of multiplexers. In order to improve their reliability, it is imperative to be able to assess it first, then select the proper hardening approach according to the available budget. So, this is the main outline in which this thesis is conceived. Its goals are twofold: (a) analyze the fault tolerance of the basic blocks in a mesh of clusters FPGA, and point out the most vulnerable components (b) propose hardening schemes at different granularity levels, depending on the hardening budget. As far as the first goal is concerned, a methodology to evaluate the reliability of the cluster is proposed. This methodology uses an existent analytical method for reliability computation of combinational circuits. The same method is employed to identify the worthiest components to be hardened. Regarding the second goal, hardening techniques are proposed at both multiplexer and transistor levels. At multiplexer level, two hardening solutions are presented. The first solution resorts to spacial redundancy and concerns the logic block structure. A novel Configurable Logic Block (CLB) architecture baptized Butterfly is introduced. It is compared with other hardened CLB architectures in terms of reliability and cost penalties. The second hardening solution is a redundanceless scheme. It is based on a “smart” synthesis that consists in seeking the most reliable design in a given founder library, instead of directly using a redundant solution. Then, at transistor level, new single-ended and dual-rail multiplexer architectures are proposed. They are compared to different other transistor structures, according to suitable design metrics
15
Baskaya, Ismail Faik. "Physical design automation for large scale field programmable analog arrays." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31810.
Повний текст джерелаАнотація:
Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.Committee Chair: David V Anderson; Committee Co-Chair: Sung Kyu Lim; Committee Member: Aaron Lanterman; Committee Member: Abhijit Chatterjee; Committee Member: Daniel Foty; Committee Member: Paul Hasler. Part of the SMARTech Electronic Thesis and Dissertation Collection.
16
Le, Pelleter Tugdual. "Méthode de discrétisation adaptée à une logique événementielle pour l'utra-faible consommation : application à la reconnaissance de signaux physiologiques." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT043/document.
Повний текст джерелаАнотація:
Les systèmes embarqués mobiles font partis intégrante de notre quotidien. Afin de les rendre plus adaptésaux usages, ils ont été miniaturisés et leur autonomie a été augmentée, parfois de façon très considérable.Toutefois, les propositions d’amélioration butent désormais sur les possibilités de la technologie des circuitsintégrés. Pour aller plus loin, il faut donc envisager de repenser la chaîne de traitement du signal afin deréduire la consommation de ces dispositifs. Cette thèse développe une approche originale pour exploiterefficacement l’échantillonnage par traversée de niveaux d’une part et, d’autre part, associe cet échantillonnageà une logique évènementielle afin de réduire drastiquement la consommation d’énergie des systèmesintégrés autonomes. Une méthode de discrétisation adaptée à une application de reconnaissance de signauxphysiologiques, utilisée comme exemple dans cette thèse, y est présentée. Un premier prototype en logiqueévènementielle (asynchrone) sur circuit FPGA a permis de valider cette stratégie et de démontrer les bénéficesde cet échantillonnage dédié en termes de réduction de l’activité par rapport à un échantillonnage uniforme.Un second prototype en logique asynchrone et conçu en technologie CMOS AMS 0.35 μm a permis de validerpar simulation électrique un gain extrêmement important sur la consommation électrique du dispositifOur everyday life is highly dependent on mobile embedded systems. In order to make them suitable to differentapplications, they have underwent size reduction and lifetime extension. However, these improvementsare currently limited by the possibilities of the integrated circuits technologies. In order to push back theboundaries, it is necessary to reconsider the whole digital signal processing chain from scratch to sustain thepower consumption reduction in this kind of system. This work develops on the first hand a strategy thatsmartly uses the level-crossing sampling scheme and on the other combines this sampling method with eventlogicto highly reduce the power consumption in mobile embedded systems. A discretisation method adaptedto the recognition of physiological patterns application is described. A first event-logic (asynchronous) prototypeimplemented on FPGA proved the potential benefits that an adapted sampling scheme could offersto reduce activity compared to a uniform sampling scheme. Electrical simulations performed on a secondprototype, also designed in asynchronous logic, with CMOS AMS 0.35 μm technology, validated a high gainin power consumption
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Sandireddy, Raja Kiran Kumar Reddy Agrawal Vishwani D. "Hierarchical fault collapsing for logic circuits." Auburn, Ala., 2005. http://repo.lib.auburn.edu/EtdRoot/2005/SPRING/Electrical_and_Computer_Engineering/Thesis/SANDIREDDY_RAJA-KIRAN-KUMAR_48.pdf.
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18
Osseiran, Adam. "Définition, étude et conception d'un microprocesseur autotestable spécifique : cobra." Grenoble INPG, 1986. http://tel.archives-ouvertes.fr/tel-00320884.
Повний текст джерелаАнотація:
Description des différentes étapes de la conception d'un microprocesseur pour le contrôle des automatismes de sécurité, en particulier pour les systèmes de transport. Ce microprocesseur est autotestable, c'est-à-dire capable de détecter ses propres erreurs. La conception du circuit est basée sur les hypothèses de pannes au niveau analytique dans la technologie NMOS. Les blocs fonctionnels «Strongly Fault Secure» et les contrôleurs «Strongly Code Disjoint» sont à la base des circuits «Self-checking», dits autotestables. Le circuit COBRA démontre la faisabilité d'un microprocesseur autotestable. COBRA gère indépendamment 19 signaux différents, date des événements externes, mesure des fréquences, surveille 14 entrées logiques et possède 7 sorties indépendantes. Le programme d'application de COBRA est contenu dans une mémoire morte programmable externe de 16 Koctets adressés par 14 bits multiplexés sur le bus interne de 8 bits. COBRA contient également une liaison série, une mémoire à accès direct de 64 octets et 3 temporisateurs de 14 bits indépendants ainsi qu'une unité arithmétique et logique de 8 bits, COBRA exécute un jeu de 43 instructions
19
Yourst, Matt T. "Peptidal processor enhanced with programmable translation and integrated dynamic acceleration logic /." Diss., Online access via UMI:, 2005.
Знайти повний текст джерелаАнотація:
Thesis (M.S.)--State University of New York at Binghamton, Department of Computer Science, Thomas J. Watson School of Engineering and Applied Science, 2005."This dissertation is a compound document (contains both a paper copy and a CD as part of the dissertation)"--ProQuest abstract document view. Includes bibliographical references.
20
Young, Fung Yu. "Algorithms for the design of VLSI floorplans and logic modules /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.
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Liu, Tai-hung. "Logic synthesis for high-performance digital circuits /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.
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22
Dhingra, Inderpreet Singh. "Formalising an integrated circuit design style in higher order logic." Thesis, University of Cambridge, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.278296.
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23
Bertrand, François. "Conception descendante appliquée aux microprocesseurs VLSI." Phd thesis, Grenoble INPG, 1985. http://tel.archives-ouvertes.fr/tel-00316026.
Повний текст джерелаАнотація:
Dans la méthode de conception sûre et descendante CAPRI applicable aux circuits intégrés VLSI, on analyse les spécifications initiales à la définition de l'architecture du circuit. La méthode proposée est une méthode par affinements successifs de spécifications dans laquelle on distingue: 1) le choix des algorithmes; 2) le choix du chemin de données associé aux blocs fonctionnels; 3) le choix de la structure de la partie contrôle. Application de la démarche descendante au microordinateur 80 C48 d'INTEL en technologie CMOS
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Modi, Manish Harsukh. "Susceptibility evaluation of combational logic in VLSI circuits." Thesis, Virginia Tech, 1990. http://hdl.handle.net/10919/42221.
Повний текст джерелаАнотація:
A number of errors occur in digital systems operating in a harsh radiation environment. These errors are due to transient faults which may cause a temporary change in the state of the system without any permanent damage. These transient faults are referred to as Single Event Upsets (SEUs). Because of their random and non-recurring nature, such faults are very difficult to detect and hence are of source of great concern.
This thesis examines the logical response of combinational logic circuits to SEUs. Time domain analyses of a large number of circuits attempts to determine the affect of an SEU on a flip-flop which might lay at the end of a chain of combinational logic gates. In this way, the concept of an upset window, as it pertains to different types of logic gates is introduced. The results of the simulations carried out on various blocks of combinational logic are discussed. A program called SUPER (SUsceptibility PrEdiction pRogram) is developed. SUPER predicts the probability of a circuit fault occurring given that a cosmic ray with certain energy characteristics impinges on an arbitrary point within an IC. IC. The input variables to SUPER include the radiation level, the duration of the radiation, the types of gates the radiation affects, the signal path, the type of voltage pulse that the radiation produces (rising or falling) and the time (with respect to the clock pulse) that the radiation is incident on the circuit. The output of SUPER consists of a prediction as to whether or not the incident radiation causes a change in the output of a flip-flop.Master of Science
25
Degnan, Brian Paul. "Temperature robust programmable subthreshold circuits through a balanced force approach." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/47548.
Повний текст джерелаАнотація:
The subthreshold region of operation has simple physics which allows for a balanced-force approach to behavioral modeling that has shown to be robust to temperature, and a model that encapsulates MOSFET behavior across all operational regions has been developed. The subthreshold region of operation also allows for injection of charge onto floating nodes that allows for persistent storage that can be used in a variety of applications. The combination of charge storage and device modeling has allowed for the development of programmable circuits for digital applications.
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Sunki, Supriya. "Performance optimization in three-dimensional programmable logic arrays (PLAs)." [Tampa, Fla.] : University of South Florida, 2005. http://purl.fcla.edu/fcla/etd/SFE0001255.
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Kim, Dongho. "Power estimation for combinational logic and low power design /." Full text (PDF) from UMI/Dissertation Abstracts International, 2001. http://wwwlib.umi.com/cr/utexas/fullcit?p3008367.
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Yee, Gin Sun. "Dynamic logic design and synthesis using clock-delayed domino /." Thesis, Connect to this title online; UW restricted, 1999. http://hdl.handle.net/1773/6039.
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Han, Yi. "A high-performance CMOS programmable logic core for system-on-chip applications /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/5948.
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Lee, Hoon S. "A CAD tool for current-mode multiple-valued CMOS circuits." Thesis, Monterey, California. Naval Postgraduate School, 1988. http://hdl.handle.net/10945/22935.
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Approved for public release; distribution is unlimitedThe contribution of this thesis is the development of a CAD (computer aided design) tool for current mode multiple-valued logic (MVL) CMOS circuits. It is only the second known MVL CAD tool and the first CAD tool for MVL CMOS. The tool accepts a specification of the function to be realized by the user, produces a minimal or near-minimal realization (if such a realization is possible), and produces a layout of a programmable logic array (PLA) integrated circuit that realizes the given function. The layout is in MAGIC format, suitable for submission to a chip manufacturer. The CAD tool also allows the user to simulate the realized function so that he/she can verify correctness of design. The CAD tool is designed also to be an analysis tool for heuristic minimization algorithms. As part of this thesis, a random function generator and statistics gathering package were developed. In the present tool, two heuristics are provided and the user can choose one or both. In the latter case, the better realization is output to the user. The CAD tool is designed to be flexible, so that future improvements can be made in the heuristic algorithms, as well as the layout generator. Thus, the tool can be used to accommodate new technologies, for example, a voltage mode CMOS PLA rather than the current mode CMOS currently implemented.
http://archive.org/details/cadtoolforcurren00leeh
Lieutenant, Republic of Korea Navy
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Holland, Mark. "Automatic creation of product-term-based reconfigurable architectures for system-on-a-chip /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6124.
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Kucic, Matthew R. "Analog programmable filters using floating-gate arrays." Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/13755.
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Stamoulis, Iakovos. "Computer graphics hardware using ASICs, FPGAs and embedded logic." Thesis, University of Sussex, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.313943.
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The introduction of new technologies such as Field Programmable Gate Arrays (FPGAs) with high gate counts and embedded memory Applications Specific Integrated Circuits (ASICs) gives greater scope to the design of computer graphics hardware. This thesis investigates the features of the current generation of FPGAs and complex programmable logic devices (CPLD) and assesses their suitability as replacements for ASIC technologies, and as prototyping tools for their verification prior to fabrication. The traditional methodologies and techniques used for digital systems are examined for application to FPGA devices and novel design flow and implementation techniques are proposed. The new methodology and design flow uses a contemporary top down approach using hardware description languages and combines the flexibility of those methods with the efficiency of detailed low level design techniques. As an example of this methodology, a set of floating point arithmetic units consisting of a adder/subtraction, multiplication and division were designed using novel alternative algorithms that significantly outperformed algorithms designed with traditional methods in terms of both size and performance.T hese techniquesu sed were used to form a ToolKit that can accelerateth e design of systems that use floating point units for computer graphics systems. This ToolKit, in combination with a precision investigation methods can be used to generate floating point arithmetic units that have the required precision with minimum required hardware resources. Another emerging technology is that of embedded memory. Recent advancements in semiconductor fabrication processes make it feasible to integrate large amounts of DRAM, SRAM and logic on a single silicon die. This thesis will show the changes in the design flow that are require to take advantage of this new technology. A new embedded logic ToolKit was created that facilitates the exploitation of this technology. Finally, as an example to this methodology, a novel processor oriented towards 3D graphics was designedA. n architecturale xploration driven by novel trace-drivenp erformancea nalysism ethods is detailed that was used to model and tune the processor for the execution of global illumination computer graphics algorithms. The adaptation of these algorithms for execution in our processor is demonstrateda nd the performancea dvantagesth at can be extracteda re shown
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Sharma, Akshay. "Place and route techniques for FPGA architecture advancement /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6108.
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Chen, Daven 1959. "COMPARISON OF SCIRTSS EFFICIENCY WITH D-ALGORITHM APPLICATION TO ITERATIVE NETWORKS (TEST)." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/275572.
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Chenard, Jean-Samuel. "Hardware-based temporal logic checkers for the debugging of digital integrated circuits." Thesis, McGill University, 2012. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=106282.
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Integrated circuit complexity is ever increasing and the debug process of modern devices pose important technical challenges and cause delays in production. A comprehensive Design-for-Debug methodology is therefore rapidly becoming a necessity. This thesis presents a comprehensive system-level approach to debugging based on insilicon hardware checkers. The proposed approach leverages existing assertion-based verification libraries by translating useful temporal logic statements into efficient hardware circuits. Those checker circuits are then integrated in the device as part of the memory map, so they can provide on-line monitoring and debug assistance in addition to accelerating the integration of performance monitoring counters. The thesis presents a set of enhancements to the translation process from temporal language to hardware, targeted such that an eventual debug process is made more efficient. Automating the integration of the checker's output and control structures is covered along with a practical method that allow transparent access to the resulting registers within a modern (Linux) operating system. Finally, a method of integration of the hardware checkers in future Network-on-Chip systems is proposed. The use of a quality metric encompassing test, monitoring and debug considerations is defined along with the necessary tool flow required to support theprocess.La complexité des circuits intégrés augmente sans cesse et à un tel point que le procéssus de déboggage pose de nombreux problèmes techniques et engendre des retards dans la production. Une approche d'ensemble de conception pour le déboggage (Design-for-Debug) devient donc rapidement une nécessité. Cette thèse propose une approche détaillée de niveau système, intégrant des circuits de surveillance sur puce. L'approche proposée s'appuie sur la réutilisation de déclarations écrites en language de logique temporelle afin de les transformer en circuits digitaux efficaces. Ces derniers seront intégrés à la puce à travers son interface d'image mémoire afin qu'ils puissent servir au processus de déboggage ainsi qu'à une utilisation dans le système lorsque la puce est intégrée dans son environement. Cette thèse présente une série d'ajout au procéssus de transformation d'instructions de logique temporelle de manière à faciliter le procéssus de déboggage. Une méthode qui automatise l'intégration des sorties et du contrôle des circuits de surveillance est présentée ainsi que la manière dont une utilisation de ces circuits peut être accomplie dans le contexte d'un système d'exploitation moderne (Linux). Finalement, une méthode globale d'intégration des circuits de vérification dans le contexte de systèmes basés sur les réseaux-sur-puce est présentée, accompagnée de la chaine d'outils requise pour supporter ce nouveau processus de conception. Cette méthode propose l'utilisation de facteurs de qualité de test, de surveillance et de déboggage (Test, Monitoring and Debug) permettant une meilleure sélection des circuits ainsi qu'une intégration plus efficace au niveau des resources matérielles.
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Eckhardt, James P. "An investigation of high-performance logic circuitry in BiCMOS." Diss., Georgia Institute of Technology, 1990. http://hdl.handle.net/1853/15759.
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Zhao, Weisheng. "Conception, evaluation and development of the non-volatile programmable logic circuits using the Magnetic Tunnel Junction (MTJ)." Paris 11, 2008. http://www.theses.fr/2008PA112051.
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Ces 20 dernières années, les circuits logiques programmables se sont développés rapidement, notamment grâce à l’avantage présenté par leur reconfigurabilité, leur facilité d’utilisation et le prix réduit de leur procédé de développement. Cependant, la volatilité intrinsèque de leur technologie de réalisation (CMOS) est à l’origine des inconvénients pour ces circuits, tels que : la perte de données en cas de pannes d’alimentation, la latence longue pour initialiser le système à chaque démarrage et la consommation d’énergie en état veille à cause des courants de fuite. Ce dernier point est devenu un défi majeur avec la minimisation des transistors sous 90nm. Ces dernières années, de nombreuses technologies émergentes ont été proposées et explorées pour résoudre ces inconvénients. Parmi celles-ci, les technologies magnétiques, basées sur la spintronique, sont parmi les plus performantes et pratiquement réalisables. Ce travail de thèse porte sur l’étude, la conception, la simulation et la réalisation des circuits reconfigurables combinant une technologie CMOS avancée et les technologies non-volatiles émergentes basées sur la nano-spintronique. Les Jonctions Tunnel Magnétiques (JTM) ont été plus particulièrement étudiées selon plusieurs modes d’écriture (écriture par champ et par transfert de spin). Des circuits hybrides ont été tout d’abord conçus et simulés électriquement. Ils montrent de grands potentiels en terme de vitesse, de non-volatilité et de consommation par rapport aux circuits classiques. Ils permettraient également des nouvelles architectures de calcul et des modes de reconfigurations avancés. Enfin, un prototype a été développé pour démontrer les comportements et performances de ces circuits de la manière physiqueOver the past 20 years, programmable logic circuits have grown rapidly, particularly through the advantages presented by their reconfigurability, ease of use and low cost of their development process. However, the inherent volatility of CMOS technology based on charge storage is the source of inconvenient for these circuits, such as: data loss in case of power failure, the long latency to initialize the system at each (re) start-up and increasing high standby power due to the leakage currents. This last point has become a major challenge as the shrinking of transistors down to 90nm or below. In recent years, numerous emerging technologies have been proposed and explored to overcome these problems. Among them, Spintronics technology, is among the most efficient and practical solutions. This thesis focuses on the study, design, simulation and implementation of reconfigurable circuits combining CMOS technology and advanced non-volatile emerging technologies based on Nano Spintronics. The Magnetic Tunnel Junction (MTJ) was particularly studied based on three modes of writing such as Spin Transfer Torque (STT). The hybrid circuits were first designed and simulated electrically. They show great potential in terms of speed, non-volatility and power compared to conventional circuits. They would promise also new computing architectures and some advanced reconfiguration methods. Finally, a prototype was developed to demonstrate the behaviour and performance of these circuits
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Twigg, Christopher M. "Floating Gate Based Large-Scale Field-Programmable Analog Arrays for Analog Signal Processing." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/11601.
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Large-scale reconfigurable and programmable analog devices provide a new option for prototyping and synthesizing analog circuits for analog signal processing and beyond. Field-programmable analog arrays (FPAAs) built upon floating gate transistor technologies provide the analog reconfigurability and programmability density required for large-scale devices on a single integrated circuit (IC). A wide variety of synthesized circuits, such as OTA followers, band-pass filters, and capacitively coupled summation/difference circuits, were measured to demonstrate the flexibility of FPAAs. Three generations of devices were designed and tested to verify the viability of such floating gate based large-scale FPAAs. Various architectures and circuit topologies were also designed and tested to explore the trade-offs present in reconfigurable analog systems. In addition, large-scale FPAAs have been incorporated into class laboratory exercises, which provide students with a much broader range of circuit and IC design experiences than have been previously possible. By combining reconfigurable analog technologies with an equivalent large-scale digital device, such as a field-programmable gate array (FPGA), an extremely powerful and flexible mixed signal development system can be produced that will enable all of the benefits possible through cooperative analog/digital signal processing (CADSP).
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Herbert, J. M. J. "Application of formal methods to digital system design." Thesis, University of Cambridge, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.233985.
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Bridges, Seth. "Low-power visual pattern classification in analog VLSI /." Thesis, Connect to this title online; UW restricted, 2006. http://hdl.handle.net/1773/6984.
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Wu, Lifei. "Minimization of Permuted Reed-Muller Trees and Reed-Muller Trees for Cellular Logic Programmable Gate Arrays." PDXScholar, 1993. https://pdxscholar.library.pdx.edu/open_access_etds/4745.
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The new family of Field Programmable Gate Arrays, CLI 6000 from Concurrent Logic Inc realizes truly Cellular Logic. It has been mainly designed for the realization of data path architectures. However, the realizable logic functions provided by its macrocells and their limited connectivity call also for new general-purpose logic synthesis methods. The basic cell of CLi 6000 can be programmed to realize a two-input multiplexer ( A*B + C*B ), an AND/EXOR cell ( A*B Ea C ), or the basic 2-input AND, OR and EXOR gate. This suggests to using these cells for tree-like expansions. These "cellular logic" devices require regular connection patterns in the netlists resulting from logic synthesis. This thesis presents a synthesis tree searching program PROMPT, which generates AND/EXOR tree circuits from given Boolean functions. Such circuits have the property that the gate structures are AND/EXOR ( A *B EB C ), AND and EXOR which could be realized by the CLI6000 cells. Also, the connection. way in the circuit is that usually the output of one level gate is the input of the next level gate of the tree. This matches ideally to the architecture of the CLI6000 bussing network where the macrocells have only connections to their neighboring cells. PROMPT is based on the Davio expansions ( an equivalent of the Shannon expansions for the EXOR gates ) as its Boolean decomposition methods. The program includes three versions: exact version, heuristic version and fixed-variable version. The exact version of PROMPT generates the Permuted Reed-Muller Tree circuit which has the minimum number of gates. Such tree circuit is obtained by searching through all possible combinations of the expansion variable orders to get the one which needs the least number of gates. The heuristic version of PROMPT is designed to decrease the time complexity of the search algorithm when dealing with logic functions having many input variables. It generates a Permuted Reed-Muller Tree which may not have the minimum number of gates. However, the tree searching time in this version decreases tremendously compared to the time necessary in the exact version. The fix-variable version is developed to generate Reed-Muller Tree circuits. Such circuits will have the same expansion variables at the same tree level, so they can be easier routed after the placement to the CLI6000 chips. In short, the program PROMPT generates the PRM and RM tree circuits which are particularly well matched to both the realization of logic cell and connection structure of the CLI6000 device. Thus, the PRM and RM circuits can be easily placed and routed on the CLI6000 FPGAs.
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Leeser, Miriam Ellen. "Reasoning about the function and timing of integrated circuits with Prolog and temporal logic." Thesis, University of Cambridge, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.232797.
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The structure of circuits is specified with Prolog; their function and timing behaviour is specified with interval temporal logic. These structural and behavioural specifications are used to formally verify the functionality of circuit elements as well as their timing characteristics. A circuit is verified by deriving its behaviour from the behaviour of its components. The derived results can be abstracted to functional descriptions with timing constraints. The functional descriptions can then be used in proofs of more complex hardware circuits. Verification is done hierarchically, with transistors as primitive elements. Transistors are modeled as switch-level devices with delay. In order to model delay, the direction of signal flow through each transistor must be assigned. This is done automatically by a set of Prolog routines which also determine the inputs and outputs of each circuit component. Interval temporal logic descriptions are expressed in Prolog and manipulated using PALM: Prolog Assistant for Logic Manipulation. With PALM, the user specifies rewrite rules and uses these rules to manipulate logical terms. In the case of reasoning about circuits, PALM is used to manipulate the temporal logic descriptions of the components to derive a temporal logic description of the circuit. These techniques are demonstrated by applying them to several commonly used complementary metal oxide semiconductor (CMOS) structures. Examples include a fully complementary dynamic latch and a 1-bit adder. Both these circuits are implemented with transistors and exploit 2-phase clocking and charge sharing. The 1-bit adder is a sophisticated full adder implemented with a dynamic CMOS design style. The derived timing and functional behaviour of the 1-bit adder is abstracted to a purely functional behaviour which can be used to derive the behaviour of an arbitrary n-bit adder.
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Ramirez, Ortiz Rolando Carleton University Dissertation Engineering Electronics. "Circuit design rules for mixed static and dynamics CMOS logic circuits." Ottawa, 1999.
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Sunwoo, John Stroud Charles E. "Built-In Self-Test of programmable resources in microcontroller based System-on-Chips." Auburn, Ala., 2005. http://repo.lib.auburn.edu/2005%20Fall/Thesis/SUNWOO_JOHN_31.pdf.
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Aziz, Syed Mahfuzul. "The realisation of high-speed, testable multipliers suitable for synthesis using differential CMOS circuits." Thesis, University of Kent, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.240166.
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Van, Aardt Stefan. "Total ionizing dose and single event upset testing of flash based field programmable gate arrays." Thesis, Nelson Mandela Metropolitan University, 2015. http://hdl.handle.net/10948/12548.
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The effectiveness of implementing field programmable gate arrays (FPGAs) in communication, military, space and high radiation environment applications, coupled with the increased accessibility of private individuals and researchers to launch satellites, has led to an increased interest in commercial off the shelf components. The metal oxide semiconductor (MOS) structures of FPGAs however, are sensitive to radiation effects which can lead to decreased reliability of the device. In order to successfully implement a FPGA based system in a radiation environment, such as on-board a satellite, the single event upset (SEU) and total ionizing dose (TID) characteristics of the device must first be established. This research experimentally determines a research procedure which could accurately determine the SEU cross sections and TID characteristics of various mitigation techniques as well as control circuits implemented in a ProASIC3 A3P1000 FPGA. To gain an understanding of the SEU effects of the implemented circuits, the test FPGA was irradiated by a 66MeV proton beam at the iTemba LABS facility. Through means of irradiation, the SEU cross section of various communication, motor control and mitigation schemes circuits, induced by high energy proton strikes was investigated. The implementation of a full global triple modular redundancy (TMR) and a combination of TMR and a AND-OR multiplexer filter was found to most effectively mitigate SEUs in comparison to the other techniques. When comparing the communication and motor control circuits, the high frequency I2C and SPI circuits experienced a higher number of upsets when compared to a low frequency servo motor control circuit. To gain a better understanding of the absorbed dose effects, experimental TID testing was conducted by irradiating the test FPGA with a cobalt-60 (Co-60) source. An accumulated absorbed dose resulted in the fluctuation of the device supply current and operating voltages as well as resulted in output errors. The TMR and TMR filtering combination mitigation techniques again were found to be the most effective methods of mitigation.
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Orr, Marc Stewart. "A Logic Formulation for the QCA Cell Arrangement Problem." PDXScholar, 2010. https://pdxscholar.library.pdx.edu/open_access_etds/438.
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Some people believe that IC densities are approaching the fundamental limits inherent to semiconductor technologies. One alternative to semiconductors is Quantum-dot Cellular Automata (QCA); QCA is a nanotechnology that offers the potential to build denser IC's that switch at higher frequencies and run on lower power. QCA's most basic building block, the QCA cell, is inherently binary; digital circuits are implemented by arranging these QCA cells in pre-defined configurations on a two dimensional plane. This paper proposes a logic formulation that describes arranging QCA cells on a two dimensional plane; it is presented as a set of rules that can be implemented with basic Boolean variables and operators. This Boolean formulation is general and can be applied to any given specification. In addition, an optimization constraint is defined so that the logic formulation will only validate the most efficient QCA cell arrangements. The correctness of the logic formulation has been empirically verified by testing it with a SAT solver. The effectiveness of the minimization constraint in conjunction with the logic formulation has been tested with a Pseudo-Boolean ILP solver.
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Schafer, Ingo. "Orthogonal and Nonorthogonal Expansions for Multi-Level Logic Synthesis for Nearly Linear Functions and their Application to Field Programmable Gate Array Mapping." PDXScholar, 1992. https://pdxscholar.library.pdx.edu/open_access_etds/1339.
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The growing complexity of integrated circuits and the large variety of architectures of Field Programmable Gate Arrays (FPGAs) require sophisticated logic design tools. In the beginning of the eighties the research in logic design was concentrated on the development of fast two-level AND-OR logic minimizers like the well known ESPRESSO. However, most logic functions have a smaller and often faster circuit realization as a multi-level circuit. Thus, synthesis tools emerged for the minimization of the circuit area in a multi-level realization. Most of these synthesis tools are based on the "unate paradigm". Therefore, the synthesis methods are only advantageous for functions having a minimal circuit realization based on AND-OR gates. However, many common functions have a minmal circuit realization having a mix of AND, OR and EXOR gates like counters, adders, multipliers, and parity generators. Therefore, the design of such functions with synthesis tools based on the "unated paradigm" is very inefficient. Circuits incorporating the EXOR gate have received less attention than AND-OR circuits because the EXOR gate was perceived as slower and larger in terms of its circuit realization than the AND and the OR gate. However, the upcoming of Field Programmable Gate Arrays (FPGAs) like the Xilinx Table-Look-Up (TLU) architecture the Actel ACTâ„¢ series and the CLi 6000 series from Concurrent Logic, which allow the realization of the EXOR gate with the same speed and circuit cost as the AND and OR gate, eliminates the disadvantages of the EXOR gate over the AND and OR gate. Thus, there is a strong need for logic synthesis tools that take advantage of EXOR gates. The mapping to the new FPGAs recently obtained an increased interest. The developed synthesis algorithms for FPGAs are based on the mapping and restructuring of the Directed Acyclic Graph (DAG) representation of the logic function. Even though the new FPGAs allow the realization of the EXOR gate without any speed and circuit size penalty in comparison to the AND and OR gate, the synthesis methods have been based on the "unate paradigm". To overcome the disadvantages of the current logic synthesis tools with respect to (nearly) linear functions and FPGA synthesis, this dissertation introduces an extended theory of spectral methods for multiple-valued input, incompletely specified binary output logic. The spectral methods have not been popular in logic synthesis because of their four major drawbacks: (1) the computational complexity, especially if no Fast Transform exists, (2) the memory requirement to store the function in the necessary minterm representation, (3) they cannot take efficiently advantage of incompletely specified functions, (4) suitable only for few applications in logic synthesis. To overcome the two last stated drawbacks, this dissertation introduces the T spectrum. The T spectrum separates the information obtained for the specified and not specified parts of the underlying function. Thus, it is possible to determine directly the contribution of the specified and the not specified part of the function to a single spectral coefficient. Moreover, the T spectrum is an extension of the known spectra like Walshtype, Adding, Arithmetic, and Reed-Muller spectra to any orthogonal and nonorthogonal transform describing logic functions. Thus, transforms can be constructed that describe certain gate structures, as for example the realizable functions of a FPGA macrocell. This allows the development of special synthesis algorithms for the different types of FPGA architectures. As an exemplification of this method, a complete multi-level synthesis algorithm is introduced for the circuit realization with multiplexer modules, which form the basic macrocell of the Actel ACfâ„¢ FPGA series. Additionally, this dissertation presents the classification of the applications of spectral methods in logic synthesis into three categories: (1) The decomposition of logic functions based on the information obtained by the computation of a single spectrum. As an example the linearization procedure developed by Karpowsky is generalized to incompletely specified multi-output Boolean functions. The linearization procedure is based on the computation of the Rademacher-Walsh spectrum with a following decomposition of the underlying function based on high value spectral coefficients. (2) The circuit realization of a logic function based on the repetitive application of (1). This synthesis method is exemplified by an multi-level synthesis algorithm for multiplexer gates. (3) The realization of a logic function as an AND-EXOR circuit based on a GF 2 (Galois Field (2)) spectrum. The GF 2 transforms exhibit the property that they describe a realization of the underlying function as a two-level AND-EXOR circuit. The Multiple-Valued Input Kronecker Reed-Muller (MIKRM) form is introduced as an application of GF 2 transforms. To overcome the drawbacks of spectral methods concerning the computational complexity and high memory requirements, this dissertation presents a computation method for spectra from disjoint representations. The introduced application of the disjoint cube representation and the Ordered Decision Diagrams for the computation of spectra proves to be an ideal concept. Thus, this dissertation presents general synthesis methods based on new spectral methods that overcome the deficiencies of current logic synthesis methods with respect to the synthesis for FPGAs as well as the computational complexity and memory requirements of spectral methods.
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Petre, Csaba. "Sim2spice a tool for compiling simulink designs on FPAA and applications to neuromorphic circuits /." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31820.
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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.Committee Chair: Paul Hasler; Committee Member: Christopher Rozell; Committee Member: David Anderson. Part of the SMARTech Electronic Thesis and Dissertation Collection.