Дисертації з теми "Progettistica hardware e software"
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Taylor, Ramsay G. "Verification of hardware dependent software." Thesis, University of Sheffield, 2012. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.575744.
Повний текст джерелаHilton, Adrian J. "High integrity hardware-software codesign." Thesis, Open University, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.402249.
Повний текст джерелаEdmison, Joshua Nathaniel. "Hardware Architectures for Software Security." Diss., Virginia Tech, 2006. http://hdl.handle.net/10919/29244.
Повний текст джерелаPh. D.
Blaha, Vít. "Hardware a software inteligentního spotřebiče." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2015. http://www.nusl.cz/ntk/nusl-221136.
Повний текст джерелаFigueiredo, Boneti Carlos Santieri de. "Exploring coordinated software and hardware support for hardware resource allocation." Doctoral thesis, Universitat Politècnica de Catalunya, 2009. http://hdl.handle.net/10803/6018.
Повний текст джерелаThis thesis targets to narrow the gap between the software and the hardware, with respect to the hardware resource allocation, by proposing a new explicit resource allocation hardware mechanism and novel schedulers that use the currently available hardware resource allocation mechanisms.
It approaches the problem in two different types of computing systems: on the high performance computing domain, we characterize the first processor to present a mechanism that allows the software to bias the allocation hardware resources, the IBM POWER5. In addition, we propose the use of hardware resource allocation as a way to balance high performance computing applications. Finally, we propose two new scheduling mechanisms that are able to transparently and successfully balance applications in real systems using the hardware resource allocation. On the soft real-time domain, we propose a hardware extension to the existing explicit resource allocation hardware and, in addition, two software schedulers that use the explicit allocation hardware to improve the schedulability of tasks in a soft real-time system.
In this thesis, we demonstrate that system performance improves by making the software aware of the mechanisms to control the amount of resources given to each running thread. In particular, for the high performance computing domain, we show that it is possible to decrease the execution time of MPI applications biasing the hardware resource assignation between threads. In addition, we show that it is possible to decrease the number of missed deadlines when scheduling tasks in a soft real-time SMT system.
Nilsson, Per. "Hardware / Software co-design for JPEG2000." Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5796.
Повний текст джерелаFor demanding applications, for example image or video processing, there may be computations that aren’t very suitable for digital signal processors. While a DSP processor is appropriate for some tasks, the instruction set could be extended in order to achieve higher performance for the tasks that such a processor normally isn’t actually design for. The platform used in this project is flexible in the sense that new hardware can be designed to speed up certain computations.
This thesis analyzes the computational complex parts of JPEG2000. In order to achieve sufficient performance for JPEG2000, there may be a need for hardware acceleration.
First, a JPEG2000 decoder was implemented for a DSP processor in assembler. When the firmware had been written, the cycle consumption of the parts was measured and estimated. From this analysis, the bottlenecks of the system were identified. Furthermore, new processor instructions are proposed that could be implemented for this system. Finally the performance improvements are estimated.
Endresen, Vegard Haugen. "Hardware-software intercommunication in reconfigurable systems." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2010. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-10762.
Повний текст джерелаIn this thesis hardware-software intercommunication in a reconfigurable system has been investigated based on a framework for run time reconfiguration. The goal has been to develop a fast and flexible link between applications running on an embedded processor and reconfigurable accelerator hardware in form of a Xilinx Virtex device. As a start the link was broken down into hardware and software components based on constraints from earlier work and a general literature search. A register architecture for reconfigurable modules, a reconfigurable interface and a backend bridge linking reconfigurable hardware with the system bus were identified as the main hardware components whereas device drivers and a hardware operating system were identified as software components. These components were developed in a bottom-up approach, then deployed, tested and evaluated. Synthesis and simulation results from this thesis suggest that a hybrid register architecture, a mix of shift based and addressable register architecture might be a good solution for a reconfigurable module. Such an architecture enables a reconfigurable interface with full duplex capability with an initially small area overhead compared to a full scale RAM implementation. Although the hybrid architecture might not be very suitable for all types of reconfigurable modules it can be a nice compromise when attempting to achieve a uniform reconfigurable interface. Backend bridge solutions were developed assuming the above hybrid reconfigurable interface. Three main types were researched: a software register backend, a data cache backend and an instruction and data cache backend. Performance evaluation shows that the instruction and data cache outperforms the other two with an average acceleration ratio of roughly 5-10. Surprisingly the data cache backend performs worst of all due to latency ratios and design choices. Aside from the BRAM component required for the cache backends, resource consumption was shown to be only marginally larger than a traditional software register solution. Caching using a controller in the backend-bridge can thus provide good speedup for little cost as far as BRAM resources are not scarce. A software-to-hardware interface has been created has been created through Linux character device driver and a hardware operating system daemon. While the device drivers provide a middleware layer for hardware access the HWOS separates applications from system management through a message queue interface. Performance testing shows a large increase in delay when involving the Linux device drivers and the HWOS as compared to calls directly from the kernel. Although this is natural, the software components are very important when providing a high performance platform. As additional work specialized cell handling for reconfigurable modules has been addressed in the context of a MPEG-4 decoder. Some light has also been shed on design of reconfigurable modules in Xilinx ISE which can radically improve development time and decrease complexity compared to a Xilinx Platform Studio flow. In the process of demonstrating run time reconfigurations it was discovered that a clock signal will resist being piped through bus macros. Also broken functionality has been shown when applying run time reconfiguration to synchronous designs using the framework for self reconfiguration.
Lu, Yandong. "Hardware/Software Partitioning of Embedded Svstems." Thesis, University of Manchester, 2010. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.520747.
Повний текст джерелаKing, Myron Decker. "A methodology for hardware-software codesign." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/84891.
Повний текст джерелаCataloged from PDF version of thesis.
Includes bibliographical references (pages 150-156).
Special purpose hardware is vital to embedded systems as it can simultaneously improve performance while reducing power consumption. The integration of special purpose hardware into applications running in software is difficult for a number of reasons. Some of the difficulty is due to the difference between the models used to program hardware and software, but great effort is also required to coordinate the simultaneous execution of the application running on the microprocessor with the accelerated kernel(s) running in hardware. To further compound the problem, current design methodologies for embedded applications require an early determination of the design partitioning which allows hardware and software to be developed simultaneously, each adhering to a rigid interface contract. This approach is problematic because often a good hardware-software decomposition is not known until deep into the design process. Fixed interfaces and the burden of reimplementation prevent the migration of functionality motivated by repartitioning. This thesis presents a two-part solution to the integration of special purpose hardware into applications running in software. The first part addresses the problem of generating infrastructure for hardware-accelerated applications. We present a methodology in which the application is represented as a dataflow graph and the computation at each node is specified for execution either in software or as specialized hardware using the programmer's language of choice. An interface compiler as been implemented which takes as input the FIFO edges of the graph and generates code to connect all the different parts of the program, including those which communicate across the hardware/software boundary. This methodology, which we demonstrate on an FPGA platform, enables programmers to effectively exploit hardware acceleration without ever leaving the application space. The second part of this thesis presents an implementation of the Bluespec Codesign Language (BCL) to address the difficulty of experimenting with hardware/software partitioning alternatives. Based on guarded atomic actions, BCL can be used to specify both hardware and low-level software. Based on Bluespec SystemVerilog (BSV) for which a hardware compiler by Bluespec Inc. is commercially available, BCL has been augmented with extensions to support more efficient software generation. In BCL, the programmer specifies the entire design, including the partitioning, allowing the compiler to synthesize efficient software and hardware, along with transactors for communication between the partitions. The benefit of using a single language to express the entire design is that a programmer can easily experiment with many different hardware/software decompositions without needing to re-write the application code. Used together, the BCL and interface compilers represent a comprehensive solution to the task of integrating specialized hardware into an application.
by Myron King.
Ph.D.
Nagaonkar, Yajuvendra. "FPGA-based Experiment Platform for Hardware-Software Codesign and Hardware Emulation." Diss., CLICK HERE for online access, 2006. http://contentdm.lib.byu.edu/ETD/image/etd1294.pdf.
Повний текст джерелаBales, Jason M. "Multi-channel hardware/software codesign on a software radio platform." Fairfax, VA : George Mason University, 2008. http://hdl.handle.net/1920/3400.
Повний текст джерелаVita: p. 89. Thesis director: David D. Hwang. Submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering. Title from PDF t.p. (viewed Mar. 9, 2009). Includes bibliographical references (p. 85-88). Also issued in print.
Lu, Lipin. "Simulation Software and Hardware for Teaching Ultrasound." Scholarly Repository, 2008. http://scholarlyrepository.miami.edu/oa_theses/143.
Повний текст джерелаChakaravarthy, Ravikumar V. "IP routing lookup: hardware and software approach." Texas A&M University, 2003. http://hdl.handle.net/1969.1/2459.
Повний текст джерелаDadashikelayeh, Majid. "Integrated hardware-software diagnosis of intermittent faults." Thesis, University of British Columbia, 2014. http://hdl.handle.net/2429/50059.
Повний текст джерелаApplied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
Zeffer, Håkan. "Hardware–Software Tradeoffs in Shared-Memory Implementations." Licentiate thesis, Uppsala universitet, Avdelningen för datorteknik, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-86369.
Повний текст джерелаKägi, Thomas. "System software support for possible hardware deficiency." Thesis, London Metropolitan University, 2012. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.567824.
Повний текст джерелаEgi, Norbert. "Software virtual routers on commodity hardware architectures." Thesis, Lancaster University, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.539674.
Повний текст джерелаKnutsen, Henrik Holenbakken. "Enhancing Software Portability with Hardware Parametrized Autotuning." Thesis, Norges teknisk-naturvitenskapelige universitet, Institutt for datateknikk og informasjonsvitenskap, 2013. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-24568.
Повний текст джерелаBissland, Lesley. "Hardware and software aspects of parallel computing." Thesis, University of Glasgow, 1996. http://theses.gla.ac.uk/3953/.
Повний текст джерелаDave, Nirav Hemant 1982. "A unified model for hardware/software codesign." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/68171.
Повний текст джерелаThis electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student submitted PDF version of thesis.
Includes bibliographical references (p. 179-188).
Embedded systems are almost always built with parts implemented in both hardware and software. Market forces encourage such systems to be developed with dierent hardware-software decompositions to meet dierent points on the price-performance-power curve. Current design methodologies make the exploration of dierent hardware-software decompositions difficult because such exploration is both expensive and introduces signicant delays in time-to-market. This thesis addresses this problem by introducing, Bluespec Codesign Language (BCL), a united language model based on guarded atomic actions for hardware-software codesign. The model provides an easy way of specifying which parts of the design should be implemented in hardware and which in software without obscuring important design decisions. In addition to describing BCL's operational semantics, we formalize the equivalence of BCL programs and use this to mechanically verify design refinements. We describe the partitioning of a BCL program via computational domains and the compilation of dierent computational domains into hardware and software, respectively.
by Nirav Dave.
Ph.D.
Cantu, Roy R. "An investigation of hardware and software mindsets." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/38802.
Повний текст джерелаIncludes bibliographical references (leaves 44-46).
by Roy R. Cantu, III.
M.Eng.
Puzović, Miloš. "Hardware/software interface for dynamic multicore scheduling." Thesis, University of Cambridge, 2013. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.648234.
Повний текст джерелаBappudi, Bhargav. "Example Modules for Hardware-software Co-design." University of Cincinnati / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1470043472.
Повний текст джерелаKulkarni, Pallavi Anil. "Hardware acceleration of software library string functions." Ann Arbor, Mich. : ProQuest, 2007. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:1447245.
Повний текст джерелаTitle from PDF title page (viewed Nov. 19, 2009). Source: Masters Abstracts International, Volume: 46-03, page: 1577. Adviser: Mitch Thornton. Includes bibliographical references.
Cuenca, Desiree. "Hurricane data collection hardware and analysis software." [Gainesville, Fla.] : University of Florida, 2002. http://purl.fcla.edu/fcla/etd/UFE1000118.
Повний текст джерелаTitle from title page of source document. Document formatted into pages; contains vi, 119 p.; also contains graphics. Includes vita. Includes bibliographical references.
Olson, John Thomas. "Hardware/software partitioning utilizing Bayesian belief networks." Diss., The University of Arizona, 2000. http://hdl.handle.net/10150/284156.
Повний текст джерелаLei, Li. "Hardware/Software Interface Assurance with Conformance Checking." PDXScholar, 2015. https://pdxscholar.library.pdx.edu/open_access_etds/2323.
Повний текст джерелаJohansson, Hanna. "Interdisciplinary Requirement Engineering for Hardware and Software Development : from a Hardware Development Perspective." Thesis, Linköpings universitet, Industriell miljöteknik, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-139097.
Повний текст джерелаSheikh, Bilal Tahir. "Interdisciplinary Requirement Engineering for Hardware and Software Development - A Software Development Perspective." Thesis, Linköpings universitet, Institutionen för datavetenskap, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-147886.
Повний текст джерелаLindholm, Jeffery L. "Utilizing IXP1200 hardware and software for packet filtering." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2004. http://handle.dtic.mil/100.2/ADA429830.
Повний текст джерелаThesis Advisor(s): Wen, Su ; Gibson, John. "December 2004." Includes bibliographical references (p. 63-64). Also available in print.
Freitas, Arthur. "Hardware/Software Co-Verification Using the SystemVerilog DPI." Universitätsbibliothek Chemnitz, 2007. http://nbn-resolving.de/urn:nbn:de:swb:ch1-200700941.
Повний текст джерелаJunered, Marcus. "Enabling hardware technology for GNSS software radio research." Licentiate thesis, Luleå : Luleå University of Technology, 2007. http://epubl.ltu.se/1402-1757/2007/32/.
Повний текст джерелаO'Nils, Mattias. "Specification, synthesis and validation of hardware/software interfaces." Doctoral thesis, Stockholm, 1999. http://www.lib.kth.se/abs99/onil0616.pdf.
Повний текст джерелаProkopski, Grzegorz. "Optimizing software-hardware interplay in efficient virtual machines." Thesis, McGill University, 2009. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=66889.
Повний текст джерелаPour avoir une meilleure performance, la plupart des langages de programmation sont compilés, soit avant leur exécution et statiquement, ou dynamiquement, pendant leur utilisation, à l'aide d'un compilateur "Just-in-Time" (JIT). Cependant, les compilateurs avec desfonctionnalités d'optimisation sont complexes, et plusieurs langages, tel que Ruby, Python, PHP, profitent mieux d'une solution flexible et portable tel qu'une machine virtuelle (MV) interprétée. Cette solution offre un échange acceptable entre la performance d'exécution et les coûts de développement. La performance de la MV est typiquement maximisée par l'utilisation de la technique d'interprétation "direct threading", qui, malheureusement, interagit mal avec les prédicteurs de branches moderne. Des techniques plus avancées, tel que "code-copying" ont été proposées [RS96,PR98,EG03c,Gag02], mais ne sont pas applicable en pratique à cause de préoccupation de sécurité. C'est sur les bases suivantes que nous avons développé deux solutions coût-efficace qui offrent une bonne performance. Premièrement, nous avons développé une extension au langage C qui permet aux programmeurs d'exprimer le besoin pour des garanties spéciales pour la technique de "code-copying". Notre technique, qui requiert très peu de maintenance, est développée comme une extension à un compilateur qui a non seulement des fonctionnalités d'optimisation très élaborées mais qui est aussi un standard d'industrie, le "GNU C Compiler" (GCC). Nous pouvons alors appliquer cette technique sur les interpréteur Java, OCaml et Ruby. Nous avons évalué la performance de ces MV sur plusieurs architectures, en collectionnant de l'information pour analyser la performance logiciel et matériel. La marge d'amélioration possible est très grande, une accélération d'ordre 2.81 pour OCaml et 1.44 pour Java sur l'architecture Intel 32-bit. Il est importan
Wiangtong, Theerayod. "Hardware/software partitioning and scheduling for reconfigurable systems." Thesis, Imperial College London, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.404907.
Повний текст джерелаDimitrov, Martin. "Architectural support for improving system hardware/software reliability." Doctoral diss., University of Central Florida, 2010. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4533.
Повний текст джерелаID: 028916717; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (Ph.D.)--University of Central Florida, 2010.; Includes bibliographical references (p. 110-119).
Ph.D.
Doctorate
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Allan, Malcolm. "Hardware/software strategies for the DC brushless motor." Thesis, Glasgow Caledonian University, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.282722.
Повний текст джерелаKasture, Harshad. "A hardware and software architecture for efficient datacenters." Thesis, Massachusetts Institute of Technology, 2017. http://hdl.handle.net/1721.1/109005.
Повний текст джерелаCataloged from PDF version of thesis.
Includes bibliographical references (pages 121-131).
Datacenters host an increasing amount of the world's compute, powering a diverse set of applications that range from scientific computing and business analytics to massive online services such as social media and online maps. Despite their growing importance, however, datacenters suffer from low resource and energy efficiency, using only 10-30% of their compute capacity on average. This overprovisioning adds billions of dollars annually to datacenter equipment costs, and wastes significant energy. This low efficiency stems from two sources. First, latency-critical applications, which form the backbone of user-facing, interactive services, need guaranteed low response times, often a few tens of milliseconds or less. By contrast, current systems are architected to maximize long-term, average performance (e.g., throughput over a period of seconds), and cannot provide the short-term performance guarantees needed by these applications. The stringent performance requirements of latency-critical applications make power management challenging, and make it hard to colocate them with other applications, as interference in shared resources hurts their responsiveness. Second, throughput-oriented batch applications, while easier to colocate, experience performance degradation as multiple colocated applications compete for shared resources on servers. This thesis presents novel hardware and software techniques that improve resource and energy efficiency for both classes of applications. First, Ubik is a dynamic cache partitioning technique that allows latency-critical and batch applications to safely share the last-level cache, maximizing batch throughput while providing latency guarantees for latency-critical applications. Ubik accurately predicts the transients that result when caches are reconfigured, and can thus mitigate latency degradation due to performance inertia, i.e., the loss of performance as an application transitions between steady states. Second, Rubik is a fine-grain voltage and frequency scaling scheme that quickly and accurately adapts to short-term load variations in latency-critical applications to minimize dynamic power consumption without hurting latency. Rubik uses a novel, lightweight statistical model that accurately predicts queued work, and accounts for variations in per-request compute requirements as well as queuing delays. Further, Rubik improves system utilization by allowing latency-critical and batch applications to safely share cores, using frequency scaling to mitigate performance degradation due to interference in per-core resources such as private caches. Third, Shepherd is a cluster scheduler that uses per-node cache-partitioning decisions to drive application placement across machines. Shepherd uses detailed application profiling data to partition the last-level cache on each machine and to predict the performance of colocated applications, and uses randomized search to find a schedule that maximizes throughput. A common theme across these techniques is the use of lightweight, general-purpose architectural support to provide performance isolation and fast state transitions, coupled with intelligent software runtimes that configure the hardware to meet application performance requirements. Unlike prior work, which often relies on heuristics, these techniques use accurate analytical modeling to guide resource allocation, boosting efficiency while satisfying applications' disparate performance goals. Ubik allows latency-critical and batch applications to be safely and efficiently colocated, improving batch throughput by an average of 17% over a static partitioning scheme while guaranteeing tail latency. Rubik further allows these two classes of applications to share cores, reducing datacenter power consumption by up to 31% while using 41% fewer machines over a scheme that segregates these applications. Shepherd improves batch throughput by 39% over a randomly scheduled, unpartitioned baseline, and significantly outperforms scheduling-only and partitioning-only approaches.
by Harshad Kasture.
Ph. D.
Salehi-Abari, Omid. "Software-hardware systems for the Internet-of-Things." Thesis, Massachusetts Institute of Technology, 2018. http://hdl.handle.net/1721.1/115767.
Повний текст джерелаCataloged from PDF version of thesis.
Includes bibliographical references (pages [187]-201).
Although interest in connected devices has surged in recent years, barriers still remain in realizing the dream of the Internet of Things (IoT). The main challenge in delivering IoT systems stems from a huge diversity in their demands and constraints. Some applications work with small sensors and operate using minimal energy and bandwidth. Others use high-data-rate multimedia and virtual reality systems, which require multiple-gigabits-per-second throughput and substantial computing power. While both extremes stress the computation, communications, and energy resources available to the underlying devices, each intrinsically requires different solutions to satisfy its needs. This thesis addresses both bandwidth and energy constraints by developing custom software-hardware systems. To tackle the bandwidth constraint, this thesis introduces three systems. First, it presents AirShare, a synchronized abstraction to the physical layer, which enables the direct implementation of diverse kinds of distributed protocols for loT sensors. This capability results in a much higher throughput in today's IoT networks. Then, it presents Agile-Link and MoVR, new millimeter wave devices and protocols which address two main problems that prevent the adoption of millimeter wave frequencies in today's networks: signal blockage and beam alignment. Lastly, this thesis shows how these systems enable new IoT applications, such as untethered high-quality virtual reality. To tackle the energy constraint, this thesis introduces a VLSI chip, which is capable of performing a million-point Fourier transform in real-time, while consuming 40 times less power than prior fast Fourier transforms. Then, it presents Caraoke, a small, low-cost and low-power sensor, which harvests its energy from solar and enables new smart city applications, such as traffic management and smart parking.
by Omid Salehi-Abari.
Ph. D.
Liucheng, Miao, Su Jiangang, and Feng Bingxuan. "HARDWARE-INDEPENDENT AND SOFTWARE-INDEPENDENT IN SYSTEM DESIGN." International Foundation for Telemetering, 2000. http://hdl.handle.net/10150/606803.
Повний текст джерелаToday, open technology has been widely used in computer and other field, including software and hardware. The “Open Technology” about hardware and software can be called “Hardware-Independent and Software-Independent”(For example, Open Operating System in Computer.). But, in telemetry technology field, the system design based on “Hardware-Independent and Software-Independent” is primary stage. In this paper, the following question will be discussed: a. Why telemetry system design needs “open technology” b. How to accomplish system design based on “Hardware-Independent and Software-Independent” c. The application prospect of “hardware-Independent and Software-Independent” in system design.
Powell, Richard, and Jeff Kuhn. "HARDWARE- VS. SOFTWARE-DRIVEN REAL-TIME DATA ACQUISITION." International Foundation for Telemetering, 2000. http://hdl.handle.net/10150/608291.
Повний текст джерелаThere are two basic approaches to developing data acquisition systems. The first is to buy or develop acquisition hardware and to then write software to input, identify, and distribute the data for processing, display, storage, and output to a network. The second is to design a system that handles some or all of these tasks in hardware instead of software. This paper describes the differences between software-driven and hardware-driven system architectures as applied to real-time data acquisition systems. In explaining the characteristics of a hardware-driven system, a high-performance real-time bus system architecture developed by L-3 will be used as an example. This architecture removes the bottlenecks and unpredictability that can plague software-driven systems when applied to complex real-time data acquisition applications. It does this by handling the input, identification, routing, and distribution of acquired data without software intervention.
Akbari, Kazem. "A new neurocomputing approach: Software and hardware designs." Case Western Reserve University School of Graduate Studies / OhioLINK, 1995. http://rave.ohiolink.edu/etdc/view?acc_num=case1058207460.
Повний текст джерелаTIWARI, ANURAG. "HARDWARE/SOFTWARE CO-DEBUGGING FOR RECONFIGURABLE COMPUTING APPLICATIONS." University of Cincinnati / OhioLINK, 2002. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1011816501.
Повний текст джерелаWee, Sewook. "Atlas : software development environment for hardware transactional memory /." May be available electronically:, 2008. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.
Повний текст джерелаLindholm, Jeffery L. "Utilizing ISP1200 hardware and software for packet filtering /." Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2004. http://library.nps.navy.mil/uhtbin/hyperion/04Dec%5FLindholm.pdf.
Повний текст джерелаReis, João Gabriel. "A framework for predictable hardware/software component reconfiguration." reponame:Repositório Institucional da UFSC, 2016. https://repositorio.ufsc.br/xmlui/handle/123456789/173819.
Повний текст джерелаMade available in DSpace on 2017-02-28T04:10:39Z (GMT). No. of bitstreams: 1 344671.pdf: 991636 bytes, checksum: 2e9b1460f30d38b6d198a17b08fe6d42 (MD5) Previous issue date: 2016
Abstract : Rigid partitions of components or modules in a hardware/software co-design flow can lead to suboptimal choices in embedded systems with dynamic or unpredictable runtime requirements. Field-Programmable Gate Array (FPGA) reconfiguration can help systems cope with dynamic non-functional requirements such as performance and power, hardware defects due to Negative-Bias Temperature Instability (NBTI) and Process, Voltage and Temperature (PVT) variations, or application requirements unforeseen at design time. This work proposes a framework for reconfigurable components whereby the reconfiguration of a component implementation is performed transparently without user intervention. The reconfiguration process is confined in system?s idle time without interfering with or being interfered by other activities occurring in the system or even peripherals performing I/O. For components with multiple implementations, our approach opportunistically and speculatively monitors system load and performance parameters to check when the reconfiguration can start. The framework differs from previous approaches in its syntax and semantics for reconfigurable components which are preserved across the multiple implementations in different substrates and the reconfiguration process that can be split into multiple steps. To quantify the impact of I/O interference on FPGA reconfiguration, we measured the execution time when loading bitstreams containing hardware components implementations from memory to the FPGA reconfiguration interface with multiple peripherals performing I/O in parallel. Moreover, a Private Automatic Branch Exchange (PABX) case study investigated the deployment of reconfigurable components in a scenario with timing constraints. A reconfiguration policy for the PABX components was proposed to deal with the unpredictable number of calls it receives by using reconfigurable hardware resources without degrading voice quality due to reconfiguration. Furthermore, we explored trade-offs between power consumption, execution time, and accuracy in a set of reconfigurable mathematical components.
O particionamento estático de componentes ou módulos ao realizar o co-design hardware/software pode levar a escolhas insatisfatórias em sistemas embarcados com requisitos dinâmicos e imprevisíveis durante tempo de execução. A reconfiguração dinâmica de Field-Programmable Gate Arrays {FPGAs) pode ajudar sistemas a se adaptar em requisitos dinâmicos e não funcionais como desempenho e consumo de energia, defeitos de hardware devido ao fenômeno Negative-Bias Temperature Instability (NBTI) e variações de Processo, Tensão e Temperatura ou ainda requisitos da aplicação que não foram levados em consideração em tempo de projeto. Esse trabalho propõe um framework para componentes reconfiguráveis onde a reconfiguração da implementação de um componente é realizada de maneira transparente e sem a intervenção do usuário. O processo de reconfiguração é confinado no tempo ocioso do sistema sem interferir ou sofrer interferência de outras atividades ou mesmo periféricos realizando operações de entrada/saída. Para componentes com múltiplas implementações, nossa abordagem monitora de maneira especulativa a carga do sistema e contadores de desempenho para escolher o momento em que a reconfiguração deve se iniciar. O framework se difere de trabalhos anteriores devido à sintaxe e semântica para componentes reconfiguráveis que são preservadas nas múltiplas implementações e em diferentes substratos e no processo de reconfiguração que pode ser dividido em diversos passos. Para quantificar o impacto da interferência de entrada/saída na reconfiguração de FPGAs, foi medido o tempo de execução para carregar bitstreams contendo implementações de componentes em hardware da memória para a interface de reconfiguração de FPGA com diversos periféricos realizando operações de entrada/saída em paralelo. Além disso, o estudo de caso de um Private Automatic Branch Exchange (PABX) investigou o uso de componentes reconfiguráveis num cenário com requisitos temporais. Uma política de reconfiguração para os componentes do (PABX) foi proposta para lidar o número imprevisível de chamadas recebidas através de recursos reconfiguráveis sem degradar a qualidade da reprodução da voz devido à reconfiguração. Foram também explorados os trade-offs entre consumo de energia, tempo de execução e exatidão dos resultados num conjunto de componentes implementando operações matemáticas.
Teng, Chang-Fang, and 鄧昌芳. "The economical analysis of hardware and software firms to develop software department and hardware department." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/00329191132150560405.
Повний текст джерела佛光大學
經濟學系
96
Since 1989, GPS industry is already approaching on the international stage, GPS application is used to professional purpose and it is toward the consumption product for main market. All electrons commodity are attached GPS’s receiver to yield a lot of growing area. Let GPS’s hardware and software firms not only have their professional industries but also they consider to using their development departments to anticipant to reach the economies of scale to reduce the products cost and expand the company of management scope. This structure of paper considers the Normal form on the strategy game model. We have through the strategic game to elaborate and evaluate from advantages and disadvantages side on the GPS industry. We can use it to find the right on track to discover which factors can cause the influence of hardware and software firms to choose develop another department to increasing the company benefit.
Carlson, Ryan L. "A study of hardware/software multithreading." Thesis, 1998. http://hdl.handle.net/1957/33562.
Повний текст джерелаGraduation date: 1999
Yeh, Jinn-Wang, and 葉進旺. "The Study on Hardware/Software CoDesign." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/02143895370729762762.
Повний текст джерела國立交通大學
電子工程系
88
This thesis investigates an effective approach to the system-level design of multimedia signal processing applications. To design these systems, we use the hardware/software codesign approach, which allows the hardware and software designs to be tightly coupled throughout the design process. Given a specification of system functionality and constraints, we propose a model to describe the system. After the model has been analyzed, partitioning is used to determine the parts of the system functionality that are delegated to application-specific hardware and the software that runs on the processor. Based on the result of hardware/software partitioning, we determine the optimal implementation of a system. We also explore issues concerning system synchronization and the implementation of hardware/software interface to accommodate communications between various parts of the system. This hardware and software codesign approach proposed makes it possible to build a time-constrained signal processing system on a chip using programmable parts and application-specific units. We use a media processor design as an example. The verification method and simulation results are also given in this thesis.
Yen, Wen-Chi, and 顏文祺. "A Hardware/Software-Concurrent JPEG2000 Encoder." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/24263295495852495855.
Повний текст джерела國立清華大學
資訊工程學系
92
We implement a JPEG2000 encoder based on an internally developed hardware/software codesign methodology. We emphasize on the concurrent execution of hardware accelerator IPs and software running on the CPU. In a programmable SOC platform, hardware acceleration of DWT and EBCOT Tier-1 sequentially gives us 70% reduction in total execution time. The proposed concurrent scheme achieves additional 14% saving. We describe our experience in bringing up such a system.