Дисертації з теми "Power Electronics Reliability"

Silicon Carbide (SiC) is a wide-bandgap (WBG) semiconductor materialwhich has several advantages such as higher maximum electric field, lowerON-state resistance, higher switching speeds, and higher maximum allowablejunction operation temperature compared to Silicon (Si). In the 1.2 kV - 1.7kV voltage range, power devices in SiC are foreseen to replace Si Insulatedgatebipolar transistors (IGBTs) for applications targeting high efficiency,high operation temperatures and/or volume reductions. In particular, theSiC Metal-oxide semiconductor field-effect transistor (MOSFET) – which isvoltage controlled and normally-OFF – is the device of choice due to the easeof its implementation in designs using Si IGBTs.In this work the reliability of SiC devices, in particular that of the SiCMOSFET, has been investigated. First, the possibility of paralleling two discreteSiC MOSFETs is investigated and validated through static and dynamictests. Parallel-connection was found to be unproblematic. Secondly, drifts ofthe threshold voltage and forward voltage of the body diode of the SiC MOSFETare investigated through long-term tests. Also these reliability aspectswere found to be unproblematic. Thirdly, the impact of the package on thechip reliability is discussed through a modeling of the parasitic inductancesof a standard module and the impact of those inductances on the gate oxide.The model shows imbalances in stray inductances and parasitic elementsthat are problematic for high-speed switching. A long-term test on the impactof humidity on junction terminations of SiC MOSFETs dies and SiCSchottky dies encapsulated in the same standard package reveals early degradationfor some modules situated outdoors. Then, the short-circuit behaviorof three different types (bipolar junction transistor, junction field-effect transistor,and MOSFET) of 1.2 kV SiC switching devices is investigated throughexperiments and simulations. The necessity to turn OFF the device quicklyduring a fault is supported with a detailed electro-thermal analysis for eachdevice. Design guidelines towards a rugged and fast short-circuit protectionare derived. For each device, a short-circuit protection driver was designed,built and validated experimentally. The possibility of designing diode-lessconverters with SiC MOSFETs is investigated with focus on surge currenttests through the body diode. The discovered fault mechanism is the triggeringof the npn parasitic bipolar transistor. Finally, a life-cycle cost analysis(LCCA) has been performed revealing that the introduction of SiC MOSFETsin already existing IGBT designs is economically interesting. In fact,the initial investment is saved later on due to a higher efficiency. Moreover,the reliability is improved, which is beneficial from a risk-management pointof-view. The total investment over 20 years is approximately 30 % lower fora converter with SiC MOSFETs although the initial converter cost is 30 %higher.
Kiselkarbid (SiC) är ett bredbandgapsmaterial (WBG) som har flera fördelar,såsom högre maximal elektrisk fältstyrka, lägre ON-state resitans, högreswitch-hastighet och högre maximalt tillåten arbetstemperatur jämförtmed kisel (Si). I spänningsområdet 1,2-1,7 kV förutses att effekthalvledarkomponenteri SiC kommer att ersätta Si Insulated-gate bipolar transistorer(IGBT:er) i tillämpningar där hög verkningsgrad, hög arbetstemperatur ellervolymreduktioner eftersträvas. Förstahandsvalet är en SiC Metal-oxidesemiconductor field-effect transistor (MOSFET) som är spänningsstyrd ochnormally-OFF, egenskaper som möjliggör enkel implementering i konstruktionersom använder Si IGBTer.I detta arbete undersöks tillförlitligheten av SiC komponenter, specielltSiC MOSFET:en. Först undersöks möjligheten att parallellkoppla tvådiskretaSiC MOSFET:ar genom statiska och dynamiska prov. Parallellkopplingbefanns vara oproblematisk. Sedan undersöks drift av tröskelspänning ochbody-diodens framspänning genom långtidsprov. Ocksådessa tillförlitlighetsaspekterbefanns vara oproblematiska. Därefter undersöks kapslingens inverkanpåchip:et genom modellering av parasitiska induktanser hos en standardmoduloch inverkan av dessa induktanser pågate-oxiden. Modellen påvisaren obalans mellan de parasitiska induktanserna, något som kan varaproblematiskt för snabb switchning. Ett långtidstest av inverkan från fuktpåkant-termineringar för SiC-MOSFET:ar och SiC-Schottky-dioder i sammastandardmodul avslöjar tidiga tecken pådegradering för vissa moduler somvarit utomhus. Därefter undersöks kortslutningsbeteende för tre typer (bipolärtransistor,junction-field-effect transistor och MOSFET) av 1.2 kV effekthalvledarswitchargenom experiment och simuleringar. Behovet att stänga avkomponenten snabbt stöds av detaljerade elektrotermiska simuleringar för allatre komponenter. Konstruktionsriktlinjer för ett robust och snabbt kortslutningsskyddtas fram. För var och en av komponenterna byggs en drivkrets medkortslutningsskydd som valideras experimentellt. Möjligheten att konstrueradiodlösa omvandlare med SiC MOSFET:ar undersöks med fokus påstötströmmargenom body-dioden. Den upptäckta felmekanismen är ett oönskat tillslagav den parasitiska npn-transistorn. Slutligen utförs en livscykelanalys(LCCA) som avslöjar att introduktionen av SiC MOSFET:ar i existerandeIGBT-konstruktioner är ekonomiskt intressant. Den initiala investeringensparas in senare pågrund av en högre verkningsgrad. Dessutom förbättrastillförlitligheten, vilket är fördelaktigt ur ett riskhanteringsperspektiv. Dentotala investeringen över 20 år är ungefär 30 % lägre för en omvandlare medSiC MOSFET:ar även om initialkostnaden är 30 % högre.

QC 20170524

Nowadays, numerous power electronics application requires operation at high temperatures. In order to address increasing change of reliability problems in power die attachments for high temperature and high reliability applications, sintering Ag nanoparticles has been used as bonding material for this work. Firstly, quantitative microstructure characterization of as-sintered Ag joints has been carried out. The resulting normalized thickness, pore size and porosity decreased, and grain size increased with increasing the sintering time. A time dependence of the form t1/n with n close to 2 or 3 can be further derived for the kinetics of the thinning, densification and grain growth within the sintered Ag joints. From the results can be seen, sintering kinetics is still in the intermediate stage, the densification had not been completed, and Ag grain would continue growing afterwards, which could further explain degradation behaviours of sintered joints during isothermal ageing tests and thermal cycling tests. Secondly, sintered Ag joints with four kinds of substrate metallization have been subjected to isothermal ageing tests at temperatures of 150°C, 200°C and 250°C for up to 32 days. The different microstructure patterns of sintered joints with four substrate finishes during isothermal ageing tests have been presented and compared, which could use the results to explain part of the degradation behaviours of the sintered Ag joints during thermal cycling tests and guide selection of suitable substrate finish for the die attachments in high temperature power electronic system. Furthermore, thermal cycling tests have been carried out to investigate the reliability of two sizes of sintered Ag joints and solder joints during temperature cycling between -55°C to 125°C and -55°C to 150°C. Microstructure evolution of sintered Ag joints was investigated by non-destructive and destructive characterization methods, which revealed the factors which could effect on the degradation during thermal cycling tests. With microstructure features of sintered joints observed from X-ray tomography and SAM, because a specific specimen can be evaluated over its lifetime, a true image of microstructure evolution of damage during operation can be obtained, and crack and degradation can be observed three-dimensionally.

Circuit assembly and packaging technologies for power electronics have not kept pace with those for digital electronics. Inside those packaged power devices as well as the state-of-the-art power modules, interconnection of power chips is accomplished with wirebonds. Wirebonds in power devices and modules are prone to resistance, noise, parasitic oscillations, fatigue and eventual failure. Furthermore, there has been an increase demand for higher power density and better efficiency for power converters. Power semiconductor suppliers have been concentrating on improving device structure, density, and process technology to lower the on-resistance of MOSFETs and voltage drop of IGBTs. Recent advances made in power semiconductor technology are pushing packaging technology to the limits for performance of these power systems since the resistance and parasitics contribution by the package and the wirebonds are roughly the same as that on the silicon. In recent years, an integrated systems approach to standardizing power electronics components and packaging techniques in the form of power electronics building blocks has emerged as a new concept in the area of power electronics. As a result, it has been envisioned that the packaging of three-dimensional high-density multichip modules (MCMs) can meet the requirement for future power electronics systems. However, the conventional wirebond interconnected power devices are excluded from three-dimensional MCMs because of their large size, limited thermal management, and incompatible processing techniques. On the other hand, advanced solder joint area-array technologies, such as flip-chip technology, has emerged in microelectronics industry due to increased speed, higher packaging density, and performance, improved reliability and low cost these technologies offer. With all these benefits to offer, solder joint area-array technology has yet to be implemented for power electronics packaging. Therefore, the first objective of this study is to design and develop a solder joint area-array interconnection technique for power chips. Solder joint reliability is a major concern for area array technologies and power chip interconnection, thus the second objective of this study is to evaluate solder joint reliability, investigate the fatigue failure behavior of solder joint and improve solder joint reliability by developing a new solder bumping process for improved solder joint geometry, underfilling solder joint with encapsulant and applying flexible substrate in the assembly. The third objective is the implementation of solder joint interconnection technique in developing chip-scale power packages and a three-dimensional integrated power electronics module structure. Solder joint area array interconnection for power chips has been designed with the considerations of parasitic resistance and inductance reduction, current handling capability, thermal management, reliability improvement and manufacturability. A new solder joint fabrication process, which is able to produce high standoff hourglass-shaped solder joint that consists of an inner cap, middle ball and outer cap, as well as the conventional solder bumping process have been successfully developed for power chips by using stencil printing. This solder bumping technology is compatible with the existing surface-mount assembly operations and potentially low cost. The fabricated solder joints have been characterized for their structure integrity, mechanical strength and electrical performances. Solder joint reliability has been improved by optimizing solder joint geometry, underfilling flipped power chip and utilizing compliant substrate. Solder joint reliability was evaluated using accelerated temperate cycling and adhesion tests. The interfaces of the triple-stacked solder joints were examined using scanning electron microscopy (SEM) and energy dispersive X-ray analysis (EDX) for the integrity of the joint. Acoustic microscopy imaging (nondestructive evaluation) was utilized to examine the quality of the bonded interfaces and to detect cracks and other defects before and during accelerated fatigue tests. Adhesion strength of both single bump barrel-shaped and stacked hourglass-shaped solder joints to bonding pads was characterized and analyzed. It was found that stacked hourglass-shaped solder joint have higher fracture stress than barrel-shaped solder joint. This verifies that hourglass-shaped solder joint has lower stress singularity at the interface between the solder bump and the silicon die as well as at the interface between the solder bump and substrate than barrel-shaped solder joint, especially around the corners of the interfaces. Furthermore, the adhesion strength of barrel-shaped solder joint decreases much faster than that of high standoff hourglass-shaped solder joint under temperature cycling, which indicates that the latter has high reliability than the former. Our accelerated temperature cycling test clearly shows that solder joint fatigue failure process consists of three phases: crack initiation, crack propagation and catastrophic failure. Solder joint geometry, underfilling and substrate flexibility were proved to affect solder joint reliability. The effects of solder joint shape and standoff height on reliability have been systematically studied experimentally for the first time. Our experimental results indicated that both hourglass shape and great standoff height could improve solder joint fatigue lifetime, with standoff height being the more effective factor. The fatigue lifetime of high standoff hourglass-shaped solder joint is improved mainly by prolonged crack propagation time, with slight improvement in crack initiation time. Experimental data suggested that shape is the dominant factor affecting crack initiation time while standoff height is the major factor influencing crack propagation time. Underfilling and flexible substrate improved the lifetime of both barrel and hourglass-shaped solder joints. The effect of underfill on solder joint reliability is well known in microelectronics packaging field. However, for the first time, it is reported in this study that flex substrate could improve solder joint reliability. It has been found that flex substrate bucks during temperature cycling and thus reduces thermal strain in solder joints, which in turn improves solder joint fatigue lifetime. Chip scale packaging can enable a few very important concepts and advantages in power electronics packaging. It offers high silicon to package footprint ratio, provides a known good die solution to power chips, improves electrical as well as thermal performance and creates an opportunity for power component standardization. Two kinds of chip-scale power packages have been developed in this research. One is called cavity down flip chip on flex; the other is termed Die Dimensional Ball Grid Array (D2BGA). Both utilize solder joint as chip-level interconnection. Electrical tests show that the VCE(sat) of the high speed IGBT chip-scale packages is improved by 20% to 30% by eliminating the device¡¯s wirebonds and other external interconnections, such as leadframe. Double-sided cooling is realized in these CSPs. Temperature cycling test shows that the CSPs are reliable. Integrated power electronics modules (IPEMs) are envisioned as integrated power modules consisting of power semiconductor devices, power integrated circuits, sensors, and protection circuits for a wide range of power electronics applications, such as inverters for motor drives and converters for power processing equipment. We have developed a three-dimensional approach, termed flip chip on flex (FCOF), for packaging high-performance IPEMs. The new concept is based on the use of solder joint (D2BGA chip scale package), not bonding wires, to interconnect power devices. This packaging approach has the potential to produce modules having superior electrical and thermal performance and improved reliability. We have demonstrated the feasibility of this approach by constructing half-bridge converters (consisting of two IGBTs, two power diodes, and a simple gate driver circuitry) which have been successfully tested at power levels over 30 kW. Switching tests have shown that parasitic inductance of the FCOF module has been reduced by 40% to 50% over conventional wire bond power modules. Better thermal management can be achieved in this three-dimensional power module structure. Compared with the state-of-the-art half-bridge power modules, the volume of the half-bridge FCOF power module is reduced by at least 65%. Reliability test shows that this flip chip on flex power module structure is potentially more reliable than wire bond power module.
Ph. D.

The emergence of the hybrid electric vehicle and electric vehicles (HEV and EV) requires the reliability assessment of power electronic devices used in the inverters. This includes the electro-thermal reliability of bipolar devices such as IGBTs and PiN diodes and more recently, the SiC MOSFETs since the SiC technology is not as mature as their bipolar counterparts. This research, in its own capacity, through the use of accurate compact models, investigates the switching performance and characteristics of silicon IGBTs, PiN diodes and SiC MOSFETs. The need for higher power densities and fast device switching causes certain concerns in the performance and terminal characteristics of the converter. SiC MOSFET is a potential power device for implementing EV drivetrain inverters. One of the major advantages of SiC MOSFET is the possibility of using their body diodes for reverse current conduction, thereby obviating the need for lossy silicon PiN diodes. The primary goal of using SiC MOSFETs is to enable high frequency switching since the significantly lower switching losses coupled with the high dI/dt and dV/dt can increase the power density. This research has investigated and modelled the use of the SiC body diode for current commutation under high dV/dt conditions. Since the body diode is not designed to operate under such conditions, the electrothermal robustness of SiC body diode is investigated by simulating parasitic BJT latch-up that results from hard current commutation under high dV/dt. In a power MOSFET, high switching rates coupled with the drain-body capacitance brings about a displacement current passing through the resistive path of the P-body in the MOSFET structure which creates a voltage at the base of the parasitic BJT within the device. This BJT latch-up under certain thermal conditions is capable of destruction of the device. Another problem induced by high switching speed is that of the electrical coupling between complementing devices in the same leg of the inverter which is known as cross-talk or parasitic gate turn-on. In this research, the unintentional switching of IGBTs and the resulting short circuit current surge passing through the devices as a consequence of reducing the dead-time as well as increasing the switching rate is investigated and modelled. This is due to the discharge of the Miller capacitance which feeds back a current into the gate of the transistor. The result is that both transistors are switching on in the same phase leg. The other problem which is addressed in this research is modelling the switching transients of parallel connected IGBTs for the purpose of delivering high current conduction capability. The electrothermal energy balancing between the parallel connected IGBTs is important as the electrothermal variation between the parallel connected devices can cause temperature imbalance, thereby, accelerating the degradation of the power module. This research investigates the variations in the electrical time constants and the thermal time constants between the parallel connected devices and models the switching behaviours. Lastly, this research has focused on designing and fabricating power modules suitable for EV application and has tried to address methods to improve the electrothermal performance of the device and has investigated the impact of parasitic inductance of the layout on the electrothermal performance of the power module.

Wide-bandgap (WBG) semiconductor materials such as silicon carbide (SiC) and gallium-nitride (GaN) allow higher voltage ratings, lower on-state voltage drops, higher switching frequencies, and higher maximum temperatures. All these advantages make them an attractive choice when high-power density and high-efficiency converters are targeted. Two different gate-driver designs for SiC power devices are presented. First, a dual-function gate-driver for a power module populated with SiC junction field-effect transistors that finds a trade-off between fast switching speeds and a low oscillative performance has been presented and experimentally verified. Second, a gate-driver for SiC metal-oxide semiconductor field-effect transistors with a short-circuit protection scheme that is able to protect the converter against short-circuit conditions without compromising the switching performance during normal operation is presented and experimentally validated. The benefits and issues of using parallel-connection as the design strategy for high-efficiency and high-power converters have been presented. In order to evaluate parallel connection, a 312 kVA three-phase SiC inverter with an efficiency of 99.3 % has been designed, built, and experimentally verified. If parallel connection is chosen as design direction, an undesired trade-off between reliability and efficiency is introduced. A reliability analysis has been performed, which has shown that the gate-source voltage stress determines the reliability of the entire system. Decreasing the positive gate-source voltage could increase the reliability without significantly affecting the efficiency. If high-temperature applications are considered, relatively little attention has been paid to passive components for harsh environments. This thesis also addresses high-temperature operation. The high-temperature performance of two different designs of inductors have been tested up to 600_C. Finally, a GaN power field-effect transistor was characterized down to cryogenic temperatures. An 85 % reduction of the on-state resistance was measured at −195_C. Finally, an experimental evaluation of a 1 kW singlephase inverter at low temperatures was performed. A 33 % reduction in losses compared to room temperature was achieved at rated power.

QC 20160922

This thesis mainly focuses on improving the conventional DC-DC converter topology by utilizing the redundancy concept (N+1) and fault-tolerant design to maintain an uninterrupted output operation even on primary switch failure. The proposed fault-tolerant converter (FTC) involves merging three configurations namely buck, boost and buck-boost to derive a new converter structure along with bidirectional capabilities. The proposed FTC is equipped with a single redundant switch and shared with one coupled inductor and one capacitor (1L-1C) to be capable of achieving the step-up and step-down operation. The major faults of the converter system are highly related to the power switching devices, which can be categorized as open circuit fault (OCF), and short circuit fault (SCF). The proposed fault diagnosis scheme is able to detect the OCF and SCF in less than half of the switching period by sampling the rising and failing edge of the pulsating signal to identify the switch fault behavior. Therefore, remedial action of the proposed FTC can be associated with the fault detection unit to anticipate the moment when the converter requires the activation of the redundant switches by providing a back-up operation. However, any reconfigurable decision is necessary to electrically isolate the faulty component in order to avoid the subsequent fault current within the circuit loop. The proposed method of isolation design adopts the joule-integral principle for selecting an appropriate rating between fuse and MOSFET pair. It provides the satisfactory result for protecting the proposed FTC. Finally, a converter reliability model is carried out based on Markov chain theory to formulate the mean time to failure (MTTF) profile for the proposed FTC. The reliability analysis shows that the proposed FTC can surpass the reliability performance of the conventional DC-DC converter through optimization of the circuit topology.

As our electric power distribution infrastructure has aged, considerable investment has been applied to modernizing the electrical power grid through weatherization and in deployment of real-time monitoring systems. A key question is whether or not these investments are reducing the number and duration of power outages, leading to improved reliability. Statistical methods are applied to analyze electrical disturbance data (from the Department of Energy, DOE) and reliability index data (from state utility public service commission regulators) to detect signs of improvement. The number of installed smart meters provided by several utilities is used to determine whether the number of smart meters correlate with a reduction in outage frequency. Indication emerged that the number of power outages may be decreasing over time. The magnitude of power loss has decreased from 2003 to 2007, and behaves cyclically from 2008 to 2014, with a few outlier points in both groups. The duration also appears to be decreasing between 2003-2014. Large blackout events exceeding 5 GW continue to be rare, and certain power outage events are seasonally dependent. There was a linear relationship between the number of customers and the magnitude of a power outage event. However, no relationship was found between the magnitude of power outages and time to restore power. The frequency of outages maybe decreasing as the number of installed smart meters has increased. Recommendations for inclusion of additional metrics, changes to formatting and semantics of datasets currently provided by federal and state regulators are made to help aid researchers in performing more effective analysis. Confounding variables and lack of information that has made the analysis diffcult is also discussed.

Battery storage devices have been widely utilized for different applications. However, for high power applications, battery storage systems come with several challenges, such as the thermal issue, low power density, low life span and high cost. Compared with batteries, supercapacitors have a lower energy density but their power density is very high, and they offer higher cyclic life and efficiency even during fast charge and discharge processes. In this dissertation, new techniques for the control and energy management of the hybrid battery-supercapacitor storage system are developed to improve the performance of the system in terms of efficiency, power quality and reliability. To evaluate the findings of this dissertation, a laboratory-scale DC microgrid system is designed and implemented. The developed microgrid utilizes a hybrid lead-acid battery and supercapacitor energy storage system and is loaded under various grid conditions. The developed microgrid has also real-time monitoring, control and energy management capabilities. A new control scheme and real-time energy management algorithm for an actively controlled hybrid DC microgrid is developed to reduce the adverse impacts of pulsed power loads. The developed control scheme is an adaptive current-voltage controller that is based on the moving average measurement technique and an adaptive proportional compensator. Unlike conventional energy control methods, the developed controller has the advantages of controlling both current and voltage of the system. This development is experimentally tested and verified. The results show significant improvements achieved in terms of enhancing the system efficiency, reducing the AC grid voltage drop and mitigating frequency fluctuation. Moreover, a novel event-based protection scheme for a multi-terminal DC power system has been developed and evaluated. In this technique, fault identification and classifications are performed based on the current derivative method and employing an artificial inductive line impedance. The developed scheme does not require high speed communication and synchronization and it transfers much less data when compared with the traditional method such as the differential protection approach. Moreover, this scheme utilizes less measurement equipment since only the DC bus data is required.

Gallium Nitride is rapidly emerging as a promising material for electronic devices in various fields. Since it is a direct bandgap semiconductor it can be used for highly efficient light emitting devices (Light Emitting Diodes and Laser Diodes) and the possibility of growing alloys containing Aluminum and Indium allow for the selection of the peak wavelength along the whole UV-green part of the radiation spectrum. Moreover, the high electron mobility, the ability of withstand high electric fields and the good thermal dissipation make GaN-based diodes and transistors devices with a good potential for high frequency and power applications. Before final products containing Gallium Nitride devices can permeate the international market, it is required to guarantee that they are reliable enough to have long lifetimes to appeal potential customers, and that their performance/cost relationship is superior compared to other competitors, at least in some specific fields of application. Aim of this thesis is to investigate the strong points of Gallium Nitrides by means of characterization and reliability tests on various different structures (LEDs, laser diodes, blocking diodes, HEMTs, GITs, MISs), in order to analyze the behavior of the material from different points of view. Within this work is reported a detailed study of the gradual degradation of InGaN-based laser diodes and Light-Emitting Diodes submitted to electro-thermal stress. The purpose is to compare the behavior of the two devices by means of electro-optical measurements, electroluminescence characterization, near field emission measurements and Deep-Level Transient Spectroscopy (DLTS) investigation in order to give a deeper understanding of the mechanisms involved in LD degradation. Particular attention is given to the role of injection efficiency decrease and non-radiative recombination. The comparison of the degradation kinetics and an analysis of the degradation modes of the two device structures allowed a complete study of the physical mechanisms responsible for the degradation. It was found that the degradation of the devices can be ascribed to an increase of the defect density, which has a strong impact on non radiative recombination kinetics. The activation energy of the detected deep level is 0.35 - 0.45 eV. As an effect of combined electrical and thermal stress tests on commercially-available InGaN-based blue laser diodes, it has been found that sometimes there is an initial decrease of the threshold current, which is ascribed to the increase of the activation of p-type dopant, promoted by the temperature and the flow of minority carriers. In order to investigate the effects of the creation of defects, two different commercial blue InGaN-based LEDs were submitted to 3 MeV proton irradiation at various fluencies (10^11, 10^12 and 10^13 p/cm2). The degradation process was characterized by combined current-voltage (I - V), optical power-current (L - I) and capacitance-voltage (C - V) measurements, in order to investigate the changes induced by the irradiation and the recovery after annealing time at high temperature (150 °C‰). The experimental data suggest the creation of non-radiative recombination centers near or into the active region of the LEDs, due to atomic displacement. This hypothesis is confirmed by the results of the recovery tests: the increase of the optical power and its correlation with the recovery of the forward current is consistent with the annealing of those defects. Part of the activity on high electron mobility transistors was devoted to the realization of measurement setups in order to carry out novel characterization techniques. Were analyzed the advantages and limitations of the current-transient method used for the study of the deep levels in GaN-based high electron mobility transistors (HEMTs), by evaluating how the procedures adopted for measurement and data analysis can influence the results of the investigation. The choice of the measurement parameters (such as the voltage levels used to induce the trapping phenomena and monitor the current transients and the duration of the filling pulses) and of the analysis procedure (the method used for the extrapolation of the time constants of the processes) can influence the results of the drain current transient investigation and can provide information on the location of the trap levels responsible for current collapse. Moreover, was collected a database of defects described in more than 60 papers on GaN and its compounds, which can be used to extract information on the nature and origin of the traps in AlGaN/GaN HEMTs. Using this newly developed technique and other more common tests, several reliability and lifetime test were carried out on various structures, in order to gain a better understanding of their problematic aspects and possible improvements. One potential variation is the composition of the gate stack. Degradation tests were performed at Vgs = -5 V and increasing Vds levels on GaN HEMTs with different gate materials: Ni/Au/Ni, ITO and Ni/ITO. At each step of the stress experiment, the electrical and optical characteristics of the transistors were measured in order to analyze the degradation process. It was found that stress induces a permanent degradation of the gate diode, consisting in an increase in the leakage current. This change is due to the generation of parasitic conductive paths, as suggested by electroluminescence (EL) mapping, and devices based on ITO showed higher reliability. These data strongly support the hypothesis that the robustness is influenced by processing parameters and/or by the gate material, since all analyzed devices come from the same epitaxial wafer. Other than varying the gate material, it is possible to add a p-type layer under the gate in order to achieve normally-off operation. This change produces a benefit in terms of performances, but can give birth to unusual trapping phenomena. It was carried out an extensive analysis of the time and field-dependent trapping processes that occur in GaN-based gate injection transistors exposed to high drain voltage levels. Results indicate that, even if the devices do not suffer from current collapse, continuous exposure to high drain voltages can induce a remarkable increase in the on-resistance (Ron). The increase in Ron can be recovered by leaving the device in rest conditions. Temperature-dependent analysis indicates that the activation energy of the detrapping process is equal to 0.47 eV. By time-resolved electroluminescence characterization, it is shown that this effect is related to the capture of electrons in the gate - drain access region. This is further confirmed by the fact that charge emission can be significantly accelerated through the injection of holes from the gate. A first-order model was developed to explain the time dependence of the trapping process. Using other deep levels characterization techniques, such as drain current transients, gate frequency sweeps and backgating, several other trap states were identified in these devices. Their activation energies are 0.13, 0.14, 0.25, 0.47 and 0.51 eV. During the accelerated lifetime tests of these devices, it was found a variation of the relative amplitude of the transconductance peaks, well correlated with the increase of the electroluminescence. This effect can be explained by the activation of the p-type dopant, a phenomenon which was detected also in laser diodes. It is possible to develop diodes able to withstand very high reverse voltages using a similar structure, deprived of the gate region and with an additional Schottky diode (Natural superjunction). In this case, the activation energies of the detected deep levels were 0.35, 0.36, 0.44 and 0.47 eV. These values are very similar to the ones found in GITs, and this fact, along with the presence of the p-dopant activation in very different devices, confirms that it is useful to study different structures based on the same material in order to gain more knowledge on its performances, possibilities and reliability aspects.
Il Nitruro di Gallio si sta rapidamente proponendo come un materiale promettente per dispositivi elettronici in vari campi applicativi. Dato che si tratta di un semiconduttore a bandgap diretto, può essere utilizzato per realizzare emettitori di radiazione luminosa altamente efficienti (LED e diodi laser), e la possibilità di realizzare leghe contenenti Alluminio e Indio permette di selezionare la lunghezza d’onda di picco all’interno dell’intervallo UV - verde dello spettro elettromagnetico. Prima che i prodotti finali basati su Nitruro di Gallio possano permeare il mercato internazionale, è necessario garantire che siano abbastanza affidabili da possedere lunghi tempi di vita ai fini di essere considerati da potenziali acquirenti, e che il loro rapporto prestazioni/costi sia superiore rispetto a quello dei dispositivi attualmente presenti nel mercato, almeno per alcune specifiche applicazioni. Lo scopo di questa tesi è analizzare i punti di forza dei materiali composti basati su Nitruro di Gallio tramite caratterizzazione e test affidabilistici su varie strutture differenti (LED, diodi laser, diodi bloccanti, HEMT, GIT, MIS), per comprendere il comportamento del materiale da diversi punti di vista. In questo lavoro viene effettuato uno studio dettagliato del degrado graduale di LED e diodi laser in InGaN sottoposti a stress elettrotermici. lo scopo è di paragonare il comportamento delle due tipologie di dispositivi tramite caratterizzazione elettrica e ottica, elettroluminescenza, mappe di emissione in campo vicino e Deep-Level Transient Spectroscopy (DLTS), in modo da ottenere una comprensione profonda dei meccanismi di degrado che causano il calo di performance dei diodi laser. Un’attenzione particolare è rivolta al ruolo del calo dell’efficienza di iniezione e alla ricombinazione non-radiativa. Il confronto delle cinetiche di degrado e l’analisi del tipo di danno nelle due diverse strutture ha permesso uno studio completo dei meccanismi fisici responsabili del calo delle prestazioni. Il degrado dei dispositivi è stato attribuito ad un aumento della concentrazione di difetti, che ha un forte impatto sulle cinetiche di ricombinazione non-radiativa. L’energia di attivazione del livello profondo rilevato è 0.35 - 0.45 eV. Come effetto dei test di vita accelerata elettrici e termici compiuti su diodi laser blu commerciali basati su InGaN, si è notato che a volte si ha un iniziale calo della corrente di soglia, dovuto all’aumento dell’attivazione del drogante di tipo p, promossa dalla temperatura e dal flusso di portatori minoritari. Per comprendere gli effetti della creazione di difetti, due differenti tipologie di LED blu commerciali basati su InGaN sono stati sottoposti a irraggiamento tramite protoni con un’energia di 3 MeV a varie fluenze (10^11, 10^12 and 10^13 p/cm2). Il processo di degrado è stato caratterizzato tramite misure corrente - tensione (I - V), potenza ottica - corrente (L - I) e capacità - tensione (C - V) combinate, per cercare di comprendere le modifiche indotte dall’irraggiamento e il recupero conseguente all’annealing ad alte temperature (150 ‰). I dati sperimentali suggeriscono la creazione di centri di ricombinazione non-radiativa vicino o all’interno della regione attiva dei LED, causati dallo spostamento di atomi. Questa ipotesi viene confermata dai risultati dei test di recupero: l’aumento della potenza ottica e la sua correlazione con il recupero della corrente diretta è consistente con l’annealing dei difetti. Parte dell’attività sui transistor ad elevata mobilità elettronica è stata dedicata alla realizzazione di setup di misura che permettessero di utilizzare tecniche di caratterizzazione avanzata. Si sono analizzati i vantaggi e i limiti della metodologia dei transienti di corrente utilizzata per lo studio dei livelli profondi in HEMT basati su GaN, verificando in che modo diverse procedure adottate per la misurazione e l’analisi dei dati possano influenzare i risultati. La scelta dei parametri di misura (come i livelli di tensione utilizzati per indurre l’intrappolamento di carica e monitorare il transiente di corrente e la durata degli impulsi di filling) e della procedura di analisi (il metodo usato per l’estrapolazione delle costanti di tempo dei processi) può influenzare i risultati e può fornire informazioni sulla posizione degli stati trappola responsabili per il calo della corrente. Inoltre, è stato raccolto un database di difetti descritti in più di 60 articoli scientifici sul Nitruro di Gallio e i suoi composti, che può essere utilizzato per ottenere informazioni sulla natura e sull’origine delle trappole negli HEMT in AlGaN/GaN. Utilizzando questa tecnica innovativa e altri test più comuni, sono stati condotti test affidabilistici e di tempo di vita su varie strutture, per ottenere una miglior comprensione delle loro problematiche e dei possibili miglioramenti. Una possibile variazione riguarda la composizione dello stack di gate. Sono stati condotti test di degrado a Vgs = -5 V e valori di Vds crescenti su HEMT in GaN con differenti materiali di gate: Ni/Au/Ni, ITO e Ni/ITO. Ad ogni passo dello stress sono state misurate le caratteristiche elettriche e ottiche dei transistor, per analizzare il processo di degrado. Si è trovato che lo stress causa un degrado permanente del diodo di gate, che consiste in un aumento della corrente di leakage. Questo cambiamento è dovuto alla generazione di cammini conduttivi parassiti, come suggerito dalle misure di elettroluminescenza (EL), e dispositivi basati su ITO hanno mostrato un’affidabilità maggiore. Questi dati sostengono fortemente l’ipotesi che la robustezza è influenzata dai parametri di processo e/o dal materiale di gate, dato che tutti i dispositivi analizzati provengono dallo stesso wafer epitassiale. Oltre a variare il materiale di gate, è possibile aggiungere uno strato di tipo p sotto il gate per ottenere un funzionamento normally-off. Questo cambiamento fornisce un incremento delle performance, ma può dar nascita a fenomeni di trapping particolari. Si è condotta un’accurata analisi dei processi di trapping dipendenti dal tempo e dal campo elettrico che si verificano nei transistor ad iniezione di corrente di gate (GIT) quando vengono sottoposti ad elevate tensioni di drain. I risultati indicano che, anche se i dispositivi non soffrono di cali di corrente per tempi brevi, l’esposizione continua a tensioni di drain elevate può indurre un aumento significativo della resistività in zona lineare (Ron). Il valore originario di Ron può essere recuperato lasciano il dispositivo a riposo. L’analisi della dipendenza dalla temperatura indica che l’energia di attivazione del processo di detrappolamento è pari a 0.47 eV. Tramite una caratterizzazione dell’elettroluminescenza risolta temporalmente, viene mostrato che questo effetto è correlato alla cattura di elettroni nella regione di accesso gate - drain. Questa interpretazione è inoltre confermata dal fatto che l’emissione della carica può essere significativamente accelerata attraverso l’iniezione di lacune dal gate. Un modello del primo ordine è stato sviluppato per spiegare la dipendenza dal tempo del processo di trapping. Utilizzando altre tecniche di caratterizzazione dei livelli profondi, come i transienti di corrente di drain, gli sweep di frequenza di gate e il backgating, in questi dispositivi si sono identificati vari altri stati trappola. Le loro energie di attivazione sono 0.13, 0.14, 0.25, 0.47 e 0.51 eV. Durante i test di vita accelerata di questi dispositivi, si è trovata una variazione dell’ampiezza relativa dei picchi di transconduttanza ben correlata con l’aumento dell’elettroluminescenza. Questo effetto può essere spiegato tramite l’attivazione del drogante p, un fenomeno che si è osservato anche nei diodi laser. Utilizzando una struttura simile, è possibile realizzare diodi capaci di sopportare tensioni inverse molto elevate, rimuovendo la regione di gate e aggiungendo un diodo Schottky (Natural Superjunction). In questo caso, si sono rilevati livelli profondi di energia di attivazione 0.35, 0.36, 0.44 e 0.47 eV. Questi valori sono molto simili a quelli trovati nei GIT, e questo fatto, insieme alla presenza dell’ativazione del drogante p in dispositivi molto differenti tra loro, conferma l’utilità dello studio di differenti strutture basate sullo stesso materiale per ottenere una maggior conoscenza delle sue performance, possibilità e aspetti affidabilistici.

This study focuses on development a planar power module with low thermal impedance and thermo-mechanical stress for high density integration of power electronics systems. With the development semiconductor technology, the heat flux generated in power device keeps increasing. As a result, more and more stringent requirements were imposed on the thermal and reliability design of power electronics packaging. In this dissertation, a boundary-dependent RC transient thermal model was developed to predict the peak transient temperature of semiconductor device in the power module. Compared to conventional RC thermal models, the RC values in the proposed model are functions of boundary conditions, geometries, and the material properties of the power module. Thus, the proposed model can provide more accurate prediction for the junction temperature of power devices under variable conditions. In addition, the transient thermal model can be extracted based on only steady-state thermal simulation, which significantly reduced the computing time. To detect the peak transient temperature in a fully packaged power module, a method for thermal impedance measurement was proposed. In the proposed method, the gate-emitter voltage of an IGBT which is much more sensitive to the temperature change than the widely used forward voltage drop of a pn junction was monitored and used as temperature sensitive parameter. A completed test circuit was designed to measure the thermal impedance of the power module using the gate-emitter voltage. With the designed test set-up, in spite of the temperature dependency of the IGBT electrical characteristics, the power dissipation in the IGBT can be regulated to be constant by adjusting the gate voltage via feedback control during the heating phase. The developed measurement system was used to evaluate thermal performance and reliability of three different die-attach materials. From the prediction of the proposed thermal model, it was found that the conventional single-sided power module with wirebond connection cannot achieve both good steady-state and transient thermal performance under high heat transfer coefficient conditions. As a result, a plate-bonded planar power module was designed to resolve the issue. The comparison of thermal performance for conventional power module and the plate-bonded power module shows that the plate-bonded power module has both better steady-state and transient thermal performance than the wirebonded power module. However, due to CTE mismatch between the copper plate and the silicon device, large thermo-mechanical stress is induced in the bonding layer of the power module. To reduce the stress in the plate-bonded power module, an improved structure called trenched copper plate structure was proposed. In the proposed structure, the large copper plate on top of the semiconductor can be partitioned into several smaller pieces that are connected together using a thin layer copper foil. The FEM simulation shows that, with the improved structure, the maximum von Mises stress and plastic strain in the solder layer were reduced by 18.7% and 67.8%, respectively. However, the thermal impedance of the power module increases with reduction of the stress. Therefore, the trade-off between these two factors was discussed. To verify better reliability brought by the trenched copper plate structure, twenty-four samples with three different copper plate structures were fabricated and thermally cycled from -40°C to 105°C. To detect the failure at the bonding layer, the curvature of these samples were measured using laser scanning before and after cycling. By monitoring the change of curvature, the degradation of bonding layer can be detected. Experimental results showed that the samples with different copper plate structure had similar curvature before thermal cycle. The curvatures of the samples with single copper plate decreased more than 80% after only 100 cycles. For the samples with 2 × 2 copper plate and the samples with 3 × 3 copper plate, the curvatures became 75.8% and 77.5% of the original values, respectively, indicating better reliability than the samples with single copper plate. The x-ray pictures of cross-sectioned samples confirmed that after 300 cycles, the bonding layer for the sample with single copper plate has many cracks and delaminations starting from the edge.
Ph. D.

L’introduction des composants grand gap dans le domaine de l’électronique de puissance requiert une optimisation de son environnement (packaging). En effet, les températures auxquelles peuvent être utilisés ce type de composants sont bien souvent plus grandes que celles supportables par le reste du module. De nouvelles techniques d’assemblage sont à l’étude et notamment certaines à base de frittage d’argent. Ces procédés présentent l’avantage de réaliser l’assemblage à une température modérée (similaire à celle d’une brasure), mais toutefois inférieure à celle de fusion de l’argent. La température de fusion du joint d’attache reste celle du matériau massif (plus de 900°C pour l’argent). Cette technique permet donc de réaliser des attaches pouvant fonctionner à très haute température. Ce travail de thèse a porté sur la mise en oeuvre d’une attache de puce par frittage d’argent. Après une étude des paramètres du procédé permettant d’obtenir la meilleure tenue mécanique (cisaillement), nous avons mis en évidence l’effet prépondérant de la finition des pièces à joindre. Lorsque la finition du substrat est de l’argent, aucun problème d’interface n’est observé et les assemblages sont fiables à t0 et en vieillissement. Généralement, la finition standard pour l’électronique de puissance est constituée d’une couche de nickel et d’or. Pour cette finition, le mécanisme semble différent selon l’épaisseur d’or présente sur le substrat ainsi que l’atmosphère utilisée pour le traitement thermique ou encore la charge appliquée. Globalement, plus l’épaisseur d’or est importante, moindre est l’accroche. Ce comportement semble fortement lié à la diffusion extrêmement rapide de l’argent en surface de l’or (et dans l’or). Cette diffusion a pour conséquence la formation d’une couche de solution solide or-argent. Cette couche a pour source de matière les grains d’argent qui permettent l’adhérence du joint d’argent fritté sur le substrat. Lorsque le volume d’or disponible pour la formation de cette couche est grand, la croissance de celle-ci est favorisée (en termes de surface et d’épaisseur). Cette croissance engendre une consommation des « piliers » d’argent et donc un affaiblissement de l’attache. L’application de pression semble augmenter fortement la concentration de piliers et améliore les résultats, tandis que sous azote, la diffusion de l’argent en surface de l’or semble inhibée, permettant l’obtention de bons résultats (à t0 et après cyclage). Ces résultats ont été mis en pratique pour la réalisation de plusieurs prototypes, dont l’un a été testé électriquement et ce de façon fonctionnelle à plus de 300°C
Use of wide band gap chip in the power electronic industry requires an optimization of the close environment (packaging). Indeed, the can often sustain lower temperature than the die, especially the solder that are used to bond the parts of the module. Consequently, new bonding methods are investigated to enhance the performance of the packages. Silver sintering bonding technique is one the most promising. This method allow to bond parts at moderate temperature and the formed joint to operate at very high temperature (until the melting point of silver). This work is focused on the development of this bonding technique in the case of bonding a dies on a substrate. A study of the influence of the different parameters on the strength of the formed bond has been done. It revealed a major influence of the finishes of the bonded parts. Bonding on silver finished substrate results in good mechanical strength of the bond even after ageing. Furthermore, no interface issues are observed. However, the most used finish for power electronic is not silver but nickel-gold. Regarding this type of finish, the bond quality depends on the gold thickness, sintering profile and also sintering atmosphere. A solid solution of silver and gold seems to develop on the surface of the substrate, decreasing the section of the silver grains in contact with the substrate. Thus the mechanical strength of the assembly is decreased. This effect should be limited by the gold available for the Au-Ag solid solution growth. When sintering under nitrogen, the diffusion of silver on the gold surface is much lower than under air. Good results have been obtained with these configurations and even after ageing. Adding pressure during the thermal treatment seems also to minimize the phenomenon, probably by increasing the number of silver grains in contact with the substrate surface and so reducing the free surface for Au-Ag layer formation. Those results have been used to build prototypes, one of whom has been electrically tested with success at temperatures up to 300°C

The main objective of this thesis is to design reliable clock-distribution networks and power-delivery networks for three-dimensional integrated circuits (3D ICs) using through-silicon vias (TSVs). This dissertation supports this goal by addressing six research topics. The first four works focus on 3D clock tree synthesis for low power, pre-bond testability, TSV-induced obstacle avoidance, and TSV utilization. The last two works develop modeling approaches for reliability analysis on 3D power-delivery networks. In the first work, a clock synthesis algorithm is developed for low-power and low-slew 3D clock network design. The impact of various design parameters on clock performance, including the wirelength, clock power, clock slew, and skew, is investigated. These parameters cover the TSV count, TSV parasitics, the maximum loading capacitance of the clock buffers, and the supply voltage. In the second work, a clock synthesis algorithm is developed to construct 3D clock networks for both pre-bond testability and post-bond operability. Pre-bond testing of 3D stacked ICs involves testing each individual die before bonding, which can improve the overall yield of 3D ICs by avoiding stacking defective dies with good ones. Two key techniques including TSV-buffer insertion and redundant tree generation are implemented to minimize clock skew and ensure pre-bond testing. The impact of TSV utilization and TSV parasitics on clock power is also investigated. In the third work, an obstacle-aware clock tree synthesis method is presented for through-silicon-via (TSV)-based 3D ICs. A unique aspect of this problem lies in the fact that various types of TSVs become obstacles during 3D clock routing including signal, power/ground, and clock TSVs. These TSVs may occupy silicon area or routing layers. The generated clock tree does not sacrifice wirelength or clock power too much and avoids TSV-induced obstacles. In the fourth work, a decision-tree-based clock synthesis (DTCS) method is developed for low-power 3D clock network design, where TSVs form a regular 2D array. This TSV array style is shown to be more manufacturable and practical than layouts with TSVs located at irregular spots. The DTCS method explores the entire solution space for the best TSV array utilization in terms of low power. Close-to-optimal solutions can be found for power efficiency with skew minimization in short runtime. In the fifth work, current crowding and its impact on 3D power grid integrity is investigated. Due to the geometry of TSVs and connections to the global power grid, significant current crowding can occur. The current density distribution within a TSV and its connections to the global power grid is explored. A simple TSV model is implemented to obtain current density distributions within a TSV and its local environment. This model is checked for accuracy by comparing with identical models simulated using finite element modeling methods. The simple TSV models are integrated with the global power wires for detailed chip-scale power analysis. In the sixth work, a comprehensive multi-physics modeling approach is developed to analyze electromigration (EM) in TSV-based 3D connections. Since a TSV has regions of high current density, grain boundaries play a significant role in EM dominating atomic transport. The transient analysis is performed on atomic transport including grain and grain boundary structures. The evolution of atomic depletion and accumulation is simulated due to current crowding. And the TSV resistance change is modeled.

The rapidly expanding wireless market requires low cost, high integration and high performance of wireless communication systems. CMOS technology provides benefits of cost effectiveness and higher levels of integration. However, the design of highly efficient linear CMOS power amplifier that meets the requirement of advanced communication standards is a challenging task because of the inherent difficulties in CMOS technology. The objective of this research is to realize PAs for wireless communication systems that overcoming the drawbacks of CMOS process, and to develop design approaches that satisfying the demands of the industry. In this dissertation, a cascode bias technique is proposed for improving linearity and reliability of the multi-stage cascode CMOS PA. In addition, to achieve load variation immunity characteristic and to enhance matching and stability, a fully-integrated balanced PA is implemented in a 0.18-m CMOS process. A triple-mode balanced PA using switched quadrature coupler is also proposed, and this work saved a large amount of quiescent current and further improved the efficiency in the back-off power. For the low losses and a high quality factor of passive output combining, a transformer-based quadrature coupler was implemented using integrated passive device (IPD) process. Various practical approaches for linear CMOS PA are suggested with the verified results, and they demonstrate the potential PA design approach for WCDMA applications using a standard CMOS technology.

We demonstrate the use of embedded CdS nanowires in improving spectral transmission loss and the low mechanical and electrical robustness of planar CdS window layer and thus enhancing the quantum efficiency and the reliability of the CdS-CdTe solar cells. CdS nanowire window layer enables light transmission gain at 300nm-550nm. A nearly ideal spectral response of quantum efficiency at a wide spectrum range provides an evidence for improving light transmission in the window layer and enhancing absorption and carrier generation in absorber. Nanowire CdS/CdTe solar cells with Cu/graphite/silver paste as back contacts, on SnO2/ITO-soda lime glass substrates, yield the highest efficiency of 12% in nanostructured CdS-CdTe solar cells. Reliability is improved by approximately 3 times over the cells with the traditional planar CdS counterpart. Junction transport mechanisms are delineated for advancing the basic understanding of device physics at the interface. Our results prove the efficacy of this nanowire approach for enhancing the quantum efficiency and the reliability in window-absorber type solar cells (CdS-CdTe, CdS-CIGS and CdS-CZTSSe etc) and other optoelectronic devices. We further introduce MoO3-x as a transparent, low barrier back contact. We design nanowire CdS-CdTe solar cells on flexible foils of metals in a superstrate device structure, which makes low-cost roll-to-roll manufacturing process feasible and greatly reduces the complexity of fabrication. The MoO3 layer reduces the valence band offset relative to the CdTe, and creates improved cell performance. Annealing as-deposited MoO3 in N2 reduces series resistance from 9.98 Ω/cm2 to 7.72 Ω/cm2, and hence efficiency of the nanowire solar cell is improved from 9.9% to 11%, which efficiency comparable to efficiency of planar counterparts. When the nanowire solar cell is illuminated from MoO3-x /Au side, it yields an efficiency of 8.7%. This reduction in efficiency is attributed to decrease in Jsc from 25.5mA/cm2 to 21mA/cm2 due to light transmission loss in the MoO3-x /Au electrode. Even though these nanowire solar cells, when illuminated from back side exhibit better performance than that of nanopillar CdS-CdTe solar cells, further development of transparent back contacts of CdTe could enable a low-cost roll-to-roll fabrication process for the superstrate structure-nanowire solar cells on Al foil substrate.

This thesis presents the RF and mechanical design of a metal-to-metal contact RF MEMS switch. Metal-to-metal contact RF MEMS switches are especially preferred in low frequency bands where capacitive switches suffer from isolation due to the limited reactance. Frequency band of operation of the designed switch is from DC to beyond X-band. Measured insertion loss of the structure is less than 0.2 dB, return loss is better than 30 dB, and isolation is better than 20 dB up to 20 GHz. Isolation is greater than 25 dB below 10 GHz. Hence, for wideband applications, this switch offers very low loss and high isolation. Time domain measurement is necessary for the investigation of the dynamic behavior of the devices, determination of the &lsquo
pull in&rsquo
and &lsquo
pull out&rsquo
voltages of the membranes, switching time and power handling of the devices. Also, failure and degradation of the switches can be monitored using the time domain setup. For these purposes a time domain setup is constructed. Moreover, failure mechanisms of the RF MEMS devices are investigated and a power electronic circuitry is constructed for the biasing of RF MEMS switches. Advantage of the biasing circuitry over the direct DC biasing is the multi-shape, high voltage output waveform capability. Lifetimes of the RF MEMS devices are investigated under different bias configurations. Finally, for measurement of complicated RF MEMS structures composed of large number of switches, a bias waveform distribution network is constructed where conventional systems are not adequate because of the high voltage levels. By this way, the necessary instrumentation is completed for controlling a large scale RF MEMS system.

La diode Schottky SiC est un composant qui peut potentiellement remplacer la diode PiN Si dans les applications de puissance. Effectivement, la tenue en tension élevée, la faible résistivité, ainsi que l’indépendance de la température du courant de recouvrement rendent cette diode idéale pour les convertis- seurs de puissance DC/DC. Cependant, face à l’abondance des composants Si sur le marché, la diode Schottky rencontre une certaine réticence. Malgré les nombreuses démonstrations de systèmes électroniques de puissance réalisés, la fiabilité de cette technologie n’arrive pas à convaincre. Cette étude porte sur la caractérisation en régime statique sur une large gamme de températures et l’évaluation de la fiabilité en surcharge des diodes Schottky et JBS SiC-4H. La caractérisation en température a permis de proposer des modèles de la carac- téristique directe et inverse sur une gamme étendue de températures. Les tests en surcharge ont permis de comparer la fiabilité de diodes expérimentales et commerciales à fin de montrer la maturité de cette technologie
The SiC Schottky diode can potentially replace the PiN diode in power appli- cations. As a matter of fact, high blocking voltage, low resistivity as well as temperature independence of the reverse recovery current make this diode ideal for DC/DC power converters. Nevertheless, Schottky diodes meet some reluc- tance before the abundance of PiN Si diodes. Despite the numerous demons- trations of power electronics systems, there are still some reliability aspects to improve. This study focuses on static characteristic in a large temperature range and reliability assessment of repetitive surge test of Schottky and JBS diodes. The measurements of forward and reverse characteristics yielded new models in a wide temperature range. Repetitive surge tests enabled us to com- pare the reliability of experimental and commercial diodes in order to prove the maturity of this technology

Le stockage d’énergie dans les systèmes embarqués fait toujours l’objet d’importants efforts de R&D car il nécessite une constante diminution du volume occupé par les composants électroniques. Il apparaît que la taille des composants discrets que sont les condensateurs est un des freins à la miniaturisation des dispositifs finaux. Bien que des technologies, principalement basées sur la gravure profonde du silicium à l’échelle micrométrique, aient permis des avancées considérables, elles se montrent dorénavant limitées en termes de densité d’intégration. De ce fait, Murata IPS a développé une nouvelle technologie 3D à l’échelle nanométrique permettant une plus forte surface développée. L’utilisation d’une telle matrice requiert une méthode de dépôt de l’empilement MIM telle que l’ALD, adaptée aux structures à fort rapport d’aspect. Le but de cette thèse est ainsi l’intégration de la structure MIM dans la nouvelle matrice 3D dans le respect des contraintes inhérentes à l’industrie de manière à donner lieu à la cinquième génération des technologies PICS™. Le premier challenge résidait dans la conformalité des dépôts que nous nous sommes efforcés d’obtenir avec un équipement de production. Cela a permis de démontrer une densité de capacité supérieure à 1µF/mm² en utilisant un film diélectrique d’alumine de 10nm. Il s’avère également que l’intégration des électrodes TiN joue un rôle important sur la structure 3D. En effet, les contraintes ont dû être réduites pour assurer la tenue mécanique de la structure, notamment en jouant sur le pulse NH3. Les interfaces métal-diélectriques ont également fait l’objet d’une étude approfondie où l’influence de l’oxydation du TiN pendant le dépôt diélectrique a pu être mise en évidence et caractérisée électriquement. Cette étude a amené à l’intégration d’un matériau supplémentaire jouant le rôle de barrière aux interfaces, produisant des condensateurs avec une durée de vie supérieure à 10ans dans les conditions d’utilisation visées
Energy storage in embedded systems is still the subject of major R&D efforts as it requires a constant decrease in the volume of electronic components. It appears that the size of the discrete components, such as capacitors, is one of the brakes to the miniaturization of the final devices. Although technologies mainly based on silicon deep etching at the micrometric scale have made considerable progresses, they are now limited in terms of integration density. As a result, Murata IPS is developing a new 3D technology enabling a higher developed surface area. The use of such a matrix requires a MIM stack deposition technique such as ALD which is adapted to high aspect ratios. The aim of this thesis has been thus to integrate the MIM structure into the new 3D matrix while respecting the constraints inherent to the industry in order to give rise to the fifth generation of PICS™ technologies. The first challenge has been the achievement of sufficient step coverage of the films with an industrial equipment. A capacitance density greater than 1µF/mm² using a 10nm alumina film has been demonstrated. It also turns out that the TiN electrodes integration plays an important role on the 3D structure. Indeed, the mechanical stress had to be reduced to ensure the mechanical robustness of the structure, in particular by playing on the NH3 pulse. The metal-dielectric interfaces have also been the subject of an in-depth study where the influence of TiN oxidation during dielectric deposition has been shown and electrically characterized. This study has then led to the integration of an additional barrier material at the interfaces, producing capacitors with a 10-year lifetime under the intended voltage and temperature conditions

Ces travaux s’inscrivent dans le cadre du projet ANR "CAPTIF" (CAPTeurs innovants Intégrés et logiciels au coeur d’un dispositif d’électronique de puissance). Ce projet s’intéresse aux solutions de suivi de vieillissement en temps réel de modules d’électronique de puissance pour réduire les coûts de maintenance et augmenter la fiabilité des systèmes de conversion d’énergie.Les limitations des modèles de fiabilité actuels sont mises en évidence et conduisent à la recherche d’une approche plus représentative des mécanismes entraînant la défaillance des modules de puissance et à une remise en question du traditionnel nombre de cycles moyens avant défaillance en tant qu’outil de gestion de la fiabilité. À partir de l’identification des mécanismes de vieillissement des assemblages de puissance, une nouvelle méthodologie de modélisation est proposée pour caractériser la durée de vie résiduelle d’un module, en s’appuyant sur un indicateur d’endommagement énergétique. La fonction de corrélation entre cet indicateur de vieillissement et les données issues de capteurs embarqués est alors construite à l’aide de méthodes de régression numérique. Une mise en application sur un assemblage représentatif illustre l’intérêt de la méthodologie
This work is part of the french Research National Agency project called "CAPTIF" (meaning"Innovative embedded sensors and software for power electronics devices"). This research project deals with power electronics health monitoring solutions in order to increase electric conversion devices reliability and decrease maintenance costs.Traditionnal reliability models limitations led to a reconsideration of life prediction methodsand mean time to failure as a reliability management tool for power electronics devices.An investigation to develop an approach more representative of failure mechanisms observed in power electronics devices was conducted. Based on ageing mechanisms of power electronics assemblies, an ageing indicator was proposed and used with a modelling methodology to characterise the residual life of a device exposed to thermal loads. The functional link between this ageing indicator and data provided by embedded sensors is approache dusing a numerical design of experiment and a response surface methodology. This modelling process is illustrated by an application to a simplified power assembly

The North European power system (Sweden, Finland, Norway, Denmark, Estonia, Latvia and Lithuania) is facing changes in its electricity production. The increasing share of intermittent power sources, such as wind power, makes the production less predictable. The decommissioning of large plants, for environmental or market reasons, leads to a decrease of production capacity while the demand can increase, which is detrimental to the power system reliability. Investments in interconnections and new power plants can be made to strengthen the system. Evaluating the reliability becomes essential to determine the investments that have to be made. For this purpose, a model of the power system is built. The power system is divided into areas, where the demand, interconnections between areas, and intermittent generation are represented by Cumulative Distribution Functions (CDF); while conventional generation plants follow a two-state behaviour. Imports from outside the system are set equal to their installed capacity, with considering that the neighbouring countries can always provide enough power. The model is set up by using only publicly available data. The model is used for generating numerous possible states of the system in a Monte Carlo simulation, to estimate two reliability indices: the risk (LOLP) and the size (EPNS) of a power deficit. As a power deficit is a rare event, an excessively large number of samples is required to estimate the reliability of the system with a sufficient confidence level. Hence, a pre-simulation, called importance sampling, is run beforehand in order to improve the efficiency of the simulation. Four simulations are run on the colder months (January, February, March, November, December) to test the reliability of the current system (2015) and of three future scenarios (2020, 2025 and 2030). The tests point out that the current weakest areas (Finland and Southern Sweden) are also the ones that will face nuclear decommissioning in years to come, and highlight that the investments in interconnections and wind power considered in the scenarios are not sufficient to maintain the current reliability levels. If today’s reliability levels are considered necessary, then possible solutions include more flexible demand, higher production and/or more interconnections.
Det nordeuropeiska elsystemet (Sverige, Finland, Norge, Danmark, Estland, Lettland och Litauen) står inför förändringar i sin elproduktion. Den ökande andelen intermittenta kraftkällor, såsom vindkraft, gör produktionen mindre förutsägbar. Avvecklingen av stora anläggningar, av miljö- eller marknadsskäl, leder till en minskning av produktionskapaciteten, medan efterfrågan kan öka, vilket är till nackdel för kraftsystemets tillförlitlighet. Investeringar i sammankopplingar och i nya kraftverk kan göras för att stärka systemet. Utvärdering av tillförlitligheten blir nödvändigt för att bestämma vilka investeringar som behövs. För detta ändamål byggs en modell av kraftsystemet. Kraftsystemet är uppdelat i områden, där efterfrågan, sammankopplingar mellan områden, och intermittent produktion representeras av fördelningsfunktioner; medan konventionella kraftverk antas ha ett två-tillståndsbeteende. Import från länder utanför systemet antas lika med deras installerade kapaciteter, med tanke på att grannländerna alltid kan ge tillräckligt med ström. Modellen bygger på allmänt tillgängliga uppgifter. Modellen används för att generera ett stort antal möjliga tillstånd av systemet i en Monte Carlo-simulering för att uppskatta två tillförlitlighetsindex: risken (LOLP) och storleken (EPNS) av en effektbrist. Eftersom effektbrist är en sällsynt händelse, krävs ett mycket stort antal tester av olika tillstånd i systemet för att uppskatta tillförlitligheten med en tillräcklig konfidensnivå. Därför utnyttjas en för-simulering, kallad ”Importance Sampling”, vilken körs i förväg i syfte att förbättra effektiviteten i simuleringen. Fyra simuleringar körs för de kallare månaderna (januari, februari, mars, november, december) för att testa tillförlitligheten i nuvarande systemet (2015) samt för tre framtidsscenarier (2020, 2025 och 2030). Testerna visar att de nuvarande svagaste områdena (Finland och södra Sverige) också är de som kommer att ställas inför en kärnkraftsavveckling under de kommande åren. De indikerar även att planerade investeringar i sammankopplingar och vindkraft i scenarierna inte är tillräckliga för att bibehålla de nuvarande tillförlitlighetsnivåerna. Om dagens tillförlitlighetsnivåer antas nödvändiga, så inkluderar möjliga lösningar mer flexibel efterfrågan, ökad produktion och/eller fler sammankopplingar.

Ces dernières années ont vu apparaître sur le marché les premiers transistors de puissance de type MOSFET en carbure de silicium. Ce type de composant est particulièrement adapté à la réalisation d’équipement électrique à haut rendement et capable de fonctionner à haute température. Néanmoins, la question de la fiabilité doit être posée avant de pouvoir envisager la mise en œuvre de ces composants dans des applications aéronautiques ou spatiales. Les mécanismes de défaillance liés à l’oxyde de grille ont pendant longtemps retardé la mise sur le marché des transistors à grille isolée en carbure de silicium. Cette étude s’attache donc à estimer la durée de vie des MOSFET SiC de 1ére génération. Dans un premier temps, le mécanisme connu sous le nom de Time Dependent Dielectric Breakdown(TDDB) a été étudié au travers de résultats expérimentaux issus de la bibliographie. Notre analyse nous a permis de justifier de l’emploi d’une loi de Weibull pour modéliser la distribution des temps à défaillance issue de ces tests. Les résultats nous ont également permis de confirmer l’amélioration significative de la fiabilité de ces structures vis-à-vis de ce mécanisme. Dans un second temps, l’impact du mécanisme d’instabilité de la tension de seuil sur la fiabilité a été quantifié au travers de tests de vieillissement de type HTGB. Les données de dégradation ainsi collectées ont été modélisées à l’aide d’un processus gamma non-homogène, qui nous a permis de prendre en compte la variabilité entre les composants testés dans des conditions identiques et de proposer des facteurs d’accélération en tension et en température pour ce mécanisme. Enfin, ces travaux ont permis d’ouvrir la voie à la mise en œuvre d’outils de pronostic de la durée de vie résiduelle pour les équipements électriques
Recent years have seen SiC MOSFET reach the industrial market. This type of device is particularly adapted to the design of power electronics equipment with high efficiency and high reliability capable to operate in high ambient temperature. Nevertheless the question of the SiC MOSFET reliability has to be addressed prior to considering the implementation of such devices in an aeronautic application. The failure mechanisms linked to the gate oxide of the SiC MOSFET have for a long time prevented the introduction of the device. In this manuscript we propose to study the reliability of the first generation of SiC MOSFET. First, the mechanism known as the Time–Dependent Dielectric Breakdown is studied through experimental results extracted from literature. Our study shows the successful application of a Weibull law to model the time-to-failure distribution extracted from the accelerated tests. The results show also a significant improvement of the SiC MOSFET structure with respect to this phenomenon. In a second step, the impact of the threshold voltage instability is quantified through accelerated tests known as High Temperature Gate Bias. The collected degradation data are modeled using a non-homogeneous Gamma process. This approach allows taking into account the variability between devices tested under the same conditions. Acceleration factors have been proposed with respect to temperature and gate voltage. Eventually the study delivers a primary estimation of the remaining useful lifetime of the SiC MOSFET in a typical aeronautic application

La fiabilité et la sureté de fonctionnement de l'électronique de puissance jouent un rôle majeur aujourd'hui dans l'industrie. Cette thèse propose un nouveau cadre d'étude de la fiabilité à partir de deux méthodes afin d'améliorer la précision des études de fiabilité : une analyse utilisant la méthode des système dégradés multi état, et une analyse par intervalles. La considération des effets de dégradation propres et couplés de chaque composant est également une problématique qu'il reste aujourd'hui à étudier et qui est traitée dans ce travail.L'étude de la fiabilité par intervalles permet d'estimer des intervalles de durée de vie des convertisseurs DC/DC en prenant en compte les dégradations propres et mutuelles des composants. Fondamentalement, cette méthode est basée sur la compréhension des phénomènes physiques. A partir de cette méthode, on peut obtenir un intervalle pour la durée de vie d'un système complet. Cette méthode n'est toutefois pas adaptée aux systèmes redondants.De son côté, la fiabilité des systèmes dégradés multi-états est capable de proposer une étude au niveau système en prenant en compte le profil de mission et la physique des dégradations. Cette méthode a été généralisée dans cette thèse au procédés subissant de multiples dégradations.L'exemple d'un convertisseur DC/DC conprenant trois composants critiques a été étudié comme cas d'application. Deux composants semiconducteurs, diode et IGBT, et un condensateur sont considérés comme trois process de dégradation et l'effet de leur vieillissement sur la durée de vie du convertisseur est discutée. Le convertisseur étudié a pour puissance 3 kW (200/400V) et est dédié aux applications de type véhicule électrique. Il subit un profil de mission typique automobile (cycle WLTP)
Reliable and unceasing exploitation of power electronic converters plays a major part in every application. This PhD thesis comes up with new opened-up reliability assessment frameworks and demonstrates the feasibility of using multistate degraded system analysis and interval analysis as well for attaining much more accuracy in reliability evaluation. Considering self- and coupling degradation effects of the items and assessing reliability in the system level are important issues which are still lacking in the previous studies and the present thesis has made an effort to overcome these problems. The thesis tries to launch two distinct reliability assessment frameworks, namely interval reliability and Multistate degraded system reliability.Interval reliability is capable of introducing an interval useful lifetime for DC-DC power electronic converters in which the self and coupling degradations effects of items have been taken into account. Fundamentally, it is based on the conventional physics of failure reliability assessment. Based on this method, instead of obtaining an inaccurate reliability value, one can attain an interval for the reliability of a global system whose useful lifetime undoubtedly lays between the boundaries. This method is able to consider degradation dependencies and assess multi-component system level reliability but not redundant system. An attempt was made to enhance the conventional reliability framework to reach a systematic approach capable of estimating a reliability assessment considering self and mutual degradation effects and being able to evaluate system-level reliability including redundant system. Multistate degraded system reliability analysis is capable of estimating system-level reliability, while mission profile and physics of failure of the system’s items are taken into account. In addition, the self and mutual degradation effects of items on the operation of the global system have been considered. The multi-state degraded system reliability model exposed to multiple failure processes has been generalized. The operating condition of the global system is defined by a finite number of states. Not only can the proposed framework be employed in determining the reliability of the degraded systems in terms of multi-state functions, but also it can obtain the states of the systems by estimating the system state probabilities.As an application, a DC-DC power electronic system containing three critical items has been studied. In this case study, two power semiconductors, namely IGBT and diode, and a power capacitor have been considered as three degradation processes and their aging effects on the useful lifetime estimation of the power electronic system have been discussed. For having a sense about newly proposed reliability frameworks, a 3000W and 200/400 V conventional DC-DC converter for electric vehicle application exposed to WLTP driving cycle is considered

The method of using Fuzzy Sets Theory(FST) and Fuzzy Reasoning(FR) to aid reliability evaluation in a complex and uncertain environment is studied, with special reference to electrical power generating system reliability evaluation. Device(component) reliability prediction contributes significantly to a system's reliability through their ability to identify source and causes of unreliability. The main factors which affect reliability are identified in Reliability Prediction Process(RPP). However, the relation between reliability and each affecting factor is not a necessary and sufficient one. It is difficult to express this kind of relation precisely in terms of quantitative mathematics. It is acknowledged that human experts possesses some special characteristics that enable them to learn and reason in a vague and fuzzy environment based on their experience. Therefore, reliability prediction can be classified as a human engineer oriented decision process. A fuzzy knowledge based reliability prediction framework, in which speciality rather than generality is emphasised, is proposed in the first part of the thesis. For this purpose, various factors affected device reliability are investigated and the knowledge trees for predicting three reliability indices, i.e. failure rate, maintenance time and human error rate are presented. Human experts' empirical and heuristic knowledge are represented by fuzzy linguistic rules and fuzzy compositional rule of inference is employed as inference tool. Two approaches to system reliability evaluation are presented in the second part of this thesis. In first approach, fuzzy arithmetic are conducted as the foundation for system reliability evaluation under the fuzzy envimnment The objective is to extend the underlying fuzzy concept into strict mathematics framework in order to arrive at decision on system adequacy based on imprecise and qualitative information. To achieve this, various reliability indices are modelled as Trapezoidal Fuzzy Numbers(TFN) and are proceeded by extended fuzzy arithmetic operators. In second approach, the knowledge of system reliability evaluation are modelled in the form of fuzzy combination production rules and device combination sequence control algorithm. System reliability are evaluated by using fuzzy inference system. Comparison of two approaches are carried out through case studies. As an application, power generating system reliability adequacy is studied. Under the assumption that both unit reliability data and load data are subjectively estimated, these fuzzy data are modelled as triangular fuzzy numbers, fuzzy capacity outage model and fuzzy load model are developed by using fuzzy arithmetic operations. Power generating system adequacy is evaluated by convoluting fuzzy capacity outage model with fuzzy load model. A fuzzy risk index named "Possibility Of Load Loss" (POLL) is defined based on the concept of fuzzy containment The proposed new index is tested on IEEE Reliability Test System (RTS) and satisfactory results are obtained Finally, the implementation issues of Fuzzy Rule Based Expert System Shell (FRBESS) are reported. The application of ERBESS to device reliability prediction and system reliability evaluation is discussed.

A reliability prediction method is proposed to determine the lifetime of IGBTs (Insulated Gate Bipolar Transistors) under power cycling test based on the performance of solder joint and wire bond. The failure characteristics of solder joint and wire bond are captured via selected PoF model respectively. To provide precise reliability prediction, PoF models are converted into probabilistic models. In addition, the failure interaction between wire bond and solder joint is studied. Wire bond lift-off is treated as the predominant failure mode based upon experiments from literature and solder joint degradation process is triggered by wire bond degradation process. Increased junction temperature is captured as it is affected by the degradation process of both components. In the end, the system reliability is computed in a series system configuration.

Transmission and Distribution Electric Utilities have a vast amount of assets distributed over their system in the form of various equipment. As part of an asset management program, electric utilities keep focusing on the inspection and maintenance activities of these assets to improve system performance, reliability, and to ensure cost-effective expenditures. Therefore methodology that will reflect these inspection and maintenance efforts in terms of overall condition of the equipment is needed. Also techniques are needed to assess the impact of inspection and maintenance activities on the overall reliability of systems performance. To achieve this, a methodology for the assessment of equipment condition and the estimation of the health index for transformers and circuit breakers was developed. After that, a technique to estimate the failure rate from the equipment health index was used. Then an IEEE test case was selected to demonstrate its impact on system reliability indices with the help of a predictive reliability assessment software tool, Milsoft Utility Solution. As part of equipment condition assessment method for transformer and circuit breaker, failure modes and maintenance practices for these equipment was reviewed. Based on this review, parameters were selected for condition assessment which will provide significant information about the equipment condition and will also justify the cost and efforts. For each of the parameters, a score and weight were defined, and guidelines were developed to assign them. Also, ways in which online monitoring systems can contribute to equipment condition assessment were presented briefly. A technique was used to convert the equipment health index into its failure rate. Then an IEEE reliability test case was modeled using the Milsoft software, incorporating this estimated failure rate and studied system’s behavior in terms of reliability indices. It was observed that developing such models will provide more realistic information about the system’s actual performance and will demonstrate the way in which impact of the inspection and maintenance efforts can be accounted.
Thesis (M.S) - Wichita State University, College of Engineering, Dept. of Electrical and Computer Science Engineering

Cette thèse de doctorat s’inscrit dans la thématique de la fiabilité des circuits intégrés dans l’industrie de la microélectronique. Un circuit intégré peut être exposé à des agresseurs électriques potentiellement dangereux pendant toute sa durée de vie. Idéalement, les circuits devraient pouvoir encaisser ces excès d’énergie sans perdre leur fonctionnalité. En réalité, des défaillances peuvent être observées lors de tests de qualification ou en application finale. Il est donc dans l’intérêt des fabricants de réduire ces défaillances. Actuellement, il existe des circuits de protection sur puce conçus pour dévier l’énergie de ces agresseurs à l’écart des composants fragiles. Le terme anglophone Electrical Overstress (EOS) englobe tous les agresseurs électriques qui dépassent une limite au-delà de laquelle les composants peuvent être détruits. La définition de ce terme est traitée en détail dans la thèse. L’objectif de cette thèse est de comprendre le statut du sujet des EOS dans l’industrie. On propose ensuite une nouvelle méthodologie de caractérisation de circuits pour quantifier leur robustesse face à des formes d’onde représentatives présélectionnées. On propose également des solutions de circuits de protection sur puce que ce soit au niveau de nouveaux composants actifs ou au niveau de la conception des circuits électroniques de protection. Par exemple on propose un nouveau composant basé sur le thyristor qui a la capacité de s’éteindre même si la tension d’alimentation est présente sur l’anode. Une autre proposition est de désactiver les circuits de protection face aux décharges électrostatiques lorsque les puces sont dans un environnement où l’on est sur ou ces agresseurs ne présentent plus de danger. Finalement, des perspectives du travail de thèse sont citées
This Ph.D. thesis concerns reliability issues in the microelectronics industry for the most advanced technology nodes. In particular, the Electrical OverStress (EOS) issue is studied. Reducing EOS failures in Integrated Circuits (ICs) is becoming more and more important. However, the EOS topic is very complex and involves many different causes, viewpoints, definitions and approaches. In this context, a complete analysis of the current status of the EOS issue is carried out. Then, the Ph.D. objectives can be defined in a clear way. In particular, robustness increase of on-chip protection structures and IC characterization against EOS-like aggressors are two of the main goals. In order to understand and quantify the behavior of ICs against these aggressors, a dedicated EOS test bench is put in place along with the definition of a characterization methodology. A full characterization and comparison is performed on two different Electro- Static Discharge (ESD) power supply clamps. After identifying the potential weaknesses of the promising Silicon-Controlled Rectifier (SCR) device, a new SCR-based device with a turn-off capability is proposed and studied thanks to 3-D Technology Computer-Aided Design (TCAD)simulation. Triggering and turn-off behaviors are studied, as well as its optimization. Finally, three different approaches are proposed for improving the robustness of the IC onchip protection circuits. They are characterized thanks to the EOS test bench which allows identifying their assets as well as their points of improvement

Le contrôle de la fiabilité des composants électroniques critiques est un des enjeux des acteurs du secteur ferroviaire. Les modules de puissance à IGBT (Insulated Gate Bipolar Transistors) appartiennent à cette liste de composants. Ils sont soumis à de fortes contraintes correspondant à celles rencontrées dans des environnements ferroviaires sévères. Les conditions environnementales rencontrées dans l’exploitation ferroviaire et les fortes exigences en termes de disponibilité imposent des niveaux de fiabilité élevés aux IGBT. Dans une optique d’amélioration de leur fiabilité, une méthodologie d’évaluation a été développée basée sur une approche probabiliste et supportée par un réseau bayesien. Pour la mise en place du modèle, plusieurs briques de travail ont été assemblées. En premier lieu, une approche originale nommée « Cycle en U» a été proposée mettant en évidence de façon biunivoque un niveau système associé au train et un niveau composant assimilable à l’IGBT considérés simultanément selon des vues fonctionnelles et dysfonctionnelles. Dans ce cadre, le travail a conduit, dans un premier temps, à mettre en évidence les mécanismes caractérisant, dans une logique descendante, l’influence de la sollicitation du train sur la sollicitation du composant puis, selon une logique ascendante, de l’impact dysfonctionnel de la défaillance au niveau composant sur la fiabilité du système. Dans un deuxième temps, les résultats de cette analyse ont débouché sur la mise en place de la structure d’un modèle bayesien dont le caractère générique lui permet d’être déployé pour la modélisation fiabiliste de tout type de système ferroviaire. Le travail de modélisation basé sur les réseaux bayesiens sert de support au rapprochement entre modèles analytiques (physique de défaillance) et données issues de l’utilisation du composant élémentaire dans son environnement de fonctionnement. Le modèle a été utilisé pour la modélisation de la fiabilité d’un IGBT dans un cadre d’application correspondant au métro de la ville de Chennai en Inde. Les données et connaissances expertes recueillies sur le projet ont permis de déterminer les tables de probabilités du réseau bayesien. Les résultats probabilistes du modèle ont été traduites en indicateurs de fiabilité
The reliability control of critical electronic components is one of the challenges to be faced by railway stakeholders. IGBT (Insulated Gate Bipolar Transistors) power modules belong to this list of components. They are subject to high stresses corresponding to those encountered in harsh railway environments. The environmental conditions encountered in rail operations and the demanding availability requirements impose high levels of reliability on IGBT. In order to improve their reliability, an evaluation methodology has been developed based on a probabilistic approach and supported by a Bayesian network. For the implementation of the model, several working elements were assembled. First, an original approach called "U-Cycle" was proposed, highlighting in a one-to-one way a system level associated with the train and a component level similar to the IGBT considered simultaneously according to functional and dysfunctional views. In this context, the work led, first, to highlight the mechanisms characterizing, in a top-down logic, the influence of train loading on component stress and, in a bottom-up logic, the dysfunctional impact of the failure at component level on system reliability. In a second step, the results of this analysis led to the implementation of the structure of a Bayesian model whose generic nature allows it to be deployed for the reliable modelling of any type of rail system. The modelling work based on Bayesian networks is used to support the reconciliation between analytical models (failure physics) and data from the use of the elementary component in its operating environment. The model was used to model the reliability of an IGBT in an application framework corresponding to the metro in the city of Chennai, India. The data and expert knowledge collected on the project made it possible to determine the probability tables of the Bayesian network. The probabilistic results of the model have been translated into reliability indicators

Power electronic converters (PECs) are used for conditioning the flow of energy between renewable energy applications and grid or stand-alone connected loads. Insulated gate bipolar transistors (IGBTs) are critical components used as switching devices in PECs. IGBTs are multi-layered devices made of different coefficient of thermal expansion (CTE) based materials. In wind and solar energy applications, IGBT’s reliability is highly influenced by the operating conditions such as variable wind speed and solar irradiance. Power losses occur in switching transient of high current/voltage which causes temperature fluctuations among the layers of the IGBTs. This is the main stress mechanism which accelerates deterioration and eventual failures among IGBT layers due to the dissimilar CTEs. Therefore, proper thermal monitoring is essential for accurate estimation of PECs reliability and end lifetime. Several thermal models have been proposed in literature, which are not capable of representing accurate temperature profiles among multichip IGBTs. These models are mostly derived from offline modelling approaches which cannot take operating conditions and control mechanisms of PECs into account and unable to represent actual heat path among each chip. This research offers an accurate and powerful electro thermal and reliability monitoring tool for such devices. Three-dimensional finite element (FE) IGBT models are implemented using COMSOL, by considering complex heat interactions among each layer. Based on the obtained thermal characteristics, electro thermal and thermo mechanical models were developed in SIMULINK to determine the thermal behaviour of each layer and provide total lifetime consumption analysis. The developed models were verified by real-time (RT) experiments using dSPACE environment. New materials, such as silicon carbide (SiC) devices, were found to exhibit approximately 20°C less thermal profile compared to conventional silicon IGBTs. For PECs used within wind energy systems, PECs driving algorithms were derived within the proposed models and by adjusting switching frequency PECs cycling temperatures were reduced by 12°C which led to a significant reduction in thermal stress; approximately 27 MPa. Total life consumption for the proposed method was calculated as 3.26x10-5 which is approximately 1x10-5 less compared to the other both methods. Effects of maximum power tracking algorithms, used in photovoltaic solar systems, on thermal stress were also explored. The converter’s thermal cycling was found approximately 3 °C higher with the IC algorithm. The steady state temperature was 52.7°C for the IC while it was 42.6 °C for P&O. In conclusion, IC algorithm offers more accurate tracking accuracy; however, this is on the expense of harsher thermal stress which has led to approximately 1.4 times of life consumption compared to P&O under specific operating conditions.

Gold wire bonding typically uses 60 KHz ultrasonic frequency. Studies have been reported that increasing ultrasonic frequency from 60KHz to 120KHz can decrease bonding time, lower bonding temperature, and/or improve the bondability of Au metalized organic substrates. This thesis presents a systematic study of the effects of 120 KHz ultrasonic frequency on the reliability of fine pitch gold wire bonding. Two wire sizes, 25.4 and 17.8 μm in diameter (1.0 and 0.7 mil, respectively) were used. The gold wires were bonded to metalized pads over organic substrates with five different metallization. The studies were carried out using a thermosonic ball bonder that is able to easily switch from ultrasonic frequency from 60 KHz to 120 KHz by changing the ultrasonic transducer and the ultrasonic generator. Bonding parameters were optimized through design of experiment methodology for four different cases: 60 KHz with 25.4 μm wire, 60 KHz with 17.8 μm wire, 120 KHz with 25.4 μm wire, and 120 KHz with 17.8 μm wire. The integrity of wire bonds was evaluated by the wire pull and the ball bond shear tests. With the optimized bonding parameters, over 2,250 bonds were made for each frequency and wire size. The samples were then divided into three groups. The first group was subjected to temperature cycling from -55°C to +125°C with one hour per cycle for up to 1000 cycles. The second group was subject to thermal aging at 125°C for up to 1000 hours. The third group was subject to humidity at 85°C/85% relative humidity (RH) for up to 1000 hours. The bond integrity was evaluated through the wire pull and the ball shear tests immediately after bonding, and after each 150, 300, 500, and 1000 hours time interval in the reliability tests. The pull and shear data are then analyzed to compare the wire bond performance between different ultrasonic frequencies.

As human society develops, there is an increasing demand for electricity. However, the reserves of fossil fuels on earth are limited and may run out in the foreseeable future. Therefore, the possibility of replacing traditional fossil fuels with renewable energy sources is widely being investigated to resolve the world-faced energy shortage and environmental problems. The first method is to utilize more renewable energy such as wind and solar power and increase the percentage of distributed generation. Another method is to popularize electric vehicles due to their environmental-friendly and energy-saving characteristics. However, the integration of distributed generation and electric vehicles may greatly influence the operation and planning of power systems in several ways. This might result in deterioration of power system reliability. Since the society development highly depends on a safe and reliable power grid, it is essential to ensure high reliability of power systems when integrated with renewable energy resources. This master thesis aims to investigate the reliability performance of power distribution systems after integrating distributed generation and electric vehicles. First, the probabilistic model of distributed generation and electric vehicles for various scenarios are simulated. After that, a set of reliability analyses based on a standard reliability test system are carried out, in which a sequential Monte-Carlo simulation method is adopted to estimate average reliability indices. The overall conclusion is that the integration of distributed generation enhances power system reliability performance through supplying power to nearby customers in island mode. For electric vehicles, the proper regulation of charging behavior can help reduce the deterioration of power system reliability to the most extent, and the Vehicle-to-Grid mode can also improve system reliability. Furthermore, the electric bus dynamic charging mode has no additional harm to power system reliability performance than non-dynamic charging and has a promising prospect.
När det mänskliga samhället utvecklas finns det en ökande efterfrågan på el. Reserverna av fossila bränslen på jorden är dock begränsade och kan ta slut inom en överskådlig framtid. Därför undersöks möjligheten att ersätta traditionella fossila bränslen med förnybara energikällor för att lösa den världsomspända energibristen och miljöproblemen. Den första metoden är att använda mer förnybar energi såsom vind- och solenergi och öka andelen distribuerad produktion. En annan metod är att popularisera elfordon på grund av deras miljövänliga och energibesparande egenskaper. Integrationen av distribuerad produktion och elfordon kan dock påverka sätt och planering av kraftsystem i hög grad på flera sätt. Detta kan leda till försämring av elsystemets tillförlitlighet. Eftersom samhällsutvecklingen i hög grad beror på ett säkert och tillförlitligt kraftnät är det viktigt att säkerställa hög tillförlitlighet hos kraftsystem när de är integrerade med förnybara energikällor. Syftet med detta examensarbete är att undersöka tillförlitligheten hos kraftdistributionssystemet efter integrering av distribuerad generation och elfordon. För det första konstrueras den probabilistiska modellen för distribuerad generation och elfordon inklusive olika scenarier. Därefter genomförs en uppsättning tillförlitlighetsanalys baserad på RBTS buss 6-system, där sekventiell Monte-Carlo-simuleringsmetod antas för att uppskatta genomsnittliga återansvarsindex. Den övergripande slutsatsen är att integreringen av distribuerad produktion förbättrar systemets tillförlitlighet genom att leverera kraft till närliggande kunder på öns plats. För elektriska fordon kan korrekt reglering av laddningsbeteendet bidra till att minska försämringen av elsystemets tillförlitlighet i största möjliga utsträckning, och läget Fordon till nät kan även förbättra systemets tillförlitlighet. Dessutom har det elektriska bussens dynamiska laddningsläge ingen ytterligare skada på kraftsystemets tillförlitlighet och har ett lovande perspektiv.

The importance of electricity in everyday life and demands to improve the reliability of distribution systems force utilities to operate and plan their networks in a more secure and economical manner. With higher demands on reliability from both customers and regulators, a big pressure has been put on the security of electricity supply which is considered as a fundamental requirement for modern societies. Thus, efficient solutions for reliability and security of supply improvements are not just of increasing interest, but also have significant socio-economic relevance. Distribution system planning (DSP) is one of the major activities of distribution utilities to deal with reliability enhancement. This thesis deals with developing optimization algorithms, which aim is to min- imize customer interruption costs, and thus maximize the reliability of the system. This is implemented either by decreasing customer interruption duration, frequency of customer interruptions or both. The algorithms are applied on a single or multi- ple DSP problems. Mixed-integer programming has been used as an optimization approach. It has been shown that solving and optimizing each one of the DSP problems contributes greatly to the reliability improvement, but brings certain challenges. Moreover, applying algorithms on multiple and integrated DSP problems together leads to even bigger complexity and burdensome. However, going toward this inte- grated approach results in a more appropriate and realistic DSP model. The idea behind the optimization is to achieve balance between reliability and the means to achieve this reliability. It is a decision making process, i.e. a trade-off between physical and pricing dimension of security of supply.

QC 20200925

La problématique de recherche abordée dans ce mémoire de thèse découle de l’étude approfondie d’une association convertisseur-machine dédiée aux modes traction et recharge d’un véhicule électrique. Il s’agit d’un onduleur triphasé constitué de trois onduleurs monophasés connectés à une machine triphasée à phases indépendantes.Dans le chapitre II, une étude comparative entre deux solutions industrielles montre que l’architecture étudiée offre des caractéristiques compétitives notamment en termes de rendement global du convertisseur, performances mécaniques, et surface de silicium nécessaire.Par ailleurs, outre la possibilité de mutualiser les trois fonctions du véhicule que sont la traction, la recharge (rapide ou lente) et l’assistance du réseau électrique, cette topologie offre plusieurs atouts : des possibilités variées d’alimentation et donc un potentiel intéressant de reconfiguration en marche dégradée. La thématique abordée dans les chapitres III et IV est donc centrée sur l’optimisation des stratégies de contrôle de cette structure vis-à-vis de deux types de défauts : les imperfections intrinsèques du système d’une part et les défaillances accidentelles d’autre part.Dans un premier temps, un travail approfondi sur les méthodes de modulation de largeur d’impulsion a permis de synthétiser une stratégie offrant une faible sensibilité vis-à-vis des imperfections de la commande et de la non-linéarité du convertisseur. Dans un second temps, il a été montré qu’en cas de défaillance d’un composant à semi-conducteur, il était obligatoire de recourir à la reconfiguration matérielle de la topologie. L’architecture permettant la continuité de service a été étudiée du point de vue de sa commande. Son analyse nous a amenés à proposer une structure de contrôle basée sur des solutions automatiques simples et efficaces. Finalement, le principe du fonctionnement en marche dégradée a été étendu au fonctionnement normal dans le but d’en améliorer le rendement sur cycle
This Ph.D. thesis focuses on a novel combination of a frequency converter and an electric machine specially dedicated to traction drive and battery recharging modes of an electric vehicle (EV). This power architecture is composed of a six legs voltage inverter connected to a three-phase open-end winding machine. Chapter II details a quantitative comparison between two industrial power architectures and concludes that the SOFRACI powertrain is a competitive solution in terms of power converter efficiency, drive mechanical performances, and required silicon area.This architecture offers the attractive possibility of combining three important functions: traction and braking, battery charging and connecting the energy storage to a smart grid. In addition, this topology offers several advantages such as various motor feeding possibilities and a high degree of reconfiguration in degraded operating mode. The third and fourth chapters of this thesis concern the optimization of control strategies with regard to two types of faults: firstly the inherent imperfections in the converter itself (non modeled non-linearity and ineffective synchronization of control values) and secondly accidental failures. In the first case, an analysis of the pulse width modulation (PWM) methods enables the creation of a PWM strategy with a very low sensitivity to PWM uncertainties and the non-linear behavior of the power converter.In the second case, in the event of a faulty semiconductor device, it is shown that a hardware reconfiguration is required to enable an emergency traction mode. The sustainability of the traction mode is then examined with respect to the control strategy. This analysis leads to an innovative control structure based on basic and easy to implement solutions. Finally, the degraded mode operation principles have been extended to normal mode operation for the purpose of enhancing the cycle efficiency

A DC-DC converter is used in electrified and hybrid vehicles to supply powerto the low voltage (ex. 24V) system including headlights, horn, air conditioningsystem, wipers, radio, etc. The converter is fed from a high voltage (ex. 650V)battery, which is available in electric/hybrid vehicles, and transfers a relativelyhigh power. SCANIA’s conventional converters, used so far, have silicon-basedswitches, i.e., Si IGBT; and there is an intention to replace the converter with theupgraded counterpart in which SiC-based transistors (SiC-MOSFET) are usedinstead. Wide band-gap silicon carbide (SiC) semiconductor material offers possibilitiesof faster switching, high-temperature operation, and higher breakdownvoltage for power transistors. SCANIA is investigating the reliability of thesecond generation converter in which the Si IGBT transistors are replaced bySiC-MOSFET transistors. In this thesis, the reliability of a SiC-based switchesused in DC-DC converter of electrified trucks is investigated. The investigationis principally based on different reliability tests results carried out in both switchand converter levels.To investigate the reliability of SIC MOSFET transistors, first different failuremechanisms, such as gate oxide layer degradation, high-frequency side effects,etc., are introduced, and corresponding test results are presented and discussed.On converter level, the reliability study of SCANIA’s first generation converteris considered, and the weak components in the converter are identified.In this thesis, the test results provided by SiC-MOSFET and converter suppliersare analyzed and compared with the similar test results conducted on the Sibasedconverter. In additions, SCANIA performs some particular tests based onits own standardization related to different environmental working conditions,such as high ambient temperature and high vibration situation, to assure thematurity and robustness of the SiC-based converter. These test results arepresented and discussed.By comparing investigation outcomes acquired from different suppliers and customers,it is shown that the SiC MOSFET transistor is more efficient that Sibasedtransistor. It is also demonstrated that SiC MOSFET is more robust andreliable in high power, high voltage, and high switching frequency applications.The SCANIA’s second generation DC-DC converter has shown advantages overthe first generation; it is more efficient, lighter, and more compact. From thereliability point of view, the second generation has passed almost all relevanttests.
En DC-DC-omvandlare används i elektrifierade fordon för att ge ström åt dess lågspänningssystem (ex. 24V) vilket kan omfatta bl.a. inklusive strålkastare, horn, luftkonditioneringssystem, vindrutetorkare, radio etc. Omvandlaren matas från fordonets högspänningsbatteri (ex 650VDC) och överför en relativt hög ef- fekt till lågspänningssystemet. SCANIAs befintliga omvandlare använder sig av kiselbaserade transistorer (Si IGBT), och det finns en avsikt att ersätta omvandlaren med en uppgraderad motsvarighet vid vilken kiselkarbidbaserade transistorer (SiC MOSFET) används istället. SiC-baserade halvledarmaterial erbjuder bl.a. möjlighet till högre switch-frekvenser, högre drifttemperatur och högre spänningstålighet. I denna avhandling utreds tillförlitligheten av SiC-baserade transistorer som används i DC-DC-omvandlare inom elektrifier- ade fordonsbranschen. Undersökningen baseras huvudsakligen på resultat från olika tillförlitlighetstester utförda på både transistor- och omvandlarnivå. För att undersöka och analysera tillförlitligheten hos SiC MOSFET-transistorer har olika felmekanismer såsom nedbrytning av ”gate oxid”-skiktet, högfrekventa biverkningar, etc., presenterats och diskuterats tillsammans med motsvarande testresultat. För jämförelse har man på omvandlarnivå, utrett tillförlitligheten av Scania’s befintliga omvandlare och identifierat dess svaga komponenterna. I denna studie har testresultaten, som tillhandahålls av leverantörer av SiC- MOSFET transistorer, analyserats och jämförts med liknande testresultat som har genomförts på Si-baserade omvandlare. Utöver det utför Scania vissa speci- fika tester som är baserade på egna standardiserade prover, för att försäkra sig om omvandlarens mognad och robusthet. Dessa är relaterade till olika miljöförhållanden, t.ex. hög omgivningstemperatur och hög vibrationsnivå. Testresultaten presenteras och diskuteras i avhandlingen. Genom att jämföra testresultat från olika leverantörer kan man dra slutsatsen att SiC MOSFET-transistorer är effektivare än Si-transistorer. Dessutom visade sig att SiC MOSFET är mer robust och tillförlitlig i applikationer som kräver högre effekter, högre spänningar och högre switching-frekvenser. Den andra generationen av Scania’s DC-DC-omvandlare har visat flera förde- lar över den första generationen; nämligen att den är mer effektiv, lättare, mer kompakt och billigare. Från ett tillförlitlighetsperspektiv har den andra generationen har passerat nästan alla relevanta tester.

Ce mémoire de thèse s'inscrit dans le cadre du programme « avion plus électrique », il comprend deux parties.La première est consacrée à la présentation détaillée du contexte, c'est-à-dire du processus qui conduit à électrifier la plupart des systèmes présents dans l'avion, un exemple d'actionneur électromécanique spécifique, conçu dans ce cadre sera aussi détaillé notamment pour ce qui concerne son mode d'alimentation. La seconde partie, plus longue, est consacrée à différents processus de fiabilisation de structures d'électroniques de puissance. Du fait de l'électrification croissante de l'avion, ces structures vont se multiplier à bord, mais la fiabilité connue de ces dispositifs n'est pas apte à satisfaire aux exigences de l'aéronautique. Les processus de fiabilisation, dans leur majorité, sont orientés, en cas de panne, vers un isolement de la source du défaut, pour permettre un fonctionnement en mode dégradé, supporté par le système. Par ailleurs, un dispositif de sécurisation de bras d'onduleur est décrit : un sectionneur commandé à thyristors et fusible (SCTF2). Ce système permet d'isoler électriquement le bras d'onduleur victime d'un défaut au sein d'un onduleur triphasé. L'emplacement de prédilection du SCTF2 est la connexion bras d'onduleur et bus continu d'alimentation. Les simulations de ce système de fiabilisation sont menées sur PSIM. Ce mémoire propose des modélisations approchées, pour l'outil de CAO adopté, des composants IGBT et fusibles, lorsque ces derniers sont soumis à un régime de courant extrême (court-circuit)
This manuscript of thesis was written in two parts for the "More Electric Aircraft" program. The first part presents in great detail the context of the thesis that is (i.e) the processes which allow electrifying the most of classic aircraft-systems. In this part, an example of special electromechanical actuator build in the More Electric aircraft program will be presented with meticulous care, in particular its command and supply systems. The second part, more extensive, is devoted to various solutions which improve the reliability of the power-electric systems. With the growth of the electrification of the aircrafts, several solutions of this kind will be multiplicated on board, but today most of these solutions haven't the reliability intended to the aeronautical applications. For the most part, the reliability processes consist in isolating the origins of a breakdown, in order that the system can continue to work in a debased mode. In addition, a system which protects inverter's legs is described; it's a controlled circuit breaker which uses thyristors and fuses (SCTF2). This system of reliability allows electrical isolating of faulty inverter's leg in a three phase inverter. The preferential position of a SCTF2 is the connexion between inverter's leg and the DC bus. Simulations of the SCTF2 are done on PSIM software. For PSIM, this manuscript poposes some approximative modelisations of the components like IGBT and fuse when they are subjected to a dangerous high-current (short-circuit)

En raison de l'attrait croissant pour les applications haute tension, haute tempé-rature et haute fréquence, le carbure de silicium (SiC) continue d'attirer l'attention du monde entier comme l'un des candidats les plus compétitifs pour remplacer le sili-cium dans le champ électrique de puissance. Entre-temps, il est important de carac-tériser les défauts des semi-conducteurs et d'évaluer leur influence sur les dispositifs de puissance puisqu'ils sont directement liés à la durée de vie du véhicule porteur. De plus, la fiabilité, qui est également affectée par les défauts, devient une question incontournable dans le domaine de l'électricité de puissance.Les défauts, y compris les défauts ponctuels et les défauts prolongés, peuvent introduire des niveaux d'énergie supplémentaires dans la bande passante du SiC en raison de divers métaux comme le Ti, le Fe ou le réseau imparfait lui-même. En tant que méthode de caractérisation des défauts largement utilisée, la spectroscopie à transitoires en profondeur (DLTS) est supérieure pour déterminer l'énergie d'activa-tion Ea , la section efficace de capture Sigma et la concentration des défauts Nt ainsi que le profil des défauts dans la région d'épuisement grâce à ses divers modes de test et son analyse numérique avancée. La détermination de la hauteur de la barrière Schottky (HBS) prête à confusion depuis longtemps. Outre les mesures expérimentales selon les caractéristiques I-V ou C-V, différents modèles ont été proposés, de la distribution gaussienne du HBS au modèle de fluctuation potentielle. Il s'est avéré que ces modèles sont reliés à l'aide d'une hauteur de barrière à bande plate Phi_BF . Le tracé de Richardson basé sur Phi_BF ainsi que le modèle de fluctuation potentielle deviennent un outil puissant pour la caractérisation HBS. Les HBSs avec différents contacts métalliques ont été caractéri-sés, et les diodes à barrières multiples sont vérifiées par différents modèles. Les défauts des électrons dans le SiC ont été étudiés avec des diodes Schottky et PiN, tandis que les défauts des trous ont été étudiés dans des conditions d'injec-tion forte sur des diodes PiN. 9 niveaux d'électrons et 4 niveaux de trous sont com-munément trouvés dans SiC-4H. Une relation linéaire entre le Ea extrait et le log(sigma) indique l'existence de la température intrinsèque de chaque défaut. Cependant, au-cune différence évidente n'a été constatée en ce qui concerne l'inhomogénéité de la barrière à l'oxyde d'éther ou le métal de contact. De plus, les pièges à électrons près de la surface et les charges positives fixes dans la couche d'oxyde ont été étudiés sur des MOSFET de puissance SiC par polarisation de porte à haute température (HTGB) et dose ionisante totale (TID) provoquées par irradiation. Un modèle HTGB-assist-TID a été établi afin d'ex-plain l'effet de synergie
Due to the increasing appeal to the high voltage, high temperature and high fre-quency applications, Silicon Carbide (SiC) is continuing attracting world’s attention as one of the most competitive candidate for replacing silicon in power electric field. Meanwhile, it is important to characterize the defects in semiconductors and to in-vestigate their influences on power devices since they are directly linked to the car-rier lifetime. Moreover, reliability that is also affected by defects becomes an una-voidable issue now in power electrics. Defects, including point defects and extended defects, can introduce additional energy levels in the bandgap of SiC due to various metallic impurities such as Ti, Fe or intrinsic defects (vacancies, interstitial…) of the cristalline lattice itself. As one of the widely used defect characterization method, Deep Level Transient Spectroscopy (DLTS) is superior in determining the activation energy Ea , capture cross section sigma and defect concentration Nt as well as the defect profile in the depletion region thanks to its diverse testing modes and advanced numerical analysis. Determination of Schottky Barrier Height (SBH) has been confusing for long time. Apart from experimental measurement according to I-V or C-V characteristics, various models from Gaussian distribution of SBH to potential fluctuation model have been put forward. Now it was found that these models are connected with the help of flat-band barrier height Phi_BF . The Richardson plot based on Phi_BF along with the potential fluctuation model becomes a powerful tool for SBH characterization. SBHs with different metal contacts were characterized, and the diodes with multi-barrier are verified by different models. Electron traps in SiC were studied in Schottky and PiN diodes, while hole traps were investigated under strong injection conditions in PiN diodes. 9 electron traps and 4 hole traps have been found in our samples of 4H-SiC. A linear relationship between the extracted Ea and log(sigma) indicates the existence of the intrinsic temper-ature of each defects. However, no obvious difference has been found related to ei-ther barrier inhomogeneity or contact metal. Furthermore, the electron traps near in-terface and fixed positive charges in the oxide layer were investigated on SiC power MOSFETs by High Temperature Gate Bias (HTGB) and Total Ionizing Dose (TID) caused by irradiation. An HTGB-assist-TID model was established in order to ex-plain the synergetic effect

Microelectronic systems are subjected to thermal cycling, power cycling, and vibration environments in various applications. These environments, whether applied sequentially or simultaneously, affect the solder joint reliability. Literature is scarce on predicting solder joint fatigue failure under such multiple loading environments. This thesis aims to develop a unified modeling methodology to study the reliability of electronic packages subjected to thermal cycling, power cycling, and vibration loading conditions. Such a modeling methodology is comprised of an enriched material model to accommodate time-, temperature-, and direction-dependent behavior of various materials in the assembly, and at the same time, will have a geometry model that can accommodate thermal- and power-cycling induced low-cycle fatigue damage mechanism as well as vibration-induced high-cycle fatigue damage mechanism. The developed modeling methodology is applied to study the reliability characteristics of ceramic area array electronic packages with lead-based solder interconnections. In particular, this thesis aims to study the reliability of such solder interconnections under thermal, power, and vibration conditions individually, and validate the model against these conditions using appropriate experimental data either from in-house experiments or existing literature. Once validated, this thesis also aims to perform a design of simulations study to understand the effect of various materials, geometry, and thermal parameters on solder joint reliability of ceramic ball grid array and ceramic column grid array packages, and use such a study to develop universal polynomial predictive equations for solder joint reliability. The thesis also aims to employ the unified modeling methodology to develop new understanding of the acceleration factor relationship between power cycling and thermal cycling. Finally, this thesis plans to use the unified modeling methodology to study solder joint reliability under the sequential application of thermal cycling and vibration loading conditions, and to validate the modeling results with first-of-its-kind experimental data. A nonlinear cumulative damage law is developed to account for the nonlinearity and effect of sequence loading under thermal cycling, power cycling, and vibration loading.

Dynamic Rating (DR) is usually associated with unlocking the capacity of power lines and transformers using available information on weather conditions. Our studies show that Dynamic Rating is a broad concept that requires further study and development. The capacity of the majority of power devices is highly dependent on the heat transfer properties of the materials which the devices are made of. To ensure correct power limits of the equipment, one must take into consideration not only the power load, but also ambient conditions, such as: temperature, wind speed, wind direction, solar irradiation, humidity, pressure, radiation into the atmosphere and magnetic losses. Dynamic rating is created as an alternative to standard constant rating that is designed with reference to extreme weather and load conditions. Some areas are more likely than others to experience extreme weather conditions, which have a chance of occurring only a few days per year for short periods of time. Such a distribution of weather parameters gives an opportunity to embed existing material properties of the power equipment and achieve a better utilization of the grid. The following thesis is divided into two simultaneous topics: Dynamic line rating and Dynamic transformer rating. The division is motivated by the importance of analysing the operation of the above-mentioned parts of the power network in greater detail. Power lines and transformers play a significant part in grid planning and have a potential to result in economic benefits when used with DR. The main focus of the doctoral project "Dynamic rating of power lines and transformers for wind energy integration" is on exploring potential ways to connect power generated from wind to the grid with the help of dynamic rating technologies. Therefore, great focus of the work lies on the analysis of DR connection of variable energy sources such as wind farms. The thesis presents the comparison of different line rating methods and proposes a new way of their classification. Evaluation of dynamic line rating application has shown the possibility to expand the power grid with additional capacity from wind power generation. Literature analysis and detailed evaluation of the conductor heat balance models have led to experimental evaluation of the convective cooling effect. The dynamic transformer rating application has shown a possibility to decrease the size of the power transformer without shortcoming in component availability.

QC 20180423

Dynamic Rating for Wind Power

Ce manuscrit est une contribution à l’étude de la fiabilité et de la robustesse des composants MOSFET sur carbure de silicium, matériau semi-conducteur grand gap qui possède des caractéristiques bien meilleures que le silicium. Ces nouveaux interrupteurs de puissances permettent d’obtenir entre autres propriétés remarquables, des fréquences de commutations et des tenues en tension plus élevées dans les systèmes de conversions de puissance. Ils sont particulièrement mis en avant depuis un peu plus d’une dizaine d’années pour les gains en performances, diminution des tailles et poids qu’ils apportent à certaines topologies de convertisseurs pour les réseaux haute tension à courant continu. Puis sont répertoriés les principaux mécanismes de défaillances de ces MOSFET SiC induits par la faiblesse de la grille. Toutes les mesures nécessaires au suivi des paramètres clés lors des prochains vieillissements sont présentées. Les résultats de nos tests sur l’instabilité de la tension de seuil sont aussi détaillés et un modèle empirique pour valider le comportement de relaxation observé est proposé. Celui-ci nous aidera par la suite à établir un protocole de mesure rigoureux de la tension de seuil. Les tests expérimentaux et résultats de vieillissement en statique et dynamique sur les composants 1,7 kV vont permettre de se rendre compte de l’importance de la dérive de la tension de seuil sur 1000 h. Dans le cas d’un vieillissement statique, il y a environ 7 % de dérive positive du VTH et un pourcentage équivalent pour les tests dynamiques. Des analyses supplémentaires (C-V et pompage de charge) sur l’oxyde de grille en cours de vieillissement sont proposées pour une meilleure compréhension des mécanismes mis en jeu dans la dégradation de l’oxyde. Enfin, les derniers tests présentés seront focalisés sur le comportement en court-circuit et courts-circuits répétitifs des mêmes composants. Avec une énergie critique évaluée autour de 1,5 J nos tests sur les MOSFET 1,7 kV montrent les limites de la robustesse de ces composants, avec une tenue en court-circuit bien inférieure à 10 µs et une incapacité à résister à plus de 150 courts-circuits successifs. L’influence de la tension entre drain et source y est notamment étudiée, et montre que l’énergie critique supportée par le composant diminue avec l’augmentation de cette tension
This manuscript is a contribution to reliability and robustness study of MOSFET components on silicon carbide “SiC”, wide band gap semiconductor with better characteristics compared to silicon “Si” material. Those new power switches can provide better switching frequencies or voltage withstanding for example in power converter. SiC MOSFET are the results of approximately 10 years of research and development and can provide increased performances and weight to some converter topology for high voltage direct current networks. Others power switches available are still introduced and an introduction to reliability is explaining why such work on this new power switches is important. Transition from Si technologies to SiC ones require a lot of work regarding its robustness. Before showing reliability and robustness results is presented I give a lot of details regarding to the measurement and monitoring of key parameters used in the next chapters. The results of our tests on the threshold voltage instability are presented and how we validated an empirical model on this drift. This was used to propose an enhanced measurement protocol on the threshold voltage. Static and dynamic experimental results presented next will show if the voltage drift during ageing is significant or not. Further analysis is proposed to add more insight on the understanding of the oxide degradation mechanisms through C-V and charge pumping measurements. Finally, the ageing results presented on 1,7 kV SiC MOSFET are focused on the short-circuit and repetitive short-circuit behavior of the same components. Drain to source voltage influence on critical energy during this particular and stressful operation mode is studied. This time, the results are worrying.The last chapter is confidential

The supply of electricity is important in modern society, so the outages of the electric grid should be few and short, especially for the transmission grid. A summary of the history of the Swedish electrical system is presented. The objective is to be able to plan the maintenance better by following the condition of the equipment. The risk matrix can be used to choose which component to be maintained. The risk matrix is improved by adding a dimension, the uncertainty of the probability. The risk can be reduced along any dimension: better measurements, preventive maintenance or more redundancy. The number of dimensions can be reduced to two by following iso-risk lines calculated for the beta distribution. This thesis lists twenty surveys about circuit breakers and disconnectors, with statistics about the failures and the lifetime. It also presents about forty condition-measuring methods for circuit breakers and disconnectors, mostly applicable to the electric contacts and the mechanical parts. A method for scheduling thermography based on analysis of variance of the current is tried. Its aim is to reduce the uncertainty of thermography and it is able to explain two thirds of the variation using the time of the day, the day of the week and the week number as explanatory variables. However, the main problem remains as the current is in general too low. A system with IR sensors has been installed at the nine contacts of six disconnectors with the purpose of avoiding outages for maintenance if the contacts are in a good condition. The measured temperatures are sent by radio and regressed against the square of the current, the best exponent found. The coefficient of determination $R^2$ is high, greater than 0.9. The higher the regression coefficient is, the more heat is produced at the contact. So this ranks the different contacts. Finally a framework for lifetime modelling and condition measuring is presented. Lifetime modelling consists in associating a distribution of time to failure with each subpopulation. Condition measuring means measuring a parameter and estimating its value in the future. If it exceeds a threshold, maintenance should be carried out. The effect of maintenance of the contacts is shown for four disconnectors. An extension of the risk matrix with uncertainty, a survey of statistics and condition monitoring methods, a system with IR sensors at contacts, a thermography scheduling method and a framework for lifetime modelling and condition measuring are presented. They can improve the planning of outages for maintenance. Finally a framework for lifetime modelling and condition measuring is presented. Lifetime modelling consists in associating a distribution of time to failure with each subpopulation. Condition measuring means measuring a parameter and estimating its value in the future. If it exceeds a threshold, maintenance should be carried out. The effect of maintenance of the contacts is shown for four disconnectors. An extension of the risk matrix with uncertainty, a survey of statistics and condition monitoring methods, a system with IR sensors at contacts, a thermography scheduling method and a framework for lifetime modelling and condition measuring are presented. They can improve the planning of outages for maintenance.
Elförsörjningen är viktig i det moderna samhället, så avbrotten bör vara få och korta, särskilt i stamnätet. En kortfattad historik över det svenska elsystemet presenteras. Målet är att kunna planera avbrotten för underhåll bättre genom att veta mera om apparaternas skick. Det är svårt att planera avbrott för underhåll och utbyggnad. Riskmatrisen är verktyg för att välja vad som ska underhållas och den kan förbättras genom att lägga till en dimension, sannolikhetens osäkerhet. Risken kan minskas längs med varje dimension: bättre mätningar, förebyggande underhåll och mer redundans. Antalet dimensioner kan igen bli två genom att följa linjer med samma risk, som är beräknade för betafördelningen. Denna avhandling tar upp tjugo studier av fel i brytare och frånskiljare med data om felorsak och livslängd. Den har också en översikt av ett fyrtiotal olika metoder för tillståndsmätningar för brytare och frånskiljare, som huvudsakligen rör de elektriska kontakterna och de mekaniska delarna. Ett system med IR sensorer har installerats på de nio kontakterna på sex frånskiljare. Målet är att minska antalet avbrott för underhåll genom att skatta skicket när frånskiljarna är i drift. De uppmätta temperaturerna tas emot genom radio och behandlas genom regression mot kvadraten av strömmen, då den bästa exponenten för strömmen visade sig vara 2,0. Förklaringsfaktorn $R^2$ är hög, över 0,9. För varje kontakt ger det en regressionskoefficient. Ju högre koefficienten är, desto mer värme utvecklas det i kontakten, vilket kan leda till skador på materialet. Koefficienterna ger en rangordning av frånskiljarna. Systemet kan också användas för att minska eller öka den tillåtna strömmen baserat på skicket. Slutligen förklaras ett ramverk för livslängdsmodellering och tillståndsmätning. Livslängdsmodellering innebär att koppla en fördelning för tiden till fel med varje delpopulation. Med tillståndsmätning avses att mäta en parameter och skatta dess värde i framtiden. Om den överskrider en tröskel, måste apparaten underhållas. Effekten av underhåll visas för fyra frånskiljare. En utveckling av riskmatrisen med osäkerheten, en sammanställning av statistik och metoder för tillståndsövervakning, ett system med IR-sensor vid kontakerna, en metod för termografiplanering och ett ramverk för livslängdsmodellering och tillståndsmätningar presenteras. De kan förbättra avbrottsplaneringen.
El suministro de energía eléctrica es importante en la sociedad moderna. Por eso los cortes eléctricos deben ser poco frecuentes y de poca duración, sobre todo en la red de transmisión. Esta tesis resume la historia del sistema eléctrico sueco. El objetivo es planificar los cortes mejor siguiendo la condición de los aparatos. La matriz de riesgo se utiliza muchas veces para escoger en qué aparatos debería realizarse mantenimiento. Esta matriz se puede mejorar añadiendo una dimensión: la incertidumbre de la probabilidad. El riesgo puede ser disminuido siguiendo cada una de las tres dimensiones: mejores mediciones, mantenimiento preventivo y mayor redundancia. El número de dimensiones puede reducirse siguiendo líneas del mismo riesgo calculadas para la distribución beta. Esta tesis presenta veinte estudios de fallos en interruptores y seccionadores con datos sobre la causa y el tiempo hasta la avería. Contiene también una visión general de cuarenta métodos para medir la condición de seccionadores e interruptores, aplicables en su mayoría a los contactos eléctricos y los componentes mecánicos. Se ha instalado un sistema con sensores infrarrojos en los seis contactos de nueve seccionadores. El objetivo es disminuir los cortes de servicio para mantenimiento, estimando la condición con el seccionador en servicio. Las temperaturas son transmitidas por radio y se hace una regresión con el cuadrado de la corriente, ya que el mejor exponente de la corriente resultó ser 2,0. $R^2$ alcanza un valor de 0,9 indicando un buen ajuste de los datos por parte del modelo. Existe un coeficiente de regresión para cada contacto y este sirve para ordenar los contactos según la necesidad de mantenimiento, ya que cuanto mayor sea el coeficiente más calor se produce en el contacto. Finalmente se explica que el modelado de tiempo hasta la avería consiste en asignar una distribución estadística a cada equipo. La monitorización del estado consiste en medir y estimar un parámetro y luego predecir su valor en el futuro. Si va a sobrepasar un cierto límite, el equipo necesitará de mantenimiento. Se presenta el efecto de mantenimiento de cuatro seccionadores. Un desarrollo de la matriz de riesgo, un conjunto de estadísticas y métodos de monitoreo de condición, un sistema de sensores IR situados cerca de los contactos, en método de planificación de termografía y un concepto para explicar la modelización de tiempo hasta la avería y de la monitorización de la condición han sido presentados y hace posible una mejor planificación de los cortes de servicio.

QC 20170928

Un des enjeux majeur de l’électronique de puissance est de pouvoir étendre l’utilisation des modules de puissance à haute température, supérieure à 200°C. Or, en température, l’endommagement des joints de brasure est un des principaux modes de défaillance des modules de puissance. C’est pourquoi, l’objectif de cette thèse consiste à développer un procédé d’assemblage alternatif : le procédé de report intermétallique (IMC) en phase liquide transitoire (TLPB) à partir du système binaire cuivre-étain. Ce procédé est très attractif car il permet de former à basse température (250°C), un joint entièrement constitué de phases IMCs qui sont réputées pour leur stabilité à très haute température (supérieure à 600°C pour la phase Cu3Sn). Afin d’optimiser le procédé, l’influence des paramètres d’assemblage sur les mécanismes de croissance des phases IMCs a été déterminée. Cette étude a permis de mettre en évidence la nécessité d’insérer une barrière de diffusion de type IMC entre les substrats et le métal d’apport afin de modifier les processus de diffusion atomique aux interfaces et ainsi d’éviter la formation d’une importante porosité au sein des joints IMCs. Après avoir mis au point un procédé de report innovant et optimal, la fiabilité des assemblages IMCs a été évaluée à partir d’essais expérimentaux et de modèles numériques par éléments finis. Il a été montré que la fiabilité en cyclage thermique des joints IMCs est très supérieure à celle des alliages de brasure de référence SnAgCu. Le procédé de report IMC développé au cours de cette thèse est donc un excellent candidat au remplacement des alliages de brasure pour des applications à haute température
To meet the future requirements of power electronics, the packaging technologies of power modules must withstand higher operation temperatures, higher than 200°C. However, an increase of the operation temperatures leads to a significant decrease of the solder joints reliability and thus to the failure of the power modules. That’s why the main objective of this PhD thesis is to develop an alternative bonding technic for high temperature applications: the Transient Liquid Phase Bonding process (TLPB) based on the copper-tin binary system. This process is very attractive because it allows the formation, at low temperature, of a joint entirely composed of intermetallic (IMC) compounds which are well known for their high thermal stability. To optimize the process, the influence of the main bonding parameters on the growth of the IMC phases has been first investigated. The results indicate that the deposition of an IMC diffusion barrier is required to alter the atomic diffusion motion at the interfaces between the Cu substrates and the Sn interlayer and to avoid the formation of large pores along the bond mid-plane. After the development of an innovative and optimal bonding process, the reliability of the IMC assemblies has been investigated through experimental tests and finite element simulations. The IMC joints show a higher thermal cycling reliability than the reference SnAgCu solder alloys. Hence, the IMC bonding process developed during this PhD thesis is an excellent alternative to the soft solder alloys for high temperature applications

L’intégration des dispositifs électroniques de puissance dans les véhicules automobiles nécessite une connaissance approfondie de leur fiabilité. Ces éléments sont soumis à des contraintes de fatigue électrothermique de plus en plus importantes. Cette étude vise à caractériser l’évolution de composants à base de MOSFET lors de tests de fatigue accélérés et contrôlés afin de déterminer les mécanismes physiques qui conduisent à sa dégradation.Nous décrivons d'abord l’évolution technologique des composants électroniques de puissance jusqu’à la technologie de type SmartMos utilisée par Freescale Semiconductor aujourd'hui. Les outils de caractérisation microstructurale (SAM, SAT, SEM, SIM, TEM, …) sont ensuite détaillés ainsi que l'échelle spécifique pour laquelle ils sont utilisés.Le vieillissement accéléré des composants est effectué sur un banc de fatigue pour déterminer la durée de vie d'un composant selon des paramètres donnés. L'analyse complète des composants détruits a permis de conclure que la zone affectée en priorité par le cyclage électro-thermique est le métal source qui comprend la métallisation en aluminium et les fils d'amenée de courants. Ces mêmes zones sont ensuite examinées après un vieillissement contrôlé correspondant à une fraction de la durée de vie. La fatigue du composant est essentiellement caractérisée par une forte augmentation de la résistance du métal source qui engendre l’augmentation de sa résistance drain-source (RdsON). Nous avons expliqué ce phénomène par une dégradation de la métallisation qui consiste en une division des grains d'aluminium et à l’apparition de fissures le long des joints de grains.Ces caractérisations sont corrélées à une étude par éléments finis (FEM) qui permet de simuler l’augmentation et le gradient de température dans un composant pendant un cycle de vieillissement, ainsi que l’impact de l’élévation de la résistance de la métallisation source sur le comportement thermoélectrique du composant
Integration of power electronic devices in automotive applications requires a perfect knowledge of their reliability as these components are subjected to more drastic electrothermal stresses. This study aims at determining the physical mechanisms responsible for degradation and failure of modern MOSFET-based power microprocessors during accelerated and controlled fatigue tests.After a description of the recent developments in power electronics that led to today's SmartMos technology from Freescale Semiconductor, the different microstructural characterizing techniques (SAM, SAT, SEM, SIM, TEM, …) and the specific scale for which they are used are detailed.The accelerated ageing of the components were carried out on a fatigue bench to evaluate the component lifetime according to parameters such as the temperature, current and pulse durations. A complete analysis of failed components showed that the area which is primarily affected by the electro-thermal cycling is the metal source that includes aluminum metallization and connection wires. In controlled ageing tests, we showed that the drain-source resistance (Rdson) increase was due to the metal source resistance augmentation. This phenomenon is linked to the degradation of the Aluminum layer that happens through grains division and crack propagation along the grain boundaries

Actuellement, dans les plateformes aérospatiales, le nombre et le besoin d’intégration des équipements électriques et électroniques sont grandissant du fait que leurs fonctions nécessitent de plus en plus de puissance. L’objectif de minimisation des coûts et surtout la disponibilité des dispositifs électroniques forcent les concepteurs et les fabricants de ces plateformes à s’orienter vers des produits commerciaux (dits grand public). La fiabilité des boîtiers des composants de puissance doit être évaluée dans les environnements sévères des applications aérospatiales. Une dizaine de composants électroniques de puissance a été sélectionnée en fonction de leur disponibilité et l’adéquation de leurs performances électriques et thermiques aux exigences des applications aérospatiales. Ces composants intègrent différents types de semi-conducteurs tels que le silicium, le carbure de silicium et le nitrure de gallium. Tout d’abord, une étude a été menée sur les potentiels modes et mécanismes de défaillance de ces composants électroniques de puissance dans ces environnements. Elle a permis de mettre en place plusieurs procédures de vieillissement accéléré ainsi que le développement de deux bancs de tests pour suivre électriquement le vieillissement de ces composants. Ces tests ont été menés sur deux diodes Schottky SiC, commercialisées par deux fabricants, regroupant les technologies des boîtiers des composants électroniques de puissance. Les analyses de défaillance ont tout d’abord mis en évidence une immaturité de la technologie de la jonction Schottky des puces SiC de l’une des deux diodes soumis à une tension inverse. Ces défaillances sont attribuées à la destruction partielle de la structure Schottky et indique une reproductibilité non maitrisée de la fabrication des puces de ce composant. Ensuite, ces analyses ont mis en évidence plusieurs mécanismes de vieillissement lors de tests simulant des régimes « On-Off » des applications (cycles thermiques de puissance). Celui considéré comme la cause de la défaillance est la fissuration de la soudure des fils d’interconnexion avec la puce. Une loi pouvant décrire la fissuration des interconnexions a été identifiée à la suite des évolutions des cycles thermiques de puissance à l’approche de la défaillance. L’étude de ces évolutions a permis de démarrer l’élaboration d’un modèle physique de défaillance adapté aux interconnexions de la puce en vue d’estimer la durée de vie des composants commerciaux.

Physical asset management in the electric power sector encompasses the scheduling of the maintenance and replacement of grid components, as well as decisions about investments in new components. Data plays a crucial role in these decisions. The importance of data is increasing with the transformation of the power system and its evolution toward smart grids. This thesis deals with questions related to data management as a way to improve the performance of asset management decisions. Data management is defined as the collection, processing, and storage of data. Here, the focus is on the collection and processing of data. First, the influence of data on the decisions related to assets is explored. In particular, the impacts of data quality on the replacement time of a generic component (a line for example) are quantified using a scenario approach, and failure modeling. In fact, decisions based on data of poor quality are most likely not optimal. In this case, faulty data related to the age of the component leads to a non-optimal scheduling of component replacement. The corresponding costs are calculated for different levels of data quality. A framework has been developed to evaluate the amount of investment needed into data quality improvement, and its profitability. Then, the ways to use available data efficiently are investigated. Especially, the possibility to use machine learning algorithms on real-world datasets is examined. New approaches are developed to use only available data for component ranking and failure prediction, which are two important concepts often used to prioritize components and schedule maintenance and replacement. A large part of the scientific literature assumes that the future of smart grids lies in big data collection, and in developing algorithms to process huge amounts of data. On the contrary, this work contributes to show how automatization and machine learning techniques can actually be used to reduce the need to collect huge amount of data, by using the available data more efficiently. One major challenge is the trade-offs needed between precision of modeling results, and costs of data management.

QC 20210330

Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2009.
Source: Dissertation Abstracts International, Volume: 70-06, Section: B, page: 3699. Includes bibliographical references (leaves 116-123) Available on microfilm from Pro Quest Information and Learning.

Dottorato in Tecnologie dell’informazione e della comunicazione, Ciclo XXXI
The wide spectrum of power electronics applications, including their role in renewable energy conversion and energy saving, require the innovation from conventional Silicon (Si) technology into new materials and architectures that allow the fabrication of increasingly lightweight, compact, efficient and reliable devices. However, the trade-off between long lifetime, high performance and low cost in the emerging technologies represents a huge limitation that has gained the attention of different research groups in the last years. Gallium Nitride (GaN) is a wide-bandgap semiconductor (WBGS) that constitutes an excellent candidate for high-power and high-frequency applications due to its remarkable features such as high operating temperature, high dielectric strength, high current density, high switching speed, and low on-resistance. Compared with its Silicon counterpart, GaN is superior in terms of high breakdown field ( 3 MV/cm), exceptional carrier mobility, and power dissipation. By taking into account other WBG materials such as SiC, GaN grown on Si substrates promises similar performance but at a much lower cost in the low to mid power and high-frequency range. Since GaN allows size and weight device reduction due to a better relationship between on-resistance and breakdown voltage, it is suitable for a variety of applications such as RF power amplifiers, power switching systems, sensors, detectors, etc. Especially, in the field of energy efficiency, GaN technology appears as a future successor of Si in power conversion circuits. However, some drawbacks related to technology cost, integration, and long-term reliability have to be overcome for its wide adoption in the power applications market. One of the worst inconveniences of AlGaN/GaN High Electron Mobility Transistors (HEMTs) is the normally-ON operation. Since a two-dimensional electron gas (2DEG) channel is formed at the AlGaN/GaN interface due to inherent material properties, a negative bias has to be applied at the gate to switch the device off. Among the proposed solutions to fabricate normally-OFF devices, the metaloxide/ insulator-semiconductor (MOS/MIS) structure with different insulators has shown remarkable improvements in gate leakage reduction and drain current increase. Also in AlGaN/GaN Schottky Barrier Diodes (SBDs), the introduction of a MOS structure to create a gated edge termination (GET) at the anode area has resulted in significant improvements in reverse diode leakage and forward diode voltage. Nevertheless, the improvement in the device performance by the introduction of a dielectric could seriously affect the device long-term reliability since additional degradation in this layer and at its interfaces with AlGaN or GaN occurs. In the case of conversion systems, power devices are continuously switched from an OFF-state condition at high drain bias to an ON-state condition at large drain current. Therefore, the reliability of GaN-based devices has to be proven for the complete ON/OFF operation. This dissertation focuses on providing a more comprehensive analysis of two main reliability issues related to the dielectric insertion under the gate/anode stacks by analyzing the use of different dielectric materials and device architectures. The first issue is the positive bias temperature instability (PBTI), which is related to the degradation of electrical parameters when high gate voltages and temperatures are applied and is especially observed during the ON-state operation of the transistor. By using MOS-HEMT structures with different gate dielectrics (SiO2, Al2O3, and AlN/Al2O3), the impact of the stress voltage, recovery voltage and temperature on the device reliability is analyzed including the role of oxide traps and the interface states to provide physical insights into this mechanism. The second phenomenon discussed in this thesis is the time-dependent dielectric breakdown (TDDB) observed on GET-SBDs during its OFF-operation. The percolation model and Weibull distribution are used to understand this degradation mechanism. As a result, it has been demonstrated that the time to breakdown tBD is influenced by the GET structure (single vs. double), the passivation thickness, the preclean process at the anode region before the GET dielectric deposition and the capping layer. Finally, by using 2D TCAD simulations, the long-term reliability improvement has been related to the reduction of the electric fie
University of Calabria

The purpose of this investigation is to introduce a new approach to model the bus load correlation in performing a reliability analysis of composite systems. This is achieved by considering different time varying load curves (referred to as the multi-dimensional load profile), corresponding to different types of loads in a composite generation and transmission system and applying the contingency enumeration technique for reliability analysis. The proposed technique determines the appropriate load levels and the corresponding geographical distribution of the loads among different buses (load states) at which the contingency analysis needs to be performed TRELSS (Transmission Reliability Analysis of Large Scale Systems), a software package developed by EPRI, is used to perform the contingency analysis on the IEEE 25 bus Modified Reliability Test System. The adequacy indices Frequency of Load Curtailment (FLC), Probability of Load Curtailment (PLC) and Expected Unserved Energy (EUE) are evaluated in this investigation. The accuracy of the results obtained by the proposed load model is determined by comparisons to results obtained by performing a detailed hour by hour contingency analysis of the system. It is shown that the proposed technique produces better results than the existing methods without spending excessive computational time. A set of algorithms and corresponding programs in MATLAB which use TRELSS for contingency enumeration and incorporates the proposed load modeling procedure is developed
acase@tulane.edu

Lastwechseltests stellen eine standardisierte und etablierte Methode zur Zuverlässigkeitsbewertung und Produktqualifizierung in der Leistungselektronik dar. Sie basieren auf der Applikation von wiederkehrenden Laststromimpulsen, welche im Leistungsbauelement in zyklischen Temperaturschwankungen umgesetzt werden. Die dabei induzierten thermo-mechanischen Spannungen, hervorgerufen durch die unterschiedlichen Werkstoffeigenschaften der im Verbundsystem beteiligten Fügepartner, führen letztendlich zu den typischen Versagensmechanismen in der Aufbau- und Verbindungstechnik. Herkömmliche Lastwechseltests bilden allerdings die komplexen Belastungssituationen unter Feldbedingungen, in welchen unterschiedliche Lastfaktoren simultan auftreten, nur ungenügend nach. Im Kontext der Einführung neuartiger Bauelement- und Package-Technologien, rauer werdenden Umgebungsbedingungen sowie steigenden Zuverlässigkeits- und funktionalen Sicherheitsanforderungen ergibt sich somit der Bedarf an verbesserten Methoden zur Zuverlässigkeitstestbewertung. Ein möglicher Ansatz besteht in der Kombination verschiedener Belastungsarten, mit dem Ziel, Testeffizienz sowie Testabdeckung zu erhöhen. Im Rahmen dieser Arbeit wurden daher unter Verwendung eines selbstentwickelten Lastwechselteststandes systematische Lastwechseltestuntersuchungen, sowohl in standardmäßiger Ausführung als auch mit überlagerten passiven Temperaturzyklen, an diskreten Leistungsbauelementen durchgeführt. Neben der Untersuchung unterschiedlicher Sperrschichttemperaturprofile erfolgte auch ein Vergleich unterschiedlicher Bauelementtypen. Auf Basis einer qualitativen und quantitativen Testauswertung wurden belastungsbasierte Lebensdauermodelle aufgestellt. Dabei zeigte sich, dass die den Standard-Lastwechseltests zugrunde-liegenden Lebensdauermodelle nicht die Testergebnisse der überlagerten Lastwechseltests vorhersagen konnten. Die Ursache dafür lag im temperaturabhängigen Werkstoffverhalten der Moldmasse begründet, welches Einfluss auf den dominierenden Fehlermodus Bonddrahtabheber hat. Daher wird die Verwendung von fall-sensitiven Lebensdauermodellen vorgeschlagen, da somit die veränderte Schädigungsphysik beim Überschreiten des Glasüberganges der Moldmasse berücksichtigt werden kann. Darüber hinaus wird in dieser Arbeit eine neue Methode zur optischen in-situ-Untersuchung von Leistungsbauelementen vorgestellt, welche zukünftig die Untersuchung von thermisch-transienten sowie thermo-mechanischen Vorgängen unter aktiver Belastung erlaubt.:Symbol- und Abkürzungsverzeichnis Danksagung Kurzfassung Abstract 1 Einleitung 1.1 Motivation 1.2 Fokus und Ziel der Arbeit 2 Grundlagen zur Leistungselektronik und zu ihrer Zuverlässigkeitsbewertung 2.1 Aufbau typischer Leistungselektronikkomponenten und Module 2.1.1 Leistungsklassen und klassische Aufbauvarianten 2.1.2 Leistungshalbleiter 2.1.3 Substrattechnologien für Leistungsmodule 2.1.4 Verbindungstechniken in Leistungselektronikmodulen 2.1.4.1 Chipflächen- und Baugruppenkontaktierung 2.1.4.2 Chipanschlusskontaktierung 2.1.4.3 Kühlkörperanbindung 2.1.5 Verkapslungskonzepte 2.1.6 Kühlkonzepte in der Leistungselektronik 2.2 Typische Fehlermodi und -mechanismen 2.3 Lebensdauerbewertung von Leistungselektronik0 2.3.1 Globale Ansätze zur Produktqualifizierung und Zuverlässigkeitsbewertung0 2.3.2 Lebensdauertests in der Leistungselektronik 2.3.2.1 Überblick und Einordnung von Lastwechseltests 2.3.2.2 Testkonzepte und -strategien 2.3.3 Lebensdauermodellierung 3 Neue methodische Ansätze und Prüfstandsentwicklung 3.1 Überlagerung von aktiven Lastwechseln mit passiven Temperaturzyklen 3.2 Entwicklung und Aufbau eines Lastwechselprüfstandes zur Untersuchung von überlagerten Belastungstests 3.2.1 Konzeption 3.2.2 Kühlkörper-Design 3.2.3 Steuer- und Auswertesoftware 3.2.4 Lastwechselteststand 3.2.5 Messprozedur 3.2.6 Validierung der Tvj-basierten Temperaturmessung 3.3 Optisches In-situ-Monitoring während Lastwechseltests 3.3.1 Testaufbau und Probenpräparation 3.3.2 IR-Messungen an angeschliffenem Prüfling 4 Prüfgegenstände, Testplanung und Testdurchführung 4.1 Auswahl und Übersicht der Prüflinge 4.2 Testkonzeption und Versuchsplanung 4.2.1 Lastwechseltests 4.2.2 Temperaturschocktests 4.3 Testaufbau und -durchführung 4.3.1 Lastwechseltests 4.3.2 Temperaturschocktests 5 Testergebnisse 5.1 Messdatenanalyse und Auswerteprozedur 5.2 Statistische Testauswertung 5.2.1 Übersicht über Testergebnisse 5.2.2 Weibull-Verteilungen 5.3 Fehleranalytik 5.3.1 Bonddrahtausfälle 5.3.2 Lotdegradation 5.4 Optische In-situ-Analyse während aktiver Belastung 5.4.1 Methodik 5.4.2 Verschiebungsfelder in Abhängigkeit von ∆Tvj und Tvj,m 5.4.3 Einfluss der Einschaltzeit ton auf Verschiebungsfelder 5.4.4 Ableitung der Dehnungsfelder und Ergebnisdiskussion 6 Lebensdauermodellierung 6.1 Belastungsbasierte Lebensdauermodelle 6.1.1 Lebensdauerdiagramme und -einflussfaktoren 6.1.2 Multiple lineare Regression 6.1.3 Berücksichtigung der effektiven Temperatur T(v)j,eff 6.1.4 Vergleich der Lebensdauermodelle mit überlagerten Testergebnissen 6.1.5 Zusammenfassung 146 6.1.6 Einordnung der ermittelten Lebensdauermodelle 6.2 FE-Analyse zur Validierung der Ergebnisse aus der Lebensdauermodellierung 7 Zusammenfassung und Ausblick Literaturverzeichnis Abbildungsverzeichnis Tabellenverzeichnis
Active power cycling tests represent a standardized and well-established method for reliability evaluation and product qualification in power electronics. They are based on the application of recurring load current pulses, which are converted into cyclic temperature swings in the power component. The thereby induced thermo-mechanical stress, caused by the different material properties of the joining partners involved in the composite system, ultimately leads to the typical failure modes and mechanisms in the devices. However, these conventional tests do not sufficiently stimulate the complex load schemes in field operations in which different load factors occur simultaneously. In the context of the introduction of novel device and package technologies, increasingly harsh environmental operation conditions as well as increasing reliability and functional safety requirements, there is a need for improved reliability test methods. One possible approach is the combination of different load factors in order to increase test efficiency and test coverage. Within the scope of this thesis, systematic reliability investigations, including standard power cycling tests as well as power cycling tests superimposed with passive thermal cycles, were therefore carried out on discrete power components using a self-developed test rig. In addition to the investigation of different junction temperature profiles, a comparison of different component types was performed. On the basis of a qualitative and quantitative test evaluation, load-based lifetime models were derived. It was found that the lifetime models determined on the basis of the standard power cycling tests could not predict the test results of the superimposed power cycling tests. The reason for this was the influence of the temperature-dependent material behaviour of the moulding com-pound, which has an influence on the failure mode wire-bond lift-off. Based on these findings, the use of case-sensitive lifetime models is suggested that are able to take the changed damage physics into account. In addition, a new method for the optical in-situ investigation of moulded power devices is presented, which allows the investigation of thermal-transient as well as thermo-mechanical processes in the package under active loading conditions.:Symbol- und Abkürzungsverzeichnis Danksagung Kurzfassung Abstract 1 Einleitung 1.1 Motivation 1.2 Fokus und Ziel der Arbeit 2 Grundlagen zur Leistungselektronik und zu ihrer Zuverlässigkeitsbewertung 2.1 Aufbau typischer Leistungselektronikkomponenten und Module 2.1.1 Leistungsklassen und klassische Aufbauvarianten 2.1.2 Leistungshalbleiter 2.1.3 Substrattechnologien für Leistungsmodule 2.1.4 Verbindungstechniken in Leistungselektronikmodulen 2.1.4.1 Chipflächen- und Baugruppenkontaktierung 2.1.4.2 Chipanschlusskontaktierung 2.1.4.3 Kühlkörperanbindung 2.1.5 Verkapslungskonzepte 2.1.6 Kühlkonzepte in der Leistungselektronik 2.2 Typische Fehlermodi und -mechanismen 2.3 Lebensdauerbewertung von Leistungselektronik0 2.3.1 Globale Ansätze zur Produktqualifizierung und Zuverlässigkeitsbewertung0 2.3.2 Lebensdauertests in der Leistungselektronik 2.3.2.1 Überblick und Einordnung von Lastwechseltests 2.3.2.2 Testkonzepte und -strategien 2.3.3 Lebensdauermodellierung 3 Neue methodische Ansätze und Prüfstandsentwicklung 3.1 Überlagerung von aktiven Lastwechseln mit passiven Temperaturzyklen 3.2 Entwicklung und Aufbau eines Lastwechselprüfstandes zur Untersuchung von überlagerten Belastungstests 3.2.1 Konzeption 3.2.2 Kühlkörper-Design 3.2.3 Steuer- und Auswertesoftware 3.2.4 Lastwechselteststand 3.2.5 Messprozedur 3.2.6 Validierung der Tvj-basierten Temperaturmessung 3.3 Optisches In-situ-Monitoring während Lastwechseltests 3.3.1 Testaufbau und Probenpräparation 3.3.2 IR-Messungen an angeschliffenem Prüfling 4 Prüfgegenstände, Testplanung und Testdurchführung 4.1 Auswahl und Übersicht der Prüflinge 4.2 Testkonzeption und Versuchsplanung 4.2.1 Lastwechseltests 4.2.2 Temperaturschocktests 4.3 Testaufbau und -durchführung 4.3.1 Lastwechseltests 4.3.2 Temperaturschocktests 5 Testergebnisse 5.1 Messdatenanalyse und Auswerteprozedur 5.2 Statistische Testauswertung 5.2.1 Übersicht über Testergebnisse 5.2.2 Weibull-Verteilungen 5.3 Fehleranalytik 5.3.1 Bonddrahtausfälle 5.3.2 Lotdegradation 5.4 Optische In-situ-Analyse während aktiver Belastung 5.4.1 Methodik 5.4.2 Verschiebungsfelder in Abhängigkeit von ∆Tvj und Tvj,m 5.4.3 Einfluss der Einschaltzeit ton auf Verschiebungsfelder 5.4.4 Ableitung der Dehnungsfelder und Ergebnisdiskussion 6 Lebensdauermodellierung 6.1 Belastungsbasierte Lebensdauermodelle 6.1.1 Lebensdauerdiagramme und -einflussfaktoren 6.1.2 Multiple lineare Regression 6.1.3 Berücksichtigung der effektiven Temperatur T(v)j,eff 6.1.4 Vergleich der Lebensdauermodelle mit überlagerten Testergebnissen 6.1.5 Zusammenfassung 146 6.1.6 Einordnung der ermittelten Lebensdauermodelle 6.2 FE-Analyse zur Validierung der Ergebnisse aus der Lebensdauermodellierung 7 Zusammenfassung und Ausblick Literaturverzeichnis Abbildungsverzeichnis Tabellenverzeichnis

碩士
國立高雄應用科技大學
電機工程系
97
This thesis proposes support vector machine（SVM）based pattern recognition technique to classify electronic power meter faults by establishing and comparing with the historical electronic meter fault data. First, this research is to simulates the current use of electronic meters in the historical fault data and to derives the electronic power meter fault models. Moreover, the SVM network model is applied to train the selected electronic power meter fault data set in order to establish the electronic meter fault multi-layer SVM classifier. The fault meters and their corresponding fault type can be analyzed and the subsequent maintenance works can be processed. Besides, function block diagram and fault tree technique are used for reliability analysis to establish of electronic power meters and calculate the largest failure rate as well as the smallest reliability. Furthermore, the possible fault parts and life time of power meters can be justified by using simple calculation steps. Calculation results can be used as a guidance for installing and producing electronic power meters in the future.