Статті в журналах: "Power Chip on Chip"

1

Tan, N., and S. Eriksson. "Low-power chip-to-chip communication circuits." Electronics Letters 30, no. 21 (October 13, 1994): 1732–33. http://dx.doi.org/10.1049/el:19941178.

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2

Yerman, AlexanderJ. "4538170 Power chip package." Microelectronics Reliability 26, no. 3 (January 1986): 594. http://dx.doi.org/10.1016/0026-2714(86)90686-4.

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3

Vali, S. Sadiq, K. B. Madhu Mohan, S. Sreenivasulu, S. S. Zahoor Ahmed, and T. Muneer. "Low Power Encoding Technique for Network on Chip." International Journal of Research Publication and Reviews 4, no. 4 (April 27, 2023): 4950–53. http://dx.doi.org/10.55248/gengpi.234.4.38292.

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4

FOK, C. W., and D. L. PULFREY. "FULL-CHIP POWER-SUPPLY NOISE: THE EFFECT OF ON-CHIP POWER-RAIL INDUCTANCE." International Journal of High Speed Electronics and Systems 12, no. 02 (June 2002): 573–82. http://dx.doi.org/10.1142/s0129156402001472.

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The importance of on-chip power-rail inductance in generating delta-I power-supply noise is examined in this paper using systematic circuit simulation of the complete integrated-circuit power net. This source of noise is compared to the resistive IR drop in the net, and to the delta-I noise due to both high-inductance- and low-inductance-bonding packages. Results are presented for a typical on-chip power net in 0.18 μm CMOS technology, and it is demonstrated that the inductance of this on-chip power net is the dominant contributor to the full-chip power-supply noise. The simultaneous switching events which produce the triggering current transients for the delta-I noise are taken to arise from core-logic switching; the mitigating, de-coupling role of the capacitance of non-switching gates within the core-logic block is considered.

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5

Eireiner, M., S. Henzler, X. Zhang, J. Berthold, and D. Schmitt-Landsiedel. "Impact of on-chip inductance on power supply integrity." Advances in Radio Science 6 (May 26, 2008): 227–32. http://dx.doi.org/10.5194/ars-6-227-2008.

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Abstract. Based on product related scenarios, the impact of on-chip inductance on power supply integrity is analyzed. The impact of varying current profiles is shown to be minimal. In a regular power grid with regular bump connections, the impact of on-chip inductance on the cycle average of the supply voltage can be neglected, even for a worst case estimation of on-chip inductance. Whereas, the maximum transient power supply drop can be significantly underestimated by neglecting on-chip inductance. The impact of on-chip inductance in a System-on-Chip (SoC) environment also can be neglected if the on-chip inductance is conservativly estimated.

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6

Li, Jun Hui, Lei Han, Ji An Duan, and Jue Zhong. "Features of Machine Variables in Thermosonic Flip Chip." Key Engineering Materials 339 (May 2007): 257–62. http://dx.doi.org/10.4028/www.scientific.net/kem.339.257.

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An assembly bed on thermosonic flip chip bonding was set up, two different structures of tool tips were designed, and a series of experiments on flip chip and bonding machine variables were carried out. Lift-off characteristics of thermosonic flip chip were investigated by using Scanning Electron Microscope (JSM-6360LV), and vibration features of tool tips driven by high frequency were tested by using PSV-400-M2 Laser Doppler Vibrometer. Results show that, for chip-press model, slippage and rotation phenomena between tool tip and chip have been solved by using tool with greater area tip pattern during flip-chip bonding process, and welding failures appeared in chip-collet model have been controlled. Greater area pattern on tool tip is better than small area pattern. The power of ‘n’ bumps on flip chip bonding is far smaller than that of n×(the power of single wire bonding). The power is directly proportion to vibration displacement driven by the power, high-power decrease positioning precision of flip chip bonding or result in slippage and rotation phenomena. The proper machine variables ranges for thermosonic flip chip had been obtained.

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7

Yin, Feng Ling, Bing Quan Huo, Hai Bo Wang, and Long Cheng. "A Design for Power Supply Monitoring." Advanced Materials Research 912-914 (April 2014): 1061–64. http://dx.doi.org/10.4028/www.scientific.net/amr.912-914.1061.

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Monitoring servers' power is very important, and a design is present for solving existed issues. Building a wireless network with Zigbee technology, there are major modules:End Device with chip CC2530, Zigbee Router with chip CC2530 and CC2591, Zigbee coordinator with chip CC2530 and CC2430.

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8

Laha, Soumyasanta, Savas Kaya, David W. Matolak, William Rayess, Dominic DiTomaso, and Avinash Kodi. "A New Frontier in Ultralow Power Wireless Links: Network-on-Chip and Chip-to-Chip Interconnects." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 34, no. 2 (February 2015): 186–98. http://dx.doi.org/10.1109/tcad.2014.2379640.

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9

Pathak, Divya, Houman Homayoun, and Ioannis Savidis. "Smart Grid on Chip: Work Load-Balanced On-Chip Power Delivery." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, no. 9 (September 2017): 2538–51. http://dx.doi.org/10.1109/tvlsi.2017.2699644.

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10

Kose, Selçuk, and Eby G. Friedman. "Distributed On-Chip Power Delivery." IEEE Journal on Emerging and Selected Topics in Circuits and Systems 2, no. 4 (December 2012): 704–13. http://dx.doi.org/10.1109/jetcas.2012.2226378.

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11

Costlow, T. "Vision chip slashes power consumption." IEEE Intelligent Systems 18, no. 6 (November 2003): 6–7. http://dx.doi.org/10.1109/mis.2003.1249162.

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12

Perotto, J.-F., C. Piguet, and C. Voirol. "One-chip low-power multiprocessor." Microprocessing and Microprogramming 28, no. 1-5 (March 1990): 129–32. http://dx.doi.org/10.1016/0165-6074(90)90161-2.

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13

Chen, Ruei Chang, and Shih Fong Lee. "Design and Layout of a High-Performance PWM Control Class D Amplifiers IC Systems." Applied Mechanics and Materials 203 (October 2012): 469–73. http://dx.doi.org/10.4028/www.scientific.net/amm.203.469.

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This paper presents the design and implementation of a novel pulse width modulation control class D amplifiers chip. With high-performance, low-voltage, low-power and small area, these circuits are employed in portable electronic systems, such as the low-power circuits, wireless communication and high-frequency circuit systems. This class D chip followed the chip implementation center advanced design flow, and then was fabricated using Taiwan Semiconductor Manufacture Company 0.35-μm 2P4M mixed-signal CMOS process. The chip supply voltage is 3.3 V which can operate at a maximum frequency of 100 MHz. The total power consumption is 2.8307 mW, and the chip area size is 1.1497×1.1497 mm2. Finally, the class D chip was tested and the experimental results are discussed. From the excellent performance of the chip verified that it can be applied to audio amplifiers, low-power circuits, etc.

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14

Li, Jiashen, and Yun Pan. "Optimal scheduling algorithms of system chip power density based on network on chip." Izvestiya vysshikh uchebnykh zavedenii. Fizika, no. 9 (2021): 120–27. http://dx.doi.org/10.17223/00213411/64/9/120.

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The improvement of chip integration leads to the increase of power density of system chips, which leads to the overheating of system chips. When dispatching the power density of system chips, some working modules are selectively closed to avoid all modules on the chip being turned on at the same time and to solve the problem of overheating. Taking 2D grid-on-chip network as the research object, an optimal scheduling algorithm of system-on-chip power density based on network-on-chip (NoC) is proposed. Under the constraints of thermal design power (TDP) and system, dynamic programming algorithm is used to solve the optimal application set throughput allocation from bottom to top by dynamic programming for the number and frequency level of each application configuration processor under the given application set of network-on-chip. On this basis, the simulated annealing algorithm is used to complete the application mapping aiming at heat dissipation effect and communication delay. The open and closed processor layout is determined. After obtaining the layout results, the TDP is adjusted. The maximum TDP constraint is iteratively searched according to the feedback loop of the system over-hot spots, and the power density scheduling performance of the system chip is maximized under this constraint, so as to ensure the system core. At the same time, chip throughput can effectively solve the problem of chip overheating. The experimental results show that the proposed algorithm increases the system chip throughput by about 11%, improves the system throughput loss, and achieves a balance between the system chip power consumption and scheduling time.

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15

Mohammad, Khader, Ahsan Kabeer, and Tarek Taha. "On-Chip Power Minimization Using Serialization-Widening with Frequent Value Encoding." VLSI Design 2014 (May 6, 2014): 1–14. http://dx.doi.org/10.1155/2014/801241.

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In chip-multiprocessors (CMP) architecture, the L2 cache is shared by the L1 cache of each processor core, resulting in a high volume of diverse data transfer through the L1-L2 cache bus. High-performance CMP and SoC systems have a significant amount of data transfer between the on-chip L2 cache and the L3 cache of off-chip memory through the power expensive off-chip memory bus. This paper addresses the problem of the high-power consumption of the on-chip data buses, exploring a framework for memory data bus power consumption minimization approach. A comprehensive analysis of the existing bus power minimization approaches is provided based on the performance, power, and area overhead consideration. A novel approaches for reducing the power consumption for the on-chip bus is introduced. In particular, a serialization-widening (SW) of data bus with frequent value encoding (FVE), called the SWE approach, is proposed as the best power savings approach for the on-chip cache data bus. The experimental results show that the SWE approach with FVE can achieve approximately 54% power savings over the conventional bus for multicore applications using a 64-bit wide data bus in 45 nm technology.

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16

He, Xun Lai, Qing Hong, Jiu He Ma, and Wen Wen Yu. "DC Motor Drive Control Circuit Design Based on IR2103S High-Power Wide Voltage MOSFET." Advanced Materials Research 1049-1050 (October 2014): 819–23. http://dx.doi.org/10.4028/www.scientific.net/amr.1049-1050.819.

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Based on IR2103S half-bridge drive chip, high-power wide voltage DC motor drive circuit is successfully designed. This paper analyses high power wide voltage DC motor drive control principle, H-bridge drive principle, control characteristics of MOSFET and drive method, moreover, this paper also introduces operating characteristics of wide voltage IR2103S half-bridge drive chip and its control logic and operation modes, in addition, it provides interface method for connecting IR2103S chip and single-chip microcomputer, and measures to control high-power wide voltage DC motor by the single-chip microcomputer.

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17

Butterbaugh, M. A. "Development of a Two Matrix Model for Thermal Analysis of a Multichip Module." Journal of Electronic Packaging 119, no. 4 (December 1, 1997): 288–93. http://dx.doi.org/10.1115/1.2792251.

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The customary one-dimensional thermal resistance model used for single chip modules is not well suited for use with multichip modules. In this paper, it is proposed to model a multichip module (MCM) using a two matrix approach. An external matrix of influence coefficients is used in conjunction with cap temperatures measured above each chip site to determine individual chip powers within the MCM. These chip powers are then used with a matrix of internal influence coefficients to determine chip temperature rise relative to the cap temperature. The proposed matrices are determined using a “thermal test module” or “computational model” where chip power, chip temperature, and cap temperature can be explicitly measured. This dual matrix model is then available for use with production modules to determine chip powers and temperatures from a measurement of cap temperatures above each chip-site. The proposed model is demonstrated for a four chip MCM using data from numerical simulations. A sample of test runs using the model predicts the chip powers and temperatures to within 3.5 and 5.5 percent, respectively, of the values from the numerical model. Module physical properties are also parametrically varied to determine their effect on matrix elements. The matrix model is also proposed as a design tool to augment more numerically intensive methods of thermal analysis.

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18

Mohamed, Mazlan, Mohd Nazri Omar, Mohamad Shaiful Ashrul Ishak, Rozyanty Rahman, Muhamad Fahmi Mohd Roslan, Muhammad Nur Hafiz Shaidan, and Zairi Ismael Rizman. "Finite element analysis of heat sink in term of thermal and temperature distribution with different chip power input." International Journal of Engineering & Technology 7, no. 2.15 (April 6, 2018): 90. http://dx.doi.org/10.14419/ijet.v7i2.15.11221.

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This paper presents the simulation of heat sink by using Workbench 18.0 Software to simulate the temperature distribution at different chip power input. 3D model of heat sink is generated using Design Modeler using the same dimension with experimental setup. The study was made for a heat sink mounted on the power source (Chip) under different types of chip powers. The results are presented in terms of temperature distribution when chip powers have been increased from 1 W to 10 W. The temperature distribution is been observed and it was found that the temperature distribution of the heat sink has lower temperature when power source at 1 W and increase significantly when the power source rise up to 10 W. The increase the temperature of heat sink is from 30.8ºC up to 96.2ºC estimated to be 212% the increase of temperature. The simulation also been verify by using different time step use during the simulation and using grid independency test to ensure the simulation result is accurate.

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19

Budiarto, Rahmat, Lelyzar Siregar, and Deris Stiawan. "Network-on-Chip Paradigm for System-on-Chip Communication." Computer Engineering and Applications Journal 6, no. 1 (March 1, 2017): 1–4. http://dx.doi.org/10.18495/comengapp.v6i1.186.

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Developments of modern technologies in electronics, such as communication, Internet, pervasive and ubiquitous computing and ambient intelligence have figured largely our life. In our day micro-electronic products inspire the ways of learning, communication and entertainment. These products such as laptop computer, mobile phones, and personal handheld sets are becoming faster, lighter in weight, smaller in size, larger in capacity, lower in power consumptions, cheaper and functionally enhanced. This trend will persistently continue. Following this trend, we could integrate more and more complex applications and even systems onto a single chip. The System-on-Chip (SoC) technologies, where complex applications are integrated onto single ULSI chips became key driving force for the developments.

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20

Kayashima, Hideto, and Hideharu Amano. "TCI Tester: A Chip Tester for Inductive Coupling Wireless Through-Chip Interface." Journal of Low Power Electronics and Applications 13, no. 3 (August 4, 2023): 48. http://dx.doi.org/10.3390/jlpea13030048.

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The building block computation system is constructed by stacking various chips three-dimensionally. The stacked chips incorporate the same TCI IP (Through Chip Interface Intellectual Property) but cannot provide identical characteristics, requiring adjustments in power supply and bias voltage. However, providing characteristics measurement hardware for all chips is difficult due to the limitation of chip area or pin numbers. To address this problem, we developed TCI Tester, a small chip to measure electric characteristics by stacking on TCI of every chip. By stacking two TCI Tester chips, it appears that the up-directional data transfer has a stricter condition than down directional one on power supply voltage and operational frequency. Also, the transfer performance is poorer than designed. Similar measurement results are obtained by stacking TCI Tester on other chips with TCI IP. To investigate the reason, we analyzed the power grid resistance of various chips with the TCI IP. Results also showed that the chips with higher resistance have a narrow operational condition and poorer performance. The results suggest that the power grid design is important for keeping the performance through the TCI channel.

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21

Zhang, Jian Qiang, Dan Ya Chen, He Huang, and Yun Lu. "Temperature and Humidity Detection System Based on Power Line Communication." Applied Mechanics and Materials 236-237 (November 2012): 242–46. http://dx.doi.org/10.4028/www.scientific.net/amm.236-237.242.

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Introduction of a intelligence control system of remote temperature & moisture adjustment based on single-chip computer. It explains hardware flow diagram, module structure and system software process flow diagram based on principle of power line carrier transmission and humiture control. With STC12C5404ADsingle chip computer and DHT21 as main control chip and humiture collection chip, the system hard ware is characterized by efficient and strong capacity of resisting disturbance compare to traditional humiture checking system.

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22

HASHIDA, Takushi, and Makoto NAGATA. "Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails." IEICE Transactions on Electronics E93-C, no. 6 (2010): 842–48. http://dx.doi.org/10.1587/transele.e93.c.842.

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23

Yuan, Yuxiang, Yoichi Yoshida, Nobuhiko Yamagishi, and Tadahiro Kuroda. "Chip-to-Chip Power Delivery by Inductive Coupling with Ripple Canceling Scheme." Japanese Journal of Applied Physics 47, no. 4 (April 25, 2008): 2797–800. http://dx.doi.org/10.1143/jjap.47.2797.

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24

Ren, Yan Ting, and Li Ji Wu. "A Power Analysis System for Cryptographic Devices." Advanced Materials Research 718-720 (July 2013): 2376–82. http://dx.doi.org/10.4028/www.scientific.net/amr.718-720.2376.

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In order to test the security of cryptographic devices against Side Channel Attacks (SCA), an automatic general-purpose power analysis system (TH-PAS-01) is designed and implemented. TH-PAS-01 is scalable and can be applied to many cryptographic devices when specific modules are installed. Using the system TH-PAS-01, correlation power analysis (CPA) are carried out on an AES chip under two working models: normal and shuffling mode. The security level of the countermeasure provided by the target chip is verified by TH-PAS-01. The experimental results show that the correct key of the AES chip is obtained with around 50,000 power traces when the chip was working under normal mode, while the whole key bits are not obtained with 960,000 power traces when the chip works under shuffling mode. The automatic general-purpose system TH-PAS-01 is feasible for security analysis on power analysis for cryptographic devices.

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25

Johns, Murray E., and Issam Mudawar. "An Ultra-High Power Two-Phase Jet-Impingement Avionic Clamshell Module." Journal of Electronic Packaging 118, no. 4 (December 1, 1996): 264–70. http://dx.doi.org/10.1115/1.2792162.

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Boiling jet impingement heat transfer from a simulated electronic chip to Fluorinert FC-72 within a clamshell avionic module was investigated for dependence upon inlet fluid temperature, nozzle diameter, nozzle to chip spacing, jet velocity, and chip length. The clamshell module was designed and fabricated to accommodate both single and multiple chip boards and to demonstrate the feasibility of an ultra-high power (on the order of several kilowatts) module. Critical heat flux (CHF) was found to be directly dependent upon subcooling and jet velocity, but relatively unaffected by the nozzle to chip spacing variations examined. The effect of varying the chip size was evaluated and found to produce higher CHF values as chip size was decreased. A correlation accounting for both geometric and subcooling effects was adapted to predict the CHF database with a mean absolute error of 9.6 percent. The module is shown to be capable of dissipating a heat load of 12,000 W at a module flow rate of 8.01 × 10−4 m3/s (12.7 gpm), thus eclipsing the current technology available in avionic cooling.

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26

Xiong, Xiao Fang, Guo Liang Wu, Bo Tao Wang, and Kai Rui Wang. "Study on Electrical Power EPON System." Advanced Materials Research 722 (July 2013): 139–42. http://dx.doi.org/10.4028/www.scientific.net/amr.722.139.

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In IEEE8023ah Protocols, the uplink bandwidth allocation algorithm is not clearly defined, which depends on the telecommunication device providers. Combined with the strong and multiples services requirements of smart distribution grid, the State Grid developed an OLT chip with QoS mechanism and responded EPON system. Compared with nowadays OLT chip in market, the highlight of our OLT chip is its multiple QoS mechanism. On the respect of dynamic bandwidth allocation, the priority allocate and bandwidth statistic multiplexing functions have been added..

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27

Fan, Xi, Hou Peng Chen, Qian Wang, Yi Feng Chen, Zhi Tang Song, Min Zhu, and Gao Ming Feng. "A Low-Power 1Kb PCRAM Chip with Elevated Write Performance." Applied Mechanics and Materials 543-547 (March 2014): 463–66. http://dx.doi.org/10.4028/www.scientific.net/amm.543-547.463.

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A low-power 1Kb phase change random access memory (PCRAM) chip is designed. The chip uses 1T1R (one transistor one resistor) structure and titanium nitride (TiN) bottom electrode (BE) for reducing power consumption. Besides, the write property of the chip is improved by employing a ramp down pulse generator. The chip is fabricated in 130nm CMOS standard technology. The test result shows a 56% power reduction based on TiN BE compared with tungsten (W) BE, which predicts a new direction to realize the commercialization of PCRAM.

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28

Hsiang, En-Lin, Ziqian He, Yuge Huang, Fangwang Gou, Yi-Fen Lan, and Shin-Tson Wu. "Improving the Power Efficiency of Micro-LED Displays with Optimized LED Chip Sizes." Crystals 10, no. 6 (June 8, 2020): 494. http://dx.doi.org/10.3390/cryst10060494.

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Micro-LED (light-emitting diode) is a potentially disruptive display technology, while power consumption is a critical issue for all display devices. In this paper, we develop a physical model to evaluate the power consumption of micro-LED displays under different ambient lighting conditions. Both power efficiency and ambient reflectance are investigated in two types of full color display structures: red/green/blue (RGB) micro-LEDs, and blue-LED pumped quantum dots color-conversion. For each type of display with uniform RGB chip size, our simulation results indicate that there exists an optimal LED chip size, which leads to 30–40% power saving. We then extend our model to analyze different RGB chip sizes, and find that with optimized chip sizes an additional 12% average power saving can be achieved over that with uniform chip size.

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29

Zhou, Z., H. Wang, J. Zhang, J. Su, and P. Ge. "LED chip-on-board package with high colour rendering index and high luminous efficacy." Lighting Research & Technology 50, no. 3 (April 19, 2017): 482–88. http://dx.doi.org/10.1177/1477153517701535.

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Existing white light LED technology uses a blue light LED chip to stimulate a phosphor powder to form white light. The phosphor layer on the surface directly affects the colour rendering index, luminous efficacy and colour temperature of the LED. We propose a high power, white LED, chip-on-board package technology to achieve high colour rendering index and high luminous efficacy by optimising the spectral power distribution. The chip-on-board package light source can achieve a colour rendering index over 90 and a luminous efficacy over 90 lm/W while the power is 45W. It can be widely used in commercial lighting applications.

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30

J., Dr Kalaivani. "Power Efficient Router Framework for Wireless Network on Chip (WNoC)." Journal of Advanced Research in Dynamical and Control Systems 12, no. 3 (March 20, 2020): 119–25. http://dx.doi.org/10.5373/jardcs/v12i3/20201173.

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31

Wang, Chang Hong, Jiang Yun Zhang, and Jin Huang. "Thermal Performances Analysis of Microelectronic Chip Cooling System with Thermoelectric Components." Advanced Materials Research 216 (March 2011): 128–33. http://dx.doi.org/10.4028/www.scientific.net/amr.216.128.

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The microelectronic chip thermoelectric cooling equipment and its test system have been developed for the deficiency of the conventional cooling technologies in this paper. The thermal resistance analysis model was applied in research the heat transfer process of the microelectronic chip cooling system and its characteristics. The results show that: When the thermoelectric cooling (TEC) system is in normal operating condition,the Peltier effect is the dominant role in the thermoelectric cooling process despite the opposite actions of the Joule and Fourier effects. The thermal resistance of TEC, which is Q2, decreases when the operating current (I) increases. For the different chip power, there is an optimum current (Iopt) making the interface thermal resistance between chip and TEC minimum (Q1). Q1can obtain the minimum 0.465°C·W-1 when the chip power is 25W and Iopt is 2.4A. The total thermal resistance (Qtotal) firstly decreases and then increases with the increase of operating current. There is an optimum current which allows the total thermal resistance is smallest. Qtotal may obtain the minimum value 0.672°C·W-1 when the chip power is 25W and Iopt is 2.4A. Furthermore, Qtotal Iopt both increase by the chip power.

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32

Guan, He, Dong Wang, Wentao Li, Duo Liu, Borui Deng, and Xiang Qu. "Simulation on an Advanced Double-Sided Cooling Flip-Chip Packaging with Diamond Material for Gallium Oxide Devices." Micromachines 15, no. 1 (January 3, 2024): 98. http://dx.doi.org/10.3390/mi15010098.

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Gallium oxide (Ga2O3) devices have shown remarkable potential for high-voltage, high-power, and low-loss power applications. However, thermal management of packaging for Ga2O3 devices becomes challenging due to the significant self-heating effect. In this paper, an advanced double-sided cooling flip-chip packaging structure for Ga2O3 devices was proposed and the overall packaging of Ga2O3 chips was researched by simulation in detail. The advanced double-sided cooling flip-chip packaging structure was formed by adding a layer of diamond material on top of the device based on the single-sided flip-chip structure. With a power density of 3.2 W/mm, it was observed that the maximum temperature of the Ga2O3 chip with the advanced double-sided cooling flip-chip packaging structure was 103 °C. Compared with traditional wire bonding packaging and single-sided cooling flip-chip packaging, the maximum temperature was reduced by about 12 °C and 7 °C, respectively. When the maximum temperature of the chip was controlled at 200 °C, the Ga2O3 chip with double-sided cooling packaging could reach a power density of 6.8 W/mm. Finally, by equipping the top of the package with additional water-cooling equipment, the maximum temperature was reduced to 186 °C. These findings highlight the effectiveness of the proposed flip-chip design with double-sided cooling in enhancing the heat dissipation capability of Ga2O3 chips, suggesting promising prospects for this advanced packaging structure.

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33

Mazlan, Mohamed, A. Rahim, M. A. Iqbal, Mohd Mustafa Al Bakri Abdullah, W. Razak, and H. M. Nor Hakim. "Numerical Investigation of Heat Transfer of Twelve Plastic Leaded Chip Carrier (PLCC) by Using Computational Fluid Dynamic, FLUENT^TM Software." Advanced Materials Research 795 (September 2013): 603–10. http://dx.doi.org/10.4028/www.scientific.net/amr.795.603.

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Plastic Leaded Chip Carrier (PLCC) package has been emerged a promising option to tackle the thermal management issue of micro-electronic devices. In the present study, three dimensional numerical analysis of heat and fluid flow through PLCC packages oriented in-line and mounted horizontally on a printed circuit board, is carried out using a commercial CFD code, FLUENTTM. The simulation is performed for 12 PLCC under different inlet velocities and chip powers. The contours of average junction temperatures are obtained for each package under different conditions. It is observed that the junction temperature of the packages decreases with increase in inlet velocity and increases with chip power. Moreover, the increase in package density significantly contributed to rise in temperature of chips. Thus the present simulation demonstrates that the chip density (the number of packages mounted on a given area), chip power and the coolant inlet velocity are strongly interconnected; hence their appropriate choice would be crucial.

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34

Liu, Chunyan, Shujiao Wang, and Yanshan Sun. "Design of power control system for student dormitory." SHS Web of Conferences 166 (2023): 01058. http://dx.doi.org/10.1051/shsconf/202316601058.

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This design is based on the residential building of boarding school as the research object. The STC89C52RC single-chip microcomputer is used as the main control chip, and the clock chip, temperature chip, smoke collection module, A/D conversion, LED digital tube display circuit, matrix keyboard, infrared wireless remote control and other controllers are used to control the power system and adjust the access control system. This system is applicable to all kinds of colleges and universities that have strict management on students' electricity consumption. It can automatically control the electricity consumption of students' dormitories according to the school management regulations, and can automatically make emergency response to emergencies such as fire.

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35

Struharik, Rastislav, and Vuk Vranjković. "Striping input feature map cache for reducing off-chip memory traffic in CNN accelerators." Telfor Journal 12, no. 2 (2020): 116–21. http://dx.doi.org/10.5937/telfor2002116s.

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Data movement between the Convolutional Neural Network (CNN) accelerators and off-chip memory is critical concerning the overall power consumption. Minimizing power consumption is particularly important for low power embedded applications. Specific CNN computes patterns offer a possibility of significant data reuse, leading to the idea of using specialized on-chip cache memories which enable a significant improvement in power consumption. However, due to the unique caching pattern present within CNNs, standard cache memories would not be efficient. In this paper, a novel on-chip cache memory architecture, based on the idea of input feature map striping, is proposed, which requires significantly less on-chip memory resources compared to previously proposed solutions. Experiment results show that the proposed cache architecture can reduce on-chip memory size by a factor of 16 or more, while increasing power consumption no more than 15%, compared to some of the previously proposed solutions.

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36

Hong, Kuo-Bin, Wei-Ta Huang, Hsin-Chan Chung, Guan-Hao Chang, Dong Yang, Zhi-Kuang Lu, Shou-Lung Chen, and Hao-Chung Kuo. "High-Speed and High-Power 940 nm Flip-Chip VCSEL Array for LiDAR Application." Crystals 11, no. 10 (October 14, 2021): 1237. http://dx.doi.org/10.3390/cryst11101237.

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In this paper, we demonstrate the design and fabrication of a high-power, high-speed flip-chip vertical cavity surface emitting laser (VCSEL) for light detection and ranging (LiDAR) systems. The optoelectronic characteristics and modulation speeds of vertical and flip-chip VCSELs were investigated numerically and experimentally. The thermal transport properties of the two samples were also numerically investigated. The measured maximum output power, slope efficiency (SE) and power conversion efficiency (PCE) of a fabricated flip-chip VCSEL array operated at room-temperature were 6.2 W, 1.11 W/A and 46.1%, respectively. The measured L-I-V curves demonstrated that the flip-chip architecture offers better thermal characteristics than the conventional vertical structure, especially for high-temperature operation. The rise time of the flip-chip VCSEL array was 218.5 ps, and the architecture of the flip-chip VCSEL with tunnel junction was chosen to accommodate the application of long-range LiDAR. The calculated PCE of such a flip-chip VCSEL was further improved from 51% to 57.8%. The device design concept and forecasting laser characteristics are suitable for LiDAR systems.

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37

Kim, Jungwon. "Chip-scale power booster for light." Science 376, no. 6599 (June 17, 2022): 1269. http://dx.doi.org/10.1126/science.abq8422.

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38

FitzGerald, Susan. "Electronic Chip Runs on Ear Power." Hearing Journal 66, no. 4 (April 2013): 4. http://dx.doi.org/10.1097/01.hj.0000429418.69162.40.

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39

Al-Hashimi, Bashir, Enrico Macii, and Kaushik Roy. "Editorial: Low-power systems-on-chip." IEE Proceedings - Computers and Digital Techniques 149, no. 4 (2002): 135. http://dx.doi.org/10.1049/ip-cdt:20020550.

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40

SHIKANO, H., J. SHIRAKO, Y. WADA, K. KIMURA, and H. KASAHARA. "Power-Aware Compiler Controllable Chip Multiprocessor." IEICE Transactions on Electronics E91-C, no. 4 (April 1, 2008): 432–39. http://dx.doi.org/10.1093/ietele/e91-c.4.432.

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41

Titus, A. H., L. Tu, and C. S. Mullin. "Autonomous low-power glare sensing chip." Electronics Letters 47, no. 8 (2011): 508. http://dx.doi.org/10.1049/el.2011.0384.

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42

Vagnon, Eric, Pierre-Olivier Jeannin, Jean-Christophe Crebier, and Yvan Avenas. "A Bus-Bar-Like Power Module Based on Three-Dimensional Power-Chip-on-Chip Hybrid Integration." IEEE Transactions on Industry Applications 46, no. 5 (September 2010): 2046–55. http://dx.doi.org/10.1109/tia.2010.2057401.

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43

Vairavan, Rajendaran, Zaliman Sauli, Vithyacharan Retnasamy, Nazuhusna Khalid, K. Anwar, and Nooraihan Abdullah. "Natural Heat Convection Analysis on Cylindrical Al Slug of LED." Applied Mechanics and Materials 487 (January 2014): 536–39. http://dx.doi.org/10.4028/www.scientific.net/amm.487.536.

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This paper presents the characterization of a single chip high power LED package through simulation. Ansys version 11 was used for the simulation. The characterization of the LED package with aluminum cylindrical heat slug was carried out under natural convection condition at ambient temperature of 25°C. The junction temperature and the stress of the LED chip was assesed. The LED chip was powered with input power of 0.1 W and 1 W and the heat dissipation was assesed. Results showed that that the junction temperature and the Von Mises Stress of the single chip LED package increases with the increased input power.

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44

Chen, Shih-Lun, Tsun-Kuang Chi, Min-Chun Tuan, Chiung-An Chen, Liang-Hung Wang, Wei-Yuan Chiang, Ming-Yi Lin, and Patricia Angela R. Abu. "A Novel Low-Power Synchronous Preamble Data Line Chip Design for Oscillator Control Interface." Electronics 9, no. 9 (September 14, 2020): 1509. http://dx.doi.org/10.3390/electronics9091509.

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In this paper, a novel low-power synchronous preamble data line protocol chip design for serial communication is proposed. The serial communication only uses two wires, chip select (CS) and secure digital (SD), to transmit and receive data between two devices. The proposed protocol aims to use a fewer number of wires for the interface, therefore reducing the complexity as well as the area of the chip design. Moreover, it increases the efficiency through a synchronous serial communication-controlled oscillator. The low-power synchronous preamble data line protocol design was successfully verified using a field-programmable gate array (FPGA) as a master device and a real chip as a slave device. The signals are checked through the use of a logic analyzer. The realized low-power synchronous preamble data line protocol chip design has a gate count of only 5.07 K gates, a low power dissipation of 12 mW, and a chip area of 453,260 μm2 using the Taiwan semiconductor manufacturing company (TSMC) 0.18 μm CMOS process. Compared with the three-wire serial peripheral interface (SPI) protocol, the proposed design has the advantages of having a lower cost and a lower power consumption.

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45

Duan, Shihua, Dejian Li, Yuan Guan, Bofu Li, Dameng Li, Baobin Yang, and Shunfeng Han. "Optimization of Package Heat Dissipation Design Based on High-power WB-BGA Industrial Chip with a Wide Temperature Range." Journal of Physics: Conference Series 2645, no. 1 (November 1, 2023): 012003. http://dx.doi.org/10.1088/1742-6596/2645/1/012003.

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Abstract With the progress of science and technology, chip integration and packaging density continue to improve, and the power density increases rapidly, leading to the increasingly prominent problem of chip heat dissipation. The service environment of industrial chips with a wide temperature range is even worse, so it is necessary to ensure reliable operation in the environment of −40°C~85°C. The thermal design and thermal management of packaging have become an important problem in the industry. Based on the wide temperature range of high-power WB-BGA industrial chips, aiming at the difficulty of chip heat dissipation in the high-temperature environment of 85°C, this paper studies and optimizes the packaging heat dissipation, and proposes a high heat dissipation packaging design scheme based on the wide temperature-range high-power WB-BGA industrial chip, which reduces the chip junction temperature by 17.9°C and has a certain reference value for the packaging design of wide temperature range industrial chip.

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46

Ding, Xijie, Juan Huang, Zuoli Zhang, and Yisen Yu. "A Low Frequency Power Amplifier Design Based on Output CapacitorLess Circuit." Academic Journal of Science and Technology 11, no. 1 (May 21, 2024): 169–73. http://dx.doi.org/10.54097/ne5xme81.

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This low-frequency power amplifier utilizes the AT89S51 microcontroller as the main control chip. The system can be divided into several modules: power amplification circuit module, pre-amplification module, band-stop filtering module, protection circuit module, volume control module, power supply voltage, AC voltage, and AC current testing module, A/D conversion module, power module, and single-chip microcomputer subsystem control module. We chose class AB audio power amplifiers. To ensure circuit stability and higher fidelity, we selected the TDA2030 integrated chip to build the OCL power amplifier circuit, preventing efficiency from being too low. Through the control of single-chip microcomputer subsystem, it can measure and display output power, the supply power of the DC power source, and overall efficiency. This system utilizes electronic switches connected with band-stop filters, with the band-stop frequency ranging from 40～60Hz.

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47

Budell, Timothy, and Eric Tremble. "PCB Effects on On-chip Capacitor Requirements and an Efficient Resonance-Prevention ASIC Methodology." International Symposium on Microelectronics 2010, no. 1 (January 1, 2010): 000392–99. http://dx.doi.org/10.4071/isom-2010-wa2-paper1.

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A method for determining adequate quantities and locations of on-chip capacitors to maintain supply voltages at all locations on a chip within pre-specified limits given the switching activity of on-chip circuits was presented in [3]. In this paper, we extend the method to include current flow from the package and PCB. The effects of on-chip capacitance and other system parasitics on the time it takes for additional supply current to flow into a chip are discussed. The relationship between switching current, capacitance, system parasitic inductances, and on-chip noise is presented. These concepts are then applied to the subject of power delivery network (PDN) resonance. A 1-dimensional model for simulating PDN resonance is presented. The model includes chip, package, and PCB components, along with explicit networks for each chip power supply and their interactions. The topology of the model and the contributions of each model component are described. A design methodology for avoiding PDN resonance, presently in use on all IBM ASIC modules, is presented.

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48

Li, Jiashen, and Yun Pan. "Optimal Scheduling Algorithms of System Chip Power Density Based on Network on Chip." Russian Physics Journal 64, no. 9 (January 2022): 1715–23. http://dx.doi.org/10.1007/s11182-022-02512-9.

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49

Sangirov, Jamshid, Ikechi Augustine Ukaegbu, Gulomjon Sangirov, Tae-Woo Lee, and Hyo-Hoon Park. "Power-aware transceiver design for half-duplex bidirectional chip-to-chip optical interconnects." Journal of Semiconductors 34, no. 12 (December 2013): 125001. http://dx.doi.org/10.1088/1674-4926/34/12/125001.

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50

Wang, Chenyuan, Yigang He, Chuankun Wang, Lie Li, and Xiaoxin Wu. "Multi-Chip IGBT Module Failure Monitoring Based on Module Transconductance with Temperature Calibration." Electronics 9, no. 10 (September 23, 2020): 1559. http://dx.doi.org/10.3390/electronics9101559.

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The Insulated Gate Bipolar Transistor (IGBT) is the component with the highest failure rate in power converters, and its reliability is a critical issue in power electronics. IGBT module failure is largely caused by solder layer fatigue or bond wires fall-off. This paper proposes a multi-chip IGBT module failure monitoring method based on the module transconductance, which can accurately monitor IGBT module chip failures and bond wire failures. The paper first introduces the failure mechanism and module structure of the multi-chip IGBT module; then, it proposes a reliability model based on the module transconductance and analyzes the relationship between chip failure, bond wire failure, and the transmission characteristic curve of the IGBT module. Finally, the module transconductance under chip failure and bond wire failure is measured and calculated through simulation, and the temperature is calibrated, which can eliminate the influence of temperature on health monitoring. The results show that the method has a high sensitivity to chip failures and bond wire failures, can realize the failure monitoring of multi-chip IGBT modules, and is of great significance for improving the reliability of power converters.

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