Дисертації: "Polymer Charge Trapping Memory"

1

Tao, Qingbo, and 陶庆波. "A study on the dielectrics of charge-trapping flash memory devices." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2013. http://hdl.handle.net/10722/196488.

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Discrete charge-trapping flash memory is being developed for the next-generation commercial flash-memory applications due to its advantages over the traditional floating-gate counterpart. Currently, Si3N4 is widely used as charge-trapping layer (CTL). However, Si3N4 has low dielectric constant and small conduction-band offset with respect to the SiO2 tunneling layer, imposing limitation on further applications. Therefore, this research emphasized on investigating new dielectrics with appropriate fabrication methods to replace Si3N4 as CTL for achieving improved memory performance. Firstly, GeON CTL annealed at different temperatures was investigated. The memory device with post-deposition annealing at 600 0C exhibited the largest memory window, the best charge retention performance, and the highest reliability. These good results are due to the fact that optimal annealing temperature could suppress shallow traps and also produce new traps with desirable energy levels in the CTL. Since ZnON has a negative conduction-band offset (NCBO) with respect to Si, the traps located in the bandgap of ZnON should have deep energy levels. The memory performances of ZrON film with and without Zn doping were studied. Experimental results showed that ZrZnON film had higher program speed and better charge retention performance due to many deeper trap levels induced by the Zn doping, as well as higher erase speed due to the direct recombination of electrons at these deeper trap levels with incoming holes and the intermediary role of these deeper trap levels under erase mode. MoO3 is another NCBO dielectric with a high K value and many oxygen vacancies. La2O3, a rare-earth metal oxide, is a promising dielectric as CTL. To combine the advantages of both La2O3 and MoO3, Mo-doped La2O3 was proposed as a new CTL. Compared to the device with pure La2O3, the one with LaMoO film as CTL had significantly larger C-V hysteresis window, much higher P/E speeds, and better charge retention due to the deeper-level traps and deeper quantum wells created by the LaMoO film. Nitrogen incorporation is a popular approach to increase the trap density in the bulk of CTL. In this research, the memory performances of GdTiO films with and without nitrogen incorporation were compared. Since the nitrogen incorporation induced smaller equivalent oxide thickness, produced nitride-related traps with desirable energy level and larger cross-section for charge capture, the GdTiON film possessed better memory performance than the GdTiO film. Finally, fluorine plasma was employed to improve the quality of blocking layer. The memory device with AlOF blocking layer obtained higher program speed, better reliability and better charge retention than that based on AlO blocking layer. The improved performance was due to the fact that the fluorine incorporation passivated the defects and removed the excess oxygen in the bulk of the blocking layer. In summary, dielectric plays important roles in the performance of charge-trapping flash memory. Memory devices with GeON, ZrZnON, LaMoO, or GdTiON as charge trapping layer and AlOF as blocking layer can produce large memory window, high program/erase speed and good charge retention.
published_or_final_version
Electrical and Electronic Engineering
Doctoral
Doctor of Philosophy

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2

Huang, Xiaodong, and 黄晓东. "A study on high-k dielectrics for discrete charge-trapping flash memory applications." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2013. http://hub.hku.hk/bib/B5043438X.

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Discrete charge-trapping flash memories are more promising than their floating-gate counterparts due to their physically discrete-trapping and coupling-free nature. Si3N4 is conventional material as charge-trapping layer (CTL) for charge storage. The shortcomings of Si3N4 are its low dielectric constant and small barrier height at its interface with SiO2 tunneling layer. Therefore, this research aims to investigate new materials as CTL for improving the performance of the memory devices. The charge-trapping characteristics of La2O3 with and without nitrogen incorporation were investigated. Compared with the memory device with La2O3 as CTL, the one with nitrided La2O3 (LaON) showed larger memory window, higher program/erase (P/E) speeds and smaller charge loss, due to the nitrided La2O3 film exhibiting less crystallized structure, higher trap density induced by nitrogen incorporation, and suppressed leakage by nitrogen passivation. In order to further improve the performance of the memory device with LaON CTL, a device with band-engineered LaTiON/LaON structure as CTL was also explored, and demonstrated to have better performance than the one with LaON CTL. This was ascribed to the variable tunneling path of charge carriers under P/E and retention modes (realized by the band-engineered charge-trapping layer), high trap density of LaTiON, and large barrier height at the LaTiON/SiO interface. SrTiO 3and BaTiO3 ,both ofwhich are typical perovskite-type dielectrics, also possess distinguished characteristics as CTL, including remarkably high dielectric constant and large conduction-band offset relative to SiO2. The charge-trapping properties of SrTiO3 with and without fluorine incorporation were studied. The device with fluorinated SrTiO3 film showed promising performance in terms of higher P/E speeds at a low gate voltage, better endurance and data retention compared with that without fluorine treatment. These advantages were associated with generated deep-level traps, reduced leakage path, and enhanced strength of the film due to the highest electro-negativity of the fluorine atoms incorporated in the film. The charge-trapping properties of BaTiO3 with and without Zr incorporation were also investigated, where Zr incorporated in BaTiO3 could strengthen the dielectric film and improve its thermodynamic stability. The device with Zr incorporation exhibited similar memory window as the one without Zr incorporation, but higher program speed at low gate voltage, better endurance and data retention, due to the Zr-doped BaTiO3 exhibiting higher charge-trapping efficiency and higher density of traps with deeper energy levels. Besides nitride-based memories, nanocrystal-based memories are another type of charge-trapping memories, where nanocrystals (NCs) embedded into a dielectric are used for charge storage. Memory devices with Ga2O3 NCs as CTL were investigated, which are compatible with the CMOS process. The Ga2O3 NCs displayed higher trap density than the Ga2O3 dielectric film. Moreover, compared with the device with Ga2O 3NCs as CTL, the one with nitrided Ga2O3 NCs showed larger memory window, higher operating speed and better data retention, mainly due to higher charge-trapping efficiency of the nitrided Ga2O3 NCs and nitrogen-induced suppressed formation of interlayer at the Ga2O/SiO interface.
published_or_final_version
Electrical and Electronic Engineering
Doctoral
Doctor of Philosophy

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3

Jakobsson, Fredrik Lars Emil. "Charge transport modulation in organic electronic diodes." Doctoral thesis, Linköpings universitet, Institutionen för teknik och naturvetenskap, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-14719.

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Since the discovery of conducting polymers three decades ago the field of organic electronics has evolved rapidly. Organic light emitting diodes have already reached the consumer market, while organic solar cells and transistors are rapidly maturing. One of the great benefits with this class of materials is that they can be processed from solution. This enables several very cheap production methods, such as printing and spin coating, and opens up the possibility to use unconventional substrates, such as flexible plastic foils and paper. Another great benefit is the possibility of tailoring the molecules through carefully controlled synthesis, resulting in a multitude of different functionalities. This thesis reports how charge transport can be altered in solid-state organic electronic devices, with specific focus on memory applications. The first six chapters give a brief review of the field of solid-state organic electronics, with focus on electronic properties, resistance switch mechanisms and systems. Paper 1 and 3 treat Rose Bengal switch devices in detail – how to improve these devices for use in cross-point arrays as well as the origin of the switch effect. Paper 2 investigates how the work function of a conducting polymer can be modified to allow for better electron injection into an organic light emitting diode. The aim of the work in papers 4 and 5 is to understand the behavior of switchable charge trap devices based on blends of photochromic molecules and organic semiconductors. With this in mind, charge transport in the presence of traps is investigated in paper 4 and photochromic molecules is investigated using quantum chemical methods in paper 5.
Elektroniska komponenter har traditionellt sett tillverkats av kisel ellerandra liknande inorganiska material. Denna teknologi har förfinats intillperfektion sedan mitten av 1900-talet och idag har kiselkretsar mycket högprestanda. Tillverkningen av dessas kretsar är dock komplicerad och är därförkostsam. Under 1970-talet upptäcktes att organiska polymerer (dvs plast) kanleda ström under vissa förutsättningar. Genom att välja lämplig polymer ochbehandla den med vissa kemikalier (så kallad dopning) kan man varieraledningsförmågan från isolerande till nästintill metallisk. Det öppnarmöjligheten för att skapa elektroniska komponenter där dessa organiskamaterial utgör den aktiva delen istället för kisel. En av de stora fördelarna medorganiska material är att de vanligtvis är lösliga i vanliga lösningsmedel. Det göratt komponenter kan tillverkas mycket enkelt och billigt genom att användakonventionell tryckteknik, där bläcket har ersatts med lösningen av detorganiska materialet. Det gör också att komponenterna kan tillverkas påokonventionella ytor såsom papper, plast eller textil. En annan spännandemöjlighet med organiska material är att dess funktioner kan skräddarsys genomvälkontrollerad kemisk syntes på molekylär nivå. Inom forskningsområdetOrganisk Elektronik studerar man de elektroniska egenskaperna i de organiskamaterialen och hur man kan använda dessa material i elektroniskakomponenter. Vi omges idag av apparater och applikationer som kräver att data sparas,som till exempel digitala kameror, datorer och mobiltelefoner. Eftersom det finnsett stort intresse från konsumenter för nya smarta produkter ökar behovet avmobila lagringsmedia med stor lagringskapacitet i rasande fart. Detta harsporrat en intensiv utveckling av större och billigare fickminnen, hårddiskar ochminneskort. Många olika typer av minneskomponenter baserade på organiskamaterial har föreslagits de senaste åren. I vissa fall har dessa påståtts kunna erbjuda både billigare och större minnen än vad dagens kiselteknologi tillåter.En typ av organiska elektroniska minnen baseras på en reversibel ochkontrollerbar förändring av ledningsförmågan i komponenten. En informationsenhet – en så kallad bit – kan då lagras genom att till exempel koda en högledningsförmåga som en ”1” och en låg ledningsförmåga som en ”0”. Den härdoktorsavhandlingen är ett försök till att öka förståelsen för sådanaminneskomponenter. Minneskomponenter bestående av det organiska materialet Rose Bengalmellan metallelektroder har undersökts. Egenskaper för system bestående avmånga sådana komponenter har beräknats. Vidare visas att minnesfenomenetinte härstammar i det organiska materialet utan i metallelektroderna.Tillsammans med studier av andra forskargrupper har det här resultatetbidragit till en debatt om huruvida minnesmekanismerna i andra typer avkomponenter verkligen beror på det organiska materialet.Olika sätt att ändra transporten av laddningar i organiska elektroniskasystem har undersökts. Det visas experimentellt hur överföringen av laddningarmellan metallelektroder och det organiska materialet kan förbättras genom attmodifiera metallelektroderna på molekylär nivå. Vidare har det studeratsteoretiskt hur laddningar kan fastna (så kallad trapping) i organiska materialoch därmed påverka ledningsförmågan i materialet.En speciell typ av organiska molekyler ändrar sin struktur, och därmedegenskaper, reversibelt när de belyses av ljus av en viss våglängd, så kalladefotokroma molekyler. Denna förändring kan användas till att ändraledningsförmågan genom en komponent och därmed skulle man kunna användamolekylerna i en minneskomponent. I den sista delen av avhandlingen användskvantkemiska metoder för att beräkna egenskaperna hos dessa molekyler för attöka förståelsen för hur de kan användas i minneskomponenter.

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4

Simon, Daniel. "Multistability, Ionic Doping, and Charge Dynamics in Electrosynthesized Polypyrrole, Polymer-Nanoparticle Blend Nonvolatile Memory, and Fixed p-i-n Junction Polymer Light-Emitting Electrochemical Cells." Doctoral thesis, University of California, Santa Cruz, USA, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-94587.

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A variety of factors make semiconducting polymers a fascinating alternative for both device development and new areas of fundamental research. Among these are solution processability, low cost, flexibility, and the strong dependence of conduction on the presence of charge compensating ions. With the lack of a complete fundamental understanding of the materials, and the growing demand for novel solutions to semiconductor device design, research in the field can take many, often multifaceted, routes. Due to ion-mediated conduction and versatility of fabrication, conducting polymers can provide a route to the study of neural signaling. In the first of three research topics presented, junctions of polypyrrole electropolymerized on microelectrode arrays are demonstrated. Individual junctions, when synthesized in a three-electrode configuration, exhibit current switching behavior analogous to neural weighting. Junctions copolymerized with thiophene exhibit current rectification and the nonlinear current-voltage behavior requisite for complex neural systems. Applications to larger networks, and eventual use in analysis of signaling, are discussed. In the second research topic, nonvolatile resistive memory consisting of gold nanoparticles embedded in a polymer film is examined using admittance spectroscopy. The frequency dependence of the devices indicates space-charge-limited transport in the high-conductivity "on" state, and similar transport in the lower-conductivity "off" state. Furthermore, a larger dc capacitance of the on state indicates that a greater amount of filling of midgap trap levels introduced by the nanoparticles increases conductivity, leading to the memory effect. Implications on the question as to whether or not the on state is the result of percolation pathways is discussed. The third and final research topic is a presentation of enhanced efficiency of polymer light-emitting electrochemical cells (LECs) by means of forming a doping self-assembled monolayer (SAM) at the cathode-polymer interface. The addition of the SAM causes a twofold increase in quantum efficiency. Photovoltaic analysis indicates that the SAM increases both open-circuit voltage and short-circuit current. Current versus voltage data are presented which indicate that the SAM does not simply introduce an interfacial dipole layer, but rather provides a fixed doping region, and thus a more stable p-i-n structure.

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5

Griffo, Michael S. "Charge dynamics in polymer-nanoparticle blends for nonvolatile memory : Surface enhanced fluorescence of a semiconducting polymer; surface plasmon assisted luminescent solar concentrator waveguides /." Diss., Digital Dissertations Database. Restricted to UC campuses, 2009. http://uclibs.org/PID/11984.

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6

Simon, Daniel Theodore. "Multistability, ionic doping, and charge dynamics in electrosynthesized polypyrrole, polymer-nanoparticle blend nonvolatile memory, and fixed P-I-N junction polymer light-emitting electrochemical cells /." Diss., Digital Dissertations Database. Restricted to UC campuses, 2007. http://uclibs.org/PID/11984.

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7

Prime, Dominic Charles. "Switching mechanisms, electrical characterisation and fabrication of nanoparticle based non-volatile polymer memory devices." Thesis, De Montfort University, 2010. http://hdl.handle.net/2086/3314.

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Polymer and organic electronic memory devices offer the potential for cheap, simple memories that could compete across the whole spectrum of digital memories, from low cost, low performance applications, up to universal memories capable of replacing all current market leading technologies, such as hard disc drives, random access memories and Flash memories. Polymer memory devices (PMDs) are simple, two terminal metal-insulator-metal (MIM) bistable devices that can exist in two distinct conductivity states, with each state being induced by applying different voltages across the device terminals. Currently there are many unknowns and much ambiguity concerning the working mechanisms behind many of these PMDs, which is impeding their development. This research explores some of these many unanswered questions and presents new experimental data concerning their operation. One prevalent theory for the conductivity change is based on charging and charge trapping of nanoparticles and other species contained in the PMD. The work in this research experimentally shows that gold nanoparticle charging is possible in these devices and in certain cases offers an explanation of the working mechanism. However, experimental evidence presented in this research, shows that in many reported devices the switching mechanism is more likely to be related to electrode effects, or a breakdown mechanism in the polymer layer. Gold nanoparticle charging via electrostatic force microscopy (EFM) was demonstrated, using a novel device structure involving depositing gold nanoparticles between lateral electrodes. This allowed the gold nanoparticles themselves to be imaged, rather than the nanoparticle loaded insulating films, which have previously been investigated. This method offers the advantages of being able to see the charging effects of nanoparticles without any influence from the insulating matrix and also allows charging voltages to be applied via the electrodes, permitting EFM images to capture the charging information in near real-time. Device characteristics of gold nanoparticle based PMDs are presented, and assessed for use under different scenarios. Configurations of memory devices based on metal-insulator-semiconductor (MIS) structures have also been demonstrated. Simple interface circuitry is presented which is capable of performing read, write and erase functions to multiple memory cells on a substrate. Electrical properties of polystyrene thin films in the nanometre thickness range are reported for the first time, with insulator trapped charges found to be present in comparable levels to those in silicon dioxide insulating films. The dielectric breakdown strength of the films was found to be significantly higher than bulk material testing would suggest, with a maximum dielectric strength of 4.7 MV•cm-1 found, compared with the manufacturers bulk value of 0.2 – 0.8 MV•cm-1. Conduction mechanisms in polystyrene were investigated with the dominant conduction mechanism found to be Schottky emission.

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8

Gebel, Thoralf. "Nanocluster-rich SiO2 layers produced by ion beam synthesis: electrical and optoelectronic properties." Forschungszentrum Dresden, 2010. http://nbn-resolving.de/urn:nbn:de:bsz:d120-qucosa-29449.

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The aim of this work was to find a correlation between the electrical, optical and microstructural properties of thin SiO2 layers containing group IV nanostructures produced by ion beam synthesis. The investigations were focused on two main topics: The electrical properties of Ge- and Si-rich oxide layers were studied in order to check their suitability for non-volatile memory applications. Secondly, photo- and electroluminescence (PL and EL) results of Ge-, Si/C- and Sn-rich SiO2 layers were compared to electrical properties to get a better understanding of the luminescence mechanism.

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9

Gebel, Thoralf. "Nanocluster-rich SiO2 layers produced by ion beam synthesis: electrical and optoelectronic properties." Forschungszentrum Rossendorf, 2002. https://hzdr.qucosa.de/id/qucosa%3A21773.

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The aim of this work was to find a correlation between the electrical, optical and microstructural properties of thin SiO2 layers containing group IV nanostructures produced by ion beam synthesis. The investigations were focused on two main topics: The electrical properties of Ge- and Si-rich oxide layers were studied in order to check their suitability for non-volatile memory applications. Secondly, photo- and electroluminescence (PL and EL) results of Ge-, Si/C- and Sn-rich SiO2 layers were compared to electrical properties to get a better understanding of the luminescence mechanism.

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10

Goh, Roland Ghim Siong. "Carbon nanotubes for organic electronics." Thesis, Queensland University of Technology, 2008. https://eprints.qut.edu.au/20849/1/Roland_Goh_Thesis.pdf.

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This thesis investigated the use of carbon nanotubes as active components in solution processible organic semiconductor devices. We investigated the use of functionalized carbon nanotubes in carbon nanotubes network transistors (CNNFET) and in photoactive composites with conjugated polymers. For CNNFETs, the objective was to obtain detailed understanding of the dependence of transistor characteristics on nanotubes bundle sizes, device geometry and processing. Single walled carbon nanotubes were functionalized by grafting octadecylamine chains onto the tubes, which rendered them dispersible in organic solvents for solution processing. To investigate the dependence of electronic properties of carbon nanotubes networks on bundle size, we developed a centrifugal fractionation protocol that enabled us to obtain nanotube bundles of different diameters. The electronic properties of networks of nanotube bundles deposited from solution were investigated within a CNNFET device configuration. By comparing devices with different degree of bundling we elucidated the dependence of key device parameters (field effect mobility and on/off ratio) on bundle sizes. We further found that, in contrast to traditional inorganic transistors, the electronic properties of the CNNFETs were dominated by the channel rather than contact resistance. Specifically, the apparent mobility of our devices increased with decreasing channel length, suggesting that the charge transport properties of CNNFETs are bulk rather than contacts dominated. This meant that charge traps in the channel of the device had a significant effect on transport properties. We found that charge traps in the channel region introduced by adsorbed oxygen and silanol groups on the SiO2 surface were responsible for the dominant p-type conductance in as-fabricated devices. Based on this understanding, we demonstrated the p-type to n-type conversion of the transistor characteristics of CNNFETs by depositing nanotubes on electron-trapfree dielectric surfaces. Finally, by combining annealing and surface treatment, we fabricated CNNFETs with high n-type mobility of 6cm2/V.s. For polymer composites, the objective was to obtain detailed understanding of the interactions between carbon nanotubes and the conjugated polymer; a prerequisite for using these composites in organic electronic devices. We fabricated well dispersed nanotube/polymer composites by using functionalized carbon nanotubes and studied the effect of nanotubes addition on the photophysical properties of the technologically important conjugated polymer poly(3-hexylthiophene) (P3HT). Measurement of the photoluminescence efficiency of nanotubes/polymer composites showed that addition of 10wt% carbon nanotubes effectively quenched the polymer emission indicating close electronic interactions. This indicated that nanotubes/polymer composites have potential in organic photovoltaic or light-sensing devices. Further analysis of the steady-state photoluminescence spectra revealed that nanotube addition resulted in increased structural disorder in the polymer. The incorporation of structural disorder into the polymer with the addition of even a small amount of carbon nanotubes may be detrimental to charge transport. UV-vis adsorption studies revealed that one-dimensional templating of P3HT chains by nanotubes resulted in a red-shifted feature in the solutionstate optical adsorption spectra of P3HT. This suggested that presence of nanotube surface templates the polymer self-organisation to produce highly ordered coating of P3HT chains around the nanotube. In order to elucidate the nanoscale origin of this phenomenon, we performed detailed STM studies on individual nanotubes adsorbed with P3HT chains. Since carbon nanotubes can be considered as rolled up sheets of graphite, we also performed STM on P3HT chains assembly on graphite for comparison. For P3HT assembly on HOPG, we found that while 2D crystals were observed when P3HT was cast onto HOPG from dilute solution, a thicker and more disordered film resulted when cast from concentrated solutions and subsequent layers were more likely to align normal to an underlying monolayer of P3HT on the HOPG surface. STM studies of nanotube/polymer mixtures revealed that the P3HT chains are adsorbed on nanotubes surface in such a way that the thiophene and hexyl moieties of the polymer associated with the nanotube surface in identical manner to P3HT monolayer depositions on graphite. This resulted in the increased order as inferred from adsorption UV-Vis spectroscopy, where the polymer chains, which are otherwise prone to chain kinks and twists in solution, adopt a planar configuration when adsorbed onto the nanotube surface.

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11

Goh, Roland Ghim Siong. "Carbon nanotubes for organic electronics." Queensland University of Technology, 2008. http://eprints.qut.edu.au/20849/.

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Анотація:

This thesis investigated the use of carbon nanotubes as active components in solution processible organic semiconductor devices. We investigated the use of functionalized carbon nanotubes in carbon nanotubes network transistors (CNNFET) and in photoactive composites with conjugated polymers. For CNNFETs, the objective was to obtain detailed understanding of the dependence of transistor characteristics on nanotubes bundle sizes, device geometry and processing. Single walled carbon nanotubes were functionalized by grafting octadecylamine chains onto the tubes, which rendered them dispersible in organic solvents for solution processing. To investigate the dependence of electronic properties of carbon nanotubes networks on bundle size, we developed a centrifugal fractionation protocol that enabled us to obtain nanotube bundles of different diameters. The electronic properties of networks of nanotube bundles deposited from solution were investigated within a CNNFET device configuration. By comparing devices with different degree of bundling we elucidated the dependence of key device parameters (field effect mobility and on/off ratio) on bundle sizes. We further found that, in contrast to traditional inorganic transistors, the electronic properties of the CNNFETs were dominated by the channel rather than contact resistance. Specifically, the apparent mobility of our devices increased with decreasing channel length, suggesting that the charge transport properties of CNNFETs are bulk rather than contacts dominated. This meant that charge traps in the channel of the device had a significant effect on transport properties. We found that charge traps in the channel region introduced by adsorbed oxygen and silanol groups on the SiO2 surface were responsible for the dominant p-type conductance in as-fabricated devices. Based on this understanding, we demonstrated the p-type to n-type conversion of the transistor characteristics of CNNFETs by depositing nanotubes on electron-trapfree dielectric surfaces. Finally, by combining annealing and surface treatment, we fabricated CNNFETs with high n-type mobility of 6cm2/V.s. For polymer composites, the objective was to obtain detailed understanding of the interactions between carbon nanotubes and the conjugated polymer; a prerequisite for using these composites in organic electronic devices. We fabricated well dispersed nanotube/polymer composites by using functionalized carbon nanotubes and studied the effect of nanotubes addition on the photophysical properties of the technologically important conjugated polymer poly(3-hexylthiophene) (P3HT). Measurement of the photoluminescence efficiency of nanotubes/polymer composites showed that addition of 10wt% carbon nanotubes effectively quenched the polymer emission indicating close electronic interactions. This indicated that nanotubes/polymer composites have potential in organic photovoltaic or light-sensing devices. Further analysis of the steady-state photoluminescence spectra revealed that nanotube addition resulted in increased structural disorder in the polymer. The incorporation of structural disorder into the polymer with the addition of even a small amount of carbon nanotubes may be detrimental to charge transport. UV-vis adsorption studies revealed that one-dimensional templating of P3HT chains by nanotubes resulted in a red-shifted feature in the solutionstate optical adsorption spectra of P3HT. This suggested that presence of nanotube surface templates the polymer self-organisation to produce highly ordered coating of P3HT chains around the nanotube. In order to elucidate the nanoscale origin of this phenomenon, we performed detailed STM studies on individual nanotubes adsorbed with P3HT chains. Since carbon nanotubes can be considered as rolled up sheets of graphite, we also performed STM on P3HT chains assembly on graphite for comparison. For P3HT assembly on HOPG, we found that while 2D crystals were observed when P3HT was cast onto HOPG from dilute solution, a thicker and more disordered film resulted when cast from concentrated solutions and subsequent layers were more likely to align normal to an underlying monolayer of P3HT on the HOPG surface. STM studies of nanotube/polymer mixtures revealed that the P3HT chains are adsorbed on nanotubes surface in such a way that the thiophene and hexyl moieties of the polymer associated with the nanotube surface in identical manner to P3HT monolayer depositions on graphite. This resulted in the increased order as inferred from adsorption UV-Vis spectroscopy, where the polymer chains, which are otherwise prone to chain kinks and twists in solution, adopt a planar configuration when adsorbed onto the nanotube surface.

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12

Yu-HaoChen and 陳昱豪. "Studies of organic non-volatile memory device with polymeric charge trapping layer." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/05335209916994038869.

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碩士
國立成功大學
光電科學與工程研究所
98
We investigated organic non-volatile memory devices that are operated at low-voltage and are based on organic thin-film transistors (OTFTs) with pentacene as an active layer. Hafnium dioxide (HfO2) was used as the main gate dielectric to reduce operation voltage. Four kinds of polymer materials were used as the charge trapping layer, which was created via a spin-coating process on the HfO2 layer. The four kinds of polymer materials that were employed included poly(vinyl alcohol) (PVA), cross-linked poly(4-vinylphenol) (C-PVP), polystyrene (PS), and polymethylmethacrylate (PMMA). The electrical characteristics of the organic non-volatile memory devices, including memory window, program/erase speed, retention, and endurance, were also discussed. We studied the influence of the surface properties of polymer charge trapping layers on the morphology of pentacene films and the electrical characteristics of the corresponding memory devices. When PVA was used as the charge trapping layer, the memory window of the device was the largest (i.e., 3.46 V) as compared to the memory windows when using the other polymer layers. Atomic force microscopy measurements indicate that the surface morphologies of PVA and the pentacene layer on PVA both exhibited a relatively high amount of surface roughness. Moreover, a large difference in surface energy was observed between the pentacene layer and the PVA surface. As a consequence, we suggest the possibility of a considerable amount of trap states in the pentacene/PVA interface, thereby causing a large threshold voltage shift in the device. Compared with other organic non-volatile memory devices, the device with the PMMA charge trapping layer shows superior electrical characteristics. Specifically, the device with PMMA has a 2.41 V memory window after a 20 V program operation for 1 sec, and approximately 81% of the memory window still remains after 103 sec. Additionally, good endurance properties were also observed after 40 program/erase cycles. In conclusion, we have demonstrated a simple and inexpensive approach for the low-temperature fabrication (＜200 ℃) of low-voltage operated (＜ 25 V) organic non-volatile memory devices with polymer charge trapping layers. These devices also show excellent endurance properties after multiple program/erase cycles.

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13

Liang, Ji-Ting, and 梁紀庭. "Schottky Barrier Multibit Charge-Trapping Flash Memory." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/26348063641353357830.

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14

Tsai, Tzu-Ting, and 蔡姿婷. "Effects of Stacked High-K Charge trapping layers on Charge Trapping-type Flash Memory Device." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/00933864216135054107.

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15

Liu, Te-Chiang, and 劉得強. "Operation Characteristic of Charge-Trapping-type Flash Memory Device with Charge-trapping layer of stacked dielectrics." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/48553041687300820363.

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16

游承諺. "Device Physics of Polymer Solar Cell: Charge Trapping Mechanism." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/14580335766815797192.

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17

En, Tseng Hao, and 曾浩恩. "Device Physics of Electroluminescent Polymer: Charge Transport and Trapping Mechanism." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/ceuqc9.

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Анотація:

博士
國立清華大學
化學工程學系
93
Poly(phenylene vinylene) (PPV), polyfluorene (PF) and their derivatives are the most popular electroluminescent polymers due to their semi-conductive and good fluorescent properties. However, the charge transport, trapping, detrapping and recombination mechanisms have not been well known so far. Issues such as the assignment of trap polarity (hole or electron), the exact effect of the trap states on the charge mobility, and the relationships between detrapping carriers and radiative recombination… etc, are rarely discussed in documents. This is because that both the semi-conduction capabilities and chain relaxation complicate these questions. As a result, standardized instruments for these researches are not commercial available now. In this research, therefore, we used homemade apparatus assemblies for thermally stimulated current (TSC), thermally stimulated luminescence (TSL), time-of-flight (TOF), and time resolved electroluminescence spectroscopy (TREL) to investigate the charge transport and trapping mechanisms of conjugated polymers. By using TOF-based TSC, the trap states of hole and electron in MEH-PPV can be clearly assigned. The hole trap is located at about 210 K with an activation energy of 0.1-0.4 eV. This trap state is not affected by the ambient air and the change of morphology, which is attributed to the extrinsic impurities. The observed electron trap is located at about 300 K with an activation energy of 0.45-0.5 eV. Since the trap concentration increases by the exposure to oxygen and is reversible, it is attributed to the molecular oxygen. It is worth noting that the trap peak shifts to higher temperature as the drain field increases. This behavior is firstly observed by TSC measurement and indicates that electron mobility decreases as field increases. It can be attributed to the field-induced localization or positional-disorder dominant transport. The transport properties observed in TSC measurement are in agreement with those from TOF measurement. In MEH-PPV, electron transport is poor and electrons can not move across a 1.5-μm-thick film. Contrarily, holes can travel through a 8-μm-thick film, indicating a better transport. The relaxation currents for side chain and main chain can be observed unambiguously by TSC measurement, indicating that TSC is chain-relaxation-sensitive technique. The peak location and activation energies of detrapping current for electrons and holes are in agreement with those of side chain and main relaxations, implying that chain motion can induce carrier detrapping. The most possible form for molecular oxygen to catch an electron is “O2- “. Since the electron affinity of O2- (0.89eV) is smaller than that of MEH-PPV (2.8 eV), an electron prefers to stay on the conjugated main chain but slightly attracted by the adjacent molecular oxygen. A complex of MEH-PPV…e…O2 is likely to form. The onset temperature for electron detrapping is close to that of main chain relaxation, indicating that electron can escape from the attraction of oxygen as long as the main-chain relaxations start. The electron could be released at room temperature. However, serious retrapping makes these sites readily for charge recombination and then non-radiative decay. This will result in low efficiencies for electroluminescence devices. By the simultaneous measurement of TSC and TSL on MEH-PPV, the TSL emission contributed by geminate pairs (an intermediate between exciton and free carrier) can be investigated. In this research, the “two step excitation” method is firstly applied and we find that geminate pairs could be dissociated by the incident light. The wavelength dependent TSL is a result of dynamic balance. The incident light not only generates excitons to form geminate pairs but also dissociate them at the same time. This behavior implies that the geminate pairs may have characteristic absorption profile. This observation is very helpful to investigate carrier generation process. By fitting of photocurrent transient equation (PTE) to the non-dispersive, dispersive, and highly dispersive photocurrents, the charge mobility μfit and diffusion coefficient D can be obtained at the same time. PTE can perfectly fit the experimental data of different polymers and their films with different morphology. The thus obtained mobility is close to those determined by t1/2 (from the TOF results), which is close to the average mobility. By defining a deviation parameter Dv=Dq/μkT, large deviation from Einstein’s law is observed in all of the investigated polymers. The degree of this deviation is in agreement with the tail-broadening parameter W, which is widely used parameter for dispersion in photocurrent transients. Therefore, Dv can be regarded as an indicator of dispersion. This result also reveals that the larger deviation from Einstein’s law, the more dispersion in the transport behaviors. Since the D value characterizes the photocurrent transients in different type of polymers and films with different morphology, it lumps all factors together that cause the dispersion in carrier transport. From the TOF measurement, the copolymer PFOR1 (containing only 1% red Ir complex) has the hole mobility 2 orders of magnitude lower than PFO; and PFOR12 (with 12 % Ir complex) has an even lower hole mobility. These results indicate the occurrence of hole trapping on the side-chain Ir complex. In the TSC measurement, however, no trap currents were found. The reason is that Ir complex is an efficient recombination center because the HOMO and LUMO lay between those of the main chain (PFO), which permits both hole and electron to be trapped and recombine at these sites. Cabarzole is a hole-transport material. However, hole traps are formed and the hole mobility decreased about one order for carbazole-grafting polyfluorene (CzPF), as compared with that of PFO. By using photoexcitation and field-induction TSC, two hole traps were found and the distribution of trap currents and activation energies are in agreement with that in PVK. This two trap states are attributed to two types of Cz-Cz dimer. From the result of time-resolved electroluminescence (TREL) measurement, the monomeric emission from the annealed device increases with time in the initial operation period but decreases with time after the bias is off. This behavior indicates that aggregates are sites for charge trapping and recombination and function as dopant. Since the activation energy of aggregates is quite small so that the detrapping currents are difficult to be detected by TSC measurement.

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18

呂承勳. "Enhanced Operation Characteristics of Charge Trapping Flash Memory Devices with Nitrogen Incorporation and Bandgap Engineering in Charge Trapping Layer." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/16456296207794730051.

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19

Wang, Yu. "Uniform and localized charge-trapping in SONOS nonvolatile memory devices /." Diss., 2005. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:3167086.

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20

Lin, Yuan-Sheng, and 林元生. "Nonvolatile Memory with Germanium-Based Material as Charge Trapping Layer." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/38360743062656892208.

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21

Po-HsienKe and 柯伯賢. "Nitrided TiO2 as Charge Trapping Layer for Nonvolatile Memory Devices." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/73puet.

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Анотація:

碩士
國立成功大學
材料科學及工程學系
102
Abstract Flash memories using poly-silicon as charge storage layers are the mainstream of conventional nonvolatile memories (NVM). However, flash memories face the difficulty in continued dimension down-scaling because of sidnificant charge losses through the floating gate. Therefore, MONOS nonvolatile memory devices have been developed to resolve the issue. Owing to their reliable charge storage capability, nitrided charge trapping layers promise to use thinner tunnelling oxide without losing the nonvolatility, and consequently to lower operating voltage and increase operating speed. In this thesis, we have successfully fabricated MONOS CTM (charge trapping memories) with an Al/ SiO2/ TiO2 (or TiON)/ SiO2 /Si structure. After a standard Radio Corporation of America (RCA) cleaning, a 3-nm SiO2 as a tunneling layer (TL) was grown on the silicon substrate by thermal dry oxidation. Then, a 3-nm TiO2 (or TiON) charge trapping layer (CTL) was deposited on the SiO2 by RF sputtering a pure Ti target in a pure O2 or mixed N2/O2 (2:1) ambient. Following that, 15-nm SiO2 blocking layer was deposited by RF sputtering a pure Si target in a pure O2 ambient. Then, the dielectric stacks went through a post deposition annealing in O2 ambient at 900℃ for 1 min. Finally, Al was sputtered and patterned as a gate electrode. All electrical measurements were carried out under a light-tight and electrically shield condition. The current density-voltage (J-V) curves were measured with the Agilent 4156 C semiconductor parameter analyzer. The capacitance-voltage (C-V) and dissipation-voltage (D-V) curves were measured with the Agilent 4294A LCR meter. The program/erase operations were done with Agilent 81101A pulse generator. The material characteristics of the high-k dielectric films were analyzed by transmission electron microscopy (TEM) and the X-ray photoelectron spectroscopy (XPS). HRTEM cross-section images of the MONOS capacitors confirm the physical thickness of the charge-trapping film for both TiO2 and TiON CTMs is 3nm. The blocking layer and tunneling layer are 15 and 3nm, respectively. Compare with the TiON one, there is an apparent interlayer at the CTL/TL interface for the TiO2 CTM, which can be futher confirmed by the XPS analysis. XPS spectra illustrate that sputtering with a nitrogen containing ambient does effectively incorporate nitrogen into TiO2 to form TiON. XPS analysis also reveals a Ti-silicate interlayer formed at the CTL/TL interface of the TiO2 CTM, but not in the TiON one. This can be ascribed to the suppression of elemental inter-diffusion owing to the nitrogen incorporation in TiO2. The excellent electrical performances (large C-V hysteresis memory window, high program/erase speed, and long retention) for TiON CTM indicate that nitrogen incorporated TiON CTL contains more and deeper trapping states in its band-gap, leading to its superior charge trapping capability as compared to the TiO2 CTL. I-V characteristics at variable temperatures (25-100℃) indicates that the leakage current of TiO2 CTM increases substantially with increasing temperature, but the leakage current of TiON CTM only increases slightly with increasing temperature. This observation can be attributed to the Ti-silicate formed at the TiO2-CTL/SiO2-TL interface, which becomes a charge loss path to degrade the leakage current. The silicate-facilitated charge loss also leads to the continuously shrunk C-V hysteresis memory window of TiO2 CTM with increasing temperature, while the memory window of TiON CTM becomes winder with increasing temperature. This study demonstrates that the TiON CTL fabricated by reactive sputtering in mixed N2/O2 (2:1) ambient will efficiently trap charges and inhibit the CTL/TL interfacial reaction, which is highly potential for high-performance charge-trapping nonvolatile memory application. Summary To fulfill the requirements of future Metal-oxide-nitride-oxide-silicon-type nonvolatile memories, e.g., large memory window, fast program/erase efficiency, and good data retention, extensive researches have been followed out to deliver high-k dielectrics for substituting Si3N4 as the charge-trapping layer (CTL) of MONOS memories, such as TiO2, HfO2, NiO, and Ga2O3, mainly due to their high charge-trapping capacity and appropriate conduction-band offset to silicon. In this work, electrical characteristics of TiO2 and nitrided TiO2 (TiON) as the CTL of MONOS memories are investigated. The interface quality, composition, and crystallinity of stack dielectric film are examined by transmission electron microscopy and X-ray photoelectron spectroscopy. Compared with the MONOS memory device without nitrogen incorporation in CTL, the one with nitrided TiO2 showed a wider memory window, a higher program speed with a low gate bias, and a fewer charge loss mainly due to nitrogen incorporation, which induces deeper charge trapping sites in the nitrided TiO2 film. In addition, the nitrided TiO2 will reduce shallow traps near the CTL/SiO2 interface, owing to the effective suppression in the formation of titanium silicate at the TiO2/SiO2 interface by nitrogen passivation.

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22

Huang, Ching Hua, and 黃清樺. "The High-k Charge Trapping Layer in Flash Memory Application." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/18415680719091711437.

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Анотація:

碩士
長庚大學
電子工程學系
99
In this thesis, the Ti-doped high-k ZrO2 material has larger dielectric constant and better characteristics. The RTA annealing process can repair the oxide defect and obtain a stronger bonding to improve the device characteristics. On the other hand, ZrO2 material was used as charge storage layer in flash memory. In our result, the ZrO2 material has better characteristics after annealing treatment at 800℃. The ZrO2 as charge storage layer has a memory window of 1.87 V, higher P/E speed, better data retention and superior endurance characteristics. In addition, we also use Ti-doped CeO2 material as charge storage layer and it shows better electrical characteristic at 900℃annealing. Finally, we study the Tb2O3 dielectric deposited on the strained-Si with in situ carbon incorporation (st-Si:C) grown on the p-type silicon substrate. The physical and electrical characteristics of Tb2O3 materials were investigated. In our result, the Tb2O3 dielectric deposited on the st-Si:C with RTA 800℃has better performance.

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23

Fu, Wei-Huan, and 傅暐洹. "Charge-Trapping Characteristics of Non-volatile Memory Using HfON Trapping Layer and HfO2/SiO2 Barriers." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/05290221402959471894.

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Анотація:

碩士
國立交通大學
光電系統研究所
101
With the developments of consumer and portable electronic devices, such as cellular phones, cameras memory cards, the nonvolatile memory (NVM) market grows rapidly recently. The NVM devices with high density, fast program/erase speed, good endurance and data retention have been attracted much attention. Have beenHowever, with flash memory entering 20nm technology node, the conventional poly-silicon floating gate (FG) flash memory faces serious challenges from stress-induced leakage current (SILC) -induced charge loss and cell-to-cell coupling. When the thickness of the tunneling oxide decreases, the SILC can discharge the whole FG via even one single defect. Moreover, traditional poly-silicon FG can cause the adjacent parasitic capacitance and make the electrons move freely between the components, and thus significantly reduce the device reliability, such as data retention and endurance. As a technology breakthrough, charge trapping flash (CTF) memory is proposed to replace the traditional FG flash memory due to its localized charge storage and coupling-free structure. With the demands for low voltage and high reliability in further scaling down, this work focused on the research on novel CTF devices with stacked high-k structures. By introducing high-k dielectrics and the concept of band engineering, we proposed novel gate stack structures for future CTF application to improve the characteristics of CTF devices. In this thesis, we proposed an improved metal/oxide/nitride/oxide/Si-substrate (MONOS) structure with a high-k HfON as trapping layer and HfO2/SiO2 barrier as double tunneling and blocking layers. The good memory performances were obtained, including a 4.7 V initial memory window, a 3.4 V retention window after 104 seconds at 25℃, and a 4.2 V endurance window after 104 cycles under ± 18 V program/erase (P/E) for 100 ms, showing a strong potential in high-performance non-volatile memory application.

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24

Hsu, Shu-Ning, and 許書寧. "AlTiO and AlTiON as charge trapping layer for nonvolatile memory applications." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/pqyg97.

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Анотація:

碩士
國立交通大學
電子研究所
105
Three-dimensional (3D) architecture has been the main trend of NAND flash memory in industry. Due to no necessity for isolating between each layer insulated charge trapping (CT) layer is used rather than traditional floating gate. Although, commercial 3D NAND was based on SONOS memory, the SONOS like memory or NC memory should be potential for the next generation 3D NAND. Since the 3D structure has a high aspect ratio, the deposition of charge trapping layer is necessary to have high conformity. An appropriate technique is atomic layer deposition (ALD). Thus, in this thesis we introduce new CT layers which were formed by a cyclic ALD deposition of TiO2 (or TiN)/Al2O3 layers and followed by rapid thermal annealing, which is named as ATO and ATON respectably. In this thesis material analysis of ATO and ATON layer was covered. ATO and ATON shown amorphous and no crystallization in the XRD analysis. In XPS analysis, ATON CT layer shows mostly TiO2 component rather than TiN and has less Ti, N ratio than which we expect. Then, MOSCAP with different CT layer was fabricated and measured. NN3 and NO3 MOSCAP can reach a 5 V memory window while NN5 and NO5 are about 3.5 V after programed 18 V for 1 sec. ATO layers show faster erase speed and poorer retention which indicates a shallower trap. Except NN3 sample, other samples can reach the commercial retention requirement of 10 years. Last, we fabricated VG TFT memory with NN3 and NN5 CT layer. The trend of memory characteristic coincide with MOSCAP. NN5 has a bigger ~6 V window and NN3 has about 3.5 V. In sum, the ATON layer deposition by ALD has a huge memory window and acceptable memory characteristics may be use as next generation 3D NAND memory

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25

Ku, I.-Chun, and 古依純. "Analysis and Modeling of Lateral Migration for Charge Trapping Flash Memory." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/33720965491595422840.

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Анотація:

碩士
國立清華大學
電子工程研究所
98
Recently, Flash technology is gradually migrated from floating-gate cells to charge-trapping devices due to lowing operating voltage and two-bit storage. However, it also a great challenge for that the local distributions of trap charges will be lateral migrated after thermal various or endurance operation. Since the gate length of the cell devices are continued to scale down, it is crucial to realize the impacts of lateral migration on device characteristics for the programmed and the erased SONOS cells, specially the variations of threshold voltage. In this paper, using diffusion equation to realize the retribution of trapped charge, and then developing the model from gate voltage equation to provide a sound understanding of threshold voltage variations due to lateral migration. Through two-dimensional TCAD simulator MEDICI, the trapped charges are distributed uniformly within the nitride layer. And the conservation of the total trapped charges is assumed in this study. The characteristic lateral migration lengths are used to indicate the degree of lateral migration. Compare the results between the simulation and the modeling to analysis what is the reason in the difference. Eventually, we hope to develop a theoretical model to explain the retention loss characteristics by lateral-migrated trapping charges.

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26

Chen, Tin An, and 陳亭安. "Fabrication and Analysis of Nanowire Schottky Barrier Charge Trapping Flash Memory." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/94549668160688690512.

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Анотація:

碩士
國立清華大學
電子工程研究所
103
This thesis experimentally explores the process fabrication and measurement characterization of Schottky barrier nanowire charge trapping memories. Two different types of hard-mask lithography were examined to fabricate the gate-all-around nanowire structure. In cell characterization, this work studies the cell reading, programming, and erasing at room and higher temperatures. Reliability characterization in cycling endurance and data retention are also investigated. The results show that the high-temperature Schottky barrier nanowire charge trapping cells preserve good electrical characteristics.

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27

Eichenlaub, Nathan. "Design, characterization and modeling of charge trapping nonvolatile semiconductor memory devices." 2009. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:1463967.

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28

Chang, Ting-Yu, and 張廷瑜. "The Investigation of Charge-Trapping Flash Nonvolatile Memory by Using Ge Diffusion into Si3N4 Trapping Layer." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/73374988888532153086.

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Анотація:

碩士
國立交通大學
電子研究所
100
The rapid advancement of technology with a wide range of consumer electronics is popularity. In recent years, the requirements for memory are increasing and a variety of memory will be invented. Non-volatile flash memory are popular because of its high density, good data retention and program/erase (P/E), while widely used in various fields of electronic products, such as flash drives, mobile phones / camera memory card, many kinds of electronic product code stored ... and so on, faced with such a huge application, so the characteristics of flash memory for upgrading and improvement is an important issue. Majority of the flash memory market still use the traditional floating-gate memory type, but because of the traditional floating-gate using poly-silicon as the charge trapping layer, after the numerous program and erase operation, carriers (electrons) have moved freely in the poly-silicon, and also very easy back to the silicon substrate through the electronic defects caused by damage in the oxide layer, resulting in the loss of a lot of information, especially serious when the size scale down. And poly-silicon also cause the adjacent parasitic capacitance between the components, making the electrons move freely between each components, and thus reduce the reliability. So for data preservation (Retention) and durability (Endurance) under consideration, nitride has the characteristic of discrete charge-trap, and has the potential to replace the traditional poly-silicon. Charge trapping type consist of the following structure: poly-silicon / metal gate - oxide - silicon nitride - silicon (SONOS / MONOS), solve the problem of the traditional floating gate, and has a good charge storage capacity, low-voltage consumption, and can be embedded with complementary metal-oxide-Semiconductor FET devices (CMOS) manufacturing process, some company have begun to use charge trapping type in their production and replace the traditional floating gate type. In order to improve the characteristics of Si3N4, we used the Ge diffusion into Si3N4 trapping layer which is different from the usage of ion implantation. We let Ge diffuse into the Si3N4 and react with Si3N4 by high temperature rapid-thermal annealing (RTA). In addition, the band offset in LaAlO3/SiO2 double tunnel layers lowers tunneling barrier for faster P/E speeds and better endurance. The high-κ blocking and trapping layers lower the P/E voltage. In this study, we compare the Si3N4 and Ge/Si3N4 Charge-Trapping (CT) flash devices. We report a Ge/Si3N4 CT flash memory at a record thinnest 3.5-nm ENT trapping layer, this device has an initial 2.9 V memory window, good retention of 1.7 V extrapolated 10-year retention window at 25oC and 2.3 V endurance window at 105 cycles were measured, under fast 100 μs and low ±16 V P/E. These were achieved by using Ge diffusion the Si3N4 and reacting with Si3N4 to form the GeSi2N4 for better charge storage.

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29

Cheng, Chia-Hsin, and 鄭家欣. "Process Study of Trapping and Blocking Layers on Gate-All-Around Junctionless Charge Trapping Flash Memory Devices." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/79s7v3.

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Анотація:

碩士
國立清華大學
工程與系統科學系
105
In recent years, flash memory device can be continuously scaled down by continuous advance in process technology. However, the scale down of planar flash memory device can not be continued due to its limitation of shrinkage. How to increase the density of memory devices and enhance operating characteristics are important issues. Some approaches have been reported to solve these issues, such as high-k material, junctionless (JL) channel, poly-Si channel, nanowire (NW) structure, gate all around (GAA) structure and 3D stack devices. In this thesis, operation characteristics of flash memory GAA devices are improved by enhance electric field at channel cornors. Operation characteristics of GAA device with different charge trapping layers and blocking oxides layers are also studied. In the first part, tunneling oxides of devices with NW and GAA structure are formed by low-temperature inductively coupled plasma chemical vapor deposition (ICPCVD) and high-temperature rapid thermal oxidation (RTO) and Si3N4/HfO2 trapping layers are applied. In this work, program speed of gate all around device is faster than that of NW one due to larger enhancement of electric field. Reliabilities of GAA decice are worse than that of NW one due to poor step coverage of tunneling oxide layers are formed by ICPCVD. In the second part, Si3N4/HfO2 and Si3N4/ZrO2 stacked trapping layers are deposited by low-pressure chemical vapor deposition (LPCVD) and atomic layer deposition (ALD), and tunneling oxides are formed by RTO. Device with Si3N4/ZrO2 stacked trapping layers shows faster erasing speed are compared to that with Si3N4/HfO2 ones. Additional Al2O3 trapping layer are added between Si3N4 and HfO2 or ZrO2 layer. Results show that both retention and endurance are improved by the additional Al2O3 layer. In the last part, effects of stacked blocking oxide layers on operation characteristics of GAA flash memory devices are investigated. Results show that programing and erasing speed of devices with or without stacked blocking layers are similar. Retention characteristics at high-temperature are improved by stacked blocking oxide layers.

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30

Yang, Hao, and 楊. 皓. "Double Stacked Charge Trapping Layer on Poly-Si Nanosheet Channels Nonvolatile Memory." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/7958x4.

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31

Hsu, Che-Jui, and 許哲睿. "Memory Characteristics of Advanced Metal-Oxide-Semiconductor Structured Nonvolatile Memory with HfLaTiON as Charge Trapping Layer." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/sfnn42.

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Анотація:

碩士
國立虎尾科技大學
機械與機電工程研究所
98
Abstract In this thesis, the development of electrical and reliability properties measurement system for nonvolatile memory devices was achieved by the visual basic (VB) software. The electrical and reliability properties include hysteresis, programming time, erasing time, endurance and retention. To avoid the personal errors, automatically measurement systems integrated with HP4284A, HP5270B, HP5250, and HP81110A instruments were developed. Memory characteristics of advanced metal-oxide-semiconductor structured nonvolatile memory with HfLaTiON as charge trapping layer were investigated. The continuous improving non-volatile memory performances are needed for faster speed, lower operation voltage and longer data retention. To achieve this goal, the HfLaTiON dielectric as charge trapping layer was used to improve the data retention. The lower operation voltage is obtained by using HfLaON as tunneling oxide. The fast speed, especially for the slow erase speed, was improved by using HfLaO/HfLaTiON/HfLaO stacked films. By modulated Ti concentrations and position in HfLaTiON dielectric embedded in HfLaON dielectric, the high-quality HfLaTiON charge trapping layer can be achieved for the nonvolatile memory (NVM) devices applications. The results indicate that the hysteresis characteristic, programming/erase time enhanced by the increases of the Ti concentrations incorporated into HfLaTiON dielectric and Ti embedded into the underneath of HfLaTiON.

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32

Shiu, Feng-Wen, and 許逢文. "Effects of Stacked High-k Blocking Layer on Charge-Trapping Flash Memory Devices." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/09742273730644922957.

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Анотація:

碩士
國立清華大學
工程與系統科學系
98
When floaging gate device can't satisfy smaller device, SONOS-Type is the one of candidate to replace it. SONOS-Type device tunneling layer thickness is about 30A ,it is a problem for retention. How to improve our device performance is very important. In our experiment, using various high-k dielectrics as stacked SONOS-Type blocking layer. Different materials has different performances , matching stacked structure by nitrogen treatment with distinct doses(2mins , 4mins, 8mins) , bandgap-engineering, k-value as a excellent blocking oxide layer. For tunneling oxide, the application of multilayer dielectric stacks is promising to realize tunnel barrier engineering. With a suitable combination of stacked tunneling oxide(low-k/high-k),a lower operation voltage can be achieve. Using Al2O3/HfAlO as blocking layer has better performance than other stacked structures. Take high bandgap material as first layer blocking layer ,and secondly stack higher k material can improve device performance. Stacking a high quality film as blocking layer first and then stack various high-k materials by PIII nitrogen treatment can reduce crystallize and enhance retention , promote device reliability after high temperature annealing process.

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33

Tsai, Cheng-Yu, and 蔡政育. "The study of charge trap flash memory device with band engineered trapping layer." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/47291991120299568898.

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Анотація:

碩士
國立清華大學
工程與系統科學系
98
1.Improvement of P/E speed for NAN structure trapping layer higher charge tunneling efficiency lower Ig 2.Trapped charge detrap easier for HfO2 compared with Si3N4,but that’s a trade-off : erasing speed ? retention 3.Improvement of endurance characteristics for NAN structure compared with single Si3N4 trapping layer barrier oxide(Al2O3) reduces the trap generation during cycling 4.Simultaneous improvement in P/E speed and retention for Si3N4/Al2O3/HfO2 structure

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34

Chen, Yen-Ting, and 陳彥廷. "Atomic Layer Deposition of HfON Thin Film for Charge Trapping Flash Memory Application." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/96822231653032390505.

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35

Lin, Wen-Shin, and 林文新. "Study on Fluorine Applied to Nonvolatile Memory Using HfO2 as Charge Trapping Layer." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/36695585983895262265.

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Анотація:

碩士
國立交通大學
電子研究所
98
In order to save the cost, increase the throughput and decrease operation voltage, many kinds of the devices are continually scaling. Undoubtedly, the nonvolatile memory (NVM) device is one of the scaling devices. Moreover, Current requirements of nonvolatile memory are the high density cells, low-power consumption, high-speed operation and good reliability for the scaling down devices. There are many studies that discuss how to improve the reliability including retention and endurance. In this study, silicon oxide (SiO2) is grown for tunnel oxide layer. The trapping layer of traditional SONOS structure is silicon nitride (Si3N4) which is replaced with hafnium oxide (HfO2). After HfO2 is deposited, we proceed to CF4 plasma treatment. Then, SiO2, composed of tetraethoxy silane (TEOS), is deposited as blocking oxide. While the memory window of HfO2 is larger than Si3N4, the retention performance -ivof HfO2 is worse than Si3N4. In order to improve the retention performance, we use CF4 plasma treatment to diffuse fluorine into HfO2 after HfO2 is deposited. The fluorine is incorporated into the HfO2 trapping layer and then formed of Hf-F bonding with hafnium. Because of CF4 plasma treatment, the shallow traps would be recovered but the deep traps would still be left. The carriers’ de-trapping effect is decreased after program operation. Hence, the retention performance would be better. We probe into the electrical characteristics of the capacitors and the SOHOS memory devices. From fundamental electric characteristic data, we could know retention information. In materials analysis, X-ray photoelectron spectroscopy (XPS) is used to analyze the devices which were carried out CF4 plasma treatment and confirm if there is the Hf-F bonding. Besides, the secondary ion mass spectroscopy (SIMS) analyses show depth profiles of fluorine in the devices. According to the experiment results, the retention performance of NVM, carried out CF4 plasma treatment, is actually improved. Moreover, CF4 plasma treatment is compatible with the conventional SONOS memory process. It is also the low thermal budget process which would not make the HfO2 film more crystallized. Therefore, we all consider the process technology is potential and expectable gradually for the memory device in the future.

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36

Liu, Chi-Ling, and 劉奇靈. "Improvement of Charge Trapping/ Detrapping Efficiency by Ion Bombardment for NAND Flash Memory." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/90775190474831345951.

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Анотація:

碩士
逢甲大學
產業研發碩士班
98
According to ITRS roadmap, flash memory have some challenge about shrinkage of device size. However, flash memory must maintain the device reliability and improve the device characteristic. These are the main topics for the future research. We used ion bombardment method as lightly damage on effective tunneling layer to improve the charge trapping/detrapping efficiency. The surface roughness was increased after ion bombardment and the local electrical field mechanism enhance the charge trapping/detrapping efficiency. Otherwise, ion bombardment method brought about additional trap sites that could improve the density of trap site. The analysis demonstrated that ion bombardment could improve the charge trapping/detrapping efficiency obviously. The program/erase speed was fast either. The memory window width was extended. In other words, we could make the operation voltage lower in the same width of memory window. This method can be made use of decreasing operation voltage for the future demands.

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37

Ye, Zong-Hao, and 葉宗浩. "Applications of Band Engineering and Nitrogen Profiles in Charge-Trapping Flash Memory Devices." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/69517986608575673412.

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Анотація:

博士
國立清華大學
工程與系統科學系
104
As the demands for personal cameras, laptops, and smart-phones increase, development of nonvolatile memory (NVM) is rapidly expanding. NVM devices with faster programming/erasing (P/E), excellent retention and endurance characteristics are required. To achieve this goal, many methods have been applied to Charge-trapping (CT) flash memory devices. This dissertation firstly reviews the literature on CT-flash memory. According to the literature, P/E speeds can be improved by applying high-k materials to the charge-trapping layer of CT-flash memory devices. However, its poor retention that arises from the low crystalline temperature of high-k materials is an issue. To overcome this issue, a stacked structure of Si3N4 and high-k materials is proposed herein. Experimental results indicate that a stacked Si3N4/HfO2 charge-trapping layer can improve the erasing and retention operations of CT-flash devices. These improvements are attributed to the smaller valence band offset of Si3N4 to Si and the higher barrier for electron detrapping from HfO2 to Si3N4. The programming and retention characteristics of CT-flash memory devices can be further enhanced by a Si3N4/Al2O3/HfO2 as the CT layer to increase the number of injected charges that are trapped at the Si3N4/Al2O3 interface, and to provide a high barrier to electron detrapping from HfO2. Band engineering must be performed on the blocking layer to improve the performance of CT-flash memory. In this dissertation, various stacked blocking layers with various band structures are studied. The results indicate excellent data retention of devices with a sealing layer (SL) / Al2O3 blocking layer without loss of P/E speeds. The programming, erasing, and retention characteristics of CT-flash devices can be further enhanced by using the high/low/high (HLH) triple barrier structure with Al2O3/HfAlO/Al2O3 blocking layers. The effects of thickness of the blocking oxides in a multilayer barrier structure are studied by simulating the gate current density in a metal/insulator/metal (MIM) device. All MIM structures with triple insulator have the same electrical oxide thickness (EOT) and different thicknesses for each layer. Simulation results show a thin second layer for triple blocking layer with an HLH barrier structure is preferred because its gate current density is smaller. Finally, the operating characteristics of CT-flash devices with different nitrogen profiles in gate stack are studied. Two peaks in the nitrogen depth profile are formed by plasma immersion ion implantation (PIII) nitridation treatment. A shallow peak is obtained in the blocking layer and a deep peak is obtained in the CT layer. Nitrogen can passivate defects in the interface and increase the number of deep trapping sites in the bulk. Therefore, the properties of nitrogen are determined by their locations in the gate stack. The results indicate that the nitrogen profile in the gate stack is more important than the nitrogen concentration therein. A nitrogen profile that has a deep peak with a high concentration and shallow one with a suitable concentration (< 18 %) is optimal for PIII nitridation treatment.

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38

Lee, Hsiang-Chen, and 李祥丞. "Effects of the scaled charge trapping layer on SONOS type non-volatile memory." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/93668147445726615028.

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Анотація:

碩士
國立清華大學
電子工程研究所
97
Recently, Flash technology is gradually migrated from floating-gate cells to charge-trapping devices due to lower operating voltage and two bits storage. However, it is also a great challenge to scale the conventional charge-trapping Flash cells for the need of high voltage operations in channel-hot-electron (CHE) programming and band-to-band-hot-hole (BBHH) erasing. This thesis experimentally examines the scaling effects of the nitride charge-trapping layers on Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) type Flash memory. The reduction of nitride charge trapping layer offers the enhancement of programming and erasing speed for the SONOS type memory cell. However, it leads to the serious degradations in the memory window during 10K programming/erasing cycling and the retention charge loss after 10K cycling stress. Trade-offs between the performance enhancement and cell reliability exist to limit the further scaling of charge trapping layers for future non-volatile memory cells.

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39

Lin, Hsin-Yi, and 林欣逸. "Study of Fin-shaped Nanowires Tunneling-Field-Effect-Transistor Charge Trapping Nonvolatile Memory." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/21574027888647336316.

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Анотація:

碩士
國立清華大學
工程與系統科學系
101
The Pi-gate polycrystalline silicon (poly-Si) nanowires tunneling field effect transistor (TFET) charge trapping(CT) nonvolatile memory (NVM) with all programming mechanisms and shows a large memory window and good reliability is demonstrated for the first time. Pi-gate nanowires structure performs faster program/erase speed. Otherwise, the SONOS-type structure can improve excellent reliability. Furthermore, due to the poly-Si channel technology, it is possible to develop in 3D high-density stacked NVM. In FN tunneling programming, operation of conducting current and program/erase are based on all quantum tunneling transportation. Pi-gate T-SONOS NVM generates a large memory window (ΔVth=4.75V at Vg = 17V, tp = 1ms) and excellent reliability of 88 % endurance behavior after 10k P/E cycles and 65 % retained ability for ten years at 85 oC. In CHE programming, Pi-gate T-SONOS NVM presents a large memory window (ΔVth=4V at Vg=8V, Vd=6V, tp=1ms), and 74 % endurance behavior after 10k P/E cycles. Moreover, a superior 81 % retention behavior for ten years at 85 oC is presented. In BBHE programming, Pi-gate T-SONOS NVM performs a high programming efficiency, larger memory window (ΔVth=4V at Vg=3V, Vs=-6V, tp=1ms), excellent reliability of 74 % endurance after 10k P/E cycles and 63 % retention for ten years at 85 oC can be achieved. Based on above-mentioned description, Pi-gate nanowires T-SONOS NVM is suitable to use in future 3D high-density embedded portable applications with low stand-by power consumption and ultra low program voltage.

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40

Chen, Guan-Syun, and 陳冠勳. "Memory Characteristics of Metal-Oxide-Semiconductor Structured Nonvolatile Memory Capacitors with Terbium Oxides as Charge Trapping Layers." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/z7b669.

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Анотація:

碩士
國立虎尾科技大學
光電與材料科技研究所
101
Memory characteristics of metal-oxide-semiconductor (MOS) structured nonvolatile memory capacitors with terbium oxides (Tb4O7) as charge trapping layers were demonstrated in this work. First, the memory characteristic of MOS structured nonvolatile memory capacitors with various tunneling oxide were demonstrated. Then, the SiO2/Tb4O7/SiO2 stacked films in MOS structured nonvolatile memory capacitors with various gas ambient treated Tb4O7 as charge trapping layers were proposed. Various gas ambient treatments include oxygen and nitrogen. Furthermore, the MOS structured nonvolatile memory capacitors with Tb4O7 charge trapping layers and various blocking oxide thicknesses were also investigated. Finally, the effects of various Pt-doped Tb4O7 as charge trapping layers of MOS structured nonvolatile memory capacitors were presented. The results suggest that the memory effect is mainly due to the holes trapping. Compared with oxygen treatment, larger memory window can be achieved by incorporated more nitrogen into Tb4O7 dielectric. Furthermore, the better properties, including programming time, erasing time, and endurance, were presented by more nitrogen treated Tb4O7 dielectric as charge trapping layers. The programming time of 10-6 s for the sample with 20 nm of blocking oxide can be achieved. On the contrary, it should be 10 and 1 s for the other samples. The endurance of 1000 times for sample with the 20 nm of blocking oxide sample is better than that of the other samples. By tuning Pt-doped Tb4O7, the excellent memory characteristics, including the hysteresis, and the programming/erasing time, were be demonstrated. Compared with the sample without Pt-doped Tb4O7 dielectronics, there is a larger shift of 6.6 V for the sample with the sputtering time of 50 s. Moreover, the retension of 4000 s and the redurance of 1000 s were also be demonstrated for the sample with the sputtering time of 50 s.

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41

Cheng, Chia-Hsiang, and 鄭嘉祥. "Memory Characteristics of Metal-Oxide-Semiconductor Structured Nonvolatile Memory Capacitors with Dysprosium Oxides as Charge Trapping Layers." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/68qkpk.

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Анотація:

碩士
國立虎尾科技大學
光電與材料科技研究所
101
Characteristics of metal-oxide-semiconductor (MOS) structured nonvolatile memory (NVM) devices with various dysprosium oxide (Dy2O3) dielectrics as charge trapping nodes have been presented in this study. The memory characteristics include hysteresis, programming/erasing time, endurance, and retention. First, various tunneling oxides were formed by tuning various rapid thermal annealing (RTA) temperatures. Then, the effects of post-deposition annealing (PDA) on Dy2O3 charge trapping layer of MOS structured NVM were investigated. Furthermore, characteristics of MOS structured NVM devices with various stacked SiO2/Dy2O3 dielectrics as blocking oxide/charge trapping nodes have been also presented. Finally, the effects of Pt-doped Dy2O3 dielectrics as charge trapping layers on characteristics of MOS structured NVM devices were demonstrated. The results suggest that the better programming time can be demonstrated for the capacitor with the SiO2 tunneling oxide annealing at 900 ℃ and the Dy2O3 trapping layer treated at 750 ℃. Then, capacitance-voltage (C-V) measurements estimate that the memory window of 3.24 V was achieved during the C-V hysteresis sweep at ?19 V. The hysteresis characteristics measurements illustrate that the memory is mainly due to holes trapping. The larger memory window and the better erasing characteristic as well as the better programming characteristic, attributable to the thicker trapping layer (Dy2O3 dielectrics) and the thinner blocking oxide layer (SiO2). Thus, the stacked SiO2/Dy2O3 dielectric of 20/15 nm was demonstrated for MOS nonvolatile memory device applications. Moreover, a larger hysteresis shift of 11.48 V sweep at ±19 V, a faster programming time, and a lower operated voltage can be achieved by the Pt-doped Dy2O3 ¬trapping layer under the sputtering time of 30 s.

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42

Lai, Sheng-Chih, and 賴昇志. "A Study of Future Non-volatile Memory Technologies - Charge Trapping NAND Flash Memory and Low Temperature Processed FeRAM." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/84983799650715087564.

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Анотація:

博士
國立清華大學
材料科學工程學系
96
Non-volatile semiconductor memories have attracted much attention due to the fast growing demand of portable electronic devices. In this thesis, the erase mechanism and the performance of the state of the art SONOS-type flash memories are critically examined, and a low temperature extended-pulse laser annealing for COI FeRAM is also studied. In the study of innovative SONOS-type flash memories, a de-trapping model for the erase mechanism of MANOS device is proposed and demonstrated. In addition, the erase and retention characteristics for MONOS, MANOS and BE-SONOS devices are fairly compared by using the transient analysis method. Moreover, an innovative BE-MANOS is proposed to overcome the erase saturation and to enlarge the memory window. However, the retention of BE-MANOS is not as good as BE-SONOS owing to the charge leakage through Al2O3 film. By inserting a SiO2 buffer layer between Al2O3 and SiN storage layer, the oxide-buffered BE-MANOS shows good performance and good reliability, and the roles of high-k Al2O3 and SiO2 buffer layer are also clarified in this work. An extended-pulse laser annealing is used to provide sufficient thermal energy and time into the PZT film to complete the crystallization, while the bulk of materials remains at low temperature. In this work, the thermal simulation is also presented to illustrate the temperature distribution in the specimen and the benefits of the extended pulse. This new low temperature process is suitable for embedded COI FeRAM for SoC applications.

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43

Keng, Wen-Chun, and 耿文駿. "Application of SiGe Buried Channel on Electrical Characteristics of Charge-trapping Flash Memory Devices." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/40030450730645372796.

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44

Chang, Wei-Jen, and 張維仁. "Application of SiGe Buried Channel on Electrical Characteristics of Charge-trapping Flash Memory Devices." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/18831586821699289989.

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Анотація:

碩士
國立清華大學
工程與系統科學系
98
Abstract Charge-trapping (CT) flash is regarded as one of the most promising nonvolatile memory devices. Some approaches were proposed to further enhance the operation properties of CT flash devices by stacked high-k charge-trapping layer , stacked tunneling oxides with thicker physic thickness , metal gate with high work function, and SiGe buried channel(small band gap) . SiGe and Ge buried channel with different annealing temperature and various thicknesses of Si-cap layer on operation characteristics of charge-trapping (CT) flash devices were studied in this work. And We use different method to formation of high concentration SiGe layer or crystalline Ge layer. We can have 5 Conclusions, 1. Programming and erasing speeds of all samples with SiGe buried channel are faster than control sample.2. The thickness of Si-cap would affect the properties of programming and retention obviously.3. For deuces with pure Ge channel , lower annealing temperature should be better for the electrical properties of devices.4. The roughness of condensed SiGe layer would be a serious issue for the device fabrication.5. Good crystalline structure and low roughness SL layer would be a good buffer layer for the growth of crystalline Ge layer.

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45

Sun, Cherng-En, and 孫晟恩. "Electrical Characteristics for Flash Memory with pn-Junction Diode as the Charge-Trapping Layer." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/99464254432375680727.

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46

Liu, Yen-Ting, and 劉晏廷. "Study on the Novel High Speed Charge Trapping Memory Devices with Poly-Si TFTs." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/56237471861596607387.

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Анотація:

碩士
國立交通大學
電子研究所
98
In recent years, many researchers have drawn attention to improve the program/erase efficiency of charge trapping memory devices owing to the program/erase efficiency of conventional charge trapping memory devices is lower than that of floating gate memory devices. However, most methods of improving the program/erase efficiency resulted in poor reliability issues. In this thesis, our investigation has been classified into two topics. At first, for Poly-Si TFT SONOS memory devices, we have proposed a FinFET structure, an omega gate structure, and a GAA structure to investigate the corner effect. Since the sharp corner geometric will increase electric field in the tunneling layer and decrease electric field in the blocking layer, the program speed can be enhanced greatly. Consequently, the SONOS memory device with a GAA structure exhibits the highest program efficiency and it proves that SONOS memory devices with more corners will enhance program efficiency. On the other hand, we have proposed novel high speed Poly-Si TFT TANVAS and THNVAS memory devices with high-k blocking layer and vacuum tunneling layer. Utilizing high-k materials, such as Al2O3 and HfO2, as blocking layer or using low-k materials, like vacuum, as tunneling layer can increase electric field in the tunneling layer and decrease electric field in the blocking layer. Based on this field enhanced scheme, the proposed memory devices reveal excellent memory performance. It is shown obviously that the TANVAS and THNVAS memory devices have higher program/erase efficiency than the TANOS and THNOS memory devices. Furthermore, the conventional SiO2 tunneling layer is always suffered from damage after program/erase cycles. Using vacuum tunneling layer can overcome this obstacle so that the TANVAS memory device exhibits better endurance characteristics. Due to the traps in oxide tunneling layer and lower conduction band offset in HfO2 blocking layer will provide leakage paths for charges, the TANOS and THNVAS memory devices are not able to preserve stored charges for a long time. The TANVAS memory device can avoid these problems and presents great retention characteristics. Through investigating and analyzing the electrical characteristics, we obtain some satisfying results. The program/erase efficiency of proposed memory device is enhanced remarkably, and exhibits great endurance and retention characteristics. They are very promising for future applications in high density circuits and SOP.

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47

Fong-Chi, Shih, and 石豐綺. "Study on LTPS-TFT Flash Memory using High-k Material as Charge Trapping Layer." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/07856442760214408383.

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Анотація:

碩士
國立交通大學
電子工程系所
96
In this thesis, electrical characteristic and Reliability of low temperature poly- silicon thin film transistor nonvolatile flash memory have studied, including programming/erasing speed, retention, endurance, retention after cycling and programming disturbances. First, three kinds of high-k materials, SiNx, Al2O3 and Hf-silicate, respectively, were applied for charge trapping layer of n-channel TFT memories. The fabricated memory devices show great retention and disturbance characteristics, attributed to the thick tunneling oxide. Among these three materials, Al2O3 performs best. Then, the same three kinds of materials as mentioned above were applied for p-channel TFT flash memories. The p-channel memory devices show better programming speed, programming voltage and data retention ability than n-channel ones, result in the lowering of power dissipation. Among all p-channel memory devices, Al2O3 performs best, also. Last, the n-channel devices after NH3 plasma treatment show obviously improvement on endurance and data retention.

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48

Lu, Yu-Chin, and 盧育勤. "Improved Operation Characteristics of Charge Trap Flash Memory Devices by Engineering Stacked Trapping Layer." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/ahj6f9.

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49

Cheng, Cheng-Hsien, and 程政憲. "Application of SiGe on P-Channel SONOS-type Nonvolatile Memory and Study of Charge Distribution in Charge Trapping Layer." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/06591321728723849033.

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50

Lin, Hsiao-Len, and 林孝倫. "Effects of Metal Gate and High-k Blocking Layer on Charge-Trapping Flash Memory Devices." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/85788773007853849370.

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