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Статті в журналах з теми "Pixel Chip"

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Автор: Grafiati

Опубліковано: 14 березня 2023

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1

Li, M., W. Wei, X. Jiang, S. Cui, J. Zhang, B. Lu, and Z. Liu. "A charge-integration pixel readout chip features IR-drop effect mitigation by distributed LDOs." Journal of Instrumentation 17, no. 09 (September 1, 2022): P09043. http://dx.doi.org/10.1088/1748-0221/17/09/p09043.

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Abstract HYLITE (High dYnamic range free electron Laser Imaging deTEctor) is a charge-integration pixel detector readout chip, which is designed for SHINE (Shanghai high repetition rate XFEL and extreme light facility). The targeting pixel array of a full-size chip is 128 × 128 with a pixel pitch of 100 μm. The dynamic range of HYLITE is 1 ∼ 10000 photons at 12 keV, and the frame rate is 10 kHz. Large array size, high dynamic range, and high readout speed result in a big challenge of large power consumption and a significant IR-Drop effect. We implemented HYLITE0.2, which is the second prototype chip fabricated in a CMOS 130 nm process. Compared with HYLITE0.1, HYLITE0.2 aims to implement a full-function chip with a further shrunk pixel size, while the foreseen problem of severe IR-Drop effect of the full-size chip must be solved. To mitigate the IR-Drop effect, we proposed a novel architecture of distributed in-array Low-Dropout Regulators (LDOs). The pixel array consists of 16 × 24 pixels, and the full functionality was implemented within a pixel pitch of 100 μm. Measurements show that pixels powered by the proposed architecture work well, and the gain gradient of those pixels is 31.8% of the pixels powered by the conventional architecture.

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2

Li, M., W. Wei, X. Jiang, S. Cui, J. Zhang, B. Lu, and Z. Liu. "Prototype characterization of a charge-integration pixel detector readout chip with in-pixel A/D conversion." Journal of Instrumentation 17, no. 01 (January 1, 2022): P01003. http://dx.doi.org/10.1088/1748-0221/17/01/p01003.

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Abstract HYLITE (High dYmamic range free electron Laser Imaging deTEctor) is a hybrid pixel detector readout chip, which is designed for advanced light sources such as X-ray Free Electron Laser (XFEL) and diffraction-limited storage rings. It is a charge-integration readout chip which has three gains for different dynamic ranges and automatic gain-switching function. The full dynamic range covered by HYLITE is 1 ∼ 104 photons with an energy of 12 keV for each pixel in every shot. In-pixel ADC is designed to achieve front-end digitization and a 10 kHz continuous frame rate. HYLITE0.1 is the first prototype chip for functional verification that was produced in CMOS 0.13 μm technology. It consists of a pixel array with 6 × 12 pixels and a periphery with full standalone operation features. The size of each pixel is 200 μm × 200 μm. Three design variations of pixels with different integrating capacitance and structures were designed to optimize between area and performance. A 10-bit Wilkinson ADC is integrated in each pixel to digitize the outputs of the pre-amplifier. Therefore, analog signal transmission of long distance is avoided and a frame rate of 10 kHz can be achieved. In this paper, we present the design of HYLITE0.1 and the test results of this prototype chip.

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3

Kim, Sang-Hwan, Byoung-Soo Choi, Jimin Lee, Junwoo Lee, Jewon Lee, Jae-Hyoun Park, Kyoung-Il Lee, and Jang-Kyoo Shin. "Averaging Pixel Current Adjustment Technique for Reducing Fixed Pattern Noise in the Bolometer-Type Uncooled Infrared Image Sensor." Sensors 19, no. 7 (April 6, 2019): 1653. http://dx.doi.org/10.3390/s19071653.

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In this paper, we propose an averaging pixel current adjustment technique for reducing fixed pattern noise (FPN) in the bolometer-type uncooled infrared image sensor. The averaging pixel current adjustment technique is composed of active pixel, reference pixel, and calibration circuit. Polysilicon resistors were used in each active pixel and reference pixel. Resistance deviation among active pixels integrated with the same resistance value cause FPN. The principle of the averaging pixel current adjustment technique for removing FPN is based on the subtraction of dark current of the active pixel from the dark current of the reference pixel. The subtracted current is converted into the voltage, which contains pixel calibration information. The calibration circuit is used to adjust the calibration current. After calibration, the nano-ampere current is output with small deviation. The proposed averaging pixel current adjustment technique is implemented by a chip composed of a pixel array, a calibration circuit, average current generators, and readout circuits. The chip was fabricated using a standard 0.35 μm CMOS process and its performance was evaluated.

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4

Zoladz, M., P. Grybos, and R. Szczygiel. "X-ray imaging of moving objects using on-chip TDI and MDX methods with single photon counting CdTe hybrid pixel detector." Journal of Instrumentation 16, no. 12 (December 1, 2021): C12014. http://dx.doi.org/10.1088/1748-0221/16/12/c12014.

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Abstract X-ray imaging of moving objects using line detectors remains the most popular method of object content and structure examination with a typical resolution limited to 0.4–1 mm. Higher resolutions are difficult to obtain as, for the detector in the form of a single pixel row, the narrower the detector is, the lower the image Signal to Noise Ratio (SNR). This is because, for smaller pixel sizes, fewer photons hit the pixel in each time unit for a given radiation intensity. To overcome the trade-off between the SNR and spatial resolution, a two-dimensional sensor, namely a pixel matrix can be used. Imaging of moving objects with a pixel matrix requires time-domain integration (TDI). Straightforward TDI implementation is based on the proper accumulation of images acquired during consecutive phases of an object’s movement. Unfortunately, this method is much more demanding regarding data transfer and processing. Data from the whole pixel matrix instead of a single pixel row must be transferred out of the chip and then processed. The alternative approach is on-chip TDI implementation. It takes advantage of photons acquired by multiple rows (a higher SNR), but generates similar data amount as a single pixel row and does not require data processing out of the chip. In this paper, on-chip TDI is described and verified by using a single photon counting two-dimensional (a matrix of 128 × 192 pixels) CdTe hybrid X-ray detector with the 100 µm × 100 µm pixel size with up to four energy thresholds per pixel. Spatial resolution verification is combined with the Material Discrimination X-ray (MDX) imaging method.

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5

Braach, Justus, Eric Buschmann, Dominik Dannheim, Katharina Dort, Thanushan Kugathasan, Magdalena Munker, Walter Snoeys, and Mateus Vicente. "Performance of the FASTPIX Sub-Nanosecond CMOS Pixel Sensor Demonstrator." Instruments 6, no. 1 (February 8, 2022): 13. http://dx.doi.org/10.3390/instruments6010013.

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Within the ATTRACT FASTPIX project, a monolithic pixel sensor demonstrator chip has been developed in a modified 180 nm CMOS imaging process, targeting sub-nanosecond timing measurements for single ionizing particles. It features a small collection electrode design on a 25 micron thick epitaxial layer and contains 32 mini matrices of 68 hexagonal pixels each, with pixel pitches ranging from 8.66 to 20 micron. Four pixels are transmitting an analog output signal and 64 are transmitting binary hit information. Various design variations are explored, aiming at accelerating the charge collection and making the timing of the charge collection more uniform over the pixel area. Signal treatment of the analog waveforms, as well as reconstruction of time and charge information, is carried out off-chip. This contribution introduces the design of the sensor and readout system and presents the first performance results for 10 μm and 20 μm pixel pitch achieved in measurements with particle beams.

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6

López-Portilla, Bárbaro M., Wladimir Valenzuela, Payman Zarkesh-Ha, and Miguel Figueroa. "A CMOS Image Readout Circuit with On-Chip Defective Pixel Detection and Correction." Sensors 23, no. 2 (January 13, 2023): 934. http://dx.doi.org/10.3390/s23020934.

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Images produced by CMOS sensors may contain defective pixels due to noise, manufacturing errors, or device malfunction, which must be detected and corrected at early processing stages in order to produce images that are useful to human users and image-processing or machine-vision algorithms. This paper proposes a defective pixel detection and correction algorithm and its implementation using CMOS analog circuits, which are integrated with the image sensor at the pixel and column levels. During photocurrent integration, the circuit detects defective values in parallel at each pixel using simple arithmetic operations within a neighborhood. At the image-column level, the circuit replaces the defective pixels with the median value of their neighborhood. To validate our approach, we designed a 128×128-pixel imager in a 0.35μm CMOS process, which integrates our defective-pixel detection/correction circuits and processes images at 694 frames per second, according to post-layout simulations. Operating at that frame rate, our proposed algorithm and its CMOS implementation produce better results than current state-of-the-art algorithms: it achieves a Peak Signal to Noise Ratio (PSNR) and Image Enhancement Factor (IEF) of 45 dB and 198.4, respectively, in images with 0.5% random defective pixels, and a PSNR of 44.4 dB and IEF of 194.2, respectively, in images with 1.0% random defective pixels.

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7

Cui, S., W. Wei, J. Zhang, M. Li, H. Li, Z. Li, X. Jiang, et al. "A prototype pixel readout chip working in single photon counting mode with a novel charge sharing suppression scheme." Journal of Instrumentation 17, no. 07 (July 1, 2022): C07017. http://dx.doi.org/10.1088/1748-0221/17/07/c07017.

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Abstract Spectral distortion due to the charge sharing effect becomes a severe issue in single-photon counting pixel detectors. The HEPS-BPIX4 prototype chip, dedicated for the HEPS in China, implements a novel architecture to mitigate charge sharing and permit spectroscopic imaging with high efficiency. In the architecture, a central pixel communicates with others in a cluster of 3 × 3 pixels. The algorithm simulation showed a charge sharing elimination accuracy better than 90%. The prototype chip has been designed in a 130 nm CMOS technology. The preliminary measurements show a charge gain of 48 mV/ke− and an equivalent noise charge of 150 e− rms. Detailed tests in a 4 × 4 pixel array for the charge sharing are performed using electrical test pulses. The hit allocation in the core four adjacent pixels of the array indicates that effective suppression of charge sharing has been realized.

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8

Pinkston, Timothy Mark, and Charles Kuznia. "Smart-pixel-based network interface chip." Applied Optics 36, no. 20 (July 10, 1997): 4871. http://dx.doi.org/10.1364/ao.36.004871.

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9

Cadeddu, S., A. Lai, and M. Caria. "KPIX: a pixel detector imaging chip." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 487, no. 1-2 (July 2002): 175–80. http://dx.doi.org/10.1016/s0168-9002(02)00962-2.

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10

Christian, D. C., J. A. Appel, G. Chiodini, J. Hoff, S. Kwan, A. Mekkaoui, and R. Yarema. "FPIX2, the BTeV pixel readout chip." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 549, no. 1-3 (September 2005): 165–70. http://dx.doi.org/10.1016/j.nima.2005.04.046.

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11

Kmon, P., R. Szczygieł, R. Kłeczek, D. Górni, G. Węgrzyn, A. Niedzielska, K. Sitko, and P. Drwal. "Spectrum1k — integrated circuit for medical imaging designed in CMOS 40 nm." Journal of Instrumentation 17, no. 03 (March 1, 2022): C03023. http://dx.doi.org/10.1088/1748-0221/17/03/c03023.

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Abstract We present a multichannel integrated circuit of pixel architecture designed in CMOS 40 nm technology. The chip is composed of 40 × 24 pixels of 75 µm pitch working in the single photon counting mode, each built of front-end amplifier, peak and hold detector, 6-bit analog to digital converter, and memory composed of 64 × 12-bit counters. Thanks to the proposed functionality it is possible to store in each pixel separately information of incoming particles energy spectrum. The chip is dedicated to operating with both electrons and holes of 2.2 ke−–35 ke− energy range. The IC occupies an area of 2 × 4.5 mm2, is already back from fabrication, and is under preliminary measurements.

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12

Ahmad, Rizwan. "The Monitoring of Pixel System (MOPS) chip for the Detector Control System of the ATLAS ITk Pixel Detector." Journal of Physics: Conference Series 2374, no. 1 (November 1, 2022): 012094. http://dx.doi.org/10.1088/1742-6596/2374/1/012094.

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The ATLAS experiment will get a new inner tracker (ITk) during the phase II upgrade. The innermost part is called the Pixel Detector. A new Detector Control System (DCS) is being developed to provide control and monitoring of the ITk pixel detector. The Monitoring of Pixel System (MOPS) chip is an Application Specific Integrated Circuit (ASIC) foreseen in the DCS to independently monitor the voltage and the temperature across the modules which constitute the front-end electronics responsible for tracking and data readout. The chip is developed by the Bergische Universität Wuppertal in collaboration with the Fachhochschule Dortmund. The modules which need to be monitored are powered serially in a chain. The MOPS chip has a 12-bit ADC which can read up to 34 channels. Controller Area Network (CAN) and CANopen protocols are used for communication. The final chip is required to be radiation hard up to an ionizing dose of 500 Mrad. In this paper, the functionality of the chip will be discussed, some results from the first version of the chip will be presented as well as a brief overview of the second version.

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13

ELIA, D., G. AGLIERI RINELLA, A. KLUGE, M. KRIVDA, and M. NICASSIO. "THE PIXEL FAST-OR SIGNAL FOR THE ALICE TRIGGER IN PROTON-PROTON COLLISIONS." International Journal of Modern Physics E 16, no. 07n08 (August 2007): 2503–8. http://dx.doi.org/10.1142/s0218301307008161.

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The silicon pixel detector of the ALICE experiment at LHC comprises the two innermost layers in the inner tracking system of the apparatus. It contains 1200 readout chips, each of them corresponding to a 8192 pixel matrix. The single chip outputs a digital Fast-OR signal which is active whenever at least one of the pixels in the matrix records a hit. The 1200 Fast-OR signals can be used to implement a triggering capability: a few details on the pixel trigger system and some of the possible applications for the event selection in p - p collisions are presented.

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14

Grybos, P., R. Kleczek, P. Kmon, A. Krzyzanowska, P. Otfinowski, R. Szczygiel, and M. Zoladz. "Pixel readout IC for CdTe detectors operating in single photon counting mode with interpixel communication." Journal of Instrumentation 17, no. 01 (January 1, 2022): C01036. http://dx.doi.org/10.1088/1748-0221/17/01/c01036.

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Abstract This paper presents a readout integrated circuit (IC) of pixel architecture called MPIX (Multithreshold PIXels), designed for CdTe pixel detectors used in X-ray imaging applications. The MPIX IC area is 9.6 mm × 20.3 mm and it is designed in a CMOS 130 nm process. The IC core is a matrix of 96 × 192 square-shaped pixels of 100 µm pitch. Each pixel contains a fast analog front-end followed by four independently working discriminators and four 12-bit ripple counters. Such pixel architecture allows photon processing one by one and selecting the X-ray photons according to their energy (X-ray colour imaging). To fit the different range of applications the MPIX IC has 8 possible different gain settings, and it can process the X-ray photons of energy up to 154 keV. The MPIX chip is bump-bonded to the CdTe 1.5 mm thick pixel sensor with a pixel pitch of 100 µm. To deal with the charge sharing effect coming from a thick semiconductor pixel sensor, multithreshold pattern recognition algorithm is implemented in the readout IC. The implemented algorithm operates both in the analog domain (to recover the total charge spread between neighboring pixels, when a single X-ray photon hits the border of the pixel) and in the digital domain (to allocate a hit position to a single pixel).

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15

Sedgwick, I., S. Benhammadi, N. Guerrini, and B. Marsh. "Development of low noise pixels and readout architectures for scientific applications in a 180 nm CMOS image sensor process." Journal of Instrumentation 17, no. 11 (November 1, 2022): C11007. http://dx.doi.org/10.1088/1748-0221/17/11/c11007.

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Abstract Noise values of below 1e− for CMOS Image Sensors are now regularly reported for pixels with high conversion gain. This has allowed advances in many fields of imaging. However, there are also scientific applications where other properties such as radiation hardness are required alongside good noise performance. The layout changes required for this however, often lead to a reduction in conversion gain, making achieving the noise performance more challenging. In this paper, we present PRECISE, a test chip designed to apply the techniques of low noise imaging to pixels for other scientific applications, particularly those requiring radiation hardness. The design of the chip will be discussed, and first test results presented on some of the pixel types on the chip.

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16

Perić, I., C. Kreidl, and P. Fischer. "Hybrid pixel detector based on capacitive chip to chip signal-transmission." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 617, no. 1-3 (May 2010): 576–81. http://dx.doi.org/10.1016/j.nima.2009.09.042.

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17

Yang, Jie, Cong Shi, Liyuan Liu, Jian Liu, and Nanjian Wu. "Pixel‐parallel feature detection on vision chip." Electronics Letters 50, no. 24 (November 2014): 1839–41. http://dx.doi.org/10.1049/el.2014.1787.

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18

Ballabriga, R., G. Blaj, M. Campbell, M. Fiederle, D. Greiffenberg, E. H. M. Heijne, X. Llopart, et al. "Characterization of the Medipix3 pixel readout chip." Journal of Instrumentation 6, no. 01 (January 11, 2011): C01052. http://dx.doi.org/10.1088/1748-0221/6/01/c01052.

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19

Ackers, M., F. Andre, L. Blanquart, V. Bonzom, G. Comes, P. Fischer, M. Keil, et al. "Pixel readout chip for the ATLAS experiment." IEEE Transactions on Nuclear Science 46, no. 6 (1999): 2033–38. http://dx.doi.org/10.1109/23.819277.

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20

Chen, Ming Fu, Chih Chung Chou, Chun Jie Lien, and Rui Cian Weng. "An Optical Inspection System for Chip Defects Using a High Rate Line Scanner." Applied Mechanics and Materials 574 (July 2014): 462–67. http://dx.doi.org/10.4028/www.scientific.net/amm.574.462.

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Based on a line scan imager, we propose anew defect inspection system to precisely identify defects with size of greater than criteria from chip backside. Only a corresponding raw image is acquiredfor each chip,and using anopto-mechanical device with very low geometry distortion to make it feasible to neglectprocesses of image calibration and mosaic. Defect inspection is based on a binary chip edge image and a novel methodof using edge pixels statistic. Thus defect size of crack, chipping and glue can be inspected quantitatively and efficiently.From test results by integrating inspection system with experimental and operational chip sorters, our system has capabilities of maximal chip moving speed of0.7 m/sec (5μm resolution) andinspecting chip defects with size accuracyof less than 1.0 pixel. Proposed system has features of automatically acquiring chip images during packaging process, improving performance of image processing and defects inspection. Moreover, manpower, time and cost for chip defect inspection manually can be saved. Chip quality control can be improved as well comparing with the one by manual way.Developed system has been integrated with operational chip sorters successfully for sale now.

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21

Kang, Hosung, Wajahat Abbasi, Seong-Woo Kim, and Jungsuk Kim. "Fully Integrated Light-Sensing Stimulator Design for Subretinal Implants." Sensors 19, no. 3 (January 28, 2019): 536. http://dx.doi.org/10.3390/s19030536.

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This paper presents a fully integrated photodiode-based low-power and low-mismatch stimulator for a subretinal prosthesis. It is known that a subretinal prosthesis achieves 1600-pixel stimulators on a limited single-chip area that is implanted beneath the bipolar cell layer. However, the high-density pixels cause high power dissipation during stimulation and high fabrication costs because of special process technologies such as the complementary metal-oxide semiconductor CMOS image sensor process. In addition, the many residual charges arising from the high-density pixel stimulation have deleterious effects, such as tissue damage and electrode corrosion, on the retina tissue. In this work, we adopted a switched-capacitor current mirror technique for the single-pixel stimulator (SPStim) that enables low power consumption and low mismatch in the subretinal device. The customized P+/N-well photodiode used to sense the incident light in the SPStim also reduces the fabrication cost. The 64-pixel stimulators are fabricated in a standard 0.35-μm CMOS process along with a global digital controller, which occupies a chip area of 4.3 × 3.2 mm2 and are ex-vivo demonstrated using a dissected pig eyeball. According to measured results, the SPStim accomplishes a maximum biphasic pulse amplitude of 143 μA, which dissipates an average power of 167 μW in a stimulation period of 5 ms, and an average mismatch of 1.12 % between the cathodic and anodic pulses.

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22

Jayakumar, Ganesh, Per-Erik Hellström, and Mikael Östling. "Monolithic Wafer Scale Integration of Silicon Nanoribbon Sensors with CMOS for Lab-on-Chip Application." Micromachines 9, no. 11 (October 25, 2018): 544. http://dx.doi.org/10.3390/mi9110544.

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Silicon ribbons (SiRi) have been well-established as highly sensitive transducers for biosensing applications thanks to their high surface to volume ratio. However, selective and multiplexed detection of biomarkers remains a challenge. Further, very few attempts have been made to integrate SiRi with complementary-metal-oxide-semiconductor (CMOS) circuits to form a complete lab-on-chip (LOC). Integration of SiRi with CMOS will facilitate real time detection of the output signal and provide a compact small sized LOC. Here, we propose a novel pixel based SiRi device monolithically integrated with CMOS field-effect-transistors (FET) for real-time selective multiplexed detection. The SiRi pixels are fabricated on a silicon-on-insulator wafer using a top-down method. Each pixel houses a control FET, fluid-gate (FG) and SiRi sensor. The pixel is controlled by simultaneously applying frontgate (VG) and backgate voltage (VBG). The liquid potential can be monitored using the FG. We report the transfer characteristics (ID-VG) of N- and P-type SiRi pixels. Further, the ID-VG characteristics of the SiRis are studied at different VBG. The application of VBG to turn ON the SiRi modulates the subthreshold slope (SS) and threshold voltage (VTH) of the control FET. Particularly, N-type pixels cannot be turned OFF due to the control NFET operating in the strong inversion regime. This is due to large VBG (≥25 V) application to turn ON the SiRi sensor. Conversely, the P-type SiRi sensors do not require large VBG to switch ON. Thus, P-type pixels exhibit excellent ION/IOFF ≥ 106, SS of 70–80 mV/dec and VTH of 0.5 V. These promising results will empower the large-scale cost-efficient production of SiRi based LOC sensors.

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23

Wang, X., T. Wei, and Z. Deng. "Experimental characterization of an X-ray photon counting detector." Journal of Instrumentation 17, no. 07 (July 1, 2022): C07005. http://dx.doi.org/10.1088/1748-0221/17/07/c07005.

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Abstract This paper presents the experimental test results of the X-ray photon counting detectors based on our pixel readout ASIC. The chip integrates a 64 × 128 array of pixels in the size of 150 µm × 150 µm and each pixel consists of four 12-bit energy windows. Two types of CdTe detectors have been bump bonded to the ASICs and have been tested. The electronic characteristics of the readout chip were evaluated first by injecting charge through the calibration capacitors. The non-uniformity of the energy thresholds among pixels was measured and then were compensated by tuning the local DACs. The detector performance was then characterized using X-ray tubes. The energy responses of the detectors were measured using the characteristic X-ray of the target materials. The global energy thresholds were then calibrated with these specific energies of photons. Polarization effects under different photon fluxes were also studied. Preliminary imaging was conducted. The detector response under uniform irradiation was investigated. The spatial uniformity of the detectors was analyzed and the flat field correction was then conducted to improve image quality. CT detailed test results will be discussed in this paper.

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24

Maj, P., T. Taguchi, and Y. Nakaye. "Tests of UFXC32k chip with CdTe pixel detector." Journal of Instrumentation 13, no. 02 (February 12, 2018): C02014. http://dx.doi.org/10.1088/1748-0221/13/02/c02014.

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25

Fischer, P., A. Helmich, M. Lindner, N. Wermes, and L. Blanquart. "A photon counting pixel chip with energy windowing." IEEE Transactions on Nuclear Science 47, no. 3 (June 2000): 881–84. http://dx.doi.org/10.1109/23.856711.

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26

Vähänen, S., H. Heikkinen, H. Pohjonen, J. Salonen, and S. Savolainen-Pulli. "Rework of flip chip bonded radiation pixel detectors." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 591, no. 1 (June 2008): 233–36. http://dx.doi.org/10.1016/j.nima.2008.03.087.

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27

Rossini, Marco. "Readout chip for the CMS pixel detector upgrade." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 765 (November 2014): 209–13. http://dx.doi.org/10.1016/j.nima.2014.06.011.

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28

Fischer, P., J. Hausmann, M. Overdick, B. Raith, N. Wermes, L. Blanquart, V. Bonzom, and P. Delpierre. "A counting pixel readout chip for imaging applications." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 405, no. 1 (March 1998): 53–59. http://dx.doi.org/10.1016/s0168-9002(97)01146-7.

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29

Christian, D. C., J. A. Appel, G. Cancelo, S. Kwan, J. Hoff, A. Mekkaoui, J. Srage, R. Yarema, and S. Zimmermann. "Development of a pixel readout chip for BTeV." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 435, no. 1-2 (October 1999): 144–52. http://dx.doi.org/10.1016/s0168-9002(99)00421-0.

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30

Liu, Yan-yan, Wei-dong Geng, and Yong-ping Dai. "OLED-on-silicon chip with new pixel circuit." Journal of Central South University 19, no. 5 (April 27, 2012): 1276–82. http://dx.doi.org/10.1007/s11771-012-1139-6.

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31

Kadlubowski, L. A., and P. Kmon. "Vernier time-to-digital converter with ring oscillators for in-pixel time-of-arrival and time-over-threshold measurement in 28 nm CMOS." Journal of Instrumentation 16, no. 12 (December 1, 2021): C12010. http://dx.doi.org/10.1088/1748-0221/16/12/c12010.

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Abstract The paper describes a design of a prototype chip in 28 nm CMOS technology, consisting of 8 × 4 pixels with 50 μm pitch, dedicated for the precise measurement of Time-of-Arrival (ToA) and Time-over-Threshold (ToT) with a resolution within the picosecond range. To address this requirement, in-pixel Vernier time-to-digital converter (TDC) has been implemented, which utilizes two ring oscillators per pixel. Overall chip architecture is introduced as well as pixel architecture and selected simulation results. The pixel consists of a recording channel and TDC part. The recording channel is composed of an inverter-based front-end amplifier with Zimmerman feedback, a discriminator, a calibration block and a threshold setting block. TDC part includes two ring oscillators together with their calibration blocks and additional logic with counters/shift registers that allow for precise ToA measurement (using Vernier method) as well as ToT measurement (using one of the oscillators). Alternatively, single photon counting (SPC) mode can be used. Frequency of oscillators is set in three steps. First, two global 8-bit digital-to-analog converters (DACs) are used for initial setting of all ring oscillators. Then, per-oscillator capacitance bank and 6-bit DAC are used for fine setting. Simulation results of core blocks suggest that the ToA resolution on the order of tens of picoseconds may be achieved. The chips are already fabricated and are currently being prepared for measurements.

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32

Cecconi, L., F. Piro, J. L. A. de Melo, W. Deng, G. H. Hong, W. Snoeys, M. Mager, et al. "Design and readout architecture of a monolithic binary active pixel sensor in TPSCo 65 nm CMOS imaging technology." Journal of Instrumentation 18, no. 02 (February 1, 2023): C02025. http://dx.doi.org/10.1088/1748-0221/18/02/c02025.

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Abstract The Digital Pixel Test Structure (DPTS) is a monolithic active pixel sensor prototype chip designed to explore the TPSCo 65 nm ISC process in the framework of the CERN-EP R&D on monolithic sensors and the ALICE ITS3 upgrade. It features a 32 × 32 binary pixel matrix at 15 μm pitch with event-driven readout, with GHz range time-encoded digital signals including Time-Over-Threshold. The chip proved fully functional and efficient in testbeam allowing early verification of the complete sensor to readout chain. This paper focuses on the design, in particular the digital readout and its perspectives with some supporting results.

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33

Missiroli, M. "Characterisation of the first digital modules with RD53B-CMS readout chips for the Phase-2 Upgrade of the CMS Inner Tracker." Journal of Instrumentation 18, no. 01 (January 1, 2023): C01027. http://dx.doi.org/10.1088/1748-0221/18/01/c01027.

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Abstract To cope with the challenges posed by the High-Luminosity LHC, the CMS experiment will feature a new silicon tracker. The modules of the upgraded inner tracker are hybrid silicon pixel modules based on a new readout chip, developed by the RD53 collaboration. Compared to the readout chip of the current pixel detector, the RD53 chip is capable of sustaining higher hit rates and radiation levels, as well as enabling the use of serial-powering chains. The qualification of the latest version of this chip (RD53B) is underway, and it will lead to the final version of the readout chip to be used in the CMS inner tracker during the HL-LHC. First digital modules featuring the RD53B-CMS chip have been assembled in 2022 (the term digital module denotes a module assembly with readout chips, but without sensors bonded to them). This contribution presents results of tests on these first prototype modules.

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34

Skrzypiec, P., and R. Szczygieł. "Readout chip with RISC-V microprocessor for hybrid pixel detectors." Journal of Instrumentation 18, no. 01 (January 1, 2023): C01030. http://dx.doi.org/10.1088/1748-0221/18/01/c01030.

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Abstract Hybrid single-photon counting pixel detectors have recently been widely used for X-ray and ionizing particle detection in medicine, high-energy physics, and material science. Many different chips have been developed for the readout of the semiconductor pixel sensor. Typically, developed ASICs have very limited digital logic and do not provide substantial data processing. In this paper, we present the readout chip that integrates the readout channels matrix with a RISC-V-based microprocessor SoC. The designed device has been prototyped in an FPGA and sent to production in a CMOS 40 nm process. Integration of a pixel matrix with the RISC-V-based central processing unit significantly improved the detector functionality. It enabled the device to work independently without external assistive device usage and execute many algorithms, e.g., calibration, threshold scanning, and data filtering, on-chip. Communication between the CPU and the pixel matrix was carried out through the dedicated Pixel Matrix Controller with the CPU standard I/O operations usage. This specialized peripheral consists of a coprocessor responsible for precise matrix control, a data converter for data conversion acceleration, and control and status registers connected to the core data bus. Many algorithms have been developed and tested, one of which is the intelligent real-time filtering of regions of interest.

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35

Caminada, L., B. Kilminster, A. Macchiolo, B. Meier, M. Senger, and S. Wiederkehr. "Development of a timing chip prototype in 110 nm CMOS technology." Journal of Physics: Conference Series 2374, no. 1 (November 1, 2022): 012081. http://dx.doi.org/10.1088/1742-6596/2374/1/012081.

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We present a readout chip prototype for future pixel detectors with timing capabilities. The prototype is intended for characterizing 4D pixel arrays with a pixel size of 100x100 μm2, where the sensors are Low Gain Avalanche Diodes (LGADs). The long term focus is towards a possible replacement of disks in the extended forward pixel system (TEPX) of the CMS experiment during the High Luminosity LHC (HL-LHC). The requirements for this ASIC are the incorporation of a Time to Digital Converter (TDC) in the small pixel area, low power consumption, and radiation tolerance up to 5 × 1015 n eq cm−2 to withstand the radiation levels in the innermost detector modules for 3000 fb−1 of the HL-LHC (in the TEPX). A prototype has been designed and produced in 110 nm CMOS technology at LFoundry and UMC with different versions of TDC structures, together with a front end circuitry to interface with the sensors. The design of the TDC will be discussed, with the test set-up for the measurements, and the first results comparing the performance of the different structures.

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36

Menouni, Mohsine, Pierre Barrillon, Leyre Flores, Denis Fougeron, Tomasz Hemperek, Eva Joly, Jelena Lalic, and Thomas Strebler. "Single event effects testing of the RD53B chip." Journal of Physics: Conference Series 2374, no. 1 (November 1, 2022): 012084. http://dx.doi.org/10.1088/1742-6596/2374/1/012084.

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The RD53 collaboration has been working since 2014 on the development of pixel chips for the CMS and ATLAS Phase 2 tracker upgrade. This work has recently led to the development of the RD53B full-scale readout chip which is using the 65nm CMOS process and containing 153600 pixels of 50 × 50 μm 2 The RD53B chip is designed to be robust against the Single Event Effects (SEE), allowing such a complex chip to operate reliably in the hostile environment of the HL-LHC. Different SEE mitigation techniques based on the Triple Modular Redundancy (TMR) have been adopted for the critical information in the chip. Furthermore, the efficiency of this mitigation scheme has been evaluated for the RD53B chip with heavy ion beams in the CYCLONE facility and with a 480 MeV proton beam in TRIUMF facility. The purpose of this paper is to describe and explain all the SEE mitigation strategies used in the RD53B chip, to report and analyze the heavy ions and proton tests results and to estimate the expected Single Event Upset (SEU) rates at the HL-LHC.

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37

Alcalde Bessia, F., J. Lipovetzky, and I. Perić. "X-ray characterization of BUSARD chip: A HV-SOI monolithic particle detector with pixel sensors under the buried oxide." Journal of Instrumentation 16, no. 12 (December 1, 2021): P12030. http://dx.doi.org/10.1088/1748-0221/16/12/p12030.

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Abstract This work presents the design of BUSARD, an application specific integrated circuit (ASIC) for the detection of ionizing particles. The ASIC is a monolithic active pixel sensor which has been fabricated in a High-Voltage Silicon-On-Insulator (HV-SOI) process that allows the fabrication of a buried N+ diffusion below the Buried OXide (BOX) as a standard processing step. The first version of the chip, BUSARD-A, takes advantage of this buried diffusion as an ionizing particle sensor. It includes a small array of 13×13 pixels, with a pitch of 80 μm, and each pixel has one buried diffusion with a charge amplifier, discriminator with offset tuning and digital processing. The detector has several operation modes including particle counting and Time-over-Threshold (ToT). An initial X-ray characterization of the detector was carried out, obtaining several pulse height and ToT spectra, which then were used to perform the energy calibration of the device. The Molybdenum 𝐊α emission was measured with a standard deviation of 127 e- of ENC by using the analog pulse output, and with 276 e- of ENC by using the ToT digital output. The resolution in ToT mode is dominated by the pixel-to-pixel variation.

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38

Yang, Ping, Xiangming Sun, Guangming Huang, Le Xiao, Chaosong Gao, Xing Huang, Wei Zhou, et al. "An asynchronous data-driven readout prototype for CEPC vertex detector." International Journal of Modern Physics A 32, no. 34 (December 10, 2017): 1746012. http://dx.doi.org/10.1142/s0217751x17460125.

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The Circular Electron Positron Collider (CEPC) is proposed as a Higgs boson and/or Z boson factory for high-precision measurements on the Higgs boson. The precision of secondary vertex impact parameter plays an important role in such measurements which typically rely on flavor-tagging. Thus silicon CMOS Pixel Sensors (CPS) are the most promising technology candidate for a CEPC vertex detector, which can most likely feature a high position resolution, a low power consumption and a fast readout simultaneously. For the R&D of the CEPC vertex detector, we have developed a prototype MIC4 in the Towerjazz 180 nm CMOS Image Sensor (CIS) process. We have proposed and implemented a new architecture of asynchronous zero-suppression data-driven readout inside the matrix combined with a binary front-end inside the pixel. The matrix contains 128 rows and 64 columns with a small pixel pitch of 25 [Formula: see text]m. The readout architecture has implemented the traditional OR-gate chain inside a super pixel combined with a priority arbiter tree between the super pixels, only reading out relevant pixels. The MIC4 architecture will be introduced in more detail in this paper. It will be taped out in May and will be characterized when the chip comes back.

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39

Calderini, G., F. Crescioli, G. F. Dalla Betta, G. Gariano, C. Gemme, F. Guescini, S. Hadzic, et al. "Test of ITk 3D sensor pre-production modules with ITkPixV1.1 chip." Journal of Instrumentation 18, no. 01 (January 1, 2023): C01010. http://dx.doi.org/10.1088/1748-0221/18/01/c01010.

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Abstract ITk detector, the new ATLAS tracking system at High Luminosity LHC, will be equipped with 3D pixel sensor modules in the innermost layer (L0). The pixel cell dimensions will be either 25 × 100 μm2 (barrel) or 50 × 50 μm2 (endcap), with one read-out electrode at the centre of a pixel and four bias electrodes at the corners. Sensors from pre-production wafers (50 × 50 μm2) produced by FBK have been bump bonded to ITkPixV1.1 chips at IZM. Bare modules have been assembled in Genoa on Single Chip Cards and characterized in laboratory and on beam.

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40

Kashikawa, Nobunari, Masafumi Yagi, Naoki Yasuda, Sadanori Okamura, Kazuhiro Shimasaku, Mamoru Doi, and Maki Sekiguchi. "Development of a 7000 × 4000 Pixel Mosaic CCD Camera." Symposium - International Astronomical Union 167 (1995): 345–46. http://dx.doi.org/10.1017/s0074180900056722.

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The CCD we use is TC215 manufactured by TI, Japan. The pixel size is 12 microns square. It is a virtual phase CCD which has a peak QE of 60% at 700 nm and 15% QE at 350 nm. It is commercially available in a package, which is too big to meet our requirement for CCD spacing. We therefore put the CCD in a specially made compact package. Each chip is mounted on a machined ceramic spacer whose thermal coefficient is matched with that of the CCD package. We glue each CCD chip on the spacer under a microscope to measure YHE x − y position and height. Then we screw the CCD chip + spacer on a copper motherboard with the help of the gauge which has a planned grid with a good accuracy. The alignment accuracy we can get with such set-up procedures is an order of 5 microns (< 0.5 pixel) in the horizontal direction and 10 microns in the vertical direction.

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41

Oliveira, Fernanda D. V. R., Hugo L. Haas, José Gabriel R. C. Gomes, and Antonio Petraglia. "CMOS Image Sensor Featuring Current-Mode Focal-Plane Image Compression." Journal of Integrated Circuits and Systems 8, no. 1 (December 27, 2013): 14–21. http://dx.doi.org/10.29292/jics.v8i1.369.

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The interest in focal-plane processing techniques, by which image processing is carried out at the pixel level, has increased since the advent of active pixel sensors in the middle 90’s. By sharing processing circuitry by a group of neighboring pixels such techniques enable high-speed imaging operation and massive parallel computation. Focal-plane image compression is particularly interesting, because it allows for further reduction in data rates. The proposed approach also benefits from processing currents rather than voltages, which not only suits current-mode APS imagers, but also enables the circuits to operate at low voltage supply levels and achieve high speed. Moreover, arithmetic computations such as additions and scaling are easily implemented in current mode. Whereas current-mode imaging architectures produce higher fixed pattern noise (FPN) figures than their voltage-mode counterparts, low FPN can be achieved by applying correlated double sampling (CDS) and gain correction techniques. This work presents a 32 × 32 gray-level imaging integrated circuit featuring focal plane image compression, such that for each 4 × 4 pixel block, analog circuits implement differential pulse-code modulation, linear transform, and vector quantization. Other processing functions implemented in the chip are CDS and A/D conversion. Theoretical details are described, as well as the test setup of the chip fabricated in a 0.35 μm CMOS process. To validate the proposed technique, experimental results and captured photographs are shown. The CMOS imager compresses captured images at 0.94 bits/pixel for an overall power consumption below 40 mW (white image), which is equivalent to approximately 36 μW per pixel. Using photographs taken from bar-target pattern inputs, it is shown that details up to 2 cycles/c mare preserved in the decoded images.

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42

Hopper, Richard, Syed Zeeshan Ali, Sophie Boual, Andrea De Luca, Ying Dai, Daniel Popa, and Florin Udrea. "A CMOS-Based Thermopile Array Fabricated on a Single SiO2 Membrane." Proceedings 2, no. 13 (November 22, 2018): 878. http://dx.doi.org/10.3390/proceedings2130878.

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We present a novel thermopile-based infrared (IR) sensor array fabricated on a single CMOS dielectric membrane, comprising of poly-silicon p+ and n+ elements. Processing of the chip is simplified by fabricating the entire array on a single membrane and by using standard CMOS Al metal layers for thermopile cold junction heatsinking. On a chip area of 1.76 mm × 1.76 mm, with a membrane size of 1.2 mm × 1.2 mm, we fabricated IR sensor arrays with 8 × 8 to 100 × 100 pixels. The 8 × 8 pixel device has <2% thermal crosstalk, a responsivity of 36 V/W and enhanced optical absorption in the 8–14 µm waveband, making it particularly suitable for people presence sensing.

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43

Grybos, P., R. Kleczek, P. Kmon, P. Otfinowski, and P. Fajardo. "Small pixel high-spatial resolution photon-counting prototype IC for synchrotron applications." Journal of Instrumentation 18, no. 01 (January 1, 2023): C01052. http://dx.doi.org/10.1088/1748-0221/18/01/c01052.

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Abstract This paper presents the design and simulation of a prototype chip in the CMOS 40 nm process for high spatial resolution operation at the ESRF-EBS synchrotron. The core of the prototype IC is the pixel matrix with 50 µm pitch, operating in a single photon counting mode. Each pixel contains a Charge Sensitive Amplifier (CSA) with a fast discharge block and detector leakage current compensation circuit. The CSA output is directly connected to the discriminator with an offset trimming capability. The chip is optimized for operation with a monochromatic X-ray beam with an energy of up to 30 keV. Furthermore, several algorithms of interpixel communication are implemented in the chip to increase detector spatial resolution by using the charge sharing effect.

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44

Mekkaoui, A., M. Garcia-Sciveres, and D. Gnani. "Results of 65 nm pixel readout chip demonstrator array." Journal of Instrumentation 8, no. 01 (January 31, 2013): C01055. http://dx.doi.org/10.1088/1748-0221/8/01/c01055.

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45

Brönnimann, Ch, R. Baur, E. F. Eikenberry, S. Kohout, M. Lindner, B. Schmitt, and R. Horisberger. "A pixel read-out chip for the PILATUS project." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 465, no. 1 (June 2001): 235–39. http://dx.doi.org/10.1016/s0168-9002(01)00396-5.

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46

Christian, D. C., J. A. Appel, G. Cancelo, J. Hoff, S. Kwan, A. Mekkaoui, R. Yarema, W. Wester, and S. Zimmermann. "FPIX2: a radiation-hard pixel readout chip for BTeV." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 473, no. 1-2 (November 2001): 152–56. http://dx.doi.org/10.1016/s0168-9002(01)01137-8.

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47

Raymond, D. M., A. J. Lewis, G. Hall, and P. H. Sharp. "A prototype pixel readout chip for asynchronous detection applications." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 310, no. 1-2 (December 1991): 552–56. http://dx.doi.org/10.1016/0168-9002(91)91098-g.

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48

Barbero, M., W. Bertl, G. Dietrich, A. Dorokhov, W. Erdmann, K. Gabathuler, St Heising, et al. "Design and test of the CMS pixel readout chip." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 517, no. 1-3 (January 2004): 349–59. http://dx.doi.org/10.1016/j.nima.2003.09.043.

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49

Perić, Ivan, Laurent Blanquart, Giacomo Comes, Peter Denes, Kevin Einsweiler, Peter Fischer, Emanuele Mandelli, and Gerrit Meddeler. "The FEI3 readout chip for the ATLAS pixel detector." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 565, no. 1 (September 2006): 178–87. http://dx.doi.org/10.1016/j.nima.2006.05.032.

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50

Allport, Philip Patrick, Seddik Benhammadi, Robert Ross Bosley, Jens Dopke, Lucian Fasselt, Samuel Flynn, Laura Gonella, et al. "DECAL: A Reconfigurable Monolithic Active Pixel Sensor for Tracking and Calorimetry in a 180 nm Image Sensor Process." Sensors 22, no. 18 (September 10, 2022): 6848. http://dx.doi.org/10.3390/s22186848.

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In this paper, we describe DECAL, a prototype Monolithic Active Pixel Sensor (MAPS) device designed to demonstrate the feasibility of both digital calorimetry and reconfigurability in ASICs for particle physics. The goal of this architecture is to help reduce the development and manufacturing costs of detectors for future colliders by developing a chip that can operate both as a digital silicon calorimeter and a tracking chip. The prototype sensor consists of a matrix of 64 × 64 55 μm pixels, and provides a readout at 40 MHz of the number of particles which have struck the matrix in the preceding 25 ns. It can be configured to report this as a total sum across the sensor (equivalent to the pad of an analogue calorimeter) or the sum per column (equivalent to a traditional strip detector). The design and operation of the sensor are described, and the results of chip characterisation are reported and compared to simulations.

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