Готові списки джерел за темами / Pixel Chip

Добірка наукової літератури з теми "Pixel Chip"

Автор: Grafiati

Опубліковано: 14 березня 2023

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Статті в журналах з теми "Pixel Chip"

Li, M., W. Wei, X. Jiang, S. Cui, J. Zhang, B. Lu, and Z. Liu. "A charge-integration pixel readout chip features IR-drop effect mitigation by distributed LDOs." Journal of Instrumentation 17, no. 09 (September 1, 2022): P09043. http://dx.doi.org/10.1088/1748-0221/17/09/p09043.

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Abstract HYLITE (High dYnamic range free electron Laser Imaging deTEctor) is a charge-integration pixel detector readout chip, which is designed for SHINE (Shanghai high repetition rate XFEL and extreme light facility). The targeting pixel array of a full-size chip is 128 × 128 with a pixel pitch of 100 μm. The dynamic range of HYLITE is 1 ∼ 10000 photons at 12 keV, and the frame rate is 10 kHz. Large array size, high dynamic range, and high readout speed result in a big challenge of large power consumption and a significant IR-Drop effect. We implemented HYLITE0.2, which is the second prototype chip fabricated in a CMOS 130 nm process. Compared with HYLITE0.1, HYLITE0.2 aims to implement a full-function chip with a further shrunk pixel size, while the foreseen problem of severe IR-Drop effect of the full-size chip must be solved. To mitigate the IR-Drop effect, we proposed a novel architecture of distributed in-array Low-Dropout Regulators (LDOs). The pixel array consists of 16 × 24 pixels, and the full functionality was implemented within a pixel pitch of 100 μm. Measurements show that pixels powered by the proposed architecture work well, and the gain gradient of those pixels is 31.8% of the pixels powered by the conventional architecture.

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Li, M., W. Wei, X. Jiang, S. Cui, J. Zhang, B. Lu, and Z. Liu. "Prototype characterization of a charge-integration pixel detector readout chip with in-pixel A/D conversion." Journal of Instrumentation 17, no. 01 (January 1, 2022): P01003. http://dx.doi.org/10.1088/1748-0221/17/01/p01003.

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Abstract HYLITE (High dYmamic range free electron Laser Imaging deTEctor) is a hybrid pixel detector readout chip, which is designed for advanced light sources such as X-ray Free Electron Laser (XFEL) and diffraction-limited storage rings. It is a charge-integration readout chip which has three gains for different dynamic ranges and automatic gain-switching function. The full dynamic range covered by HYLITE is 1 ∼ 104 photons with an energy of 12 keV for each pixel in every shot. In-pixel ADC is designed to achieve front-end digitization and a 10 kHz continuous frame rate. HYLITE0.1 is the first prototype chip for functional verification that was produced in CMOS 0.13 μm technology. It consists of a pixel array with 6 × 12 pixels and a periphery with full standalone operation features. The size of each pixel is 200 μm × 200 μm. Three design variations of pixels with different integrating capacitance and structures were designed to optimize between area and performance. A 10-bit Wilkinson ADC is integrated in each pixel to digitize the outputs of the pre-amplifier. Therefore, analog signal transmission of long distance is avoided and a frame rate of 10 kHz can be achieved. In this paper, we present the design of HYLITE0.1 and the test results of this prototype chip.

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Kim, Sang-Hwan, Byoung-Soo Choi, Jimin Lee, Junwoo Lee, Jewon Lee, Jae-Hyoun Park, Kyoung-Il Lee, and Jang-Kyoo Shin. "Averaging Pixel Current Adjustment Technique for Reducing Fixed Pattern Noise in the Bolometer-Type Uncooled Infrared Image Sensor." Sensors 19, no. 7 (April 6, 2019): 1653. http://dx.doi.org/10.3390/s19071653.

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In this paper, we propose an averaging pixel current adjustment technique for reducing fixed pattern noise (FPN) in the bolometer-type uncooled infrared image sensor. The averaging pixel current adjustment technique is composed of active pixel, reference pixel, and calibration circuit. Polysilicon resistors were used in each active pixel and reference pixel. Resistance deviation among active pixels integrated with the same resistance value cause FPN. The principle of the averaging pixel current adjustment technique for removing FPN is based on the subtraction of dark current of the active pixel from the dark current of the reference pixel. The subtracted current is converted into the voltage, which contains pixel calibration information. The calibration circuit is used to adjust the calibration current. After calibration, the nano-ampere current is output with small deviation. The proposed averaging pixel current adjustment technique is implemented by a chip composed of a pixel array, a calibration circuit, average current generators, and readout circuits. The chip was fabricated using a standard 0.35 μm CMOS process and its performance was evaluated.

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Zoladz, M., P. Grybos, and R. Szczygiel. "X-ray imaging of moving objects using on-chip TDI and MDX methods with single photon counting CdTe hybrid pixel detector." Journal of Instrumentation 16, no. 12 (December 1, 2021): C12014. http://dx.doi.org/10.1088/1748-0221/16/12/c12014.

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Abstract X-ray imaging of moving objects using line detectors remains the most popular method of object content and structure examination with a typical resolution limited to 0.4–1 mm. Higher resolutions are difficult to obtain as, for the detector in the form of a single pixel row, the narrower the detector is, the lower the image Signal to Noise Ratio (SNR). This is because, for smaller pixel sizes, fewer photons hit the pixel in each time unit for a given radiation intensity. To overcome the trade-off between the SNR and spatial resolution, a two-dimensional sensor, namely a pixel matrix can be used. Imaging of moving objects with a pixel matrix requires time-domain integration (TDI). Straightforward TDI implementation is based on the proper accumulation of images acquired during consecutive phases of an object’s movement. Unfortunately, this method is much more demanding regarding data transfer and processing. Data from the whole pixel matrix instead of a single pixel row must be transferred out of the chip and then processed. The alternative approach is on-chip TDI implementation. It takes advantage of photons acquired by multiple rows (a higher SNR), but generates similar data amount as a single pixel row and does not require data processing out of the chip. In this paper, on-chip TDI is described and verified by using a single photon counting two-dimensional (a matrix of 128 × 192 pixels) CdTe hybrid X-ray detector with the 100 µm × 100 µm pixel size with up to four energy thresholds per pixel. Spatial resolution verification is combined with the Material Discrimination X-ray (MDX) imaging method.

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Braach, Justus, Eric Buschmann, Dominik Dannheim, Katharina Dort, Thanushan Kugathasan, Magdalena Munker, Walter Snoeys, and Mateus Vicente. "Performance of the FASTPIX Sub-Nanosecond CMOS Pixel Sensor Demonstrator." Instruments 6, no. 1 (February 8, 2022): 13. http://dx.doi.org/10.3390/instruments6010013.

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Within the ATTRACT FASTPIX project, a monolithic pixel sensor demonstrator chip has been developed in a modified 180 nm CMOS imaging process, targeting sub-nanosecond timing measurements for single ionizing particles. It features a small collection electrode design on a 25 micron thick epitaxial layer and contains 32 mini matrices of 68 hexagonal pixels each, with pixel pitches ranging from 8.66 to 20 micron. Four pixels are transmitting an analog output signal and 64 are transmitting binary hit information. Various design variations are explored, aiming at accelerating the charge collection and making the timing of the charge collection more uniform over the pixel area. Signal treatment of the analog waveforms, as well as reconstruction of time and charge information, is carried out off-chip. This contribution introduces the design of the sensor and readout system and presents the first performance results for 10 μm and 20 μm pixel pitch achieved in measurements with particle beams.

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López-Portilla, Bárbaro M., Wladimir Valenzuela, Payman Zarkesh-Ha, and Miguel Figueroa. "A CMOS Image Readout Circuit with On-Chip Defective Pixel Detection and Correction." Sensors 23, no. 2 (January 13, 2023): 934. http://dx.doi.org/10.3390/s23020934.

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Images produced by CMOS sensors may contain defective pixels due to noise, manufacturing errors, or device malfunction, which must be detected and corrected at early processing stages in order to produce images that are useful to human users and image-processing or machine-vision algorithms. This paper proposes a defective pixel detection and correction algorithm and its implementation using CMOS analog circuits, which are integrated with the image sensor at the pixel and column levels. During photocurrent integration, the circuit detects defective values in parallel at each pixel using simple arithmetic operations within a neighborhood. At the image-column level, the circuit replaces the defective pixels with the median value of their neighborhood. To validate our approach, we designed a 128×128-pixel imager in a 0.35μm CMOS process, which integrates our defective-pixel detection/correction circuits and processes images at 694 frames per second, according to post-layout simulations. Operating at that frame rate, our proposed algorithm and its CMOS implementation produce better results than current state-of-the-art algorithms: it achieves a Peak Signal to Noise Ratio (PSNR) and Image Enhancement Factor (IEF) of 45 dB and 198.4, respectively, in images with 0.5% random defective pixels, and a PSNR of 44.4 dB and IEF of 194.2, respectively, in images with 1.0% random defective pixels.

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Cui, S., W. Wei, J. Zhang, M. Li, H. Li, Z. Li, X. Jiang, et al. "A prototype pixel readout chip working in single photon counting mode with a novel charge sharing suppression scheme." Journal of Instrumentation 17, no. 07 (July 1, 2022): C07017. http://dx.doi.org/10.1088/1748-0221/17/07/c07017.

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Abstract Spectral distortion due to the charge sharing effect becomes a severe issue in single-photon counting pixel detectors. The HEPS-BPIX4 prototype chip, dedicated for the HEPS in China, implements a novel architecture to mitigate charge sharing and permit spectroscopic imaging with high efficiency. In the architecture, a central pixel communicates with others in a cluster of 3 × 3 pixels. The algorithm simulation showed a charge sharing elimination accuracy better than 90%. The prototype chip has been designed in a 130 nm CMOS technology. The preliminary measurements show a charge gain of 48 mV/ke− and an equivalent noise charge of 150 e− rms. Detailed tests in a 4 × 4 pixel array for the charge sharing are performed using electrical test pulses. The hit allocation in the core four adjacent pixels of the array indicates that effective suppression of charge sharing has been realized.

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Pinkston, Timothy Mark, and Charles Kuznia. "Smart-pixel-based network interface chip." Applied Optics 36, no. 20 (July 10, 1997): 4871. http://dx.doi.org/10.1364/ao.36.004871.

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Cadeddu, S., A. Lai, and M. Caria. "KPIX: a pixel detector imaging chip." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 487, no. 1-2 (July 2002): 175–80. http://dx.doi.org/10.1016/s0168-9002(02)00962-2.

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Christian, D. C., J. A. Appel, G. Chiodini, J. Hoff, S. Kwan, A. Mekkaoui, and R. Yarema. "FPIX2, the BTeV pixel readout chip." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 549, no. 1-3 (September 2005): 165–70. http://dx.doi.org/10.1016/j.nima.2005.04.046.

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Дисертації з теми "Pixel Chip"

Hong, Augustin Jinwoo. "Self-calibrating random access logarithmic pixel for on chip camera." Thesis, Texas A&M University, 2003. http://hdl.handle.net/1969.1/2328.

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CMOS active pixel sensors (APS) have shown competitive performance with charge-coupled device (CCD) and offer many advantages in cost, system power reduction and on-chip integration of VLSI electronics. Among CMOS image sensors, sensors with logarithmic pixels are particularly applicable for outdoor environment where the light intensity varies over a wide range. They are also randomly accessible in both time and space. A major drawback comes from process variations during fabrication. This gives rise to a considerable fixed pattern noise (FPN) which deteriorates the image quality. In this thesis, a technique that greatly reduces FPN using on-chip calibration is introduced. An image sensor that consists of 64x64 active pixels has been designed, fabricated and tested. Pixel pitch is 18um x 19.2um? and is fabricated in a 0.5-um? CMOS process. The proposed pixel circuit considerably reduces the FPN as predicted in theoretical analysis. The measured FPN value is 2.29% of output voltage swing and column-wise FPN is 1.49% of mean output voltage over each column.

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Hong, Canaan Sungkuk. "On-chip spatial image processing with CMOS active pixel sensors." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/NQ65248.pdf.

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Zhao, Ruiguang. "Development of a CMOS pixel sensor with on-chip artificial neural networks." Thesis, Strasbourg, 2019. http://www.theses.fr/2019STRAE050.

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Dans le détecteur de vertex de l'ILC (International Linear Collider), un nombre élevé d'impacts supplémentaires seront générés par des électrons résultant de processus liés au bruit de fond des faisceaux. Leur impulsion se trouve typiquement est inférieure à celle des particules issues d'événements associés à des processus physiques. Notre groupe à l'IPHC a proposé d'explorer le concept d'un capteur à pixels CMOS avec des ANNs intégrés pour marquer et supprimer les pixels touchés (hits) générés par ces électrons.Au cours de ma thèse de doctorat, je me suis concentré sur l'étude d'un capteur à pixels CMOS avec des ANNs intégrés portant sur les aspects suivants :1. L'implémentation de modules de prétraitement et d'un ANN dans un composant FPGA pour l'étude de faisabilité ; 2. Un algorithme pour la recherche de clusters, qui fait partie des modules de prétraitement, a été proposé en vue d'être intégré dans la conception de l'ASIC
In the vertex detector of the ILC (International Linear Collider), a large number of extra hits will be generated by electrons coming from the beam background. Momenta of these background electrons typically are lower than particles coming from physics events. Our group in IPHC has proposed the concept of a CMOS pixel sensor with on-chip ANNs to tag and remove hits generated by background particles.During my PhD thesis, I focused on the study of a CMOS pixel sensor with on-chip ANNs from the following aspects :1. The implementation of preprocessing modules and an ANN in an FPGA device for the feasibility study ;2. An on-chip algorithm for cluster search which is a part of preprocessing modules has been proposed to integrate into the ASIC design

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Sjödin, Saron Anteneh. "Indium Bump Fabrication using Electroplating for Flip Chip Bonding." Thesis, Mittuniversitetet, Avdelningen för elektronikkonstruktion, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-27939.

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Hybrid pixel detectors are widely used in many fields, including military, environment, industry and medical treatment. When integrating such a detector, a vertical connection technique called flip-chip bonding is almost the only way to realize the high-density interconnection between each pixel detector to the read-out chip. Such bonding can offer high-density I/O and a short interconnect distance, which can make the resulting device show excellent performance. Electro deposition is a promising approach to enable a low cost and high yield bump bonding process, compared with conventional sputtering or evaporation which is currently utilized for small-scale production. Due to that, Indium bumping process using electroplating is selected, as a result of which indium bump arrays with a pitch of 220 μm and a diameter of 30 μm have been fabricated using a standard silicon wafer processing. UBM (under bump metallization) for indium bumping was Ti/Ni (300 Å/ 2000 Å). It helps to increase adhesion between the wafer and the bumps and also serves as an excellent diffusion barrier both at room temperature and at 200°C. The indium is electroplated, using an indium sulfamate plating bath, and then formed into bumps through a reflow process. The reflow is made on a 200°C hot plate with a continuous flow of nitrogen over the wafer. During the reflow the indium is melted and forms into bumps due to surface tension. All the corresponding procedural processing steps and results are incorporated in this paper.

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Obermann, Theresa [Verfasser]. "Performance evaluation of a fully depleted monolithic pixel detector chip in 150 nm CMOS technology / Theresa Obermann." Bonn : Universitäts- und Landesbibliothek Bonn, 2017. http://d-nb.info/1140525980/34.

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COLLU, ALBERTO. "Development and characterisation of Monolithic Active Pixel Sensor prototypes for the upgrade of the ALICE Inner Tracking System." Doctoral thesis, Università degli Studi di Cagliari, 2015. http://hdl.handle.net/11584/266792.

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ALICE (A Large Ion Collider Experiment) is dedicated to the study and characterisation of the Quark-‐Gluon Plasma (QGP), exploiting the unique potential of ultrarelativistic heavy-‐ion collisions at the CERN Large Hadron Collider (LHC). The increase of the LHC luminosity leading up to about 50 kHz Pb-‐Pb interaction rate after the second long shutdown (in 2018-‐2019) will offer the possibility to perform high precision measurements of rare probes over a wide range of momenta. These measurements are statistically limited or not even possible with the present experimental set up. For this reason, an upgrade strategy for several ALICE detectors is being pursued. In particular, it is foreseen to replace the Inner Tracking System (ITS) by a new detector which will significantly improve the tracking and vertexing capabilities of ALICE in the upgrade scenario. The new ITS will have a barrel geometry consisting of seven layers of Monolithic Active Pixel Sensors (MAPS) with high granularity, which will fulfil the material budget, readout and radiation hardness requirements for the upgrade. Intensive R&D has been carried out in the last four years on MAPS in the framework of the ALICE ITS upgrade. Various small scale sensors have been designed in the TowerJazz 0.18 um imaging sensor technology to study noise, charge collection efficiency and signal-‐to-‐noise ratio. This work presents the main characterization results obtained from the measurements performed on two small scale prototypes (MIMOSA-‐32 and MIMOSA-‐32ter) with X-‐ray sources and beams of particles. The architecture of an innovative full scale MAPS prototype (Alice Pixel Detector, ALPIDE) is also presented that is based on an AC-‐sensitive front end and on a hit-‐ driven readout. The first results on the ALPIDE prototype showed that the sensor is fully functional and that it provides performance in terms of readout time, power density and noise much better than the state of the art MAPS based on the rolling shutter readout, which makes this type of sensors very attractive for employment in the new ALICE ITS.

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TANG, JIANJING. "DESIGN AND ANALYSIS OF A 32X32-BIT DATABASE FILTER CHIP BASED ON A CMOS COMPATIBLE PHOTONIC VLSI DEVICE TECHNOLOGY." University of Cincinnati / OhioLINK, 2003. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1059399964.

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Trimpl, Marcel. "Design of a current based readout chip and development of a DEPFET pixel prototype system for the ILC vertex detector." Bonn : Physikalisches Inst, 2005. http://deposit.d-nb.de/cgi-bin/dokserv?idn=978422228.

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Wong, Winnie. "A Hybrid Pixel Detector ASIC with Energy Binning for Real-Time, Spectroscopic Dose Measurements." Doctoral thesis, Mittuniversitetet, Institutionen för informationsteknologi och medier, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-16171.

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Hybrid pixel detectors have been demonstrated to provide excellent quality detection of ionising photon radiation, particularly in X-ray imaging. Recently, there has been interest in developing a hybrid pixel detector specifically for photon dosimetry. This thesis is on the design, implementation, and preliminary characterisation of the Dosepix readout chip. Dosepix has 256 square pixels of 220 mm side-length, constituting 12.4 mm2 of photo-sensitive area per detector. The combination of multiple pixels provides many parallel processors with limited input flux, resulting in a radiation dose monitor which can continuously record data and provide a real-time report on personal dose equivalent. Energy measurements are obtained by measuring the time over threshold of each photon and a state machine in the pixel sorts the detected photon event into appropriate energy bins. Each pixel contains 16 digital thresholds with 16 registers to store the associated energy bins. Preliminary measurements of Dosepix chips bump bonded to silicon sensors show very promising results. The pixel has a frontend noise of 120 e-. In low power mode, each chip consumes 15 mW, permitting its use in a portable, battery-powered system. Direct time over threshold output from the hybrid pixel detector assembly reveal distinctive photo-peaks correctly identifying the nature of incident photons, and verification measurements indicate that the pixel binning state machines accurately categorise charge spectra. Personal dose equivalent reconstruction using this data has a flat response for a large range of photon energies and personal dose equivalent rates.

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Wang, Jia. "Design of a low noise, limited area and full on-chip power management for CMOS pixel sensors in high energy physics experiments." Phd thesis, Université de Strasbourg, 2012. http://tel.archives-ouvertes.fr/tel-00758209.

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What are the elementary particles and how did the universe originate are the main driving forces in the high energy physics. In order to further demonstrate the standard model and discover new physics, several detectors are built for the high energy physics experiments. CMOS pixel sensors (CPS) can achieve an attractive tradeoff among many performance parameters, such as readout speed, granularity, material budget, power dissipation, radiation tolerance and integrating readout circuitry on the same substrate, compared with the hybrid pixel sensors and charge coupled devices. Thus, the CPS is a good candidate for tracking the charged particles in vertex detectors and beam telescopes.The power distribution becomes an important issue in the future detectors, since a considerable amount of sensors will be installed. Unfortunately, the independent powering has been proved to fail. In order to solve the power distribution challenges and to provide noiseless voltages, this thesis focuses on the design of a low noise, limited area, low power consumption and full on-chip power management in CPS chips. The CPS are firstly introduced drawing the design requirements of the power management. The power distribution dedicated to CPS chips is then proposed, in which the power management is utilized as the second power conversion stage. Two full on-chip regulators are proposed to generate the analog power supply voltage and the reference voltage required by correlated double sampling operation, respectively. Two prototypes have verified these regulators. They can meet the requirements of CPS. Moreover, the power management techniques and the radiation tolerance design are also presented in this thesis.

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Книги з теми "Pixel Chip"

Dudek, Piotr. Vision. Oxford University Press, 2018. http://dx.doi.org/10.1093/oso/9780199674923.003.0014.

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Vision is a sensory modality of primary importance to many animal species. The efficient implementation of visual perception is also one of the main challenges in the design of intelligent robotic systems. This chapter reviews the principles of operation and key features of the early stages of biological vision systems. Following the observation that visual information processing starts in the eye, it reviews several approaches to constructing biomimetic artificial vision systems. It presents devices inspired by the morphology of the insects’ compound eyes, and devices tightly integrating image sensing and processing circuitry. These include silicon integrated circuits mimicking the operation of vertebrate retinas, and bio-inspired systems oriented towards machine vision applications, such as dynamic vision sensors and vision chips with pixel-parallel cellular processor arrays. It elucidates the advantages of the near-sensor processing of the visual information, and potential for future developments of neuromorphic vision sensors.

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Частини книг з теми "Pixel Chip"

Liu, Yue. "VCSEL based smart pixel array technology enables chip-to-chip optical interconnect." In Lecture Notes in Computer Science, 1133. Berlin, Heidelberg: Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/3-540-45591-4_155.

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Rassau, A. M., G. Alagoda, D. Lucas, J. Austin-Crowe, and K. Eshraghian. "Massively Parallel Intelligent Pixel Implementation of a Zerotree Entropy Video Codec for Multimedia Communications." In VLSI: Systems on a Chip, 89–100. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/978-0-387-35498-9_9.

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Kawahito, Shoji, Kazuaki Sawada, Koji Tada, Makoto Ishida, and Yoshiaki Tadokoro. "A Chopperless Pyroelectric Active Pixel Infrared Image Sensor Using Chip Shift Operation." In Transducers ’01 Eurosensors XV, 574–77. Berlin, Heidelberg: Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/978-3-642-59497-7_136.

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Grassi, M., V. Ferragina, P. Malcovati, S. Caccia, G. Bertuccio, D. Martin, P. Bastia, I. Cappelluti, and N. Ratti. "A 32 × 32-Channels Chip for X-Ray Pixel Detector Read-Out." In Lecture Notes in Electrical Engineering, 307–10. Dordrecht: Springer Netherlands, 2009. http://dx.doi.org/10.1007/978-90-481-3606-3_60.

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Komuro, Takashi, and Masatoshi Ishikawa. "64 × 64 Pixels General Purpose Digital Vision Chip." In IFIP Advances in Information and Communication Technology, 15–26. Boston, MA: Springer US, 2002. http://dx.doi.org/10.1007/978-0-387-35597-9_2.

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Sheu, Bing J., and Joongho Choi. "Smart-Pixel, Cellular Neural Network, and Chaotic Chips." In Neural Information Processing and VLSI, 397–466. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2247-8_14.

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Ohta, Jun, Akihiro Uehara, Takashi Tokuda, and Masahiro Nunoshita. "Pulse-Modulated Vision Chips with Versatile-Interconnected Pixels." In Lecture Notes in Computer Science, 1063–71. Berlin, Heidelberg: Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/3-540-45591-4_146.

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Maria Margarit, Josep. "Pixel Test Chips in 0.35- and 0.15- $$\,\upmu $$ m CMOS Technologies." In Low-Power CMOS Digital Pixel Imagers for High-Speed Uncooled PbSe IR Applications, 101–34. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-49962-8_4.

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Maria Margarit, Josep. "Imager Test Chips in 2.5-, 0.35- and 0.15- $$\upmu $$ μ m CMOS Technologies." In Low-Power CMOS Digital Pixel Imagers for High-Speed Uncooled PbSe IR Applications, 135–68. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-49962-8_5.

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Vasavi, S., Ayesha Farha Shaik, and Phani chaitanya Krishna Sunkara. "Moving Object Classification Under Illumination Changes Using Binary Descriptors." In Optoelectronics in Machine Vision-Based Theories and Applications, 188–232. IGI Global, 2019. http://dx.doi.org/10.4018/978-1-5225-5751-7.ch007.

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Object recognition and classification has become important in a surveillance video situated at prominent areas such as airports, banks, military installations, etc. Outdoor environments are more challenging for moving object classification because of incomplete appearance details of moving objects due to illumination changes and large distance between the camera and moving objects. As such, there is a need to monitor and classify the moving objects by considering the challenges of video in the real time. Training the classifiers using feature-based approaches is easier and faster than pixel-based approaches in object classification. Extraction of a set of features from the object of interest is most important for classification. Viewpoint and sources of light illumination plays major role in the appearance of an object. Abrupt transitions are identified using Chi-square and corners are detected using Harris corner detection. Silhouettes are captured using background subtraction and feature extraction is done using ORB. k-NN classifier is used for classification.

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Тези доповідей конференцій з теми "Pixel Chip"

Haney, Michael W., and Marc P. Christensen. "Smart Pixel Based Viterbi Decoder." In Optical Computing. Washington, D.C.: Optica Publishing Group, 1995. http://dx.doi.org/10.1364/optcomp.1995.omd2.

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As voice and data communications networks proliferate, they face ever increasing demands for reliability, portability, and bandwidth. In many applications, the transmitted power is limited by practical considerations. Examples include satellite, cellular, and undersea long haul fiber communications systems. In these applications Forward Error Correction (FEC) techniques may be used to achieve reliable communications within the constrained power. FEC techniques are ultimately limited in their performance by the conflicting requirements of high speed, high computational complexity, and low size and power consumption. VLSI implementations of the elegant and powerful Viterbi convolutional decoding algorithm (VA) [1], which uses a recursive parallel search computation, are limited by the massive intra- and inter-chip communications requirements between nodes of the search graph. This constraint limits the number of states (nodes of the VA graph), for high-speed applications, and hence the overall performance of the VA. Current high speed single chip VLSI implementations are limited to a convolutional constraint length of about 7 and therefore require 27=128 processing nodes. Incrementing the constraint length by one provides nearly an order of magnitude improvement in BER [2], but requires twice as many computational and communications resources -- beyond the capabilities of a single chip. This size constraint limits single chip VLSI implementations to a coding gain of ~7dB. Strong motivation exists for using longer constraint length codes, requiring several decoding ICs. A multi-chip VLSI VA implementation is impractical for high speed applications due to the inter-chip communications bottleneck. The approach discussed in this paper overcomes this limitation by employing free-space optical interconnects to provide the required inter-chip connection, while maintaining on-chip speeds between chips.

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Choi, Dong-Hwi, and Dong-Woo Jee. "A 1984-Pixels, 1.26nW/Pixel Retinal Prosthesis Chip with Time-Domain In-Pixel Image Processing." In 2022 IEEE Asian Solid-State Circuits Conference (A-SSCC). IEEE, 2022. http://dx.doi.org/10.1109/a-sscc56115.2022.9980617.

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Hayes, E. M., R. D. Snyder, R. Jurrat, P. J. Stanko, S. A. Feld, C. W. Wilmsen, K. D. Choquette, K. M. Geib, and H. Q. Hou. "8×8 Database Filter Array Chip Fabricated with Field Effect Transistors and Vertical Cavity Surface Emitting Lasers." In The European Conference on Lasers and Electro-Optics. Washington, D.C.: Optica Publishing Group, 1996. http://dx.doi.org/10.1364/cleo_europe.1996.cthd4.

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In order to compete with electronic solutions, parallel optical signal processing & computing require large smart pixel arrays that arc fast, reliable, and reasonably priced with uniform performance across the array. To meet all of these qualifications requires the use of a well developed foundry. This paper presents the design and experimental results of an 8×8 array of GaAs smart pixels in which the high speed input photodetectors, logic gates and output driver are monolithically integrated and fabricated by a foundry. Each pixel of the array is made up of three MSM photodetectors, one AND and one XOR logic gate composed of enhancement mode MESFETs and one four stage laser driver with bump bonding pads, all fabricated by Vitesse through the MOSIS foundry. Vertical cavity surface emitting lasers (VCSELs) will be flip chip-bump bonded to the completed Vitesse fabricated chips using a coplanar contacting technique similar to the one developed by Goossen et al. [1]. This technique allows the VCSELs to be stand alone devices embedded in each pixel and not occupy space remote to the optical processors, thus saving space and reducing interconnect capacitance. In addition, as the array size becomes large, electrically connecting the pixels with the remotely placed output devices becomes difficult and defeats the purpose of the optical interconnects.

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Pu, R., R. Jurrat, E. M. Hayes, C. W. Wilmsen, K. D. Choquette, and K. M. Geib. "Optical processing arrays based on VCSELs bonded directly to GaAs smart pixels." In Spatial Light Modulators. Washington, D.C.: Optica Publishing Group, 1997. http://dx.doi.org/10.1364/slmo.1997.smb.4.

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VCSELs are near ideal light sources for free space, parallel optical interconnects since they are highly efficient, can be fabricated into 2D arrays and emit a low divergence column of light normal to the surface. However, integrating the VCSELs into smart pixels introduces fabrication problems since they can not be grown on foundry fabricated Si CMOS or GaAs MESFET circuits. Thus, the fabrication of complex pixels is difficult. Three methods of electrically connecting VCSELs to electronic chips have been discussed by Bryan et al. [1]; wire bonding, bridge bonding, and flip chip bonding to the whole VCSEL chip to a separate area of the electronic chip. Unfortunately none of these techniques are suitable for large-high speed arrays since they involve excessive numbers of long electrical lead wires or thin film traces which occupy a large area and add significantly to the capacitance and inductance of the circuit. Recently Goosen et al. [2] have developed a co-planar flip-chip bonding process for the attachment of SEED devices to CMOS chips. Their process has been shown to be both scalable and reliable [3]. This technique significantly increases the combined array size and decreases the interconnect capacitance and inductance allowing for much faster operation. The present paper reports the development of a co-planar bonding technique for VCSELs onto prefabricated pixel chips. This paper presents the details of this flip-chip bump-bonding integration.

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Yoon, J. H., S. E. Lee, and O'Dae Kwon. "Mega-pixel photonic quantum ring laser chip." In 2007 Conference on Lasers and Electro-Optics - Pacific Rim. IEEE, 2007. http://dx.doi.org/10.1109/cleopr.2007.4391586.

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McCallum, D. S., J. W. Kim, P. S. Guilfoyle, W. H. Chang, J. Mu, and M. Feng. "GaAs Smart Pixel Arrays for High Performance Optoelectronic Computing Modules." In Optics in Computing. Washington, D.C.: Optica Publishing Group, 1997. http://dx.doi.org/10.1364/oc.1997.ofb.3.

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Optoelectronic logic gates interconnected by free space optics (smart pixels) show great promise for efficient implementation of high performance switching, signal processing, and computing systems. Optical interconnects have a number of advantages over electrical interconnects, including (1) lower energy per bit for point to point interconnections; (2) lower chip area used per interconnection which allows a larger interconnect density; and (3) ability to implement high fan-out and high fan-in processing architectures. OptiComp is currently developing smart pixel arrays in GaAs and Si which will contain up to 1,000 smart pixels, each operating at a data rate of hundreds of Mb/s, on a 1 cm2 die. In this paper, we will describe the design of GaAs-based smart pixel arrays which contain up to 8 x 8 elements in a 9 x 9 mm area, and which are projected to operate at data rates in excess of 1 Gb/s/channel. These smart pixel arrays are suitable for incorporation in high performance optoelectronic computing (HPOC) modules.

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Forrest, S. R. "Optically powered smart pixels." In OSA Annual Meeting. Washington, D.C.: Optica Publishing Group, 1991. http://dx.doi.org/10.1364/oam.1991.thh2.

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Recently, there is an increasing interest in smart pixel arrays for use in high density, high bandwidth interconnection networks.1,2 Optoelectronic integrated circuits (OEICs) are attractive components for such arrays. There are, however, critical limitations associated with 2-D chip architectures that prevent the OEIC-based design from achieving the expected high performance. One issue is the electrical voltage supply and pixel logic control lines which must be routed to each pixel. The nonzero impedance of these interconnects introduces crosstalk which ultimately limits the bandwidth of the system. In addition, the dc bias lines and their associated ac decoupling circuitry consume valuable chip area. We propose a novel interconnection architecture to confront the issues of crosstalk and layout, which utilizes the principle of optically powered smart pixels.3 Here, optical powering is locally provided to each pixel using an integrated photovoltaic cell. In this paper, we demonstrate an optically powered, integrated smart pixel. The InP based circuit can be dynamically tuned with an optical control beam to operate as an amplifier, bistable switch or as a latch/reset. The circuit has an optoelectronic gain of 2.5–11, and operates at 80 Mbit/s with an optical switching energy of only 3.8 pJ.

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Novotny, R. A., A. L. Lentine, D. B. Buchholz, and A. V. Krishnamoorthy. "Analysis of Parasitic Front-end Capacitance and Thermal Resistance in Hybrid Flip-chip-bonded GaAs SEED/Si CMOS Receivers." In Optical Computing. Washington, D.C.: Optica Publishing Group, 1995. http://dx.doi.org/10.1364/optcomp.1995.otue17.

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Smart pixels[1] consisting of photodetectors, electronic circuitry, and E/O converters utilizing free-space optical interconnections show promise to relieve the interconnection bottleneck in computing and switching systems.[2] To reduce the propagation delay through a smart pixel, the receiver requires a fast response, hence it is essential to reduce the front end capacitance (Cin). Cin has three main components: the photodiode active area, the amplifier input, and the stray interconnect capacitance (Cs). The FET-SEED technology minimizes Cs through the monolithic integration of photodetectors, modulators and electronic circuitry.[3][4]] However, current system demonstrations using FET-SEEDs have been limited to using medium scale integration (MSI) smart pixel arrays. Hybrid integration of VLSI Si CMOS electronic circuitry with photodetectors, modulators, or emitters is an attractive approach in obtaining VLSI smart pixels in the near term.

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Chen, C. H., B. Hoanca, C. B. Kuznia, J. M. Wu, and A. A. Sawchuk. "Smart Pixel Array Network Interface (SAPIENT) for 2D Parallel Data Packet Networks." In Optics in Computing. Washington, D.C.: Optica Publishing Group, 1997. http://dx.doi.org/10.1364/oc.1997.othd.11.

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We describe a SmArt PIxEl for NeTwork Interface (SAPIENT) chip that performs interfacing of processors to 2-D parallel optical free space networks. This network transfers 2-D parallel data packets between processors on digital optical channels. We assume these parallel data packets contain address information for the destination processor, similar to the format of an ATM packet network, except the packets are passed between processors in a parallel format, in a single clock cycle. Each SAPIENT chip is capable of checking the address bits of an incoming parallel data packet, re-transmitting (or downloading) the packet, and loading electronic data onto the optical network from its host processor. Each data packet arrives as a 2D page-wide (9 bits) packet of network data and can be easily scaled up to larger N × N packets. The SAPIENT demonstration chip contains a 3 × 3 array of smart pixels that provide optical detection and transmission. The SAPIENT also contains address detection and contention avoidance circuitry. In this paper, we describe the optoelectronic technology involved and the circuit function of the SAPIENT chip. We describe a SAPIENT chip in a multiple processor network and present simulation of the SAPIENT interface.

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Tanemura, Takuo, Taichiro Fukui, Kento Komatsu, Yusuke Kohno, and Yoshiaki Nakano. "Single-Pixel Imaging Using Optical Phased Array Chip." In Asia Communications and Photonics Conference. Washington, D.C.: OSA, 2020. http://dx.doi.org/10.1364/acpc.2020.s4b.6.

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Звіти організацій з теми "Pixel Chip"

Trevino, M. C. Vargas. The Development of Software to Characterize the Fermilab Pixel Readout Chip for the BTeV Experiment. Office of Scientific and Technical Information (OSTI), January 2000. http://dx.doi.org/10.2172/1421426.

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