Дисертації з теми "Partitioning and placement algorithms"
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Stan, Oana. "Placement of tasks under uncertainty on massively multicore architectures." Thesis, Compiègne, 2013. http://www.theses.fr/2013COMP2116/document.
Повний текст джерелаThis PhD thesis is devoted to the study of combinatorial optimization problems related to massively parallel embedded architectures when taking into account uncertain data (e.g. execution time). Our focus is on chance constrained programs with the objective of finding the best solution which is feasible with a preset probability guarantee. A qualitative analysis of the uncertain data we have to treat (dependent random variables, multimodal, multidimensional, difficult to characterize through classical distributions) has lead us to design a non parametric method, the so-called "robust binomial approach", valid whatever the joint distribution and which is based on robust optimization and statistical hypothesis testing. We also propose a methodology for adapting approximate algorithms for solving stochastic problems by integrating the robust binomial approach when verifying for solution feasibility. The paractical relevance of our approach is validated through two problems arising in the compilation of dataflow application for manycore platforms. The first problem treats the stochastic partitioning of networks of processes on a fixed set of nodes, by taking into account the load of each node and the uncertainty affecting the weight of the processes. For finding stochastic solutions, a semi-greedy iterative algorithm has been proposed which allowed measuring the robustness and cost of the solutions with regard to those for the deterministic version of the problem. The second problem consists in studying the global placement and routing of dataflow applications on a clusterized architecture. The purpose being to place the processes on clusters such that it exists a feasible routing, a GRASP heuristic has been conceived first for the deterministic case and afterwards extended for the chance constrained variant of the problem
URGESE, GIANVITO. "Computational Methods for Bioinformatics Analysis and Neuromorphic Computing." Doctoral thesis, Politecnico di Torino, 2016. http://hdl.handle.net/11583/2646486.
Повний текст джерелаTrifunovic, Aleksandar. "Parallel algorithms for hypergraph partitioning." Thesis, Imperial College London, 2006. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.430537.
Повний текст джерелаAslan, Burak Galip Püskülcü Halis. "Heuristic container placement algorithms/." [s.l.]: [s.n.], 2003. http://library.iyte.edu.tr/tezler/master/bilgisayaryazilimi/T000268.rar.
Повний текст джерелаBahoshy, Nimatallah M. "Parallelization of algorithms by explicit partitioning." Thesis, Loughborough University, 1992. https://dspace.lboro.ac.uk/2134/27004.
Повний текст джерелаZanetti, Luca. "Algorithms for partitioning well-clustered graphs." Thesis, University of Bristol, 2018. http://hdl.handle.net/1983/e6ba8929-6488-4277-b91b-4f4f7eda2b26.
Повний текст джерелаMUPPIDI, SRINIVAS REDDY. "GENETIC ALGORITHMS FOR MULTI-OBJECTIVE PARTITIONING." University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1080827924.
Повний текст джерелаVijaya, Satya Ravi. "ALGORITHMS FOR HAPLOTYPE INFERENCE AND BLOCK PARTITIONING." Doctoral diss., University of Central Florida, 2006. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/2490.
Повний текст джерелаPh.D.
Other
Engineering and Computer Science
Computer Science
Martin, Nicolas. "Network partitioning algorithms with scale-free objective." Thesis, Université Grenoble Alpes, 2020. http://www.theses.fr/2020GRALT001.
Повний текст джерелаIn light of the complexity induced by large-scale networks, the design of network partitioning algorithms and related problematics are at the heart of this thesis. First, we raise a preliminary question on the structure of the partition itself: as the parts may includes disconnected nodes, we want to quantify the drawbacks to impose the nodes inside each part to be connected. Then we study the design of a partitioning algorithm inducing a reduced scale-free network. This allows to take advantage of the inherent features of this type of network. We also focus on the properties to preserve to respect the physical and dynamical profile of the initial network. We investigate then how to partition a network between measured and unmeasured nodes ensuring that the average of the unmeasured nodes can be efficiently reconstructed. In particular we show that, under hypothesis, this problem can be reduced to a problem of detection of subgraph with particular properties. Methods to achieve this detection are proposed. Finally, three applications are presented: first we apply the partitioning algorithm inducing scale-freeness to a large-scale urban traffic network. We show then that, thanks to the properties preserved through the partition, the reduced network can be used as an abstraction of the initial network. The second and third applications deal with network epidemics. First, we show that the scale-freeness of the abstracting network can be used to build a cure-assignation strategy. In the last application, we take advantage of the result on average reconstruction to estimate the evolution of a disease on a large-scale network
Liu, Huiqun. "Circuit partitioning algorithms for CAD VLSI design /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.
Повний текст джерелаOladeji, Olamide. "Network partitioning algorithms for electricity consumer clustering." Thesis, Massachusetts Institute of Technology, 2018. https://hdl.handle.net/1721.1/122917.
Повний текст джерелаThesis: S.M. in Technology and Policy, Massachusetts Institute of Technology, School of Engineering, Institute for Data, Systems, and Society, Technology and Policy Program, 2018
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2018
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 97-103).
In many developing countries, access to electricity remains a significant challenge. Electrification planners in these countries often have to make important decisions on the mode of electrification and the planning of electrical networks for those without access, while under resource constraints. To facilitate the achievement of universal energy access, the Reference Electrification Model (REM), a computational model capable of providing techno-economic analysis and data-driven decision support for these planning efforts, has been developed. Primary among REM's capabilities is the recommendation of the least-cost mode of electrification - i.e by electric grid extension or off-grid systems - for non-electrified consumers in a region under analysis, while considering technical, economic and environmental constraints.
This is achieved by the identification of consumer clusters (either as clusters of off-grid microgrids, stand-alone systems or grid-extension projects) using underlying clustering methods in the model. This thesis focuses on the development and implementation of partitioning algorithms to achieve this purpose. Building on previously implemented efforts on the clustering and recommendation capabilities of REM, this work presents the development, analysis and performance evaluation of alternative approaches to the consumer clustering process, in comparison with REM's previously incorporated clustering methodology. Results show that the alternative methodology proposed can compare favorably with the hitherto implemented method in REM. Consequently, the integration of the pro- posed network partitioning procedures within REM, as well as some potential future research directions, is discussed.
Finally, this thesis concludes with a discourse on the social and regulatory aspects of energy access and electricity planning in developing countries, providing some perspectives on the development policies and business models that complement the technological contributions of this work.
by Olamide Oladeji.
S.M. in Technology and Policy
S.M.
S.M.inTechnologyandPolicy Massachusetts Institute of Technology, School of Engineering, Institute for Data, Systems, and Society, Technology and Policy Program
S.M. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science
Schwartz, Victor Scott. "Dynamic platform-independent meta-algorithms for graph-partitioning." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1998. http://handle.dtic.mil/100.2/ADA356541.
Повний текст джерелаThesis advisor(s): Gordon H. Bradley. "September 1998." Includes bibliographical references (p. 99-100). Also available online.
Mehrotra, Anuj. "Constrained graph partitioning : decomposition, polyhedral structure and algorithms." Diss., Georgia Institute of Technology, 1992. http://hdl.handle.net/1853/24234.
Повний текст джерелаGwalani, Harsha. "Spatial Partitioning Algorithms for Solving Location-Allocation Problems." Thesis, University of North Texas, 2019. https://digital.library.unt.edu/ark:/67531/metadc1609062/.
Повний текст джерелаChandrasekhar, Suresh. "Partitioning Methods and Algorithms for Configurable Computing Machines." Thesis, Virginia Tech, 1998. http://hdl.handle.net/10919/36909.
Повний текст джерелаMaster of Science
Khan, Shoab Ahmad. "Logic and algorithm partitioning." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/13738.
Повний текст джерелаAndersen, Reid. "Local algorithms for graph partitioning and finding dense subgraphs." Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2007. http://wwwlib.umi.com/cr/ucsd/fullcit?p3259059.
Повний текст джерелаTitle from first page of PDF file (viewed June 11, 2007). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 92-95).
Leija, Antonio M. "AN INVESTIGATION INTO PARTITIONING ALGORITHMS FOR AUTOMATIC HETEROGENEOUS COMPILERS." DigitalCommons@CalPoly, 2015. https://digitalcommons.calpoly.edu/theses/1546.
Повний текст джерелаSamaranayake, Thellamurege Meththa. "Force directed algorithms for integrated circuit module placement." Thesis, Manchester Metropolitan University, 2010. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.529267.
Повний текст джерелаZhuo, Yue. "Timing and Congestion Driven Algorithms for FPGA Placement." Thesis, University of North Texas, 2006. https://digital.library.unt.edu/ark:/67531/metadc5423/.
Повний текст джерелаAlemany, Juan A. "Data placement algorithms for news-on-demand servers /." Thesis, Connect to this title online; UW restricted, 1997. http://hdl.handle.net/1773/6982.
Повний текст джерелаSerdar, Tatjana. "Automatic datapath tile placement and routing /." Thesis, Connect to this title online; UW restricted, 2000. http://hdl.handle.net/1773/6110.
Повний текст джерелаSazonova, Nadezhda A. "Parsimony-based genetic algorithm for haplotype resolution and block partitioning." Morgantown, W. Va. : [West Virginia University Libraries], 2007. https://eidr.wvu.edu/etd/documentdata.eTD?documentid=5499.
Повний текст джерелаTitle from document title page. Document formatted into pages; contains xi, 127 p. : ill. Includes abstract. Includes bibliographical references (p. 109-114).
Bobda, Christophe. "Synthesis of dataflow graphs for reconfigurable systems using temporal partitioning and temporal placement." [S.l. : s.n.], 2003. http://deposit.ddb.de/cgi-bin/dokserv?idn=968530567.
Повний текст джерелаPrasad, Abhijit. "Power supply partitioning for placement of built-in current sensors for IDDQ testing." Texas A&M University, 2003. http://hdl.handle.net/1969.1/103.
Повний текст джерелаHuang, Dachuan. "Improving Performance in Data Processing Distributed Systems by Exploiting Data Placement and Partitioning." The Ohio State University, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=osu1483312415041341.
Повний текст джерелаAddanki, Ravichandra. "Learning generalizable device placement algorithms for distributed machine learning." Thesis, Massachusetts Institute of Technology, 2019. https://hdl.handle.net/1721.1/122746.
Повний текст джерелаCataloged from PDF version of thesis.
Includes bibliographical references (pages 47-50).
We present Placeto, a reinforcement learning (RL) approach to efficiently find device placements for distributed neural network training. Unlike prior approaches that only find a device placement for a specific computation graph, Placeto can learn generalizable device placement policies that can be applied to any graph. We propose two key ideas in our approach: (1) we represent the policy as performing iterative placement improvements, rather than outputting a placement in one shot; (2) we use graph embeddings to capture relevant information about the structure of the computation graph, without relying on node labels for indexing. These ideas allow Placeto to train efficiently and generalize to unseen graphs. Our experiments show that Placeto requires up to 6.1 x fewer training steps to find placements that are on par with or better than the best placements found by prior approaches. Moreover, Placeto is able to learn a generalizable placement policy for any given family of graphs, which can then be used without any retraining to predict optimized placements for unseen graphs from the same family. This eliminates the large overhead incurred by prior RL approaches whose lack of generalizability necessitates re-training from scratch every time a new graph is to be placed.
by Ravichandra Addanki.
S.M.
S.M. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science
Enciso, Rosa. "Alliances in Graphs: Parameterized Algorithms and on Partitioning Series-Parallel Graphs." Doctoral diss., University of Central Florida, 2009. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/2479.
Повний текст джерелаPh.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Computer Science PhD
Enciso, Rosa I. "Alliances in graphs parameterized algorithms and on partitioning series-parallel graphs /." Orlando, Fla. : University of Central Florida, 2009. http://purl.fcla.edu/fcla/etd/CFE0002956.
Повний текст джерелаObenaus, Stefan Thomas Henning. "Fast placement algorithms for grids in two and three dimensions." Thesis, McGill University, 2000. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=37744.
Повний текст джерелаOriginal research contributions are provided in chapters 1, 4, and 5.
In chapter 1, the extension of relevant combinatorial grid placement problems to hypergraphs and multi-dimensional grids constitute a modest original contribution.
Entirely original work is presented in chapter 4, where we introduce a novel force-directed iterative placement algorithm for two- and three-dimensional placements. This algorithm is designed to produce good minimum-wire-length placements for large circuits, for which no comparison results exist. The three-dimensional implementation of our placement algorithm pioneers the 3-D placement field in which previously no efficient algorithms had been published. In order to avoid operating in a vacuum, we were forced to create a comparison algorithm based on an accepted standard placement technique. With this reference placer, we generated the first published 3-D placement results, and 2-D placement results for large benchmark circuits for which no published comparison results exist. Our placement algorithm out-performs the reference placer substantially in both run time and wire-length. Further, we use our algorithm to present some experimental evidence of the estimated wire-length savings when utilizing the third dimension.
Our final original contribution is a method presented in chapter 5 for efficiently placing a modern network topology, the star graph, into multi-dimensional grids such that all star graph neighbours are joined by a common grid line. The basic placement technique, originally published in [Obe95], is made efficient by compacting and contracting the bendless embedding in an effective manner.
Kashyap, Srinivas Raaghav. "Algorithms for data placement, reconfiguration and monitoring in storage networks." College Park, Md.: University of Maryland, 2007. http://hdl.handle.net/1903/7583.
Повний текст джерелаThesis research directed by: Dept. of Computer Science. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
Korupolu, Madhukar. "Placement algorithms for hierarchical cooperative caching and other location problems /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.
Повний текст джерелаVita. Includes bibliographical references (leaves 143-150), Copy 2 (p. 135-142). Available also in a digital version from Dissertation Abstracts.
Lindmark, Gustav. "Methods and algorithms for control input placement in complex networks." Licentiate thesis, Linköpings universitet, Reglerteknik, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-150886.
Повний текст джерелаMinor corrections are made in the electronic version of the thesis (Abstract). / Mindre korreigeringar är gjorda i den elektroniska versionen av avhandlingen (i Abstract).
Pardella, Gregor L. [Verfasser]. "Efficient Polynomial-Time Algorithms for Special Graph Partitioning Problems / Gregor L. Pardella." München : Verlag Dr. Hut, 2011. http://d-nb.info/1015604919/34.
Повний текст джерелаFarrag, Lamis M. "Applications of graph partitioning algorithms to terrain visibility and shortest path problems." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp01/MQ32386.pdf.
Повний текст джерелаGadde, Srimanth. "Graph Partitioning Algorithms for Minimizing Inter-node Communication on a Distributed System." University of Toledo / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1376561814.
Повний текст джерелаMenegola, Bruno. "A study of the k-way graph partitioning problem." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2012. http://hdl.handle.net/10183/67181.
Повний текст джерелаThe balanced graph partitioning problem asks to find a k-partition of the vertex set of an undirected graph, which minimizes the total cut size and such that the size of no part exceeds en/k , for some ee > [1, k]. This dissertation studies this problem, providing a recent review of constructive heuristics, refinement heuristics and multilevel techniques. We also propose a new hybrid algorithm for solving this partitioning problem. We show how several good existing strategies for constructing and improving partitions, as well as some newly proposed ones, can be integrated to form a GRASP with path-relinking. We report computational experiments that show that this approach obtains solutions competitive with state-of-the-art partitioners. In particular, the hybrid algorithm is able to find new best known values in some of the smaller instances, indicating that it can make a qualitative contribution compared to existing methods.
Cooklis, John T. "CPGA : a two-dimensional order-based algorithm for cell placement /." Online version of thesis, 1991. http://hdl.handle.net/1850/10709.
Повний текст джерелаTiberg, Jesper. "An evaluation of algorithms for real-time strategic placement of sensors." Thesis, University of Skövde, School of Humanities and Informatics, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:his:diva-865.
Повний текст джерелаIn this work an investigation is performed in whether the algorithms Simultaneous Perturbation Stochastic Approximation (SPSA) and Virtual Force Algorithm (VFA) are suitable for real-time strategic placement of sensors in a dynamic environment. An evaluation of these algorithms is conducted and compared to Simulated Annealing (SA), which has been used before in similar applications.
For the tests, a computer based model of the sensors and the environment in which they are used, is implemented. The model handles sensors, moving objects, specifications for the area the sensors are supposed to monitor, and all interaction between components within the model.
It was the belief of the authors that SPSA and VFA are suited for this kind of problem, and that they have advantages over SA in complex scenarios. The results shows this to be true although SA seems to perform better when it comes to smaller number of sensors to be placed
Eatmon, Dedra. "Evaluating Placement Algorithms with the DREAM Framework for Reconfigurable Hardware Devices." NCSU, 2000. http://www.lib.ncsu.edu/theses/available/etd-20000807-062016.
Повний текст джерелаThe field programmable gate array (FPGA) has become one of the most utilized configurable devices in the area of reconfigurable computing. FPGAs have alarge amount of flexibility and provide a high degree of parallel computing capability. Since their introduction in the 1980's, these configurable logicdevices have experienced a dramatic increase in programming capabilities and performance. Both factors have been significant in the changing roles ofconfigurable devices in custom-computing machines. However, the improvements in capability and performance have not eliminated the issues related toefficient placement of applications on these devices.
This thesis presents a tool that evaluates placement algorithms for configurable logic devices. Written in Java, the tool is a framework in whichvarious placement algorithms can be executed and the performance and quality ofeach placement evaluated using a cost function. Based on devices thatsupport relocatable hardware modules (RHMs), the tool places modules with user-specified placement algorithms and provides feedback that can be usedfor a comparative analysis. The framework manages module mappings to the logicdevice that are both independent of each other and do not requirepin-to-pin routing connections. Such a tool is valuable for the identification of effective placement algorithms for real-time placement of RHMs in run-time reconfigurable systems.
The Dynamic Resource Allocation and Management (DREAM) framework, has been designed and developed to evaluate FPGA placement algorithms/heuristics. Aportion of the evaluation is based on a simplistic cost function that calculates the amount of contiguous unused space remaining on the device intwo dimensions. In our experiments, we use an FPGA logic core generator to produce several rectangular RHMs. In addition to the rectangular RHMs producedby the logic core generation tool, our framework can handle arbitrary circuit profiles. Several scenarios consisting of approximately 500insertions/deletions of both rectangular and non-rectangular RHMs are used as test data sets for placement. Three placement algorithms are presented todemonstrate the flexibility of the framework. The first algorithm tested in the DREAM framework is a random placement algorithm. The second algorithm isan adaptation of a traditional best-fit algorithm that we call exhaustivesearch. The third algorithm is a modified version of first-fit.Future work will involve the development of additional placement algorithms andthe incorporation ofplacement issues that relate to requests for central reconfigurable computing resources originating from a remote site.
The DREAM framework answers the call for a tool that is sorely needed to identify placement algorithms that can be effectively used for real-timeplacement. In addition to providing results that can be used to benchmark the performance of placement algorithms in real-time on a configurablesystem, this tool also allows the end-user methods to store and load placementsfor future optimization. By taking full advantage of the partial andfull dynamic reconfiguration capabilities of logic devices currently used in run-time reconfigurable systems, the goal of DREAM is to provide a tool with whichthe quality of placement algorithms can be quantified and compared.
Dong, Shaoqiang Agrawal Prathima. "Node placement, routing and localization algorithms for heterogeneous wireless sensor networks." Auburn, Ala, 2008. http://repo.lib.auburn.edu/EtdRoot/2008/SPRING/Electrical_and_Computer_Engineering/Thesis/Dong_Shaoqiang_40.pdf.
Повний текст джерелаHANDA, MANISH. "ONLINE PLACEMENT AND SCHEDULING ALGORITHMS AND METHODOLOGIES FOR RECONFIGURABLE COMPUTING SYSTEMS." University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100030953.
Повний текст джерелаSensen, Norbert. "Lower bounds and exact algorithms for the graph partitioning problem using multicommodity flows." [S.l. : s.n.], 2003. http://deposit.ddb.de/cgi-bin/dokserv?idn=971568243.
Повний текст джерелаJacobson, Jay Alan. "State space partitioning methods for solving a class of stochastic network problems." Diss., Georgia Institute of Technology, 1993. http://hdl.handle.net/1853/24928.
Повний текст джерелаAgnihotri, Ameya Ramesh. "Combinatorial optimization techniques for VLSI placement." Diss., Online access via UMI:, 2007.
Знайти повний текст джерелаEl-Darzi, E. "Methods for solving the set covering and set partitioning problems using graph theoretic (relaxation) algorithms." Thesis, Brunel University, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.381678.
Повний текст джерелаSchultz, Xavier da Silveira Luís Fernando. "Turán Triangles, Cell Covers, Road Placement and Train Scheduling." Thesis, Université d'Ottawa / University of Ottawa, 2020. http://hdl.handle.net/10393/40569.
Повний текст джерелаMofya, Enock Chisonge. "Exact and Heuristic Algorithms for Solving the Generalized Minimum Filter Placement Problem." Diss., Tucson, Arizona : University of Arizona, 2005. http://etd.library.arizona.edu/etd/GetFileServlet?file=file:///data1/pdf/etd/azu%5Fetd%5F1311%5F1%5Fm.pdf&type=application/pdf.
Повний текст джерелаHsueh, Tsu-Yun, and 薛祖雲. "Partitioning Related Research and Placement-Aware Partitioning Algorithm." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/88545870473406146763.
Повний текст джерела中原大學
資訊工程研究所
99
Abstract As the process technology progress, there are more and more components on a chip. Therefore, how to partition the circuit effectively is a very important issue. Partitioning-based placement is a common placement method. A good partition method can get a good placement result. In our study of previous research, we find the partitioning methods [13][18][19] can not effectively consider the connection of external nets in global view. Therefore, we propose a new partitioning method which can consider the connection of external nets and minimize the number of cuts in the partitioning area. In the past, we have done partitioning research for 3D ICs. We implement two partitioning methods which are two-way partition and k-way partition under 3D ICs to compare the performance of the two methods. As shown in the experimental results, on average, the two-way partition is 69% less than k-way partition in terms of TSV number and 4.35x faster in terms of run time. According to the experimental results, the performance of two-way partition is better than k-way partition. Therefore, we use the two-way partitioning method to develop a Placement-aware Partitioning algorithm. We use our algorithm to compare with two kinds of methods. The one of the methods is do partition with traditional terminal propagation, another one is without terminal propagation. As shown in the experimental results, on average, the result of our algorithm is 10% and 37% shorter in terms of HPWL (Half-perimeter Wirelength), 9% and 31% shorter in terms of STWL (Steiner Tree Wirelength), respectively. And we use a Golden Router which is provide by 2011 ISPD contest to route the result, on average, our wirelength is shorter than those two methods 36% and 55%, respectively.
Yuan, Ming-Huan, and 袁明煥. "Global Placement by Circuit Partitioning with Hyperedge Clique ModelingGlobal Placement by Circuit Partitioning with Hyperedge Clique Modeling." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/39026823847514684108.
Повний текст джерела元智大學
資訊工程學系
93
As VLSI technology advances, more transistors will be on a chip. In standard cell designs, transistors are grouped into cells of the same height to perform some basic logic function. There will be more than a million cells in a VLSI design. Placement of these cells on a chip is increasingly difficult, but bearing the responsibility of deciding the length of interconnects. It will certainly affect chip area, routability, performance, etc. Several placement algorithms have been proposed in the past. We choose the multi-level hierarchical technique for placement. hMetis is a software package for partitioning a large hypergraph based on multi-level hypergraph partitioning. This program provides high quality partition for VLSI designs. This program is fast than the other widely used partitioning algorithms. Clique is a complete subgraph contained in a larger graph. Clique is often used to convert a hyperedge into edges such that a hypergraph can be transformed into a graph. It has been found that clique modeling of hyperedges in circuit partitioning could lead to a cut size as small as that obtained by hMetis without using clique modeling and up to 15% reduction in external degree if a circuit is partitioned into a large number of parts. A placer is designed to place the results obtained from the partitioning of graphs with clique modeling. Global placement by circuit partitioning with hyperedge clique could obtained small wirelength than non-clique model by our experiments. The results shown up to 10% improve in the wirelength with clique model than non-clique model.