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Опубліковано: 10 грудня 2022
Оновлено: 28 січня 2023

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Статті в журналах з теми "Parity check decoder"

1

Zhang, Zhe, Liang Zhou, and Zhi Heng Zhou. "Design of A Parallel Decoding Method for LDPC Code Generated via Primitive Polynomial." Electronics 10, no. 4 (February 9, 2021): 425. http://dx.doi.org/10.3390/electronics10040425.

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Анотація:
An effective way of improving decoding performance of an LDPC code is to extend the single-decoder decoding method to a parallel decoding method with multiple sub-decoders. To this end, this paper proposes a parallel decoding method for the LDPC codes constructed by m-sequence. In this method, the sub-decoders have two types. The first one contains only one decoding module using the original parity-check constraints to implement a belief propagation (BP) algorithm. The second one consists of a pre-decode module and a decoding module. The parity-check matrices for pre-decode modules are generated by the parity-check constraints of the sub-sequences sampled from an m-sequence. Then, the number of iterations of the BP process in each pre-decode module is set as half of the girth of the parity-check matrix, resulting in the elimination of the impact of short cycles. Using maximum a posterior (MAP), the least metric selector (LMS) finally picks out a codeword from the outputs of sub-decoders. Our simulation results show that the performance gain of the proposed parallel decoding method with five sub-decoders is about 0.4 dB, compared to the single-decoder decoding method at the bit error rate (BER) of 10−5.
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2

Jan, Qasim, Shahid Hussain, Muhammad Furqan, Zhiwen Pan, Nan Liu, and Xiaohu You. "Parity-Check-CRC Concatenated Polar Codes SSCFlip Decoder." Electronics 11, no. 23 (November 22, 2022): 3839. http://dx.doi.org/10.3390/electronics11233839.

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Successive cancellation flip decoding requires a large number of extra successive cancellation decoding attempts at low signal-to-noise ratios (SNRs), resulting in high decoding complexity. In addition, it has a long decoding latency. Although modifications have been proposed in successive cancellation flip decoding, these still have high computational complexity at low SNRs due to a huge number of additional successive cancellation decoding attempts. It is desirable to detect the unsuccessful successive cancellation decoding process at an early stage in the additional successive cancellation flip attempts and stop it that can reduce the decoding complexity. This paper combines the parity-check-CRC concatenated polar codes with the low-latency simplified successive cancellation decoding and proposes a parity-check-CRC concatenated polar codes simplified successive cancellation flip (PC-CRC-SSCFlip) decoder. It further employs the parity-check vector to identify the unsuccessful simplified successive cancellation flip decoding at an early stage and terminates so that it can minimize the decoding complexity on average. Additionally, this work proposes an error-prone flipping list by incorporating the empirically observed indices based on channel-induced error distribution along with the first bit of each Rate-1 node. The proposed technique can identify more than one error-prone bit through a flipping list and correct them. In addition, the parity-check vector further narrows down the search space for the identification of erroneous decisions. Simulation results show that 60% of unsuccessful additional successive cancellation decoding attempts terminate early rather than decode the whole codeword. The proposed PC-CRC-SSCFlip decoder has approximately 0.7 dB and 0.3 dB gains over successive cancellation and successive cancellation flip decoders, respectively, at a fixed block error rate (BLER) = 10−3. Additionally, it reduces the average computational complexity and decoding latency of the successive cancellation flip decoder at low-to-medium SNRs while approaching successive cancellation decoding complexity at medium-to-high SNRs.
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3

Sułek, W. "Pipeline processing in low-density parity-check codes hardware decoder." Bulletin of the Polish Academy of Sciences: Technical Sciences 59, no. 2 (June 1, 2011): 149–55. http://dx.doi.org/10.2478/v10175-011-0019-9.

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Pipeline processing in low-density parity-check codes hardware decoderLow-Density Parity-Check (LDPC) codes are one of the best known error correcting coding methods. This article concerns the hardware iterative decoder for a subclass of LDPC codes that are implementation oriented, known also as Architecture Aware LDPC. The decoder has been implemented in a form of synthesizable VHDL description. To achieve high clock frequency of the decoder hardware implementation - and in consequence high data-throughput, a large number of pipeline registers has been used in the processing chain. However, the registers increase the processing path delay, since the number of clock cycles required for data propagating is increased. Thus in general the idle cycles must be introduced between decoding subiterations. In this paper we study the conditions for necessity of idle cycles and provide a method for calculation the exact number of required idle cycles on the basis of parity check matrix of the code. Then we propose a parity check matrix optimization method to minimize the total number of required idle cycles and hence, maximize the decoder throughput. The proposed matrix optimization by sorting rows and columns does not change the code properties. Results, presented in the paper, show that the decoder throughput can be significantly increased with the proposed optimization method.
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4

Arul Murugan, C., B. Banuselvasaraswathy, K. Gayathree, and M. Ishwarya Niranjana. "Efficient high throughput decoding architecture for non-binary LDPC codes." International Journal of Engineering & Technology 7, no. 2.8 (March 19, 2018): 195. http://dx.doi.org/10.14419/ijet.v7i2.8.10407.

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This article, deals with efficient trellis inbuilt decoding architecture for non-binary Linear Density Parity Check (LDPC) codes. In this decoder, a bidirectional recursion is embedded to enhance the layered scheduling and decoding latency, which in turn is used to minimize the number of iterations compared to existing techniques. Consequently, it is necessary to increase the throughput for improving the efficiency of the system. In addition, a compression technique is implemented for reducing the requirements of memory and the area. Trellis based decoder was used to reinforce the check node processing. The proposed decoder for LDPC codes yields high throughput when compared to other similar decoders presented in preceding works. The designed architecture was implemented using Cadence Virtuoso software. This decoder provides a throughput of about 39.21 Mb/s at clock frequency of 190MHz.
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5

Zhang, Chuan, Lulu Ge, Xingchi Zhang, Wei Wei, Jing Zhao, Zaichen Zhang, Zhongfeng Wang, and Xiaohu You. "A Uniform Molecular Low-Density Parity Check Decoder." ACS Synthetic Biology 8, no. 1 (December 4, 2018): 82–90. http://dx.doi.org/10.1021/acssynbio.8b00304.

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6

Dinh, The Cuong, Huyen Pham Thi, Hung Dao Tuan, and Nghia Pham Xuan. "ONE-MINIUM-ONLY BASIC-SET TRELLIS MIN-MAX DECODER ARCHITECTURE FOR NONBINARY LDPC CODE." Journal of Computer Science and Cybernetics 37, no. 2 (May 31, 2021): 91–106. http://dx.doi.org/10.15625/1813-9663/37/2/15917.

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Nonbinary low-density-parity-check (NB-LDPC) code outperforms their binary counterpart in terms of error-correcting performance and error-floor property when the code length is moderate. However, the drawback of NB-LDPC decoders is high complexity and the complexity increases considerably when increasing the Galois-field order. In this paper, an One-Minimum-Only basic-set trellis min-max (OMO-BS-TMM) algorithm and the corresponding decoder architecture are proposed for NBLDPC codes to greatly reduce the complexity of the check node unit (CNU) as well as the whole decoder. In the proposed OMO-BS-TMM algorithm, only the first minimum values are used for generating the check node messages instead of using both the first and second minimum values, and the number of messages exchanged between the check node and the variable node is reduced in comparison with the previous works. Layered decoder architectures based on the proposed algorithm were implemented for the (837, 726) NB-LDPC code over GF(32) using 90-nm CMOS technology. The implementation results showed that the OMO-BS-TMM algorithm achieves the almost similar error-correcting performance, and a reduction of the complexity by 31.8% and 20.5% for the whole decoder, compared to previous works. Moreover, the proposed decoder achieves a higher throughput at 1.4 Gbps, compared with the other state-of-the-art NBLDPC decoders.
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7

Revathy, M., and R. Saravanan. "A Low-Complexity Euclidean Orthogonal LDPC Architecture for Low Power Applications." Scientific World Journal 2015 (2015): 1–8. http://dx.doi.org/10.1155/2015/327357.

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Low-density parity-check (LDPC) codes have been implemented in latest digital video broadcasting, broadband wireless access (WiMax), and fourth generation of wireless standards. In this paper, we have proposed a high efficient low-density parity-check code (LDPC) decoder architecture for low power applications. This study also considers the design and analysis of check node and variable node units and Euclidean orthogonal generator in LDPC decoder architecture. The Euclidean orthogonal generator is used to reduce the error rate of the proposed LDPC architecture, which can be incorporated between check and variable node architecture. This proposed decoder design is synthesized on Xilinx 9.2i platform and simulated using Modelsim, which is targeted to 45 nm devices. Synthesis report proves that the proposed architecture greatly reduces the power consumption and hardware utilizations on comparing with different conventional architectures.
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8

Baldi, Marco, Giovanni Cancellieri, and Franco Chiaraluce. "Iterative Soft-Decision Decoding of Binary Cyclic Codes." Journal of Communications Software and Systems 4, no. 2 (June 22, 2008): 142. http://dx.doi.org/10.24138/jcomss.v4i2.227.

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Binary cyclic codes achieve good error correction performance and allow the implementation of very simpleencoder and decoder circuits. Among them, BCH codesrepresent a very important class of t-error correcting codes, with known structural properties and error correction capability. Decoding of binary cyclic codes is often accomplished through hard-decision decoders, although it is recognized that softdecision decoding algorithms can produce significant coding gain with respect to hard-decision techniques. Several approaches have been proposed to implement iterative soft-decision decoding of binary cyclic codes. We study the technique based on “extended parity-check matrices”, and show that such method is not suitable for high rates or long codes. We propose a new approach, based on “reduced parity-check matrices” and “spread parity-check matrices”, that can achieve better correction performance in many practical cases, without increasing the complexity.
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9

Yao, Chang-Kun, Yun-Ching Tang, and Hongchin Lin. "Energy-Efficient and Area-Efficient QC-LDPC with RS Decoders Using 2M-LMSA." Journal of Circuits, Systems and Computers 24, no. 02 (November 27, 2014): 1550026. http://dx.doi.org/10.1142/s0218126615500267.

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This study proposes an energy-efficient and area-efficient dual-path low-density parity-check (LDPC) with Reed–Solomon (RS) decoder for communication systems. Hardware complexity is reduced by applying a dual-path 2-bit modified layered min-sum algorithm (2M-LMSA) to a (2550, 2040) quasi-cyclic LDPC (QC-LDPC) code with the column and row weights of 3 and 15, respectively. The simplified check node units (CNUs) reduce memory and routing complexity as well as the energy needed to decode each bit. A throughput of 11 Gb/s is achieved by using 90-nm CMOS technology at a clock frequency of 208 MHz at 0.9 V with average power of 244 mW on a chip area of 3.05 mm2. Decoding performance is further improved by appending the (255, 239) RS decoder after the LDPC decoder. The LDPC plus RS decoder consumes the power of 434 mW on the area of 3.45 mm2.
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10

Ismail, Mohamed, Imran Ahmed, and Justin Coon. "Low Power Decoding of LDPC Codes." ISRN Sensor Networks 2013 (January 17, 2013): 1–12. http://dx.doi.org/10.1155/2013/650740.

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Wireless sensor networks are used in many diverse application scenarios that require the network designer to trade off different factors. Two such factors of importance in many wireless sensor networks are communication reliability and battery life. This paper describes an efficient, low complexity, high throughput channel decoder suited to decoding low-density parity-check (LDPC) codes. LDPC codes have demonstrated excellent error-correcting ability such that a number of recent wireless standards have opted for their inclusion. Hardware realisation of practical LDPC decoders is a challenging area especially when power efficient solutions are needed. Implementation details are given for an LDPC decoding algorithm, termed adaptive threshold bit flipping (ATBF), designed for low complexity and low power operation. The ATBF decoder was implemented in 90 nm CMOS at 0.9 V using a standard cell design flow and was shown to operate at 250 MHz achieving a throughput of 252 Gb/s/iteration. The decoder area was 0.72 mm2 with a power consumption of 33.14 mW and a very small energy/decoded bit figure of 1.3 pJ.
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Дисертації з теми "Parity check decoder"

1

Vijayakumar, Suresh Mikler Armin. "FPGA implementation of low density parity check codes decoder." [Denton, Tex.] : University of North Texas, 2009. http://digital.library.unt.edu/permalink/meta-dc-11003.

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2

Zhang, Kai. "High-Performance Decoder Architectures For Low-Density Parity-Check Codes." Digital WPI, 2012. https://digitalcommons.wpi.edu/etd-dissertations/17.

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The Low-Density Parity-Check (LDPC) codes, which were invented by Gallager back in 1960s, have attracted considerable attentions recently. Compared with other error correction codes, LDPC codes are well suited for wireless, optical, and magnetic recording systems due to their near- Shannon-limit error-correcting capacity, high intrinsic parallelism and high-throughput potentials. With these remarkable characteristics, LDPC codes have been adopted in several recent communication standards such as 802.11n (Wi-Fi), 802.16e (WiMax), 802.15.3c (WPAN), DVB-S2 and CMMB. This dissertation is devoted to exploring efficient VLSI architectures for high-performance LDPC decoders and LDPC-like detectors in sparse inter-symbol interference (ISI) channels. The performance of an LDPC decoder is mainly evaluated by area efficiency, error-correcting capability, throughput and rate flexibility. With this work we investigate tradeoffs between the four performance aspects and develop several decoder architectures to improve one or several performance aspects while maintaining acceptable values for other aspects. Firstly, we present a high-throughput decoder design for the Quasi-Cyclic (QC) LDPC codes. Two new techniques are proposed for the first time, including parallel layered decoding architecture (PLDA) and critical path splitting. Parallel layered decoding architecture enables parallel processing for all layers by establishing dedicated message passing paths among them. The decoder avoids crossbar-based large interconnect network. Critical path splitting technique is based on articulate adjustment of the starting point of each layer to maximize the time intervals between adjacent layers, such that the critical path delay can be split into pipeline stages. Furthermore, min-sum and loosely coupled algorithms are employed for area efficiency. As a case study, a rate-1/2 2304-bit irregular LDPC decoder is implemented using ASIC design in 90 nm CMOS process. The decoder can achieve an input throughput of 1.1 Gbps, that is, 3 or 4 times improvement over state-of-art LDPC decoders, while maintaining a comparable chip size of 2.9 mm^2. Secondly, we present a high-throughput decoder architecture for rate-compatible (RC) LDPC codes which supports arbitrary code rates between the rate of mother code and 1. While the original PLDA is lack of rate flexibility, the problem is solved gracefully by incorporating the puncturing scheme. Simulation results show that our selected puncturing scheme only introduces the BER performance degradation of less than 0.2dB, compared with the dedicated codes for different rates specified in the IEEE 802.16e (WiMax) standard. Subsequently, PLDA is employed for high throughput decoder design. As a case study, a RC- LDPC decoder based on the rate-1/2 WiMax LDPC code is implemented in CMOS 90 nm process. The decoder can achieve an input throughput of 975 Mbps and supports any rate between 1/2 and 1. Thirdly, we develop a low-complexity VLSI architecture and implementation for LDPC decoder used in China Multimedia Mobile Broadcasting (CMMB) systems. An area-efficient layered decoding architecture based on min-sum algorithm is incorporated in the design. A novel split-memory architecture is developed to efficiently handle the weight-2 submatrices that are rarely seen in conventional LDPC decoders. In addition, the check-node processing unit is highly optimized to minimize complexity and computing latency while facilitating a reconfigurable decoding core. Finally, we propose an LDPC-decoder-like channel detector for sparse ISI channels using belief propagation (BP). The BP-based detection computationally depends on the number of nonzero interferers only and are thus more suited for sparse ISI channels which are characterized by long delay but a small fraction of nonzero interferers. Layered decoding algorithm, which is popular in LDPC decoding, is also adopted in this paper. Simulation results show that the layered decoding doubles the convergence speed of the iterative belief propagation process. Exploring the special structure of the connections between the check nodes and the variable nodes on the factor graph, we propose an effective detector architecture for generic sparse ISI channels to facilitate the practical application of the proposed detection algorithm. The proposed architecture is also reconfigurable in order to switch flexible connections on the factor graph in the time-varying ISI channels.
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3

Kopparthi, Sunitha. "Flexible encoder and decoder designs for low-density parity-check codes." Diss., Manhattan, Kan. : Kansas State University, 2010. http://hdl.handle.net/2097/4190.

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4

Hussein, Ahmed Refaey Ahmed. "Universal Decoder for Low Density Parity Check, Turbo and Convolutional Codes." Thesis, Université Laval, 2011. http://www.theses.ulaval.ca/2011/28154/28154.pdf.

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5

Selvarathinam, Anand Manivannan. "High throughput low power decoder architectures for low density parity check codes." Texas A&M University, 2005. http://hdl.handle.net/1969.1/2529.

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A high throughput scalable decoder architecture, a tiling approach to reduce the complexity of the scalable architecture, and two low power decoding schemes have been proposed in this research. The proposed scalable design is generated from a serial architecture by scaling the combinational logic; memory partitioning and constructing a novel H matrix to make parallelization possible. The scalable architecture achieves a high throughput for higher values of the parallelization factor M. The switch logic used to route the bit nodes to the appropriate checks is an important constituent of the scalable architecture and its complexity is high with higher M. The proposed tiling approach is applied to the scalable architecture to simplify the switch logic and reduce gate complexity. The tiling approach generates patterns that are used to construct the H matrix by repeating a fixed number of those generated patterns. The advantages of the proposed approach are two-fold. First, the information stored about the H matrix is reduced by onethird. Second, the switch logic of the scalable architecture is simplified. The H matrix information is also embedded in the switch and no external memory is needed to store the H matrix. Scalable architecture and tiling approach are proposed at the architectural level of the LDPC decoder. We propose two low power decoding schemes that take advantage of the distribution of errors in the received packets. Both schemes use a hard iteration after a fixed number of soft iterations. The dynamic scheme performs X soft iterations, then a parity checker cHT that computes the number of parity checks in error. Based on cHT value, the decoder decides on performing either soft iterations or a hard iteration. The advantage of the hard iteration is so significant that the second low power scheme performs a fixed number of iterations followed by a hard iteration. To compensate the bit error rate performance, the number of soft iterations in this case is higher than that of those performed before cHT in the first scheme.
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6

Cai, Fang. "Efficient VLSI Architectures for Non-binary Low Density Parity Check Decoding." Case Western Reserve University School of Graduate Studies / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=case1300821245.

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Shadab, Rakin Muhammad. "Statistical Analysis of a Channel Emulator for Noisy Gradient Descent Low Density Parity Check Decoder." DigitalCommons@USU, 2019. https://digitalcommons.usu.edu/etd/7582.

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The purpose of a channel emulator is to emulate a communication channel in real-life use case scenario. These emulators are often used in the domains of research in digital and wireless communication. One such area is error correction coding, where transmitted data bits over a channel are decoded and corrected to prevent data loss. A channel emulator that does not follow the properties of the channel it is intended to replicate can lead to mistakes while analyzing the performance of an error-correcting decoder. Hence, it is crucial to validate an emulator for a particular communication channel. This work delves into the statistics of a channel emulator and analyzes its effects on a particular decoder.
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8

Yang, Lei. "VLSI implementation of low-error-floor multi-rate capacity-approaching low-density parity-check code decoder /." Thesis, Connect to this title online; UW restricted, 2006. http://hdl.handle.net/1773/5966.

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9

Von, Leipzig Mirko. "Code generation and simulation of an automatic, flexible QC-LDPC hardware decoder." Thesis, Stellenbosch : Stellenbosch University, 2015. http://hdl.handle.net/10019.1/96835.

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Thesis (MEng)--Stellenbosch University, 2015.
ENGLISH ABSTRACT: Iterative error correcting codes such as LDPC codes have become prominent in modern forward error correction systems. A particular subclass of LDPC codes known as quasicyclic LDPC codes has been incorporated in numerous high speed wireless communication and video broadcasting standards. These standards feature multiple codes with varying codeword lengths and code rates and require a high throughput. Flexible hardware that is capable of decoding multiple quasi-cyclic LDPC codes is therefore desirable. This thesis investigates binary quasi-cyclic LDPC codes and designs a generic, flexible VHDL decoder. The decoder is further enhanced to automatically select the most likely decoder based on the initial a posterior probability of the parity-check equation syndromes. A software system is developed that generates hardware code for such a decoder based on a small user specification. The system is extended to provide performance simulations for this generated decoder.
AFRIKAANSE OPSOMMING: Iteratiewe foutkorreksiekodes soos LDPC-kodes word wyd gebruik in moderne voorwaartse foutkorreksiestelsels. ’n Subklas van LDPC-kodes, bekend as kwasisikliese LDPC-kodes, word in verskeie hoëspoed-kommunikasie- en video-uitsaaistelselstandaarde gebruik. Hierdie standaarde inkorporeer verskeie kodes van wisselende lengtes en kodetempos, en vereis hoë deurset. Buigsame apparatuur, wat die vermoë het om ’n verskeidenheid kwasisikliese LDPC-kodes te dekodeer, is gevolglik van belang. Hierdie tesis ondersoek binêre kwasisikliese LDPC-kodes, en ontwerp ’n generiese, buigsame VHDL-dekodeerder. Die dekodeerder word verder verbeter om outomaties die mees waarskynlike dekodeerder te selekteer, gebaseer op die aanvanklike a posteriori-waarskynlikheid van die pariteitstoetsvergelykings se sindrome. ’n Programmatuurstelsel word ontwikkel wat die fermware-kode vir so ’n dekodeerder genereer, gebaseer op ’n beknopte gebruikerspesifikasie. Die stelsel word uitgebrei om werksverrigting te simuleer vir die gegenereerde dekodeerder.
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Yang, Lan. "An Area-Efficient Architecture for the Implementation of LDPC Decoder." Case Western Reserve University School of Graduate Studies / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=case1300337576.

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Частини книг з теми "Parity check decoder"

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Benhayoun, Mhammed, Mouhcine Razi, Anas Mansouri, and Ali Ahaitouf. "Efficient Memory Parity Check Matrix Optimization for Low Latency Quasi Cyclic LDPC Decoder." In Lecture Notes in Electrical Engineering, 71–79. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-6259-4_5.

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Lou, Der-Chyuan, Jiang-Lung Liu, and Hao-Kuan Tso. "Evolution of Information-Hiding Technology." In Information Security and Ethics, 144–54. IGI Global, 2008. http://dx.doi.org/10.4018/978-1-59904-937-3.ch010.

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Information-hiding technology is an ancient art and has existed for several centuries. In the past, messages could easily be intercepted because there was no technology of secret communication. Hence, a third party was able to read the message easily. This was all changed during 440 B.C., that is, the Greek Herod’s era. The Greek historian Herodotus in his writing of histories stated that Demaratus was the first person who used the technique of information hiding. Demaratus, a Greek who lived in Persia, smuggled a secret message to Sparta under the cover of wax. The main intent was to warn Sparta that Xerxes, king of Persia, was planning an invasion on Greece by using his great naval fleet. He knew it would be very difficult to send the message to Sparta without it being intercepted. Hence, he came up with the idea of using a wax tablet to hide the secret message. In order to hide the secret message, he removed all the wax from the tablet, leaving only the wood underneath. He then wrote the secret message into the wood and recovered the tablet with the wax. The wax covered his message to make the wax tablet look like a blank one. Demaratus’ message was hidden and never discovered by the Persians. Hence, the secret message was sent to Sparta successfully. Greece was able to defeat the invading Persians by using the secret message. Another example of information hiding was employed by another Greek named Histaiaeus. Histaiaeus wanted to instigate a revolt against the Persian king and had to deliver a secret message about the revolt to Persia. He came up with the shaved-head technique. Histaiaeus decided to shave the head of his most trusted slave and then tattooed the secret message on his bald scalp. When the hair grew back, the secret message was covered, and then Histaiaeus ordered the slave to leave for Persia. When the slave reached his destination, his head was shaved, showing the secret message to the intended recipient. Around 100 A.D., transparent inks made it into the secret field of information hiding. Pliny discovered that the milk of the thithymallus plant could easily be used as transparent ink. If a message was written with the milk, it would soon evaporate and left no residue. It seemed that the message was completely erased. But once the completely dried milk was heated, it would begin to char and turned to a brown color. Hence, the secret message could be written on anything that was not too flammable. The reason it turned brown was because the milk was loaded with carbon, and when carbon was heated, it tended to char. Information hiding became downfallen and won no respect until World Wars I and II. Invisible inks, such as milk, vinegar, fruit juices, and urine, were extensively used during the wars. All of them would darken when they were heated. The technology was quite simple and noticeable. Furthermore, World War II also brought about two inventions of new technologies. The first one was the invention of the microdot technology. The microdot technology was invented by the Germans to convey secret messages to their allies. The microdot was basically a highly detailed picture shrunk to about the size of a period or dot, which permitted hiding large amounts of data into the little microdot. By using a microscope, the hidden message would be revealed. The Germans would put their dots into their letters, and they were almost undetectable to the naked eye. The other technology was the use of open-coded messages. For open-coded messages, certain letters of each word were used to spell out the secret message. Open-coded messages used normal words and messages to write the buffer text that hid the message. Because they seemed normal, they often passed the check of security. For example, the following message was a common example of open-coded messages and was actually sent by a German spy during World War II. Apparently neutral’s protest is thoroughly discounted and ignored. Isman hard hit. Blockade issue affects pretext for embargo on by-products, ejecting suets and vegetable oils. By extracting the second letter in each word, the secret message was revealed: Pershing sails from NY June 1. This technique was effective because it could pass through the check of security and was easy for someone to decode (Johnson, Duric, & Jajodia, 2001; Katzenbeisser & Petitcolas, 2000; Schaefer, 2001). The technologies mentioned here are different ways of information hiding in different eras. With the development of computer technology, it is becoming hard for the third party to discover the secret message.
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Тези доповідей конференцій з теми "Parity check decoder"

1

Praveena, H., and K. Kalyani. "FPGA implementation of Parity Check Matrix based Low Density Parity Check Decoder." In 2018 2nd International Conference on Inventive Systems and Control (ICISC). IEEE, 2018. http://dx.doi.org/10.1109/icisc.2018.8398997.

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2

Ishikawa, Tatsuyuki, Kazunori Shimizu, Takeshi Ikenaga, and Satoshi Goto. "High-throughput decoder for low-density parity-check code." In the 2006 conference. New York, New York, USA: ACM Press, 2006. http://dx.doi.org/10.1145/1118299.1118332.

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3

Phillips, Braden J., Daniel R. Kelly, and Brian W. Ng. "Estimating adders for a low density parity check decoder." In SPIE Optics + Photonics, edited by Franklin T. Luk. SPIE, 2006. http://dx.doi.org/10.1117/12.680199.

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4

Tong, Jiajie, Huazi Zhang, Xianbin Wang, Shengchen Dai, Rong Li, and Jun Wang. "A Soft Cancellation Decoder for Parity-Check Polar Codes." In 2020 IEEE 31st Annual International Symposium on Personal, Indoor and Mobile Radio Communications. IEEE, 2020. http://dx.doi.org/10.1109/pimrc48278.2020.9217144.

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5

Alleyne, Damien, and Janak Sodha. "Pseudo-ARQ for a Low Density Parity Check Code Decoder." In Third IEEE International Conference on Wireless and Mobile Computing, Networking and Communications (WiMob 2007). IEEE, 2007. http://dx.doi.org/10.1109/wimob.2007.4390813.

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6

Petrovic, Vladimir L. "Flexible Encoder and Decoder of Low-Density Parity-Check Codes." In 2022 30th Telecommunications Forum (TELFOR). IEEE, 2022. http://dx.doi.org/10.1109/telfor56187.2022.9983744.

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7

Kanur, Sudeep, Georgios Georgakarakos, Antti Siirila, Jeremie Lagraviere, Kristian Nybom, Sebastien Lafond, and Johan Lilius. "Parallel decoder for low density parity check codes: A MPSoC study." In 2013 International Conference on High Performance Computing & Simulation (HPCS). IEEE, 2013. http://dx.doi.org/10.1109/hpcsim.2013.6641414.

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8

Zarubica, Radivoje, Stephen G. Wilson, and Eric Hall. "Multi-Gbps FPGA-Based Low Density Parity Check (LDPC) Decoder Design." In IEEE GLOBECOM 2007-2007 IEEE Global Telecommunications Conference. IEEE, 2007. http://dx.doi.org/10.1109/glocom.2007.108.

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9

Zarubica, Radivoje, and Stephen Wilson. "A Wiring-Efficient, High-Throughput Low Density Parity Check Decoder Design." In 2006 40th Annual Conference on Information Sciences and Systems. IEEE, 2006. http://dx.doi.org/10.1109/ciss.2006.286580.

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10

Choi, Eun-A., N. Kim, I. Lee, and J. Jung. "Optimal Structure of Decoder Design for Low Density Parity Check Codes." In 22nd AIAA International Communications Satellite Systems Conference & Exhibit 2004 (ICSSC). Reston, Virigina: American Institute of Aeronautics and Astronautics, 2004. http://dx.doi.org/10.2514/6.2004-3110.

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