Дисертації з теми "Ordinateurs – Mémoires – Informatique"
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Lalam, Mustapha. "Mémoire multiport série pour processeurs vectoriels." Toulouse 3, 1990. http://www.theses.fr/1990TOU30165.
Повний текст джерелаThiria, Sylvie. "L'Apprentissage supervisé dans les modèles connexionnistes." Paris 5, 1989. http://www.theses.fr/1989PA05S004.
Повний текст джерелаTourancheau, Bernard. "Algorithmique parallèle pour les machines à mémoire distribuée : application aux algorithmes matriciels." Grenoble INPG, 1989. http://tel.archives-ouvertes.fr/tel-00332663/.
Повний текст джерелаLefebvre, Vincent. "Restructuration automatique des variables d'un programme en vue de sa parallélisation." Versailles-St Quentin en Yvelines, 1998. http://www.theses.fr/1998VERS0008.
Повний текст джерелаAcquaviva, Jean-Thomas. "Architecture DSM et calcul scientifique : étude de la prédiction de la cohérence de données." Versailles-St Quentin en Yvelines, 2000. http://www.theses.fr/2000VERS0017.
Повний текст джерелаBernardi, Fabrice. "Conception de bibliothèques hiérarchisées de modèles réutilisables selon une approche orientée objet." Corte, 2002. http://www.theses.fr/2002CORT3068.
Повний текст джерелаLacroix, Patrice. "RTL-Check : a practical static analysis framework to verify memory safety and more." Thesis, Université Laval, 2006. http://www.theses.ulaval.ca/2006/23909/23909.pdf.
Повний текст джерелаSince computers are ubiquitous in our society and we depend more and more on programs to accomplish our everyday activities, bugs can sometimes have serious consequences. A large proportion of existing programs are written in C or C++ and the main source of errors with these programming languages is the absence of memory safety. Our long term goal is to be able to verify if a C or C++ program accesses memory correctly in spite of the deficiencies of these languages. To that end, we have created a static analysis framework which we present in this thesis. It allows building analyses from small reusable components that are automatically bound together by metaprogramming. It also incorporates the visitor design pattern and algorithms that are useful for the development of static analyses. Moreover, it provides an object model for RTL, the low-level intermediate representation for all languages supported by GCC. This implies that it is possible to design analyses that are independent of programming languages. We also describe the modules that comprise the static analysis we have developed using our framework and which aims to verify if a program is memory-safe. This analysis is not yet complete, but it is designed to be easily improved. Both our framework and our memory access analysis modules are distributed in RTL-Check, an open-source project.
Petri, Gustavo. "Operational semantics of relaxed memory models." Nice, 2010. http://www.theses.fr/2010NICE4087.
Повний текст джерелаMost current multiprocessor architectures and shared memory parallel programming languages are not sequentially consistent for parallel programs. Their possible behaviors are characterized by weak or relaxed memory models. A memory model describes the way in which parallel programs can interact by reading and writing the shared memory. Thus, a relaxed memory model exhibits more behaviors than sequential consistency (a “strong” memory model). The fact that most architectures have relaxed memory models has been known for decades, and yet few programmers understand which are the exact behaviors a parallel program can have in such architectures. We argue in this thesis that the problem stems from the difficulty in understanding the specification of these relaxed memory models. Firstly because few architectures or programming languages provide a formal definition of their memory model. And secondly because the majority of the existing formal definitions are axiomatic, which hinders their understandability and makes them unsuitable for language-based techniques such as static analysis or model checking. We propose an alternative characterization of relaxed memory models. Our characterization is operational, which we believe makes it simpler to understand for the programmer, and better suited to standard language-based techniques. Our first contribution in this thesis is the operational formalization of writebuffering architectures. Write-buffering is pervasive across multi-core architectures, and thus its understanding is fundamental for parallel programming in such architectures. By means of standard programming languages concepts, we prove that the standard DRF guarantee is satisfied by our formalization. Hence, reasoning about sequentially consistent computations is sound for programs free of simultaneous accesses on a single memory location. Our second contribution is a framework for the operational characterization of speculative computation techniques. This framework allows us to formally define the intuitive notion of valid speculation. For this framework two languages are considered; a high-level programming language that supports locks; and a low-level programming language, closer to the Instruction Set Architecture (ISA) of a machine, that only supports barriers and a simple compare-and-swap instruction. We identify properties for programs of both of these languages that are sufficient to guarantee that only sequentially consistent behaviors can be observed when the programs are executed speculatively. The final contribution is the instantiation of the write-buffering and speculative frameworks to formalize the TSO, PSO and RMO memory models of the Sparc architecture. In particular, we observe that the framework of write buffers is not well suited to formalize liberal relaxations as allowed by RMO. We prove a correspondence result between the formalizations of PSO and TSO I ii in both frameworks. The fact that RMO cannot be instantiated by means of write-buffers is a good indication that the speculative framework is more general than the one of write buffers
Barral, Pierre. "Un modèle neuro-mimétique de mémoire associative." Limoges, 1997. http://www.theses.fr/1997LIMO0029.
Повний текст джерелаHammami, Omar. "Anticipation et gestion mémoire." Toulouse 3, 1992. http://www.theses.fr/1992TOU30159.
Повний текст джерелаYin, Shaoyi. "Un modèle de stockage et d'indexation pour des données embarquées en mémoire flash." Versailles-St Quentin en Yvelines, 2011. http://www.theses.fr/2011VERS0008.
Повний текст джерелаNAND Flash has become the most popular stable storage medium for embedded systems. Efficient storage and indexing techniques are very challenging to design due to a combination of NAND Flash constraints and embedded system constraints. In this thesis, we propose a new model relying on two basic principles: database serialization and database stratification. An indexing technique called PBFilter is presented to illustrate these principles. Analytical and experimental results show that the new approach meets very well the embedded system requirements. The PBFilter technique has been integrated into a complete embedded DBMS engine PlugDB. PlugDB is used in a real-life application implementing a secure and portable medico-social folder. PlugDB can be also seen as a central building block for a global vision named Personal Data Server, whose objective is to manage personal information in a secure, privacy-preserving and user-controlled way
Pham, Tuong Hai. "Techniques matérielles d'accélération des accès mémoire dans les processeurs superscalaires." Toulouse 3, 1997. http://www.theses.fr/1997TOU30182.
Повний текст джерелаClere, Pascal. "Etude de l'architecture du processeur d'une machine pour les applications temps réel en intelligence artificielle : maia." Paris 11, 1989. http://www.theses.fr/1989PA112179.
Повний текст джерелаMAIA is a joint project between the Centre National d'Etudes des Télécommunications (CNET) at LANNION and the Compagnie Générale d'Electricité at Laboratoires de Marcoussis. MAIA is both a workstation for software development and for executing applications which need powerful syrnbolic computation and real-time supports. As far many specialized workstations, MAlAis a language-machine, both Lisp-machine and Prelog-machine, with microprogrammed support for list manipulation and memory management, hardware for dynarnic data types checking, collecter assist and Lisp stack heads. The software is made of an integrated environment based on Lisp. It includes a Lisp compiler and interpreter as well as a Prolog compiler and interpreter. The kernel system includes real-time multi-processing based on SCEPTRE, garbage-collection based on the MOON's algorithm and virtual memory management
Chu, Chengbin. "Nouvelles approches analytiques et concept de mémoire artificielle pour divers problèmes d'ordonnancement." Metz, 1990. http://docnum.univ-lorraine.fr/public/UPV-M/Theses/1990/Chu.Chengbin.SMZ9021.pdf.
Повний текст джерелаVet, Jean-Yves. "Parallélisme de tâches et localité de données dans un contexte multi-modèle de programmation pour supercalculateurs hiérarchiques et hétérogènes." Paris 6, 2013. http://www.theses.fr/2013PA066483.
Повний текст джерелаThis thesis makes several distinct contributions which rely on a dedicated task-based programming model. The novelty of this model resides in a dynamic adjustment of the quantity of embedded operations depending on the targeted processing unit. It is particularly well adapted to dynamically balance workloads between heterogeneous processing units. It better harnesses those units by strengthening responsiveness in the presence of execution times fluctuations induced by irregular codes or unpredictable hardware mechanisms. Moreover, the semantics and programming interface of the task-parallel model facilitates the use of automated behaviors such as data coherency of deported memories. It alleviates the burden of developers by taking care of this tedious work and which can be a source of errors. We developed H3LMS an execution platform designed to combine the propositions detailed in the thesis. The platform is integrated to the MPC programming environment in order to enhance cohabitation with other programming models and thus better harness clusters. H3LMS is elaborated to improve task scheduling between homogeneous and heterogeneous processing units by reducing the need to resort to distant accesses in a cluster node. This thesis also focuses on the adaptation of legacy codes which are originally designed to exploit traditional processors and may also consist of hundreds of thousand lines of code. The performance of this solution is evaluated on the Linpack library and on a legacy numerical application from the CEA
L'Excellent, Jean-Yves. "Utilisation de préconditionneurs élément-par-élément pour la résolution de problèmes d'optimisation de grande taille." Toulouse, INPT, 1995. http://www.theses.fr/1995INPT091H.
Повний текст джерелаPetit, Éric. "Vers un partitionnement automatique d'applications en codelets spéculatifs pour les systèmes hétérogènes à mémoires distribuées." Rennes 1, 2009. http://www.theses.fr/2009REN1S087.
Повний текст джерелаIn light of the increase of development cost, power consumption and silicon area for new single-core architecture optimisations, the new way for performance improvements leads to multicore architecture, with parallel programming and specialised coprocessors. They give the best trade-off between high computing performance and required resources. In order to efficiently address this new kind of architecture, applications have to be split into tasks, also called codelets, which will be mapped onto the different computing units of the host system. The purpose of this thesis is to propose an automatic and efficient model to generate speculative codelets from applications. Speculation allows the compiler to handle a number of optimisations which would have been impossible or unavailable without speculative data. My second contribution deals with the data transfer optimisation between the processor and the coprocessor by using speculation
Ben, Fradj Hanene. "Optimisation de l'énergie dans une architecture mémoire multi-bancs pour des applications multi-tâches temps réel." Phd thesis, Université de Nice Sophia-Antipolis, 2006. http://tel.archives-ouvertes.fr/tel-00192473.
Повний текст джерелаKiefer, Renaud. "Etude et conception d'un système de stockage et d'adressage photonique de données." Université Louis Pasteur (Strasbourg) (1971-2008), 2002. http://www.theses.fr/2002STR13199.
Повний текст джерелаThe increase in the speed of microprocessors, the evolution of multimedia and of the Internet has created a growing need of data storage solutions. Encouraged by the rapid technological progress over the past decade, this need has grown exponentially. Even if DVD technology satisfies the present data storage demand (about 10 bit/æmø), certain new applications such as 3D imaging and huge data bases need the development of new technology. The objective of this thesis has been to study and conceive a data storage and addressing system based on holographic memories. This kind of memory shows interesting possibilities for massive volume data storage (about 100 bit/æm3). The system allows a rapid access time (ms), on a large angular bandwidth, at any informations stored on the diffractive memory. Analysis of optical memories based on dichromated gelatin has allowed the determination of their domain of use and set the constrains of the addressing system. The originality of the work has been to associate MEMS (integrated micro mirrors) and an acousto-optic cell. We have measured the deformation of the MEMS to evaluate the influence on the reading of the information stored in diffractive memories. Experimental results show the possibility of obtaining an address rate of 100Gbits/s. The reading system limitations are due to the low oscillating frequency of the MEMS and principally to the low acquisition rate of the CCD camera. The use of high speed cameras will allow to increase the readout rate
Burgod, Céline. "Contribution à la sécurisation du routage dans les réseaux ad hoc." Limoges, 2009. https://aurore.unilim.fr/theses/nxfile/default/e252c1c0-3541-48df-85fd-a4e7e7d12206/blobholder:0/2009LIMO4046.pdf.
Повний текст джерелаIn the scope of this thesis, we have focused on the security of the routing functions. Our approach consists on one hand in preventing attacks against the control messages, and on the other hand in providing a reliable support for the detection of malicious behaviors. To mitigate the limits of the existing approaches, we study the use of a tamper resistant hardware. We describe a control scheme, located between the data link layer and the network layer, allowing to accurately detect and locate corrupted entities with regards to the elementary operations required by any routing protocols. In the second part of this work, we propose a systematic security analysis for the OLSR (Optimized Link State Routing) routing protocol. Within our framework, we describe : (1) the various elements which define the OLSR protocol, (2) the possible attacks in the form of elementary illegal actions, then (3) the causal relationships between various illegal actions and the extent of disruptions. This representation allows to build a substantial reference base from which it is possible to compare several reinforced versions of OLSR
Spir, Eric. "Etude et implantation d'un glaneur de cellules adaptatif pour LISP." Paris 7, 1989. http://www.theses.fr/1989PA077117.
Повний текст джерелаLalanne, Philippe. "Les réseaux de neurones formels et leurs réalisations optoélectroniques : génération optique de tableaux de nombres aléatoires." Paris 11, 1989. http://www.theses.fr/1989PA112240.
Повний текст джерелаTwo purposes concerning the field of neural networks research are investigated in this thesis. First, we study optical implementation of neural networks. We show that higher order models, i. E. Multineuron synapsis models, allow us to increase strongly the network capacity with respect to the number of stable stored states. Optical implementations of such models necessary suppose both optical interconnects and boolean logic gates built into matrices. We propose a general approach for these implementations. In our hybrid architecture, the strength of optics, linear transformation for massive interconnects and the strength of electronics, point nonlinearities are both used to advantage. In the second part, we use speckle as a fast binary random number arrays generator. A theoretical approach and experimental evidences show that this kind of random generator may be of interest for optoelectronic implementation of parallel stochastic algorithms
Margery, David. "Environnement logiciel temps-réel distribué pour la simulation sur réseau de PC." Rennes 1, 2001. http://www.theses.fr/2001REN10132.
Повний текст джерелаCourbot, Alexandre. "Spécialisation tardive de systèmes Java embarqués pour petits objets portables et sécurisés." Phd thesis, Université des Sciences et Technologie de Lille - Lille I, 2006. http://tel.archives-ouvertes.fr/tel-00113765.
Повний текст джерелаBonet, Zordan Leonardo Henrique. "Test de mémoires SRAM à faible consommation." Thesis, Montpellier 2, 2013. http://www.theses.fr/2013MON20080.
Повний текст джерелаNowadays, embedded memories are the densest components within System-On-Chips (SOCs), accounting for more than 90% of the overall SOC area. Among different types of memories, SRAMs are still widely used for realizing complex SOCs, especially because they allow high access performance, high density and fast integration in CMOS designs. On the other hand, high density SRAMs designed with deep-submicrometer technologies have become the main contributor to the overall SOC power consumption. Hence, there is an increasing need to design low-power SRAMs, which embed mechanisms to reduce their power consumption. Moreover, due to their dense structure, SRAMs are more are more prone to defects compared to other circuit blocks, especially in recent technologies. Hence, SRAMs are arising as the main SOC yield detractor, which raises the need to develop efficient test solutions targeting such devices.In this thesis, failure analysis based on electrical simulations has been exploited to predict faulty behaviors caused by realistic defects affecting circuit blocks that are specific to low-power SRAMs, such as power gating mechanisms and voltage regulation systems. Based on identified faulty behaviors, efficient March tests and low area overhead design for testability schemes have been proposed to detect studied defects. Moreover, the reuse of read and write assist circuits, which are commonly embedded in low-power SRAMs, has been evaluated as an alternative to increase stress in the SRAM during test phase and then improve the defect coverage
Godard, Benoît. "Techniques de conception en vue d'améliorer la fiabilité des mémoires Flash embarquées." Montpellier 2, 2008. http://www.theses.fr/2008MON20080.
Повний текст джерелаFlash memories are non-volatile memories present in a growing number of integrated circuits used in portable electronic devices. The non-volatility, low power consumption and flexibility make them extremely popular. Nevertheless, the reliability is currently a major issue and a characteristic that must be improved. Effectives fault tolerance solutions that are low cost and that can be easily integrated must be found. First, this work was the occasion to establish a reliability model for a floating gate cell depending on various parameters. Secondly, two fault tolerance techniques merging error correcting codes and redundancy were developped. For each case, a mathematical study and a reliability architecture have been proposed. Developped techniques allow significant improvements of the memory reliability at very low cost. They constitute efficient alternative solutions to standard scheme usually used in the industy
Carver, Damien. "Advanced consolidation for dynamic containers." Electronic Thesis or Diss., Sorbonne université, 2019. http://www.theses.fr/2019SORUS513.
Повний текст джерелаThe virtualization of computing resources has given rise to cloud computing. More recently, container-based lightweight virtualization has become increasingly popular. Containers offer performance isolation comparable to that of virtual machines, but promise better resource consolidation due to their flexibility. In this thesis we highlight performance isolation losses assumed to be guaranteed to an active container. These losses occur during consolidation, i.e. when the unused memory of an inactive container is transferred to a new container that starts. However, in a non-virtualized environment, this memory consolidation scenario does not result in a drop in performance among the most active processes. We therefore propose, as a first step, to measure the memory activity of containers using state-of-the-art metrics. Then, to ensure the isolation of the most active containers during memory consolidations, we modify the behavior of the Linux kernel in order to reclaim the memory of the containers defined as being the most inactive by the metric. In a second step, we propose another method for estimating the memory activity of containers based on a global clock of memory events. This method is more reactive than the previous one because it seeks to protect containers with the most recent memory activity
Wakrim, Tariq. "Commutation de capacitance dans les mémoires résistives (ReRAM), application aux mémoires d’impédance (ZRAM ou mem-capacitors)." Thesis, Université Grenoble Alpes (ComUE), 2018. http://www.theses.fr/2018GREAT085/document.
Повний текст джерелаResistive random access memories (ReRAM) hold great potential for replacing Flash memories. A ReRAM memory (or MEMRISTOR) uses a resistive switching phenomenon found in Metal-Insulator-Metal (MIM) structures under a voltage stress. Most researches were focused on the mechanisms governing the resistance switching in ReRAM devices and less attention has been paid to capacitance variation of MIM structures under a voltage stress. Our work is focused on that latter phenomenon. We study impedance variation (conductance and capacitance in the RF domain) in HfO2-based MIM structures. Above a threshold voltage (Set), concurrently to conductance increase, a decrease in the capacitance value is observed. Reproducible capacitance-voltage (C-V) and conductance-voltage (G-V) memory cycles are obtained. Frequency dependent characterizations (C-f and G-f), under different DC bias voltages, are performed with the aim of understanding the mechanisms of impedance switching. The capacitance decrease observed in the conducting (ON) state is attributed to the inductance of the filament created during the Set stage. Transport phenomena responsible for the filament inductive behavior are discussed. Impact of HfO2 deposition process (ALD), as well as the use of bi-layer structures, on C-V and G-V characteristics are shown. This work paves the way for the realization of new capacitance memory devices (mem-capacitors) and most generally for impedance memories (ZRAM). Potential of these devices to design reconfigurable filters (controlled by voltage bias) is demonstrated in a practical way
Cargnini, Luís Vitório. "Applications des technologies mémoires MRAM appliquées aux processeurs embarqués." Thesis, Montpellier 2, 2013. http://www.theses.fr/2013MON20091/document.
Повний текст джерелаThe Semiconductors Industry with the advent of submicronic manufacturing flows below 45 nm began to face new challenges to keep evolving according with the Moore's Law. Regarding the widespread adoption of embedded systems one major constraint became power consumption of IC. Also, memory technologies like the current standard of integrated memory technology for memory hierarchy, the SRAM, or the FLASH for non-volatile storage have extreme intricate constraints to be able to yield memory arrays at technological nodes below 45nm. One important is up until now Non-Volatile Memory weren't adopted into the memory hierarchy, due to its density and like flash the necessity of multi-voltage operation. These theses has by objective work into these constraints and provide some answers. Into the thesis will be presented methods and results extracted from this methods to corroborate our goal of delineate a roadmap to adopt a new memory technology, non-volatile, low-power, low-leakage, SEU/MEU-resistant, scalable and with similar performance as the current SRAM, physically equivalent to SRAM, or even better with a area density between 4 to 8 times the area of a SRAM cell, without the necessity of multi-voltage domain like FLASH. This memory is the MRAM (Magnetic Memory), according with the ITRS one candidate to replace SRAM in the near future. MRAM instead of storing charge, they store the magnetic orientation provided by the spin-torque orientation of the free-layer alloy in the MTJ (Magnetic Tunnel Junction). Spin is a quantical state of matter, that in some metallic materials can have it orientation or its torque switched applying a polarized current in the sense of the field orientation desired. Once the magnetic field orientation is set, using a sense amplifier, and a current flow through the MTJ, the memory cell element of MRAM, it is possible to measure the orientation given the resistance variation, higher the resistance lower the passing current, the sense will identify a logic zero, lower the resistance the SA will sense a one logic. So the information is not a charge stored, instead it is a magnetic field orientation, reason why it is not affected by SEU or MEU caused due to high energy particles. Also it is not due to voltages variations to change the memory cell content, trapping charges in a floating gate. Regarding the MRAM, this thesis has by objective address the following aspects: MRAM applied to memory Hierarchy: - By describing the current state of the art in MRAM design and use into memory hierarchy; - by providing an overview of a mechanism to mitigate the latency of writing into MRAM at the cache level (Principle to composite memory bank); - By analyzing power characteristics of a system based on MRAM on CACHE L1 and L2, using a dedicated evaluation flow- by proposing a methodology to infer a system power consumption, and performances.- and for last based into the memory banks analysing a Composite Memory Bank, a simple description on how to generate a memory bank, with some compromise in power, but equivalent latency to the SRAM, that keeps similar performance
Torres, Lucio Domingo. "Elaboration et validation de LAPMAM : processeur parallèle SIMD/MIMD dédié au traitement bas et moyen niveau d'images." Nancy 1, 1999. http://www.theses.fr/1999NAN10293.
Повний текст джерелаCogniaux, Geoffroy. "Exécution d'applications stockées dans la mémoire non-adressable d'une carte à puce." Phd thesis, Université des Sciences et Technologie de Lille - Lille I, 2012. http://tel.archives-ouvertes.fr/tel-00855002.
Повний текст джерелаBartoli, Jonathan. "Développement et caractérisation d'architectures mémoires non volatiles pour des applications basse consommation." Thesis, Aix-Marseille, 2015. http://www.theses.fr/2015AIXM4373.
Повний текст джерелаWith the evolution of technologies and the development of connected objects, the circuit consumption is becoming an important subject. In this thesis, we focus on the consumption of trap-charge non-volatile memories. To decrease the consumption, different architectures have emerged, like 2T or Split Gate memories. We propose two new memory architectures allowing to decrease the consumption compared to the standard Flash memory. The first, called ATW (Asymmetrical Tunnel Window), is composed of an oxide step in the tunnel oxide which allows to be less consumer than a standard Flash memory. A second memory architecture called eSTM (embedded Select Trench Memory) is also presented. Its main advantage is its select transistor which is essential to obtain a lower consumption. Thanks to its architecture, this cell is better than the previously proposed architecture (ATW). The last study has been performed to optimize the process flow of the eSTM memory to make it more robust
Roman-Alonso, Graciela. "Contribution à l'étude du placement dynamique sur machines parallèles de type MIMD." Phd thesis, Université de Technologie de Compiègne, 1997. http://tel.archives-ouvertes.fr/tel-00944934.
Повний текст джерелаDulong, Rémi. "Towards new memory paradigms : Integrating non-volatile main memory and remote direct memory access in modern systems." Electronic Thesis or Diss., Institut polytechnique de Paris, 2023. http://www.theses.fr/2023IPPAS027.
Повний текст джерелаModern computers are built around two main parts: their Central Processing Unit (CPU), and their volatile main memory, or Random Access Memory (RAM). The basis of this architecture takes its roots in the 1970's first computers. Since, this principle has been constantly upgraded to provide more functionnality and performance.In this thesis, we study two memory paradigms that drastically change the way we can interact with memory in modern systems: non-volatile memory and remote memory access. We implement software tools that leverage them in order to make them compatible and exploit their performance with concrete applications. We also analyze the impact of the technologies underlying these new memory medium, and the perspectives of their evolution in the coming years.For non-volatile memory, as the main memory performance is key to unlock the full potential of a CPU, this feature has historically been abandoned on the race for performance. Even if the first computers were designed with non-volatile forms of memory, computer architects started to use volatile RAM for its incomparable performance compared to durable storage, and never questioned this decision for years. However, in 2019 Intel released a new component called Optane DC Persistent Memory (DCPMM), a device that made possible the use of Non-Volatile Main Memory (NVMM). That product, by its capabilities, provides a new way of thinking about data persistence. Yet, it also challenges the hardware architecture used in our current machines and the way we program them.With this new form of memory we implemented NVCACHE, a cache designed for non-volatile memory that helps boosting the interactions with slower persistent storage medias, such as solid state drive (SSD). We find NVCACHE to be quite performant for workloads that require a high granularity of persistence guarantees, while being as easy to use as the traditional POSIX interface. Compared to file systems designed for NVMM, NVCACHE can reach similar or higher throughput when the non-volatile memory is used. In addition, NVCACHE allows the code to exploit NVMM performance while not being limited by the amount of NVMM installed in the machine.Another major change of in the computer landscape has been the popularity of distributed systems. As individual machines tend to reach performance limitations, using several machines and sharing workloads became the new way to build powerful computers. While this mode of computation allows the software to scale up the number of CPUs used simultaneously, it requires fast interconnection between the computing nodes. For that reason, several communication protocols implemented Remote Direct Memory Access (RDMA), a way to read or write directly into a distant machine's memory. RDMA provides low latencies and high throughput, bypassing many steps of the traditional network stack.However, RDMA remains limited in its native features. For instance, there is no advanced multicast equivalent for the most efficient RDMA functions. Thanks to a programmable switch (the Intel Tofino), we implemented a special mode for RDMA that allows a client to read or write in multiple servers at the same time, with no performance penalty. Our system called Byp4ss makes the switch participate in transfers, duplicating RDMA packets. On top of Byp4ss, we implement a consensus protocol named DISMU, which shows the typical use of Byp4ss features and its impact on performance. By design, DISMU is optimal in terms of latency and throughput, as it can reduce to the minimum the number of packets exchanged through the network to reach a consensus.Finally, by using these two technologies, we notice that future generations of hardware may require a new interface for memories of all kinds, in order to ease the interoperability in systems that tend to get more and more heterogeneous and complex
Claisse, Harry. "Structures chainées et environnement paginé." Compiègne, 1987. http://www.theses.fr/1987COMPI270.
Повний текст джерелаThis thesis discusses problems related to pointer data structures. The first part is concerned with results of design decisions that can influence execution efficiency in a paged LISP environment. The main problem can be summarized as a continuing search to reduce the number of page faults. Measurements are used to distinguish crucial points such as structure of core memory, working set sizes and garbage collection. We study several storage implementations of symbols (strings of characters identifying each entities) and we evaluate their performances. The conclusions are applied directly to query data base a used at UTC
Postel-Pellerin, Jérémy. "Fiabilité des Mémoires Non-Volatiles de type Flash en architectures NOR et NAND." Phd thesis, Université de Provence - Aix-Marseille I, 2008. http://tel.archives-ouvertes.fr/tel-00370377.
Повний текст джерелаOnkaraiah, Santhosh. "Modélisation et conception de circuits à base de mémoires non-volatiles résistives innovantes." Thesis, Aix-Marseille, 2013. http://www.theses.fr/2013AIXM4759.
Повний текст джерелаThe grave challenges to future of traditional memories (flash and DRAM) at 1X nm regime has resulted in increased quest for new physical state variables (other than charge or voltage), new devices and architectures offering memory and logic functions beyond traditional transistors. Many thin film devices with resistance change phenomena have been extensively reported as ’promising candidates’. Among them, Ox- ide Resistive Memory (OxRRAM) and Conductive Bridge Resistive Memory (CBRAM) are leading contenders for the next generation high density memories. In this work, we focus on the role of Resistive Memories in embedded memories and their impact on FPGAs in particular. We begin with the discussion on the compact modeling of resistive memory devices for design enabling, we have designed novel circuits of non- volatile flip-flop (NVFF), non-volatile look-up table (NVLUT), non-volatile 2x2 switch and non-volatile SRAM (NVSRAM) using Resistive Memories. We simulated the impact of these design structures on the FPGA system assessing the performance parameters of area, delay and power. By using the novel 1T-2R memory element concept of CBRAMs in FPGAs to implement Look-up Tables (NVLUT), we would scale down the area impact by 5%, enhance speed by 24% and reduce the power by 18% compared to SRAM based FPGAs. The thesis addresses aspects of compact modeling, circuit design and system evaluation using resistive memories
Le, Sergent Thierry. "Méthodes d'exécution et machines virtuelles parallèles pour l'implantation distribuée du langage de programmation parallèle LCS." Toulouse 3, 1993. http://www.theses.fr/1993TOU30021.
Повний текст джерелаBresch, Cyril. "Approches, Stratégies, et Implémentations de Protections Mémoire dans les Systèmes Embarqués Critiques et Contraints." Thesis, Université Grenoble Alpes, 2020. http://www.theses.fr/2020GRALT043.
Повний текст джерелаThis thesis deals with the memory safety issue in life-critical medical devices. Over the last few years, several vulnerabilities such as memory exploits have been identified in various Internet of Medical Things (IoMT) devices. In the worst case, such vulnerabilities allow an attacker to remotely force an application to execute malicious actions. While many countermeasures against software exploits have beenproposed so far, only a few of them seem to be suitable for medical devices. Indeed,these devices are constrained by their size, real-time performances, and safety requirements making the integration of security challenging. To address this issue,the thesis proposes two approaches. Both address the memory safety issue fromthe software design-time to its run-time on the hardware. A first approach assumesthat memory defenses can be implemented both in hardware and software. Thisapproach results in TrustFlow, a framework composed of a compiler able to generatesecure code for an extended processor that can prevent, detect, log, andself-heal critical applications from memory attacks. The second approach considersthat hardware is immutable. Following this constraint, defenses only rely uponsoftware. This second approach results in BackGuard a modified compiler that efficiently hardens embedded applications while ensuring control-flow integrity
Mugwaneza, Léon. "Contrôle des communications dans les machines parallèles à mémoire distribuée : contribution au routage automatique des messages." Grenoble INPG, 1993. http://tel.archives-ouvertes.fr/tel-00005138.
Повний текст джерелаMartinez, Peck Mariano. "Application-Level Virtual Memory for Object-Oriented Systems." Phd thesis, Université des Sciences et Technologie de Lille - Lille I, 2012. http://tel.archives-ouvertes.fr/tel-00764991.
Повний текст джерелаSalihoglu, Utku. "Toward a brain-like memory with recurrent neural networks." Doctoral thesis, Universite Libre de Bruxelles, 2009. http://hdl.handle.net/2013/ULB-DIPOT:oai:dipot.ulb.ac.be:2013/210221.
Повний текст джерела
Based on these assumptions, this thesis provides a computer model of neural network simulation of a brain-like memory. It first shows experimentally that the more information is to be stored in robust cyclic attractors, the more chaos appears as a regime in the background, erratically itinerating among brief appearances of these attractors. Chaos does not appear to be the cause, but the consequence of the learning. However, it appears as an helpful consequence that widens the network’s encoding capacity. To learn the information to be stored, two supervised iterative Hebbian learning algorithm are proposed. One leaves the semantics of the attractors to be associated with the feeding data unprescribed, while the other defines it a priori. Both algorithms show good results, even though the first one is more robust and has a greater storing capacity. Using these promising results, a biologically plausible alternative to these algorithms is proposed using cell assemblies as substrate for information. Even though this is not new, the mechanisms underlying their formation are poorly understood and, so far, there are no biologically plausible algorithms that can explain how external stimuli can be online stored in cell assemblies. This thesis provide such a solution combining a fast Hebbian/anti-Hebbian learning of the network's recurrent connections for the creation of new cell assemblies, and a slower feedback signal which stabilizes the cell assemblies by learning the feed forward input connections. This last mechanism is inspired by the retroaxonal hypothesis.
Doctorat en Sciences
info:eu-repo/semantics/nonPublished
Guitarra, Silvana Raquel. "Modélisation multi-échelles des mémoires de type résistives (ReRAM)." Thesis, Aix-Marseille, 2018. http://www.theses.fr/2018AIXM0537/document.
Повний текст джерелаA model for the switching of resistive random-access memories (ReRAM) is presented. This model is based on two hypotheses: (1) the resistive switching is caused by changes that occur in the narrow zone (active region) of the conductive filament under the influence of the electric field and (2) the resistive switching is a stochastic process governed by a switching probability. The active region is represented by a net of vertical connections, each one composed of three electrical elements: two of them are always low resistive (LR) while the third one acts as a breaker and can be low or high resistive (HR). In the model, the change of the breaker's state is governed by a switching probability (P$_{s}$) that is compared with a random number $p$. P$_{s}$ depend on the voltage drop along the breaker and the threshold voltage, V$_{set}$ or V$_{reset}$ for set (HR to LR) or reset (LR to HR) processes. Two conduction mechanism has been proposed: ohmic for the low resistive state and trap-assisted tunneling (TAT) for the high resistive state. The model has been implemented in Python and works with an external C-library that optimizes calculations and processing time. The simulation results have been successfully validated by comparing measured and modeled IV curves of HfO$_{2}$-based ReRAM devices of nine different areas. It is important to note that the flexibility and easy implementation of this resistive switching model allow it to be a powerful tool for the design and study of ReRAM memories
Hsu, Lung-Cheng. "Pbase : une base de données déductive en Prolog." Compiègne, 1988. http://www.theses.fr/1988COMPD126.
Повний текст джерелаThis thesis describes a relational database system coupling PROLOG II and VAX RMS (Record Management Services). The SQL-like DDL (Data Definition Language) and DML (Data Manipulation Language) are implemented in PROLOG and the management of storage and research of fact record is delegated to RMS. The indexed file organization is adopted to provide a satisfactory response time. An interface written in PASCAL is called to enable the communication between PROLOG and RMS. Once the interface is established, access to the database is transparent. No precompilation is requiert. PBASE can be used as a general DBMS or it can cooperate with an expert system (Our SQL translation module can be considered as such) to manage the voluminous facts stored in the secondary memory. It can also cooperate with VAX RDB (Relational DataBase) to constitute a powerful deductive database. Although PBASE works for normalized relations as well as non-normalized ones, a normalization module is included to avoid the problems caused by the redundancy of data
Ezzadeen, Mona. "Conception d'un circuit dédié au calcul dans la mémoire à base de technologie 3D innovante." Electronic Thesis or Diss., Aix-Marseille, 2022. http://theses.univ-amu.fr.lama.univ-amu.fr/221212_EZZADEEN_955e754k888gvxorp699jljcho_TH.pdf.
Повний текст джерелаWith the advent of edge devices and artificial intelligence, the data deluge is a reality, making energy-efficient computing systems a must-have. Unfortunately, classical von Neumann architectures suffer from the high cost of data transfers between memories and processing units. At the same time, CMOS scaling seems more and more challenging and costly to afford, limiting the chips' performance due to power consumption issues.In this context, bringing the computation directly inside or near memories (I/NMC) seems an appealing solution. However, data-centric applications require an important amount of non-volatile storage, and modern Flash memories suffer from scaling issues and are not very suited for I/NMC. On the other hand, emerging memory technologies such as ReRAM present very appealing memory performances, good scalability, and interesting I/NMC features. However, they suffer from variability issues and from a degraded density integration if an access transistor per bitcell (1T1R) is used to limit the sneak-path currents. This thesis work aims to overcome these two challenges. First, the variability impact on read and I/NMC operations is assessed and new robust and low-overhead ReRAM-based boolean operations are proposed. In the context of neural networks, new ReRAM-based neuromorphic accelerators are developed and characterized, with an emphasis on good robustness against variability, good parallelism, and high energy efficiency. Second, to resolve the density integration issues, an ultra-dense 3D 1T1R ReRAM-based Cube and its architecture are proposed, which can be used as a 3D NOR memory as well as a low overhead and energy-efficient I/NMC accelerator
Nesvadba, Jan. "Segmentation sémantique des contenus audio-visuels." Bordeaux 1, 2007. http://www.theses.fr/2007BOR13456.
Повний текст джерелаNovembre, Christophe. "Architectures des systèmes de l'information adaptées aux technologies nanométriques et/ou moléculaires : développement d'un composant moléculaire neuromorphique." Lille 1, 2007. https://pepite-depot.univ-lille.fr/LIBRE/Th_Num/2007/50376-2007-Novembre.pdf.
Повний текст джерелаTeste, Olivier. "Modélisation et manipulation d'entrepôts de données complexes et historisées." Phd thesis, Université Paul Sabatier - Toulouse III, 2000. http://tel.archives-ouvertes.fr/tel-00088986.
Повний текст джерелаAu niveau de l'entrepôt, nous définissons un modèle de données permettant de décrire l'évolution temporelle des objets complexes. Dans notre proposition, l'objet entrepôt intègre des états courants, passés et archivés modélisant les données décisionnelles et leurs évolutions. L'extension du concept d'objet engendre une extension du concept de classe. Cette extension est composée de filtres (temporels et d'archives) pour construire les états passés et archivés ainsi que d'une fonction de construction modélisant le processus d'extraction (origine source). Nous introduisons également le concept d'environnement qui définit des parties temporelles cohérentes de tailles adaptées aux exigences des décideurs. La manipulation des données est une extension des algèbres objet prenant en compte les caractéristiques du modèle de représentation de l'entrepôt. L'extension se situe au niveau des opérateurs temporels et des opérateurs de manipulation des ensembles d'états.
Au niveau des magasins, nous définissons un modèle de données multidimensionnelles permettant de représenter l'information en une constellation de faits ainsi que de dimensions munies de hiérarchies multiples. La manipulation des données s'appuie sur une algèbre englobant l'ensemble des opérations multidimensionnelles et offrant des opérations spécifiques à notre modèle. Nous proposons une démarche d'élaboration des magasins à partir de l'entrepôt.
Pour valider nos propositions, nous présentons le logiciel GEDOOH (Générateur d'Entrepôts de Données Orientées Objet et Historisées) d'aide à la conception et à la création des entrepôts dans le cadre de l'application médicale REANIMATIC.
Decouchant, Dominique. "Partage et migration de l'information dans un système réparti à objets." Phd thesis, Grenoble 1, 1987. http://tel.archives-ouvertes.fr/tel-00324431.
Повний текст джерелаNono, Wouafo Hugues Gérald. "Architectures matérielles numériques intégrées et réseaux de neurones à codage parcimonieux." Thesis, Lorient, 2016. http://www.theses.fr/2016LORIS394/document.
Повний текст джерелаNowadays, artificial neural networks are widely used in many applications such as image and signal processing. Recently, a new model of neural network was proposed to design associative memories, the GBNN (Gripon-Berrou Neural Network). This model offers a storage capacity exceeding those of Hopfield networks when the information to be stored has a uniform distribution. Methods improving performance for non-uniform distributions and hardware architectures implementing the GBNN networks were proposed. However, on one hand, these solutions are very expensive in terms of hardware resources and on the other hand, the proposed architectures can only implement fixed size networks and are not scalable. The objectives of this thesis are: (1) to design GBNN inspired models outperforming the state of the art, (2) to propose architectures cheaper than existing solutions and (3) to design a generic architecture implementing the proposed models and able to handle various sizes of networks. The results of these works are exposed in several parts. Initially, the concept of clone based neural networks and its variants are presented. These networks offer better performance than the state of the art for the same memory cost when a non-uniform distribution of the information to be stored is considered. The hardware architecture optimizations are then introduced to significantly reduce the cost in terms of resources. Finally, a generic scalable architecture able to handle various sizes of networks is proposed