Увійти

Готові списки джерел за темами / On-Wafer characterization / Статті в журналах

Статті в журналах з теми "On-Wafer characterization"

Щоб переглянути інші типи публікацій з цієї теми, перейдіть за посиланням: On-Wafer characterization.

Автор: Grafiati

Опубліковано: 7 липня 2024

Оформте джерело за APA, MLA, Chicago, Harvard та іншими стилями

Оберіть тип джерела:

Ознайомтеся з топ-50 статей у журналах для дослідження на тему "On-Wafer characterization".

Біля кожної праці в переліку літератури доступна кнопка «Додати до бібліографії». Скористайтеся нею – і ми автоматично оформимо бібліографічне посилання на обрану працю в потрібному вам стилі цитування: APA, MLA, «Гарвард», «Чикаго», «Ванкувер» тощо.

Також ви можете завантажити повний текст наукової публікації у форматі «.pdf» та прочитати онлайн анотацію до роботи, якщо відповідні параметри наявні в метаданих.

Переглядайте статті в журналах для різних дисциплін та оформлюйте правильно вашу бібліографію.

1

Saedon, Juri B., Siti Musalmah Md Ibrahim, Amir Radzi Abd Ghani, and Muhammad Hafizi Bin Abd Razak. "Dicing Characterization on Optical Silicon Wafer Waveguide." Applied Mechanics and Materials 899 (June 2020): 163–68. http://dx.doi.org/10.4028/www.scientific.net/amm.899.163.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Анотація:

Silicon wafers are a key component in integrated circuits which comprised of various electronic components that are arranged to perform a specific function. Wafer dicing is a mechanical process of removing material from a wafer by synthetic diamonds as abrasive particles. Chipping along the cut line crucial to the wafer dicing operation has been identified by semiconductor manufacturers as a relevant area for improvement. The purposed of this study is to characterize the effect of dicing operation on the optical silicon wafer coating material. The effect of the blade wear and silicon wafer kerf width will be analyzed in this work

2

Koolen, M. C. A. M. "On-wafer high-frequency device characterization." Microelectronic Engineering 19, no. 1-4 (September 1992): 679–86. http://dx.doi.org/10.1016/0167-9317(92)90521-r.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

3

Lau, J. H., P.-J. Tzeng, C.-K. Lee, C.-J. Zhan, M.-J. Dai, Li Li, C.-T. Ko, et al. "Wafer Bumping and Characterizations of Fine-Pitch Lead-Free Solder Microbumps on 12” (300mm) wafer for 3D IC Integration." International Symposium on Microelectronics 2011, no. 1 (January 1, 2011): 000650–56. http://dx.doi.org/10.4071/isom-2011-wa6-paper2.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Анотація:

In this study, the wafer bumping and characterization of fine-pitch lead-free solder microbumps on 300mm wafer for 3D IC integration are investigated. Emphasis is placed on the Cu-plating solutions (conformal and bottom-up). Also, the amount of Cu and solder (Sn) volumes is examined. Furthermore, characterizations such as shearing test and aging of the microbumps are provided and cross sections/SEM images of the microbumps before and after test are discussed. Finally, the process windows of applying the conventional electroplating wafer bumping method of the ordinary solder bumps to the microbumps are also presented.

4

Teixeira, Jorge, Mário Ribeiro, and Nélson Pinho. "Advanced warpage characterization for FOWLP." International Symposium on Microelectronics 2013, no. 1 (January 1, 2013): 000641–46. http://dx.doi.org/10.4071/isom-2013-wp21.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Анотація:

Current standards for silicon wafers shape characterization use simple metrics. Warpage and bow are computed as the mean surface wafer height range or the mean surface wafer center height, respectively [1]. These metrics are valid for silicon wafers because of their homogenous and linear thermomechanical properties [2]. In fan-out wafer level package (FO-WLP), embedded Wafer Level Ball Grid Array in specific (eWLB), the use of epoxy mold compound that works both as the physical carrier of the dies and as the base of second level connections has a major impact on the overall macroscopic behavior of the wafer, inducing shapes that do not follow a simple bended or bowed wafer, impacting wafer processability [3]. Warped wafers can affect device performance, reliability, and linewidth control in various processing steps [3]. Early detection will minimize cost and processing time. In our research, we present a solution for wafer characterization in FO-WLP by increasing the information vector that one obtains from standard automated non-contact scanning equipment. For this, we defined wafer shape and wafer ratio as the two new metrics besides warpage, creating a three dimensional vector that can be used to compare and evaluate wafers in high volume production or even single wafer analysis. This is a major improvement over previously used approaches, in which only the average warpage is considered. These metrics were determined by the developed numeric algorithm and their validity was demonstrated through the use of different production conditions, wafer constructions and production monitoring. The proposed approach requires no extra processing steps and time, as compared to conventional off-line methods. Experimental results demonstrate its feasibility and repeatability. This methodology was successfully used in the field and proved to be of high value when evaluating wafer geometrical requirements for both product development and process monitoring.

5

Kerepesi, Péter, Bernhard Rebhan, Matthias Danner, Karin Stadlmann, Heiko Groiss, Peter Oberhumer, Jiri Duchoslav, and Kurt Hingerl. "Oxide-Free SiC-SiC Direct Wafer Bonding and Its Characterization." ECS Transactions 112, no. 3 (September 29, 2023): 159–72. http://dx.doi.org/10.1149/11203.0159ecst.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Анотація:

In this study, the feasibility of oxide-free room temperature wafer bonding process was demonstrated for 4H-SiC wafers with in situ surface oxide removal. The investigations covered three areas: incoming metrology of the original wafer, characterization of activated single wafer and analysis of bonded wafer pairs. The focus was on compositional, chemical, mechanical and morphological analysis of the surfaces and of the bonded interfaces. Incoming wafers were inspected whether they fulfill the requirements of wafer bonding, and activated wafers were characterized to measure the surface modifications. The quality of the bonded wafers and the bonding energy were verified using scanning acoustic microscopy measurements as well as the Maszara blade test. Furthermore, cross-section transmission electron microscopy was used to investigate the amorphous layer at the bonding interface. The work reported is a demonstration of the capability of different characterization methods regarding SiC-SiC wafer bonding.

6

Deleniv, Anatoly, Andrei Vorobiev, and Spartak Gevorgian. "On-Wafer Characterization of Varactor Using Resonating Microprobes." IEEE Transactions on Microwave Theory and Techniques 56, no. 5 (May 2008): 1105–11. http://dx.doi.org/10.1109/tmtt.2008.921283.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

7

Laskar, J., J. J. Bautista, M. Nishimoto, M. Hamai, and R. Lai. "Development of accurate on-wafer, cryogenic characterization techniques." IEEE Transactions on Microwave Theory and Techniques 44, no. 7 (July 1996): 1178–83. http://dx.doi.org/10.1109/22.508659.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

8

Moore, B., M. Margala, and C. Backhouse. "Design of wireless on-wafer submicron characterization system." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13, no. 2 (February 2005): 169–80. http://dx.doi.org/10.1109/tvlsi.2004.840780.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

9

CHEN, CHIH-HUNG. "ACCURACY ISSUES OF ON-WAFER MICROWAVE NOISE MEASUREMENTS." Fluctuation and Noise Letters 08, no. 03n04 (December 2008): L281—L303. http://dx.doi.org/10.1142/s0219477508005136.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Анотація:

The accuracy issues of on-wafer noise characterization for a linear noisy two-port are presented in this paper. It starts with the description of a microwave noise measurement system and the possible source of error due to the microwave power meter in the measurement system. With the description of noise characterization techniques, this paper reviews a couple of methods for noise parameter extraction to handle the errors in the measured noise powers, noise factors, and source admittances. It also presents the methods to extract the physical noise parameters and to take care of different source admittances in the hot and cold states for accuracy enhancement.

10

Seong, Inho, Jinho Lee, Sijun Kim, Youngseok Lee, Chulhee Cho, Jangjae Lee, Wonnyoung Jeong, Yebin You, and Shinjae You. "Characterization of an Etch Profile at a Wafer Edge in Capacitively Coupled Plasma." Nanomaterials 12, no. 22 (November 10, 2022): 3963. http://dx.doi.org/10.3390/nano12223963.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Анотація:

Recently, the uniformity in the wafer edge area that is normally abandoned in the fabrication process has become important for improving the process yield. The wafer edge structure normally has a difference of height between wafer and electrode, which can result in a sheath bend, distorting important parameters of the etch, such as ionic properties, resulting in nonuniform etching. This problem nowadays is resolved by introducing the supplemented structure called a focus ring on the periphery of the wafer. However, the focus ring is known to be easily eroded by the bombardment of high-energy ions, resulting in etch nonuniformity again, so that the focus ring is a consumable part and must be replaced periodically. Because of this issue, there are many simulation studies being conducted on the correlation between the sheath structural characteristics and materials of focus rings to find the replacement period, but the experimental data and an analysis based on this are not sufficient yet. In this study, in order to experimentally investigate the etching characteristics of the wafer edge area according to the sheath structure of the wafer edge, the etching was performed by increasing the wafer height (thickness) in the wafer edge area. The result shows that the degree of tilt in the etch profile at the wafer edge and the area where the tilt is observed severely are increased with the height difference between the wafer and electrode. This study is expected to provide a database for the characteristics of the etching at the wafer edge and useful information regarding the tolerance of the height difference for untilted etch profile and the replacement period of the etch ring.

11

Hong, Hao-Chiao, and Long-Yi Lin. "Accurate and Fast On-Wafer Test Circuitry for Device Array Characterization in Wafer Acceptance Test." IEEE Transactions on Circuits and Systems I: Regular Papers 66, no. 9 (September 2019): 3467–79. http://dx.doi.org/10.1109/tcsi.2019.2924251.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

12

Kerepesi, Péter, Bernhard Rebhan, Matthias Danner, Karin Stadlmann, Heiko Groiss, Peter Oberhumer, Jiri Duchoslav, and Kurt Hingerl. "Oxide-Free SiC-SiC Direct Wafer Bonding and Its Characterization." ECS Meeting Abstracts MA2023-02, no. 33 (December 22, 2023): 1603. http://dx.doi.org/10.1149/ma2023-02331603mtgabs.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Анотація:

There are different requirements for the production process and the final product of SiC-SiC wafer bonding. The manufacturing of devices that are sensitive to high temperature processing – due to broadened doping profiles and induced thermal stresses – requires room temperature bonding with high bond strength, while for electrical devices, it is mandatory that the bonding interface with a thin amorphous layer is oxide-free.[1] Reduced complexity of processes is also an important point for the final production. Hence, the goal of this work was to perform and characterize direct bonding of SiC-SiC without any added/deposited bonding layer. This type of bonded SiC wafers can be used for power electronics such as for the fabrication of traction inverter for automotive applications, DC/DC converter, on board charger or charging station.[2] For the wafer bonding processes standard 100 mm 4H SiC wafers were bonded with their Si-terminated faces in order to fabricate oxide-free bonds. The wafer bonding process was performed using the EVG ComBond® system: first the native oxides from both wafer surfaces were removed using an ion beam sputtering process, followed by the transfer of both wafers to the bonding process station operated in ultra-high vacuum (UHV) to significantly retard the oxidation process. Finally, the bonding process was performed at room temperature (RT). The goal of this study was to demonstrate the feasibility of the bonding process and to gain insight on the surface chemistry after activation. The investigations covered three areas: incoming inspection of the original wafer, characterization of activated single wafer and analysis of bonded wafer pairs. The focus was on compositional, chemical, mechanical and morphological analysis of the surfaces and of the bonded interfaces. In the case of single wafers, the focus of the incoming inspection was on whether the wafers fulfill the requirements of wafer bonding, and on the characterization of activated wafers to measure the surface modifications. Atomic force microscopy (AFM), white light interferometry (WLI) and spectroscopic ellipsometry (SE) were used to determine the surface roughness, the wafer topography and the surface layer structure, respectively. All three parameters are essential for successful RT SiC-SiC wafer bonding. The change of the surface chemistry was investigated by angle resolved x-ray photoelectron spectroscopy (AR-XPS). The quality of the bonded wafers and the bonding energy were verified using scanning acoustic microscopy (SAM) measurements (Fig. 1) as well as the Maszara blade test. Furthermore, cross-section transmission electron microscopy (X-TEM) showed a bonding interface with a thin amorphous layer and no noticeable additional oxygen containing layer (Fig. 2). In order to gain quantitative elemental distributions of oxygen and argon, energy dispersive x-ray spectroscopy (EDXS) was applied. The work reported is a demonstration of the capability of the different characterization methods regarding SiC-SiC wafer bonding. Future work will focus on the investigation of the bonded interface characteristics in the function of the bonding process parameters and the annealing conditions. [1] F. Mu, M. Fujino, T. Suga, Y. Takahashi, H. Nakazawa and K. Iguchi, "Wafer bonding of SiC-SiC and SiC-Si by modified surface activated bonding method" 2015 International Conference on Electronics Packaging and iMAPS All Asia Conference (ICEP-IAAC), Kyoto, Japan, 2015, pp. 542-545, doi: 10.1109/ICEP-IAAC.2015.7111073. [2] Tsunenobu Kimoto, "Material science and device physics in SiC technology for high-voltage power devices" Jpn. J. Appl. Phys. 54 040103 (2015), doi: 10.7567/JJAP.54.040103. Figure 1

13

Field, Daniel E., James W. Pomeroy, Farzan Gity, Michael Schmidt, Pasqualino Torchia, Fan Li, Peter M. Gammon, Vishal A. Shah, and Martin Kuball. "Thermal characterization of direct wafer bonded Si-on-SiC." Applied Physics Letters 120, no. 11 (March 14, 2022): 113503. http://dx.doi.org/10.1063/5.0080668.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Анотація:

Direct bonded Si-on-SiC is an interesting alternative to silicon-on-insulator (SOI) for improved thermal management in power conversion and radio frequency applications in space. We have used transient thermoreflectance and finite element simulations to characterize the thermal properties of direct bonded Si-on-4H–SiC samples, utilizing a hydrophobic and hydrophilic bonding process. In both instances, the interface has good thermal properties resulting in TBReff values of 6 + 4/−2 m2 K GW−1 (hydrophobic) and 9 + 3/−2 m2 K GW−1 (hydrophilic). Two-dimensional finite element simulations for an equivalent MOSFET showed the significant thermal benefit of using Si-on-SiC over SOI. In these simulations, a MOSFET with a 200 nm thick, 42 μm wide Si drift region was recreated on a SOI structure (2 μm buried oxide) and on the Si-on-SiC material characterized here. At 5 W mm−1 power dissipation, the Si-on-SiC was shown to result in a >60% decrease in temperature rise compared to the SOI structure.

14

Liu, Kai, YongTaek Lee, HyunTai Kim, MaPhooPwint Hlaing, Susan Park, and Billy Ahn. "Electrical Characterization on a High-Speed Wafer-Level Package." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, DPC (January 1, 2013): 001937–62. http://dx.doi.org/10.4071/2013dpc-tha23.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Анотація:

In this paper, a 2-layer eWLB (embedded Wafer-Level BGA) is studied and its performance is compared with an equivalent 4-layer laminate package. Since eWLB package is processed by using lithographical method, design rules on width (W) and spacing (S) are much finer (usually 2–3 times finer) than those for laminate package. In other words, signal traces can be implemented in smaller fan-out regions. The smaller feature sizes for signal traces would end up with more metal loss per unit length. But as the signal traces can be implemented in smaller fan-out regions, overall trace-routing may be shorter, and equivalent insertion-loss may be achieved. In eWLB, the ground plane is closer to the signal traces. This actually helps to reduce cross-talk between wide I/O buses, as the electrical field is contained in a smaller region by the closer ground plane. Another key advantage from wafer-level package is a smoother metal surface, which greatly reduces the extra signal loss, due to surface-roughness effect, especially for higher-frequency and higher-speed applications. In addition, through-via structures for wafer-level package are typically 2–3 times smaller. This allows to implement power/ground planes in a more continuous way, achieving better resistance and inductance for power/ground nets. Overall electrical performance, which takes into account of all the impacts above, can be evaluated by signal-integrity analysis (E-diagram). Measurement data of a 2-layer eWLB package for a LPDDR application will be presented, which shows the comparable performance typically obtained from a 4-layer laminate package

15

Kazemi Esfeh, Babak, Khaled Ben Ali, and Jean-Pierre Raskin. "Compact On-Wafer Test Structures for Device RF Characterization." IEEE Transactions on Electron Devices 64, no. 8 (August 2017): 3101–7. http://dx.doi.org/10.1109/ted.2017.2717196.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

16

Dunleavy, L. P., J. Randa, D. K. Walker, R. Billinger, and J. Rice. "Characterization and applications of on-wafer diode noise sources." IEEE Transactions on Microwave Theory and Techniques 46, no. 12 (1998): 2620–28. http://dx.doi.org/10.1109/22.739255.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

17

Imai, M., Y. Miyamura, D. Murata, and A. Ogi. "Characterization of SiGe Layer on Insulator by In-Plane Diffraction Method." Solid State Phenomena 108-109 (December 2005): 451–56. http://dx.doi.org/10.4028/www.scientific.net/ssp.108-109.451.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Анотація:

Four types of SGOI (SiGe on Insulator) wafers were fabricated by the combination of SiGe epitaxial growth, SIMOX (Separation by Implanted Oxygen) processes and oxidation. By the cross-sectional TEM (Transmission Electron Microscopy) and EDS (Energy Dispersive Spectroscopy), it is confirmed that each wafer has smooth interface between a top layer (Si or SiGe) and a BOX (buried oxide) layer and Ge atoms in SiGe layer distribute homogeneously for SGOI_A and SGOI_B. Using high-resolution X-ray diffractometry, the crystallographic properties of SiGe layer are characterized with in-plane and out of plane diffraction methods. The lattice constants are calculated for the planes of perpendicular and parallel to wafer surface and the degree of relaxation are estimated for the SiGe layer of each wafer. The rocking curve measurements reveal that the lattice turbulence of SiGe layer is influenced by SIMOX process conditions, Ge content and the layer thickness.

18

Hoff, A. M., and E. Oborina. "Fast Non-Contact Dielectric Characterization for SiC MOS Processing." Materials Science Forum 527-529 (October 2006): 1035–38. http://dx.doi.org/10.4028/www.scientific.net/msf.527-529.1035.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Анотація:

Non-contact corona-voltage metrology is utilized to characterize as-grown thermal oxide films on 4H SiC substrates. Contact potential difference mapping is coupled with incremental application of corona charge to provide whole-wafer images of process related effects and multiplepoint capacitance-voltage characteristics respectively. Correspondence between wafer VCPD images and process details is suggested along with examples of fast electrical dielectric thickness determination and non-contact C-V characteristic acquisition.

19

Caddemi, Alina, Emanuele Cardillo, Giovanni Crupi, Luciano Boglione, and Jason Roussos. "Microwave Linear Characterization Procedures of On-Wafer Scaled GaAs pHEMTs for Low-Noise Applications." Electronics 8, no. 11 (November 18, 2019): 1365. http://dx.doi.org/10.3390/electronics8111365.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Анотація:

This contribution deals with the microwave linear characterization and noise figure measurement of four on-wafer GaAs pseudomorphic high-electron mobility transistors having scaled gate widths. The proposed measurement campaign has been fulfilled in two different laboratories: The University of Messina, Italy and US Naval Research Laboratory, Washington, DC, USA. Two equivalent approaches have been straightforwardly employed: a standard tuner-based technique and a novel tuner-less technique. The effectiveness of the novel technique has been confirmed as carried out independently by the two laboratories, evidencing the benefits of both techniques. The proposed experimental activity highlights the applicability of the tunerless technique for the noise characterization of advanced on-wafer devices without the constraint imposed by the addition of a source tuner to the standard measurement setup.

20

Cavaco, Celso, Lan Peng, Koen De Leersnijder, Stefano Guerrieri, Deniz S. Tezcan, and Haris Osman. "Copper Oxide Direct Bonding of 200mm CMOS Wafers: Morphological and Electrical Characterization." International Symposium on Microelectronics 2015, no. 1 (October 1, 2015): 000594–97. http://dx.doi.org/10.4071/isom-2015-tha26.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Анотація:

We show for the first time complete data on 200mm wafer to wafer copper oxide direct bonding of two metal levels. Both surface acoustic microscope (SAM) and cross-section scanning electron microscope (X-SEM) images taken across the bonded wafer pairs confirm the good direct bonding quality of the resulting interface. Daisy chains with up to 3200 copper to copper bonded pads and of about 50mOhm/pad, are shown to be connected successfully and its resistance value to match a target value, as well as to scale linearly with the increase of connections in the chain.

21

Marino, Nobuaki, Kiichirou Murai, and Yoshinori Kataora. "Characterization of Surface Contaminants by a Silver Film-Enhanced IR—Johnson Method." Applied Spectroscopy 51, no. 10 (October 1997): 1460–63. http://dx.doi.org/10.1366/0003702971939226.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Анотація:

Characterization of nanometer-order organic contaminants on polymer film and silicon wafer surface has been investigated by a modified IR–Johnson method. We have proposed a silver film-enhanced IR–Johnson method that is useful for surface contaminant analysis. In the present method, organic traces are transferred from the surface of a polymer film or silicon wafer onto the KBr particles deposited with silver film, and then the KBr particles are analyzed directly by diffuse reflectance infrared Fourier transform spectroscopy (DRIFTS). Infrared absorption of organic traces was enhanced by the presence of silver island film. With this method, a spectrum of nanometer-order organic traces can be obtained without any interference from the polymer film substrate. The present method is as surface-sensitive as X-ray photoelectron spectroscopy (XPS) and provides a large amount of information on the chemical structure of surface contaminants. This is a promising method for the surface characterization of polymer films and silicon wafer. Index Headings: Infrared; Diffuse reflectance; Surface enhancement.

22

Chun, C., A. Pham, J. Laskar, and B. Hutchison. "Development of microwave package models utilizing on-wafer characterization techniques." IEEE Transactions on Microwave Theory and Techniques 45, no. 10 (1997): 1948–54. http://dx.doi.org/10.1109/22.641800.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

23

Simons, R. N., and R. Q. Lee. "On-wafer characterization of millimeter-wave antennas for wireless applications." IEEE Transactions on Microwave Theory and Techniques 47, no. 1 (1999): 92–96. http://dx.doi.org/10.1109/22.740086.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

24

Russell, Damon, Kieran Cleary, and Rodrigo Reeves. "Cryogenic probe station for on-wafer characterization of electrical devices." Review of Scientific Instruments 83, no. 4 (April 2012): 044703. http://dx.doi.org/10.1063/1.3700213.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

25

Descamps, Philippe, Dolphin Abessolo-Bidzo, and Patrick Poirier. "Improved test structure for on-wafer microwave characterization of components." Microwave and Optical Technology Letters 53, no. 2 (December 15, 2010): 249–54. http://dx.doi.org/10.1002/mop.25738.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

26

Fresquet, Gilles, and Jean-Philippe Piel. "Optical Characterization and Defect inspection for 3D stacked IC technology." International Symposium on Microelectronics 2014, no. 1 (October 1, 2014): 000630–34. http://dx.doi.org/10.4071/isom-wp17.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Анотація:

Advanced packaging technologies are rapidly evolving and 3D architectures requires new inspection and metrology techniques. Existing techniques need to be improved but new techniques must be developed to address new challenges induced by the last fabrication processes. To increase the development speed, it is a big advantage that metrology and defect inspection need to be present on the same platform and a flexible tool, with multi sensors, to be more versatile facing the different step of the process will be presented in this paper As 3D IC devices utilize TSVs for direct interconnect, the depth, top and bottom CD (critical diameter) of such TSVs with a diameter as small as 5 μm with a high aspect ratio is characterized. During wafer temporary bounding, which is an handling technique that allows wafer thinning with a thickness of less than 100 μm, by selecting the most sensitive sensor, determination of the thickness of each layer of the stack could be determined at the same time: silicon substrate, thin glue layer of few microns only and carrier which could be silicon or glass. After back-side processing and wafer thinning, the determination of the remaining silicon thickness (RST) below the TSV could be determined. Moreover back side roughness after grinding is also determined. After wafer thinning process, the TSVs are revealed at the back side of the wafer, leaving to appear copper pillars. The pillars height and co-planarity measurements are then addressed. Post CMP process control will be addressed by full field interferometry especially prior Copper to Copper direct bonding. Concerning the defect inspection, the NIR microscopy is used to control die to wafer stacking process, to reveal voids in the glue and cracks on the grinded silicon substrate. In this paper, we will present fast and nondestructive optical sensors based on low coherence infrared and white light interferometry and spectrometry techniques. These different sensors mounted on the same tool allow characterizing specifically and with an excellent sensitivity the different process steps described above. Concerning the defect inspections, techniques based on infrared microscopy and images techniques processing will be detailed and results will be presented to illustrate the possibilities of this inspection by microscopy.

27

Kim, Taehyun, Sangwug Han, Jubum Lee, Yeeun Na, Joontaek Jung, Yun Chang Park, Jaesub Oh, Chungmo Yang, and Hee Yeoun Kim. "Development and Characterization of Low Temperature Wafer-Level Vacuum Packaging Using Cu-Sn Bonding and Nanomultilayer Getter." Micromachines 14, no. 2 (February 14, 2023): 448. http://dx.doi.org/10.3390/mi14020448.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Анотація:

Most microsensors are composed of devices and covers. Due to the complicated structure of the cover and various other requirements, it difficult to use wafer-level packaging with such microsensors. In particular, for monolithic microsensors combined with read-out ICs, the available process margins are further reduced due to the thermal and mechanical effects applied to IC wafers during the packaging process. This research proposes a low-temperature, wafer-level vacuum packaging technology based on Cu-Sn bonding and nano-multilayer getter materials for use with microbolometers. In Cu-Sn bonding, the Cu/Cu3Sn/Cu microstructure required to ensure reliability can be obtained by optimizing the bonding temperature, pressure, and time. The Zr-Ti-Ru based nanomultilayer getter coating inside the cap wafer with high step height has been improved by self-aligned shadow masking. The device pad, composed of bonded wafer, was opened by wafer grinding, and the thermoelectrical properties were evaluated at the wafer-level. The bonding strength and vacuum level were characterized by a shear test and thermoelectrical test using microbolometer test pixels. The vacuum level of the packaged samples showed very narrow distribution near 50 mTorr. This wafer-level packaging platform could be very useful for sensor development whereby high reliability and excellent mechanical/optical performance are both required. Due to its reliability and the low material cost and bonding temperature, this wafer-based packaging approach is suitable for commercial applications.

28

Majeed, Bivragh, Chengxun Liu, Erik Sohn, Lut Van Acker, Koen De Wijs, Deniz Sabuncuoglu, and Liesbet Lagae. "Silicon based cell sorting device: Fabrication, characterization and applications." International Symposium on Microelectronics 2016, no. 1 (October 1, 2016): 000019–24. http://dx.doi.org/10.4071/isom-2016-tp15.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Анотація:

Abstract Cell sorting is an important diagnostic tool used in various aspect of medical prognosis. Numerous cell sorting techniques are currently available on market but they are quite bulky, expensive and at the same time requires very trained operators. In this paper we report on wafer level fabrication technique that will allows for a small form factor device targeting cell sorting. We give detailed overview for the fabrication of our miniaturized cell sorter that is formed with a CMOS compatible process. It used standard fabrication technique in combination with photo-patternable polymer, that has excellent properties for microfluidics applications. The ability to process on wafer level distinguish this from other processes, whose yields are limited to few test samples. The device fabrication includes: processing of micro-heaters, definition of polymer microfluidic channels and collective die-to-wafer bonding of glass substrate onto the polymer channels. We report on the initial characterization of the cell sorting targeting sorting rate and sorting yield. We have achieved sorting rate of 5,000 cells/s and yield of 70% is obtained in initial investigations.

29

Haisu, M., Uda Hashim, and Q. Humayun. "Micro-Gap Electrodes Fabrication by Low Cost Conventional Photo Lithography Technique and Surface Characterization by Nanoprofiler." Advanced Materials Research 925 (April 2014): 635–40. http://dx.doi.org/10.4028/www.scientific.net/amr.925.635.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Анотація:

The fabrication of sensitive and selective nanodevices is one of the important challenges for future detection of low concentration single bio molecule. The current research article is one of the attempts to achieve such sensitive and selective micro-gap electrodes by simple, low cost controllable process. Therefore high sensitive chrome mask was designed for micro-gap design transformation to wafer samples. At first the positive photoresist namely PR-1 2000A was spin coated on the samples wafer at different rotation speed. Then by implementation of low cost conventional photolithography technique an initial structure of micro-gap was patterned on wafer sample. Finally by using surface Nanoprofiler the thickness of resist coated wafer samples were investigated. The obtained results show that the thickness of the resist is directly related with spin coating speed of spin coater.

30

Cakmak, Erkan, Bioh Kim, and Viorel Dragoi. "Characterization of Wafer Level Metal Thermo-Compression Bonding." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, DPC (January 1, 2010): 002326–60. http://dx.doi.org/10.4071/2010dpc-tha34.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Анотація:

The process of wafer-level bonding is being successfully used to form MEMS devices. Wafer level bonding may be realized by different methods such as thermo compression, transient liquid phase, anodic, glass frit, or polymer bonding. These methods have different requirements and the choice of wafer level bonding method is defined by the application type. Metal TCB has a wide variety of applications with materials of choice including Au, Cu and Al. 3D electrical connections are created by the use of Cu-Cu TCB; while CMOS MEMS devices may be realized by Al-Al TCB. In this study the wafer level bonding process of Cu-Cu and Al-Al TCB are characterized. The effects and significance of various bonding process parameters and surface treatment methods are reported on the final bond interfaces integrity and strength. Analysis methods include SAM, SEM, AFM, and four point bending test. Al-Al TCB samples were investigated on the interfacial adhesion energy and bond quality. IAE and bond quality were found to be positively correlated with bonding temperature. A bonding temperature of 500 °C or greater is necessary to obtain bond strengths of 8–10 J/m2. A positive relation between IAE and bonding temperature was observed for Cu-Cu TCB. IAE's of greater then 10 J/m2 were obtained on bonded samples that do not show a post bond residual seam on the bonding interface. An acid based pre treatment was shown to impact the surface properties of the initial metal surface hence affecting the IAE. Post bond annealing processes showed the most significant impact on the IAE of the Cu-Cu TCB system. To obtain comparable IAE values the Al-Al TCB method requires a higher bonding temperature. However the Cu-Cu TCB is sensitive to the initial metal surface condition and requires surface treatment processes prior to bonding to obtain high quality bonding results.

31

INABA, Michihiko. "Present and Future of Surface Characterization. Surface Characterization on Si Wafer for Semiconductor Devices." Journal of the Japan Society for Precision Engineering 61, no. 11 (1995): 1511–15. http://dx.doi.org/10.2493/jjspe.61.1511.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

32

Tajima, Michio, E. Higashi, Toshihiko Hayashi, Hiroyuki Kinoshita, and Hiromu Shiomi. "Characterization of SiC Wafers by Photoluminescence Mapping." Materials Science Forum 527-529 (October 2006): 711–16. http://dx.doi.org/10.4028/www.scientific.net/msf.527-529.711.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Анотація:

The effectiveness of room-temperature photoluminescence (PL) mapping was demonstrated for nondestructive detection of structural defects, such as dislocations, micropipes and stacking faults, in SiC wafers. PL spectra of bulk wafers were dominated by deep-level emissions due to Si vacancies, vanadium and undefined centers like UD-1 at room temperature, while those from epitaxial wafers involved near band-edge emission. We developed a whole-wafer PL intensity mapping system with a capability of zooming in on the area of interest with a spatial resolution as high as 1 μm, and showed that the mapping patterns agree well with the etch-pit patterns originating from the structural defects both on a wafer scale and on a microscopic scale. The intensity contrast around the defects varied depending on the emission band, suggesting differences in their interactions with impurities and point defects.

33

Yu, Hengshu, Junbo Wang, Yulan Lu, Bo Xie, Yanlong Shang, and Zhao Liu. "A silicon resonant pressure sensor based on thermal stresses matched structures." Journal of Physics: Conference Series 2740, no. 1 (April 1, 2024): 012041. http://dx.doi.org/10.1088/1742-6596/2740/1/012041.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Анотація:

Abstract This paper introduced a silicon resonant pressure sensor based on thermal stress-matched structures to extend the operating temperature range. The sensor designed this time consists of an SOI wafer with a pressure-sensitive diaphragm for pressure sensing and two integrated resonators, a silicon wafer for vacuum packaging, and a glass wafer for additional stress isolation. The multilayer structures were bonded together to form a thermal stress-matched part to address the problem of temperature inflection points of conventional resonant pressure sensors within broad temperature zones. Finite element analyses optimized the sensor’s pressure- and temperature-sensitive characteristics. Micromachining based on eutectic and anodic bonding to fabricate sensor chips. Characterization results indicated the developed pressure sensor can work stably in a wide temperature range of -55∼125°C and has excellent fitting accuracy exceeding ±0.01% FS., which showed a better performance than previously reported counterparts.

34

Ferrero, A., and U. Pisani. "An improved calibration technique for on-wafer large-signal transistor characterization." IEEE Transactions on Instrumentation and Measurement 42, no. 2 (April 1993): 360–64. http://dx.doi.org/10.1109/19.278582.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

35

Archer, J. W., and R. A. Batchelor. "Fully automated on-wafer noise characterization of GaAs MESFETs and HEMTs." IEEE Transactions on Microwave Theory and Techniques 40, no. 2 (1992): 209–16. http://dx.doi.org/10.1109/22.120092.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

36

Scholz, M., D. Linten, S. Thijs, S. Sangameswaran, M. Sawada, T. Nakaei, T. Hasebe, and G. Groeseneken. "ESD On-Wafer Characterization: Is TLP Still the Right Measurement Tool?" IEEE Transactions on Instrumentation and Measurement 58, no. 10 (October 2009): 3418–26. http://dx.doi.org/10.1109/tim.2009.2017657.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

37

Tiemeijer, Luuk F., Ralf M. T. Pijper, and Edwin van der Heijden. "Complete On-Wafer Noise-Figure Characterization of 60-GHz Differential Amplifiers." IEEE Transactions on Microwave Theory and Techniques 58, no. 6 (June 2010): 1599–608. http://dx.doi.org/10.1109/tmtt.2010.2049167.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

38

Caddemi, A., and N. Donato. "Temperature-dependent noise characterization and modeling of on-wafer microwave transistors." Microelectronics Reliability 42, no. 3 (March 2002): 361–66. http://dx.doi.org/10.1016/s0026-2714(02)00004-5.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

39

Linz, Sarah, Florian Oesterle, Stefan Lindner, Sebastian Mann, Robert Weigel, and Alexander Koelpin. "Test Method for Contactless On-Wafer MEMS Characterization and Production Monitoring." IEEE Transactions on Microwave Theory and Techniques 64, no. 11 (November 2016): 3918–26. http://dx.doi.org/10.1109/tmtt.2016.2612664.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

40

Terayama, Yuki, Motoyasu Kobayashi, Sono Sasaki, Osami Sakata, and Atsushi Takahara. "Structural Characterization of Surface-grafted Poly (Vinyl Alcohol) on Silicon Wafer." Transactions of the Materials Research Society of Japan 32, no. 1 (2007): 259–62. http://dx.doi.org/10.14723/tmrsj.32.259.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

41

Stake, Jan, and Hans Grönqvist. "An on-wafer method for C-V characterization of heterostructure diodes." Microwave and Optical Technology Letters 9, no. 2 (June 5, 1995): 63–66. http://dx.doi.org/10.1002/mop.4650090202.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

42

Lederer, Dimitri, and Jean-Pierre Raskin. "On-wafer wideband characterization: a powerful tool for improving the IC technologies." Journal of Telecommunications and Information Technology, no. 2 (June 25, 2023): 69–77. http://dx.doi.org/10.26636/jtit.2007.2.811.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Анотація:

In the present paper, the interest of wideband characterization for the development of integrated technologies is highlighted through several advanced devices, such as 120 nm partially depleted (PD) silicon-on-insulator (SOI) MOSFETs, 120 nm dynamic threshold (DT) voltage – SOI MOSFETs, 50 nm FinFETs as well as long-channel planar double gate (DG) MOSFETs.

43

Torimi, Satoshi, Norihito Yabuki, Takuya Sakaguchi, Masato Shinohara, Yoji Teramoto, Satoru Nogami, Makoto Kitabatake, and Junji Senzaki. "Characterization of pn-Diode Fabricated from Surface Damage-Free 4H-SiC Wafer Using Si-Vapor Etching Process." Materials Science Forum 924 (June 2018): 349–52. http://dx.doi.org/10.4028/www.scientific.net/msf.924.349.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Анотація:

We investigate electrical characteristics of the pn-diode fabricated using the epitaxial films on the surface damage-free 4H-SiC (0001) Si-face 4° off-cut wafers prepared by the completely thermal-chemical etching process; Si-vapor etching (Si-VE) technology. The forward and reverse current-voltage (I-V) characteristics of pn-diodes correlated to the epitaxial defects are discussed. The device at the defect-free area includes 11 % failed diodes on the chemo-mechanical polishing (CMP) wafer while 0 % on the Si-VE wafer. The latent scratches and mechanical damages, which increase the forward and reverse leakage current of the pn-diodes, are completely removed by the Si-VE. The Si-VE exposes the carbon inclusions in the wafer to form the small bump which ends up with the larger bump defect on the epitaxial surface. These bumps cause leak current of the forward characteristics while all of the reverse characteristics are normal. The epitaxial film on the Si-VE surface has less density of the basal plane dislocations (BPDs) than the conventional CMP. It is hard to recognize the safe device on the CMP wafer without additional reliability test. The Si-VE wafer shows the apparent breakdown voltage fail on every small-number diode including BPDs under the simple test. It is considered that the Si-VE is possible to reduce ambiguity of the device characteristics under the relationship with the defects in comparison with the CMP.

44

Wang, Yibang, Xingchang Fu, Aihua Wu, Chen Liu, Peng Luan, Faguo Liang, Wei Zhao, and Xiaobang Shang. "Development of gallium-arsenide-based GCPW calibration kits for on-wafer measurements in the W-band." International Journal of Microwave and Wireless Technologies 12, no. 5 (December 12, 2019): 367–71. http://dx.doi.org/10.1017/s1759078719001521.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Анотація:

AbstractWe present details of on-wafer-level 16-term error model calibration kits used for the characterization of W-band circuits based on a grounded coplanar waveguide (GCPW). These circuits were fabricated on a thin gallium arsenide (GaAs) substrate, and via holes, were utilized to ensure single mode propagation (i.e., eliminating the parallel-plate mode or surface mode). To ensure the accuracy of the definition for the calibration kits, multi-line thru-reflect-line (MTRL) assistant standards were also fabricated on the same wafer and measured. The same wafer also contained passive and active devices, which were measured subject to both 16-term and conventional line-reflect-reflect-match calibrations. Measurement results show that 16-term calibration kits are capable of determining the cross-talk more accurately. Other typical calibration techniques were also implemented using the standards on the GCPW calibration kits, and were compared with the MTRL calibration using a passive device under test. This revealed that the proposed GCPW GaAs calibration substrate could be a feasible alternative to conventional CPW impedance standard substrates, for on-wafer measurements at W-band and above.

45

Zhu, Liang, Biao Mei, Weidong Zhu, and Wei Li. "Laser-based Thickness Control in a Double-Side Polishing System for Silicon Wafers." Sensors 20, no. 6 (March 13, 2020): 1603. http://dx.doi.org/10.3390/s20061603.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Анотація:

Thickness control is a critical process of automated polishing of large and thin Si wafers in the semiconductor industry. In this paper, an elaborate double-side polishing (DSP) system is demonstrated, which has a polishing unit with feedback control of wafer thickness based on the scan data of a laser probe. Firstly, the mechanical structure, as well as the signal transmission and control of the DSP system, are discussed, in which the thickness feedback control is emphasized. Then, the precise positioning of the laser probe is explored to obtain the continuous and valid scan data of the wafer thickness. After that, a B-spline model is applied for the characterization of the wafer thickness function to provide the thickness control system with credible thickness deviation information. Finally, experiments of wafer-thickness evaluation and control are conducted on the presented DSP system. With the advisable number of control points in B-spline fitting, the thickness variation can be effectively controlled in wafer polishing with the DSP system, according to the experimental results of curve fitting and the statistical analysis of the experimental data.

46

Chan, Mu-Hsuan, Yu-Po Wang, Ivan Chang, James Chiang, George Pan, Nicholas Kao, and David Wang. "Development and Challenges of Warpage for Fan-Out Wafer-Level Package Technology." International Symposium on Microelectronics 2016, no. 1 (October 1, 2016): 000524–28. http://dx.doi.org/10.4071/isom-2016-poster4.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Анотація:

Abstract Fan-out wafer-level-packaging (FO-WLP) technology has been widely investigated recently with its advantages of thin form factor structure, cost effectiveness and high performance for wide range applications. Reducing wafer warpage is one of the most challenging needs to be addressed for success on subsequent processes. Therefore, the majority of studies focus on the ratio of die and compound thickness, structure design. In order to optimize the warpage for success on subsequent processes, it is indispensable to consider whole wafer process including thermal loading and stress. In this study, reducdution of wafer warpage at each process was proposed in terms of material selection, and process optimization through finite element analysis (FEA) and experiment. Wafer process dependent modeling results were validated by experimental measurement data. The mutual relationship and effects of material property, compound thickness, and corresponding thermal influences were both investigated and addressed. Key parameters were identified based on FEA modeling results: thickness ratio of die/compound andmolding compound materials. Therefore, the geometry design with balanced die/compound ratio is optimal for warpage improvement. The effect of process will be discussed and should be considered for future package warpage characterization. Such findings have been successfully used in process optimization to reduce wafer warapge after grinding process.

47

Han, Chansu, Yoonsung Koo, Jaehwan Kim, Kwangwook Choi, and Sangjeen Hong. "Wafer Type Ion Energy Monitoring Sensor for Plasma Diagnosis." Sensors 23, no. 5 (February 22, 2023): 2410. http://dx.doi.org/10.3390/s23052410.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Анотація:

We propose a wafer-type ion energy monitoring sensor (IEMS) that can measure the spatially resolved distribution of ion energy over the 150 mm plasma chamber for the in situ monitoring of the semiconductor fabrication process. The IEMS can directly be applied to the semiconductor chip production equipment without further modification of the automated wafer handling system. Thus, it can be adopted as an in situ data acquisition platform for plasma characterization inside the process chamber. To achieve ion energy measurement on the wafer-type sensor, the injected ion flux energy from the plasma sheath was converted into the induced currents on each electrode over the wafer-type sensor, and the generated currents from the ion injection were compared along the position of electrodes. The IEMS operates without problems in the plasma environment and has the same trends as the result predicted through the equation.

48

Marzouk, Jaouad, Steve Arscott, Abdelhatif El Fellahi, Kamel Haddadi, Tuami Lasri, Christophe Boyaval, and Gilles Dambrine. "MEMS probes for on-wafer RF microwave characterization of future microelectronics: design, fabrication and characterization." Journal of Micromechanics and Microengineering 25, no. 7 (June 24, 2015): 075024. http://dx.doi.org/10.1088/0960-1317/25/7/075024.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

49

Arias, Abraham, Nicola Nedev, Mario Curiel, Diana Nesheva, Emil Manolov, Benjamin Valdez, David Mateos, Oscar Contreras, Oscar Raymond, and Jesus M. Siqueiros. "Electrical Characterization of Interface Defects in MOS Structures Containing Silicon Nanoclusters." Advanced Materials Research 976 (June 2014): 129–32. http://dx.doi.org/10.4028/www.scientific.net/amr.976.129.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Анотація:

The effect of annealing temperature on the properties of c-Si wafer/SiOx interface (x = 1.15 and 1.3) is studied by Transmission Electron Microscopy and Capacitance/Conductance-Voltage measurements. Furnace annealing for 60 min at 700 and 1000 °C is used to grow amorphous or crystalline Si nanoparticles. The high temperature process leads to an epitaxial overgrowth of the Si wafer and an increase of the interface roughness, 3-4 monolayers at 700 °C and 4-5 monolayers at 1000 °C. The increased surface roughness is in correlation with the higher density of electrically active interface states.

50

Neudeck, Philip G., Liang Yu Chen, David J. Spry, Glenn M. Beheim, and Carl W. Chang. "Electrical Characterization of a 4H-SiC JFET Wafer: DC Parameter Variations for Extreme Temperature IC Design." Materials Science Forum 821-823 (June 2015): 781–84. http://dx.doi.org/10.4028/www.scientific.net/msf.821-823.781.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Анотація:

This work reports DC electrical characterization of a 76 mm diameter 4H-SiC JFET test wafer fabricated as part of NASA’s on-going efforts to realize medium-scale ICs with prolonged and stable circuit operation at temperatures as high as 500 °C. In particular, these measurements provide quantitative parameter ranges for use in JFET IC design and simulation. Larger than expected parameter variations were observed both as a function of position across the wafer as well as a function of ambient testing temperature from 23 °C to 500 °C.