Дисертації з теми "On-Wafer characterization"

Les mesures de précision jouent un rôle crucial dans l'électronique, en particulier dans la caractérisation des transistors bipolaires à hétérojonction (HBT) à base de silicium embarqués dans des dispositifs pour applications THz utilisant la technologie BiCMOS. Grâce aux innovations récentes en termes de fabrication de technologies à l'échelle nanométrique, les dispositifs capables de fonctionner dans la région des ondes submillimétriques deviennent une réalité et doivent répondre à la demande de circuits et de systèmes haute-fréquence. Pour disposer de modèles précis à de telles fréquences, il n'est plus possible de limiter l'extraction des paramètres en dessous de 110 GHz, et de nouvelles techniques permettant d'obtenir des mesures fiables de dispositifs passifs et actifs doivent être étudiées.Dans cette thèse, nous examinerons la caractérisation des paramètres S sur silicium (on-wafer) de différentes structures de test passives et des HBT SiGe en technologie B55 de STMicroelectronics, jusqu'à 500 GHz. Nous commencerons par une introduction de l'équipement de mesure habituellement utilisé pour ce type d'analyse, puis nous passerons aux différents bancs de mesure adoptés au laboratoire IMS, et enfin nous nous concentrerons sur les techniques de calibrage et d’épluchage (de-embedding), en passant en revue les principales criticités de la caractérisation haute-fréquence et en comparant deux algorithmes de calibrage on-wafer (SOLT et TRL) jusqu'à la bande WR-2.2.Deux cycles de production de photomasques pour la caractérisation on-wafer, tous deux conçus à l'IMS, seront présentés: nous introduirons un nouveau design du floorplan et évaluerons sa capacité à limiter les effets parasites ainsi que l'effet de son environnement (substrat, structures voisines et diaphonie). Pour notre analyse, nous nous appuierons sur des simulations électromagnétiques et des simulations EM mixtes de modèle compacte + sonde, toutes deux incluant les modèles des sonde pour une évaluation des résultats de mesure plus proche des conditions réelles.Enfin, nous présenterons quelques structures de test pour évaluer les impacts indésirables sur les mesures d'ondes millimétriques et de nouvelles solutions de conception de lignes de transmission. Deux designs prometteurs seront soigneusement étudiées: le "layout M3", qui vise à caractériser le DUT dans un étalonnage à un seul niveau, et les "lignes à méandre", qui maintiennent la distance entre les deux sondes constante en évitant tout déplacement pendant les mesures sur silicium
Precision measurements play a crucial role in electronic engineering, particularly in the characterization of silicon-based heterojunction bipolar transistors (HBTs) embedded into devices for THz applications using the BiCMOS technology. Thanks to ongoing innovations in terms of nanoscale technology manufacturing, devices capable of operating in the sub-millimeter wave region are becoming a reality, and need to support the demand for high frequency circuits and systems. To have accurate models at such frequencies, it is no longer possible to limit the parameter extraction below 110 GHz, and new techniques for obtaining reliable measurements of passive and active devices must be investigated.In this thesis, we examine the on-wafer S-parameters characterization of various passive test structures and SiGe HBTs in STMicroelectronics' B55 technology, up to 500 GHz. We start with an introduction of the measuring equipment usually employed for this type of analysis, then moving on to the various probe stations adopted at the IMS Laboratory, and finally focusing on calibration and deembedding techniques, reviewing the major criticalities of high-frequency characterization and comparing two on-wafer calibration algorithms (SOLT and TRL) up to the WR-2.2 band.Two photomask production runs for on-wafer characterization, both designed at IMS, are considered: we introduce a new floorplan design and evaluate its ability to limit parasitic effects as well as the effect of the environment (substrate, neighbors, and crosstalk). For our analysis, we rely on electromagnetic simulations and joint device model + probe EM simulations, both including probe models for an evaluation of measurement results closer to real-world conditions.Finally, we present some test structures to evaluate unwanted impacts on millimeter wave measurements and novel transmission line design solutions. Two promising designs are carefully studied: the "M3 layout", which aims to characterize the DUT in a single-tier calibration, and the "meander lines", which keeps the inter-probe distance constant by avoiding any sort of probe displacement during on-wafer measurements

Cubic boron nitride (cBN) thin films offer attractive mechanical and electrical properties. The synthesis of cBN films have been deposited using both physical and chemical vapor deposition methods, which generate internal residual, stresses that result in delamination of the film from substrates. Boron nitride films were deposited using electron beam evaporation without bias voltage and nitrogen bombardment (to reduce stresses) were characterize using FTIR, XRD, SEM, EDS, TEM, and AFM techniques. In addition, a pin-on-disk tribological test was used to measure coefficient of friction. Results indicated that samples deposited at 400°C contained higher cubic phase of BN compared to those films deposited at room temperature. A BN film containing cubic phase deposited at 400°C for 2 hours showed 0.1 friction coefficient.

In this thesis, we are making a new approach to fabricate silicon on insulator (SOI). By replacing the buried silicon dioxide and the silicon handling wafer with silicon carbide through hydrophilic wafer bonding, we have achieved silicon on crystalline silicon carbide for the first time and silicon on polycrystalline silicon carbide substrates at 150 mm wafer size. The conditions for the wafer bonding are studied and the surface and bond interface are characterized. Stress free and interfacial defect free hybrid wafer bonding has been achieved. The thermally unfavourable interfacial oxide that originates from the hydrophilic treatment has been removed through high temperature annealing, denoted as Ox-away. Based on the experimental observations, a model to explain the dynamics of this process has been proposed. Ox-away together with spheroidization are found to be the responsible theories for the behaviour. The activation energy for this process is estimated as 6.4 eV. Wafer bonding of Si and polycrystalline SiC has been realised by an intermediate layer of amorphous Si. This layer recrystallizes to some extent during heat treatment. Electronic and thermal testing structures have been fabricated on the 150 mm silicon on polycrystalline silicon carbide hybrid substrate and on the SOI reference substrate. It is shown that our hybrid substrates have similar or improved electrical performance and 2.5 times better thermal conductivity than their SOI counterpart. 2D simulations together with the experimental measurements have been carried out to extract the thermal conductivity of polycrystalline silicon carbide as κpSiC = 2.7 WK-1cm-1. The realised Si-on-SiC hybrid wafer has been shown to be thermally and electrically superior to conventional SOI and opens up for hybrid integration of silicon and wide band gap material as SiC and GaN.

The development of modern digital communication systems has been entered a new era with faster signal transmission and processing capability, called high-speed circuit systems. As their clock frequencies have increased and rise times of signals have decreased, the signal integrity of interconnects in the packaging and printed circuit boards plays a more and more important role. In high-speed circuit systems, the well-designed logic functions most likely will not work well if their interconnects are not taken into account.This dissertation addresses to profoundly understand the signal integrity knowledge, be proficient in calculation, simulation and measurements, and be capable of solving related signal integrity problems. The research mainly emphasizes on three aspects. First of all, the impact of on-wafer calibration methods on the measured results of coplanar waveguide circuits is comprehensively investigated, with their measurement repeatability and accuracy. Furthermore, a method is presented to characterize the physically-consistent broadband material properties for both rigid and flexible dielectric materials. Last but not least, a hybrid method for efficient modeling of three dimensional via structures is developed, in order to simplify the traditional 3D full-length via simulations and dramatically reduce the via build and simulation time and complexity.

In der vorliegenden Arbeit wird eine Methode zur Charakterisierung von Mikrosystemen mit beweglichen Komponenten dargestellt. Sie erlaubt, funktionsrelevante Parameter und deren Schwankungen produktionsbegleitend auf Waferlevel zu ermitteln. Dabei wird vorausgesetzt, dass die Sollform der Struktur und die Abweichungsarten bekannt sind. Die Methode beruht auf dem Vergleich von numerisch berechneten mit experimentell ermittelten Eigenfrequenzen der untersuchten Mikrosysteme. Dazu wird die Abhängigkeit verschiedener Eigenfrequenzen von den gesuchten Parametern mittels einer Parametervariationsanalyse berechnet und durch eine geeignete Funktion angenähert. Die Messung der dynamischen Eigenschaften erfolgt mit Hilfe eines Bewegungsanalysators, der auf einem Laser-Doppler-Vibrometer basiert. Im letzen Schritt werden die gesuchten Parameter berechnet. Kernpunkt der entwickelten Methode sind Messungen auf der Basis von speziellen Teststrukturen, die im Waferlayout neben den eigentlichen Nutzstrukturen platziert sind und parallel mit den Nutzstrukturen prozessiert werden. Es werden Algorithmen zur Generierung des Designs der Teststrukturen und ihrer Platzierung im Waferlayout entwickelt. Dabei werden das Design der Nutzstruktur und deren funktionsrelevante Parameter, der technologische Ablauf und materialspezifische Kennwerte berücksichtigt. Im Ergebnis liegt eine Bibliothek von Standard-Teststrukturen vor, die für produktionsbegleitende Messungen sowie für die Übertragbarkeit der Ergebnisse geeignet sind. Außerdem werden allgemeingültige Richtlinien zur Durchführung der Messungen an den Standard-Teststrukturen abgeleitet. Das Messverfahren wurde an unterschiedlichen Mikrosystemen mit beweglichen Komponenten überprüft und zu einer allgemeinen Messmethode für diese Klasse von Mikrosystemen erweitert
In this work a method for the characterization of microsystems with movable components is presented. The method allows to determine the relevant parameters and their variations on wafer level if the nominal shape of the structure and the type of deviations are known. The method is based on a comparison of the numerically calculated and experimentally measured Eigenfrequencies of the microsystems. For that purpose, the relationships between various Eigenfrequencies and the searched parameters are calculated by parameter variation analysis and the results of this analysis are approximated with appropriate functions. A Laser Doppler vibrometer based motion analyzer is used to determine the frequency response function of the micromechanical structure and extract Eigenfrequencies. The comparison of the measured and the calculated frequencies provides values for the searched parameters. The key element of the developed method is the measurement on special test structures that are placed in the wafer layout next to the actual microsystems and processed in the same technological process parallel to the actual microsystems. Algorithms for designing the test structures and their placement in the wafer layout are shown, taking into account the design of the actual microsystems and the function parameters of the technological process as well as material characteristics. As a result, a library of standard test structures for function relevant parameters is available. A general guideline for the measurement on the test structures is presented. The presented method is verified on various microsystems and extended to a whole class of microsystems with movable components

With increasing amount of user data and applications in wireless communication technology, demands are growing on performance and fabrication costs. One way to decrease cost is to integrate the building blocks in an RF system where digital blocks and high power amplifiers then are combined on one chip. This thesis presents LDMOS transistors integrated in a 65 nm CMOS process without adding extra process steps or masks. High power performance of the LDMOS is demonstrated for an integrated WLAN-PA design at 2.45 GHz with 32.8 dBm output power and measurements also showed that high output power is achievable at 5.8 GHz. For the first time, this kind of device is moreover demonstrated at X-band with over 300 mW/mm output power, targeting communication and radar systems at 8 GHz. As SOI is increasing in popularity due to better device performance and RF benefits, the buried oxide can cause thermal problems, especially for high power devices. To deal with self-heating effects and decrease the RF substrate losses further, this thesis presents a hybrid substrate consisting of silicon on top of polycrystalline silicon carbide (Si-on-poly-SiC). This hybrid substrate utilizes the high thermal conductivity of poly-SiC to reduce device self-heating and the semi-insulating properties to reduce RF losses. Hybrid substrates were successfully fabricated for the first time in 150 mm wafer size by wafer bonding and evaluation was performed in terms of both electrical and thermal measurements and compared to a SOI reference. Successful LDMOS transistors were fabricated for the first time on this type of hybrid substrate where no degradation in electrical performance was seen comparing the LDMOS to identical transistors on the SOI reference. Measurements on calibrated resistors showed that the thermal conductivity was 2.5 times better for the hybrid substrate compared to the SOI substrate. Moreover, RF performance of the hybrid substrate was investigated and the semi-insulating property of poly-SiC showed to be beneficial in achieving a high equivalent substrate parallel resistance and thereby low substrate losses. In a transistor this would be equal to better efficiency and output power. In terms of integration, the hybrid substrate also opens up the possibility of heterogeneous integration where silicon devices and GaN devices can be fabricated on the same chip.

La rentabilité des cellules à base de silicium est un point essentiel pour le marché photovoltaïque et cela passe notamment par l'amélioration du rendement électrique, la baisse des coûts de production ainsi que le renforcement de la fiabilité/durabilité des wafers. Des procédés innovants émergent, qui permettent d'obtenir des wafers ultra minces avec moins de perte de matière première. Cependant il est nécessaire de mettre en place des méthodes de caractérisation afin d’analyser la rigidité et la tenue mécanique de ces matériaux. Dans ce travail, des essais de flexion ont été effectués pour caractériser à la fois la rigidité et la rupture. Afin d’étudier la rupture fragile, une caméra rapide a été utilisée, des analyses fractographiques ont été menées. La diffraction d'électrons rétrodiffusés et la diffraction par rayon X de Laue ont été utilisées afin d'explorer le lien entre les orientations cristallographiques et les comportements observés. Conjointement, des simulations numériques EF ont été mise en place. Grâce à ce couplage expériences-simulations numériques, une caractérisation fiable de la rigidité des wafers a été effectuée. Une stratégie d'identification de l'origine de la rupture est également proposée. L'étude de la rupture du silicium monocristallin a mis en évidence la stabilité du clivage (110), la grande vitesse d'amorçage de la fissure, la dépendance de la forme du front de fissure à la vitesse de propagation ainsi que l'apparition de "Front Waves" pour les fissures à très grande vitesse. L'étude de la rupture des wafers multi-cristallins démontre une fissuration intra-granulaire. Des éprouvettes jumelles ont permis d’étudier la répétabilité du chemin de fissuration : une attention particulière a été portée à la nature des plans de clivage ainsi que l'effet des joints de grains. Enfin, une modélisation par la méthode des éléments finis étendus est proposée. Elle permet de reproduire le chemin de fissuration expérimentalement observé
The profitability of silicon solar cells is a critical point for the PV market and it requires improved electrical performance, lower wafer production costs and enhancing reliability and durability of the cells. Innovative processes are emerging that provide thinner wafers with less raw material loss. But the induced crystallinity and distribution of defects compared to the classical wafers are unclear. It is therefore necessary to develop methods of microstructural and mechanical characterization to assess the rigidity and mechanical strength of these materials. In this work, 4-point bending tests were performed under quasi-static loading. This allowed to conduct both the stiffness estimation and the rupture study. A high speed camera was set up in order to track the fracture process thanks to a 45° tilted mirror. Fractographic analysis were performed using confocal optical microscope, scanning electron microscope and atomic force microscope. Electron Back-Scatter Diffraction and Laue X-Ray diffraction were used to explore the relationship between the microstructural grains orientations/textures of our material and the observed mechanical behavior. Jointly, finite element modeling and simulations were carried out to provide auxiliary characterization tools and help to understand the involved fracture mechanism. Thanks to the experiment-simulation coupled method, we have assessed accurately the rigidity of silicon wafers stemming from different manufacturing processes. A fracture origin identification strategy has been proposed combining high speed imaging and post-mortem fractography. Fracture investigations on silicon single crystals have highlighted the deflection free (110) cleavage path, the high initial crack velocity, the velocity dependent crack front shape and the onset of front waves in high velocity crack propagation. The investigations on the fracture of multi-crystalline wafers demonstrate a systematic transgranular cracking. Furthermore, thanks to twin multi-crystalline silicon plates, we have addressed the crack path reproducibility. A special attention has been paid to the nature of the cleavage planes and the grain boundaries barrier effect. Finally, based on these observations, an extended finite element model (XFEM) has been carried out which fairly reproduces the experimental crack path

À l'ère des technologies de l'information, nous assistons à une augmentation continue du volume de données échangées. Celle-ci s'accompagne d'un besoin constant d'augmenter la bande passante des systèmes de communications optiques et radio-fréquences. Cette demande continue d'augmentation de la bande passante nécessite la conceptions de circuits toujours plus rapides capables de supporter la demande croissante de trafic de données. Ces circuits doivent eux-même s'appuyer sur des technologies de composants électroniques toujours plus rapides. C'est dans ce contexte que sont développés les transistors bipolaires à double hétérojonction (TBDH) en InP/InGaAs. Grâce aux propriétés des semi-conducteurs III-V, ces composants sont capable de fonctionner à des fréquences très élevées (> 500 GHz) tout en maintenant une tension de claquage relativement élevé (> 4V).Les travaux de cette thèse portent sur l'amélioration des performances de ces composants. Nous commencerons par nous intéresser à l'amélioration des mesures haute-fréquences des transistors afin de pouvoir évaluer leurs performances fréquentielles. Nous détaillerons les différents choix associées aux mesures (calibration, de-embedding, modèle de pointes RF) et proposerons des nouveaux plots de mesure. Dans un second temps, nous développerons un modèle analytique tenant comptes des spécifités du dessin et de la technologie du composant. Une fois calibré sur des mesures, celui-ci servira à déterminer les principaux axes d'amélioration des performances. Ensuite nous étudierons les performances de plusieures structures épitaxiales dans le but de réduire le temps de transit des électrons tout en maximisant les performances fréquentielles. Une nouvelle structure, optimisée pour maximiser la fréquence transition, sans dégrader la fréquence maximale d'oscillation, sera proposée. Par la suite nous étudierons les phénomènes physiques qui limitent la tension de claquage du transistor. Enfin, nous nous intéresserons au phénomène d'auto-échauffement qui dégrade les performances du transistor. Nous proposerons une modélisation de la résistance thermique et les pistes d'améliorations associées
In the era of information technology, we are witnessing a continuous increase in the volume of exchanged data. This comes with a constant need to enhance the bandwidth of optical and radio-frequency communication systems. The ongoing demand for increased bandwidth requires the design of faster circuits capable of supporting the growing data traffic. These circuits, in turn, must rely on ever-faster electronic component technologies. It is in this context that double-heterojunction bipolar transistors (DHBTs) in InP/InGaAs are developed. Thanks to the properties of III-V semiconductors, these components can operate at very high frequencies (> 500 GHz) while maintaining a relatively high breakdown voltage (> 4V).This thesis focus on improving the performance of these components. We will begin by addressing the improvement of high-frequency measurements of transistors to evaluate their frequency performance. We will delve into various choices associated with measurements (calibration, de-embedding, RF probe models) and introduce new measurement pads. In the second part, we will develop an analytical model, taking into account the specifics of the design and technology of the component. Once calibrated on measurements, this model will be used to determine the main axes for improving performance. Next, we will study the performance of several epitaxial structures with the aim of reducing electron transit time while maximizing frequency performance. A new structure, optimized to maximize the transition frequency without degrading the maximum oscillation frequency, will be proposed. Subsequently, we will investigate the physical phenomena limiting the breakdown voltage of the transistor. Finally, we will focus on the self-heating phenomenon that degrades transistor performance. We will propose a thermal resistance model and associated improvement strategies

碩士
逢甲大學
化學工程學所
96
The aim of this study was to fix the antibodies on the substrates with different ways of bonding. A self-assembled monolayer(SAM) was firmly formed on the surface of silicon wafer through chemistry absorbed or bonding. Its interactive bonding was includes Vander Waals forces and Hydrogen bonds. First, a heating treats the surface of wafer to form O-H bonds on the wafer surface, then self-assembled monolayer on silane molecule 3-Aminopropyl trimethoxysilane (APTMS) was formed on modify silicon wafer. We activated the adipic acid carboxyl and adipoyl chloride COCl base respectively, then bonding those with the amine base of APTMS. The same process was applied to the bonding process of the Rabbit anti-mouse IgG-FITC on silicon wafer. In order to demonstrated the self-assembled APTMS monolayer film on substrate. The modify silicon wafer immersed in goldnano solution, the amine base have good affinity effects to absorb goldnano particles. The surface morphology of these layers was studied by the atomic force microscope (AFM). The fluorescence measurement of antibodies was by fluorescent microscope. The parts of adipic acid conjugated rabbit anti-mouse IgG-FITC (IgG), the fluorescence effects are still unclear, which means antibodies oneself fluorescence effects was weak after fluorescence emission. Before the adipic acid conjugated fluorescence antibodies, it was dark on silicon wafer totally. On the parts of adipoyl chloride conjugated IgG, it gave a clear picture of a fluorescence microscope, this work demonstrated the fluorescence antibodies conjugate on the silicon wafer. Furthermore, we utilize a modifying probe by silane molecule APTMS self-assembled, to measurements the surface morphology of fluorescence antibodies layers on the silicon wafer. This work demonstrated the modify probe with the amine base has good affinity effects on carboxyl of fluorescence antibodies. The kind of affinity effect was a help to the surface morphology by AFM measurements.

碩士
國立臺南大學
材料科學系碩士班
101
Low conversion efficiency is still the main limiting factor for current solar cells. Most of the energy loss during solar cell operation is attributed to light reflection. To reduce the light reflection, we can change the path of light entering the solar-cell. In addition, to increase the energy conversion efficiency, light trapping is a key point to the cell structure. We can increase light trapping by a textured transparent conduction oxide (TCO) layer. Because the textured films can enhance the light trapping, the textured TCO films can get thinner compared with the thicker flat films. There are two parts in this study. First, we etched the pyramidal structure on silicon wafer to get the hierarchical structure by an electroless metal deposition-assisted etching method. We changed the Ag deposition time, etching temperature, HF concentration, H2O2 concentration and etching time, and discussed the influence of the different parameters on the structure and optical properties of the silicon wafer. Second, we used a sol-gel method to get the textured ZnO films. We changed sol-gel concentration, different preheat temperature, different heat treatment temperature, to discuss the influence of different parameter on the preparation of wrinkles films. Then we got high transmittance, high haze, low resistivity by coating FTO films on ZnO films. We showed the lowest reflectance about 1.7 % at wavelength 550 nm by moderating the H2O2 concentration during Si etching. By changing zinc oxide concentration, we showed the best result of about 72.2 % haze, 83 % transmittance and sheet resistance 44 Ω/□. ZnO wrinkles will be impressed by the doping of Al and their dimensions get flatter, resulting the ZnO films with a lower haze.

碩士
國立中山大學
電機工程學系研究所
96
This thesis devotes to develop a wafer-level packaging technique of the planar AgCl-based micro reference electrode and to investigate its various electrochemical characteristics (including the potential stability and offset voltage, AC impedance, cyclic-voltammetry analysis, electrochemical noise and reproducibility). The miniaturized all-solid-state reference electrode can integrated with many biomedical or biochemical sensors for substantially reduce the dimension of the whole sensing system and improve the commercial capability of portable detecting products. This study reports firstly a smallest module of the micro reference electrode with dimension only about 9 mm (L) × 6 mm (W) × 1 mm (H) in the worldwide using the silicon bulk-micromachining technology, thin film deposition and chloridation techniques. The packaged reference electrode module is constructed by two bonded wafers with different functions. One wafer of this module is defined as “electrode chip” and it has a Ti/Pd/Ag/AgCl planar quasi-reference electrode deposited on its surface. Another wafer is called as “packaging chip” and it has two bulk-micromachined silicon cavities for the filling/sealing of 1.33 ~ 6.40 μL KCl-gel (as the salt-bridge of electrode) and electrical connection. Many electrochemical characteristics of the encapsulated solid-state micro reference electrode are tested and improved for the commercial applications. Including a very stable cell potential (<4 mV in 30000 sec.), an approximately zero offset-voltage, a low AC impedance (1~20 KΩ), and high reproducibility (drift less than 3~8 mV in 30000 sec. and the range of offset voltage is -6 ~ 3 mV) of the packaged micro reference electrode are demonstrated. Furthermore, stable CV curve of the packaged Ti/Pd/Ag/AgCl/KCl-gel reference electrode were proved by cyclic-voltammetry analysis and its low electrochemical noise spectrum was investigated and discussed in this work. Compared with the commercial reference electrode, the planar miniaturized AgCl reference electrode module developed in this thesis has displayed its many excellent characteristics and with a dimension only 250 times smaller than the conventional reference electrode.

碩士
國立臺灣科技大學
材料科學與工程系
100
This study consisted of two parts, the first one was the fabrication of polymer brushes on silicon wafer, including surface hydrophilic modification, the synthesis of the silane self assembly monolayer (SAM), the immobilization of the initiator of polymerization, and the polymerization of Poly(glycidyl methacrylate) brushes (PGMA) initiated from the surface of silicon wafer via atom transfer radical polymerization (ATRP). By varying the polymerization time, we achieved different thickness of PGMA brushes between 15.7 and 110.0nm. Chemical analysis by Fourier transform infrared spectroscope (FT-IR) and Electron spectroscopy for chemical analysis system (ESCA) demonstrated the surface after ATRP contained lots of C-H and C-O/C=O bonds, and the content of carbon and oxygen was 71.68% and 28.04%. Atomic force microscope (AFM) analysis showed the roughness increased from 0.202nm to 1.056nm after ATRP. Additionally, we used the linear photoresist-modified wafers fabricated by lithography to form the silane SAM, and the photoresist was removed prior to immobilize the ATRP initiator. Sequentially, we synthesized the patterned PGMA brushes with difference height and width by varying the reaction time of ATRP and the scales of the photoresist. AFM analysis showed the maximum height of linear pattern reached to 113.1nm. 　　High reactivity of the epoxy ring on the PGMA side chain makes it a good position for ring-opening addition reaction. The second part of this study included the synthesis of the hydroxyl-capped Cadmium sulfide, and took it as a nucleophile to bind to the epoxy ring on PGMA. Thus, we obtained the fluorescent patterned PGMA brushes. The particle size of CdS obtained by Field emission transmission electron microscope (TEM) image was 5nm, and the 578nm emission light was analyzed by Photoluminescence spectrometry (PL). ESCA analysis showed the content of cadmium and sulfur was 2.68% and 3.79% from the CdS-PGMA brushes. Finally, Spectral confocal and multiphoton system (SCMS) imaged the different width fluorescent patterns, and demonstrated CdS was bound to the patterned PGMA brushes.

碩士
元智大學
通訊工程學系
97
This thesis improves the LST（Line-Series-shunT） calibration technique of resistor which must be lumped device, and can be achieves for on-wafer S-parameter measurement of GaAs 0.15 p-HEMT devices. In addition, characteristic impedance of the transmission line also is be evaluated. The DUT of real characteristic data finally can be extracted by the method of characteristic impedance mapping. Goal of the thesis is completed for accuracy improvement for LST calibration technique. Besides, original LST calibration technique presents a method of getting characteristic impedance of the transmission line by self-calibration. The method is be demonstrated for on-wafer S-parameter measurement of TSMC 0.18 CMOS devices in millimeter wave regions.