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Готові списки джерел за темами / On-Wafer characterization

Добірка наукової літератури з теми "On-Wafer characterization"

Автор: Grafiati

Опубліковано: 7 липня 2024

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Статті в журналах з теми "On-Wafer characterization":

1

Saedon, Juri B., Siti Musalmah Md Ibrahim, Amir Radzi Abd Ghani, and Muhammad Hafizi Bin Abd Razak. "Dicing Characterization on Optical Silicon Wafer Waveguide." Applied Mechanics and Materials 899 (June 2020): 163–68. http://dx.doi.org/10.4028/www.scientific.net/amm.899.163.

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Silicon wafers are a key component in integrated circuits which comprised of various electronic components that are arranged to perform a specific function. Wafer dicing is a mechanical process of removing material from a wafer by synthetic diamonds as abrasive particles. Chipping along the cut line crucial to the wafer dicing operation has been identified by semiconductor manufacturers as a relevant area for improvement. The purposed of this study is to characterize the effect of dicing operation on the optical silicon wafer coating material. The effect of the blade wear and silicon wafer kerf width will be analyzed in this work

2

Koolen, M. C. A. M. "On-wafer high-frequency device characterization." Microelectronic Engineering 19, no. 1-4 (September 1992): 679–86. http://dx.doi.org/10.1016/0167-9317(92)90521-r.

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3

Lau, J. H., P.-J. Tzeng, C.-K. Lee, C.-J. Zhan, M.-J. Dai, Li Li, C.-T. Ko, et al. "Wafer Bumping and Characterizations of Fine-Pitch Lead-Free Solder Microbumps on 12” (300mm) wafer for 3D IC Integration." International Symposium on Microelectronics 2011, no. 1 (January 1, 2011): 000650–56. http://dx.doi.org/10.4071/isom-2011-wa6-paper2.

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In this study, the wafer bumping and characterization of fine-pitch lead-free solder microbumps on 300mm wafer for 3D IC integration are investigated. Emphasis is placed on the Cu-plating solutions (conformal and bottom-up). Also, the amount of Cu and solder (Sn) volumes is examined. Furthermore, characterizations such as shearing test and aging of the microbumps are provided and cross sections/SEM images of the microbumps before and after test are discussed. Finally, the process windows of applying the conventional electroplating wafer bumping method of the ordinary solder bumps to the microbumps are also presented.

4

Teixeira, Jorge, Mário Ribeiro, and Nélson Pinho. "Advanced warpage characterization for FOWLP." International Symposium on Microelectronics 2013, no. 1 (January 1, 2013): 000641–46. http://dx.doi.org/10.4071/isom-2013-wp21.

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Current standards for silicon wafers shape characterization use simple metrics. Warpage and bow are computed as the mean surface wafer height range or the mean surface wafer center height, respectively [1]. These metrics are valid for silicon wafers because of their homogenous and linear thermomechanical properties [2]. In fan-out wafer level package (FO-WLP), embedded Wafer Level Ball Grid Array in specific (eWLB), the use of epoxy mold compound that works both as the physical carrier of the dies and as the base of second level connections has a major impact on the overall macroscopic behavior of the wafer, inducing shapes that do not follow a simple bended or bowed wafer, impacting wafer processability [3]. Warped wafers can affect device performance, reliability, and linewidth control in various processing steps [3]. Early detection will minimize cost and processing time. In our research, we present a solution for wafer characterization in FO-WLP by increasing the information vector that one obtains from standard automated non-contact scanning equipment. For this, we defined wafer shape and wafer ratio as the two new metrics besides warpage, creating a three dimensional vector that can be used to compare and evaluate wafers in high volume production or even single wafer analysis. This is a major improvement over previously used approaches, in which only the average warpage is considered. These metrics were determined by the developed numeric algorithm and their validity was demonstrated through the use of different production conditions, wafer constructions and production monitoring. The proposed approach requires no extra processing steps and time, as compared to conventional off-line methods. Experimental results demonstrate its feasibility and repeatability. This methodology was successfully used in the field and proved to be of high value when evaluating wafer geometrical requirements for both product development and process monitoring.

5

Kerepesi, Péter, Bernhard Rebhan, Matthias Danner, Karin Stadlmann, Heiko Groiss, Peter Oberhumer, Jiri Duchoslav, and Kurt Hingerl. "Oxide-Free SiC-SiC Direct Wafer Bonding and Its Characterization." ECS Transactions 112, no. 3 (September 29, 2023): 159–72. http://dx.doi.org/10.1149/11203.0159ecst.

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In this study, the feasibility of oxide-free room temperature wafer bonding process was demonstrated for 4H-SiC wafers with in situ surface oxide removal. The investigations covered three areas: incoming metrology of the original wafer, characterization of activated single wafer and analysis of bonded wafer pairs. The focus was on compositional, chemical, mechanical and morphological analysis of the surfaces and of the bonded interfaces. Incoming wafers were inspected whether they fulfill the requirements of wafer bonding, and activated wafers were characterized to measure the surface modifications. The quality of the bonded wafers and the bonding energy were verified using scanning acoustic microscopy measurements as well as the Maszara blade test. Furthermore, cross-section transmission electron microscopy was used to investigate the amorphous layer at the bonding interface. The work reported is a demonstration of the capability of different characterization methods regarding SiC-SiC wafer bonding.

6

Deleniv, Anatoly, Andrei Vorobiev, and Spartak Gevorgian. "On-Wafer Characterization of Varactor Using Resonating Microprobes." IEEE Transactions on Microwave Theory and Techniques 56, no. 5 (May 2008): 1105–11. http://dx.doi.org/10.1109/tmtt.2008.921283.

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7

Laskar, J., J. J. Bautista, M. Nishimoto, M. Hamai, and R. Lai. "Development of accurate on-wafer, cryogenic characterization techniques." IEEE Transactions on Microwave Theory and Techniques 44, no. 7 (July 1996): 1178–83. http://dx.doi.org/10.1109/22.508659.

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8

Moore, B., M. Margala, and C. Backhouse. "Design of wireless on-wafer submicron characterization system." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13, no. 2 (February 2005): 169–80. http://dx.doi.org/10.1109/tvlsi.2004.840780.

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9

CHEN, CHIH-HUNG. "ACCURACY ISSUES OF ON-WAFER MICROWAVE NOISE MEASUREMENTS." Fluctuation and Noise Letters 08, no. 03n04 (December 2008): L281—L303. http://dx.doi.org/10.1142/s0219477508005136.

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The accuracy issues of on-wafer noise characterization for a linear noisy two-port are presented in this paper. It starts with the description of a microwave noise measurement system and the possible source of error due to the microwave power meter in the measurement system. With the description of noise characterization techniques, this paper reviews a couple of methods for noise parameter extraction to handle the errors in the measured noise powers, noise factors, and source admittances. It also presents the methods to extract the physical noise parameters and to take care of different source admittances in the hot and cold states for accuracy enhancement.

10

Seong, Inho, Jinho Lee, Sijun Kim, Youngseok Lee, Chulhee Cho, Jangjae Lee, Wonnyoung Jeong, Yebin You, and Shinjae You. "Characterization of an Etch Profile at a Wafer Edge in Capacitively Coupled Plasma." Nanomaterials 12, no. 22 (November 10, 2022): 3963. http://dx.doi.org/10.3390/nano12223963.

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Recently, the uniformity in the wafer edge area that is normally abandoned in the fabrication process has become important for improving the process yield. The wafer edge structure normally has a difference of height between wafer and electrode, which can result in a sheath bend, distorting important parameters of the etch, such as ionic properties, resulting in nonuniform etching. This problem nowadays is resolved by introducing the supplemented structure called a focus ring on the periphery of the wafer. However, the focus ring is known to be easily eroded by the bombardment of high-energy ions, resulting in etch nonuniformity again, so that the focus ring is a consumable part and must be replaced periodically. Because of this issue, there are many simulation studies being conducted on the correlation between the sheath structural characteristics and materials of focus rings to find the replacement period, but the experimental data and an analysis based on this are not sufficient yet. In this study, in order to experimentally investigate the etching characteristics of the wafer edge area according to the sheath structure of the wafer edge, the etching was performed by increasing the wafer height (thickness) in the wafer edge area. The result shows that the degree of tilt in the etch profile at the wafer edge and the area where the tilt is observed severely are increased with the height difference between the wafer and electrode. This study is expected to provide a database for the characteristics of the etching at the wafer edge and useful information regarding the tolerance of the height difference for untilted etch profile and the replacement period of the etch ring.

Більше джерел

Дисертації з теми "On-Wafer characterization":

1

Lee, Jun Seok. "On-Wafer Characterization of Electromagnetic Properties of Thin-Film RF Materials." The Ohio State University, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=osu1308311479.

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2

Cabbia, Marco. "(Sub)-millimeter wave on-wafer calibration and device characterization." Thesis, Bordeaux, 2021. http://www.theses.fr/2021BORD0017.

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Les mesures de précision jouent un rôle crucial dans l'électronique, en particulier dans la caractérisation des transistors bipolaires à hétérojonction (HBT) à base de silicium embarqués dans des dispositifs pour applications THz utilisant la technologie BiCMOS. Grâce aux innovations récentes en termes de fabrication de technologies à l'échelle nanométrique, les dispositifs capables de fonctionner dans la région des ondes submillimétriques deviennent une réalité et doivent répondre à la demande de circuits et de systèmes haute-fréquence. Pour disposer de modèles précis à de telles fréquences, il n'est plus possible de limiter l'extraction des paramètres en dessous de 110 GHz, et de nouvelles techniques permettant d'obtenir des mesures fiables de dispositifs passifs et actifs doivent être étudiées.Dans cette thèse, nous examinerons la caractérisation des paramètres S sur silicium (on-wafer) de différentes structures de test passives et des HBT SiGe en technologie B55 de STMicroelectronics, jusqu'à 500 GHz. Nous commencerons par une introduction de l'équipement de mesure habituellement utilisé pour ce type d'analyse, puis nous passerons aux différents bancs de mesure adoptés au laboratoire IMS, et enfin nous nous concentrerons sur les techniques de calibrage et d’épluchage (de-embedding), en passant en revue les principales criticités de la caractérisation haute-fréquence et en comparant deux algorithmes de calibrage on-wafer (SOLT et TRL) jusqu'à la bande WR-2.2.Deux cycles de production de photomasques pour la caractérisation on-wafer, tous deux conçus à l'IMS, seront présentés: nous introduirons un nouveau design du floorplan et évaluerons sa capacité à limiter les effets parasites ainsi que l'effet de son environnement (substrat, structures voisines et diaphonie). Pour notre analyse, nous nous appuierons sur des simulations électromagnétiques et des simulations EM mixtes de modèle compacte + sonde, toutes deux incluant les modèles des sonde pour une évaluation des résultats de mesure plus proche des conditions réelles.Enfin, nous présenterons quelques structures de test pour évaluer les impacts indésirables sur les mesures d'ondes millimétriques et de nouvelles solutions de conception de lignes de transmission. Deux designs prometteurs seront soigneusement étudiées: le "layout M3", qui vise à caractériser le DUT dans un étalonnage à un seul niveau, et les "lignes à méandre", qui maintiennent la distance entre les deux sondes constante en évitant tout déplacement pendant les mesures sur silicium
Precision measurements play a crucial role in electronic engineering, particularly in the characterization of silicon-based heterojunction bipolar transistors (HBTs) embedded into devices for THz applications using the BiCMOS technology. Thanks to ongoing innovations in terms of nanoscale technology manufacturing, devices capable of operating in the sub-millimeter wave region are becoming a reality, and need to support the demand for high frequency circuits and systems. To have accurate models at such frequencies, it is no longer possible to limit the parameter extraction below 110 GHz, and new techniques for obtaining reliable measurements of passive and active devices must be investigated.In this thesis, we examine the on-wafer S-parameters characterization of various passive test structures and SiGe HBTs in STMicroelectronics' B55 technology, up to 500 GHz. We start with an introduction of the measuring equipment usually employed for this type of analysis, then moving on to the various probe stations adopted at the IMS Laboratory, and finally focusing on calibration and deembedding techniques, reviewing the major criticalities of high-frequency characterization and comparing two on-wafer calibration algorithms (SOLT and TRL) up to the WR-2.2 band.Two photomask production runs for on-wafer characterization, both designed at IMS, are considered: we introduce a new floorplan design and evaluate its ability to limit parasitic effects as well as the effect of the environment (substrate, neighbors, and crosstalk). For our analysis, we rely on electromagnetic simulations and joint device model + probe EM simulations, both including probe models for an evaluation of measurement results closer to real-world conditions.Finally, we present some test structures to evaluate unwanted impacts on millimeter wave measurements and novel transmission line design solutions. Two promising designs are carefully studied: the "M3 layout", which aims to characterize the DUT in a single-tier calibration, and the "meander lines", which keeps the inter-probe distance constant by avoiding any sort of probe displacement during on-wafer measurements

3

Maranon, Walter. "Characterization of Boron Nitride Thin Films on Silicon (100) Wafer." Thesis, University of North Texas, 2007. https://digital.library.unt.edu/ark:/67531/metadc3942/.

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Cubic boron nitride (cBN) thin films offer attractive mechanical and electrical properties. The synthesis of cBN films have been deposited using both physical and chemical vapor deposition methods, which generate internal residual, stresses that result in delamination of the film from substrates. Boron nitride films were deposited using electron beam evaporation without bias voltage and nitrogen bombardment (to reduce stresses) were characterize using FTIR, XRD, SEM, EDS, TEM, and AFM techniques. In addition, a pin-on-disk tribological test was used to measure coefficient of friction. Results indicated that samples deposited at 400°C contained higher cubic phase of BN compared to those films deposited at room temperature. A BN film containing cubic phase deposited at 400°C for 2 hours showed 0.1 friction coefficient.

4

Li, Ling-Guang. "Fabrication and Characterization of Si-on-SiC Hybrid Substrates." Doctoral thesis, Uppsala universitet, Fasta tillståndets elektronik, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-221664.

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In this thesis, we are making a new approach to fabricate silicon on insulator (SOI). By replacing the buried silicon dioxide and the silicon handling wafer with silicon carbide through hydrophilic wafer bonding, we have achieved silicon on crystalline silicon carbide for the first time and silicon on polycrystalline silicon carbide substrates at 150 mm wafer size. The conditions for the wafer bonding are studied and the surface and bond interface are characterized. Stress free and interfacial defect free hybrid wafer bonding has been achieved. The thermally unfavourable interfacial oxide that originates from the hydrophilic treatment has been removed through high temperature annealing, denoted as Ox-away. Based on the experimental observations, a model to explain the dynamics of this process has been proposed. Ox-away together with spheroidization are found to be the responsible theories for the behaviour. The activation energy for this process is estimated as 6.4 eV. Wafer bonding of Si and polycrystalline SiC has been realised by an intermediate layer of amorphous Si. This layer recrystallizes to some extent during heat treatment. Electronic and thermal testing structures have been fabricated on the 150 mm silicon on polycrystalline silicon carbide hybrid substrate and on the SOI reference substrate. It is shown that our hybrid substrates have similar or improved electrical performance and 2.5 times better thermal conductivity than their SOI counterpart. 2D simulations together with the experimental measurements have been carried out to extract the thermal conductivity of polycrystalline silicon carbide as κpSiC = 2.7 WK-1cm-1. The realised Si-on-SiC hybrid wafer has been shown to be thermally and electrically superior to conventional SOI and opens up for hybrid integration of silicon and wide band gap material as SiC and GaN.

5

Li, Qian. "SIGNAL INTEGRITY ANALYSIS ON MATERIALS AND VIA STRUCTURES MODELING AND CHARACTERIZATION." Diss., The University of Arizona, 2011. http://hdl.handle.net/10150/203472.

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The development of modern digital communication systems has been entered a new era with faster signal transmission and processing capability, called high-speed circuit systems. As their clock frequencies have increased and rise times of signals have decreased, the signal integrity of interconnects in the packaging and printed circuit boards plays a more and more important role. In high-speed circuit systems, the well-designed logic functions most likely will not work well if their interconnects are not taken into account.This dissertation addresses to profoundly understand the signal integrity knowledge, be proficient in calculation, simulation and measurements, and be capable of solving related signal integrity problems. The research mainly emphasizes on three aspects. First of all, the impact of on-wafer calibration methods on the measured results of coplanar waveguide circuits is comprehensively investigated, with their measurement repeatability and accuracy. Furthermore, a method is presented to characterize the physically-consistent broadband material properties for both rigid and flexible dielectric materials. Last but not least, a hybrid method for efficient modeling of three dimensional via structures is developed, in order to simplify the traditional 3D full-length via simulations and dramatically reduce the via build and simulation time and complexity.

6

Shaporin, Alexey. "Dynamic parameter identification techniques and test structures for microsystems characterization on wafer level." Doctoral thesis, Chemnitz Univ.-Verl, 2009. http://d-nb.info/1000815250/04.

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7

Shaporin, Alexey. "Dynamic parameter identification techniques and test structures for microsystems characterization on wafer level." Doctoral thesis, Universitätsbibliothek Chemnitz, 2010. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-200901902.

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In der vorliegenden Arbeit wird eine Methode zur Charakterisierung von Mikrosystemen mit beweglichen Komponenten dargestellt. Sie erlaubt, funktionsrelevante Parameter und deren Schwankungen produktionsbegleitend auf Waferlevel zu ermitteln. Dabei wird vorausgesetzt, dass die Sollform der Struktur und die Abweichungsarten bekannt sind. Die Methode beruht auf dem Vergleich von numerisch berechneten mit experimentell ermittelten Eigenfrequenzen der untersuchten Mikrosysteme. Dazu wird die Abhängigkeit verschiedener Eigenfrequenzen von den gesuchten Parametern mittels einer Parametervariationsanalyse berechnet und durch eine geeignete Funktion angenähert. Die Messung der dynamischen Eigenschaften erfolgt mit Hilfe eines Bewegungsanalysators, der auf einem Laser-Doppler-Vibrometer basiert. Im letzen Schritt werden die gesuchten Parameter berechnet. Kernpunkt der entwickelten Methode sind Messungen auf der Basis von speziellen Teststrukturen, die im Waferlayout neben den eigentlichen Nutzstrukturen platziert sind und parallel mit den Nutzstrukturen prozessiert werden. Es werden Algorithmen zur Generierung des Designs der Teststrukturen und ihrer Platzierung im Waferlayout entwickelt. Dabei werden das Design der Nutzstruktur und deren funktionsrelevante Parameter, der technologische Ablauf und materialspezifische Kennwerte berücksichtigt. Im Ergebnis liegt eine Bibliothek von Standard-Teststrukturen vor, die für produktionsbegleitende Messungen sowie für die Übertragbarkeit der Ergebnisse geeignet sind. Außerdem werden allgemeingültige Richtlinien zur Durchführung der Messungen an den Standard-Teststrukturen abgeleitet. Das Messverfahren wurde an unterschiedlichen Mikrosystemen mit beweglichen Komponenten überprüft und zu einer allgemeinen Messmethode für diese Klasse von Mikrosystemen erweitert
In this work a method for the characterization of microsystems with movable components is presented. The method allows to determine the relevant parameters and their variations on wafer level if the nominal shape of the structure and the type of deviations are known. The method is based on a comparison of the numerically calculated and experimentally measured Eigenfrequencies of the microsystems. For that purpose, the relationships between various Eigenfrequencies and the searched parameters are calculated by parameter variation analysis and the results of this analysis are approximated with appropriate functions. A Laser Doppler vibrometer based motion analyzer is used to determine the frequency response function of the micromechanical structure and extract Eigenfrequencies. The comparison of the measured and the calculated frequencies provides values for the searched parameters. The key element of the developed method is the measurement on special test structures that are placed in the wafer layout next to the actual microsystems and processed in the same technological process parallel to the actual microsystems. Algorithms for designing the test structures and their placement in the wafer layout are shown, taking into account the design of the actual microsystems and the function parameters of the technological process as well as material characteristics. As a result, a library of standard test structures for function relevant parameters is available. A general guideline for the measurement on the test structures is presented. The presented method is verified on various microsystems and extended to a whole class of microsystems with movable components

8

Jamshidifar, Mehran [Verfasser]. "On-wafer characterization of mm-wave and THz circuits using electrooptic sampling / Mehran Jamshidifar." Siegen : Universitätsbibliothek der Universität Siegen, 2017. http://d-nb.info/112945326X/34.

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9

Lotfi, Sara. "Design and Characterization of RF-LDMOS Transistors and Si-on-SiC Hybrid Substrates." Doctoral thesis, Uppsala universitet, Fasta tillståndets elektronik, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-215390.

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With increasing amount of user data and applications in wireless communication technology, demands are growing on performance and fabrication costs. One way to decrease cost is to integrate the building blocks in an RF system where digital blocks and high power amplifiers then are combined on one chip. This thesis presents LDMOS transistors integrated in a 65 nm CMOS process without adding extra process steps or masks. High power performance of the LDMOS is demonstrated for an integrated WLAN-PA design at 2.45 GHz with 32.8 dBm output power and measurements also showed that high output power is achievable at 5.8 GHz. For the first time, this kind of device is moreover demonstrated at X-band with over 300 mW/mm output power, targeting communication and radar systems at 8 GHz. As SOI is increasing in popularity due to better device performance and RF benefits, the buried oxide can cause thermal problems, especially for high power devices. To deal with self-heating effects and decrease the RF substrate losses further, this thesis presents a hybrid substrate consisting of silicon on top of polycrystalline silicon carbide (Si-on-poly-SiC). This hybrid substrate utilizes the high thermal conductivity of poly-SiC to reduce device self-heating and the semi-insulating properties to reduce RF losses. Hybrid substrates were successfully fabricated for the first time in 150 mm wafer size by wafer bonding and evaluation was performed in terms of both electrical and thermal measurements and compared to a SOI reference. Successful LDMOS transistors were fabricated for the first time on this type of hybrid substrate where no degradation in electrical performance was seen comparing the LDMOS to identical transistors on the SOI reference. Measurements on calibrated resistors showed that the thermal conductivity was 2.5 times better for the hybrid substrate compared to the SOI substrate. Moreover, RF performance of the hybrid substrate was investigated and the semi-insulating property of poly-SiC showed to be beneficial in achieving a high equivalent substrate parallel resistance and thereby low substrate losses. In a transistor this would be equal to better efficiency and output power. In terms of integration, the hybrid substrate also opens up the possibility of heterogeneous integration where silicon devices and GaN devices can be fabricated on the same chip.

10

Zhao, Lv. "On the fracture of solar grade crystalline silicon wafer." Thesis, Lyon, 2016. http://www.theses.fr/2016LYSEI134/document.

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Анотація:

La rentabilité des cellules à base de silicium est un point essentiel pour le marché photovoltaïque et cela passe notamment par l'amélioration du rendement électrique, la baisse des coûts de production ainsi que le renforcement de la fiabilité/durabilité des wafers. Des procédés innovants émergent, qui permettent d'obtenir des wafers ultra minces avec moins de perte de matière première. Cependant il est nécessaire de mettre en place des méthodes de caractérisation afin d’analyser la rigidité et la tenue mécanique de ces matériaux. Dans ce travail, des essais de flexion ont été effectués pour caractériser à la fois la rigidité et la rupture. Afin d’étudier la rupture fragile, une caméra rapide a été utilisée, des analyses fractographiques ont été menées. La diffraction d'électrons rétrodiffusés et la diffraction par rayon X de Laue ont été utilisées afin d'explorer le lien entre les orientations cristallographiques et les comportements observés. Conjointement, des simulations numériques EF ont été mise en place. Grâce à ce couplage expériences-simulations numériques, une caractérisation fiable de la rigidité des wafers a été effectuée. Une stratégie d'identification de l'origine de la rupture est également proposée. L'étude de la rupture du silicium monocristallin a mis en évidence la stabilité du clivage (110), la grande vitesse d'amorçage de la fissure, la dépendance de la forme du front de fissure à la vitesse de propagation ainsi que l'apparition de "Front Waves" pour les fissures à très grande vitesse. L'étude de la rupture des wafers multi-cristallins démontre une fissuration intra-granulaire. Des éprouvettes jumelles ont permis d’étudier la répétabilité du chemin de fissuration : une attention particulière a été portée à la nature des plans de clivage ainsi que l'effet des joints de grains. Enfin, une modélisation par la méthode des éléments finis étendus est proposée. Elle permet de reproduire le chemin de fissuration expérimentalement observé
The profitability of silicon solar cells is a critical point for the PV market and it requires improved electrical performance, lower wafer production costs and enhancing reliability and durability of the cells. Innovative processes are emerging that provide thinner wafers with less raw material loss. But the induced crystallinity and distribution of defects compared to the classical wafers are unclear. It is therefore necessary to develop methods of microstructural and mechanical characterization to assess the rigidity and mechanical strength of these materials. In this work, 4-point bending tests were performed under quasi-static loading. This allowed to conduct both the stiffness estimation and the rupture study. A high speed camera was set up in order to track the fracture process thanks to a 45° tilted mirror. Fractographic analysis were performed using confocal optical microscope, scanning electron microscope and atomic force microscope. Electron Back-Scatter Diffraction and Laue X-Ray diffraction were used to explore the relationship between the microstructural grains orientations/textures of our material and the observed mechanical behavior. Jointly, finite element modeling and simulations were carried out to provide auxiliary characterization tools and help to understand the involved fracture mechanism. Thanks to the experiment-simulation coupled method, we have assessed accurately the rigidity of silicon wafers stemming from different manufacturing processes. A fracture origin identification strategy has been proposed combining high speed imaging and post-mortem fractography. Fracture investigations on silicon single crystals have highlighted the deflection free (110) cleavage path, the high initial crack velocity, the velocity dependent crack front shape and the onset of front waves in high velocity crack propagation. The investigations on the fracture of multi-crystalline wafers demonstrate a systematic transgranular cracking. Furthermore, thanks to twin multi-crystalline silicon plates, we have addressed the crack path reproducibility. A special attention has been paid to the nature of the cleavage planes and the grain boundaries barrier effect. Finally, based on these observations, an extended finite element model (XFEM) has been carried out which fairly reproduces the experimental crack path

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Книги з теми "On-Wafer characterization":

1

Rumiantsev, Andrej. On-Wafer Calibration Techniques Enabling Accurate Characterization of High-Performance Silicon Devices at the mm-Wave Range and Beyond. New York: River Publishers, 2022. http://dx.doi.org/10.1201/9781003338994.

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2

Symposium on Nondestructive Wafer Characterization for Compound Semiconductor Materials (1995 Reno, Nevada). Proceedings of the Symposium on Nondestructive Wafer Characterization for Compound Materials and the twenty-second State-of-the-Art Program on Compound Semiconductors (SOTAPOCS XXII). Pennington, NJ: Electrochemical Society, 1995.

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3

Rumiantsev, Andrej. On-Wafer Calibration Techniques Enabling Accurate Characterization of High-Performance Silicon Devices at the Mm-Wave Range. River Publishers, 2019.

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4

Rumiantsev, Andrej. On-Wafer Calibration Techniques Enabling Accurate Characterization of High-Performance Silicon Devices at the Mm-Wave Range and Beyond. River Publishers, 2022.

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Rumiantsev, Andrej. On-Wafer Calibration Techniques Enabling Accurate Characterization of High-Performance Silicon Devices at the Mm-Wave Range and Beyond. River Publishers, 2019.

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Rumiantsev, Andrej. On-Wafer Calibration Techniques Enabling Accurate Characterization of High-Performance Silicon Devices at the Mm-Wave Range and Beyond. River Publishers, 2022.

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7

Automatic RF Techniques Group Conference. 63rd Arftg Conference Digest, Spring 2004: Automatic RF Techniques Group: On Wafer Characterization, 11 June 2004, Fort Worth, TX. Institute of Electrical & Electronics Enginee, 2004.

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Rumiantsev, Andrej. On-Wafer Calibration Techniques Enabling Accurate Characterization of High-Performance Silicon Devices at the Mm-Wave Range and Beyond. River Publishers, 2022.

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9

Swaminathan, V. Proceedings of the Symposium on Nondestructive Wafer Characterization for Compound Materials and the Twenty-Second State-Of-The-Art Program on Compoun (Proceeding). Electrochemical Society, 1995.

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Частини книг з теми "On-Wafer characterization":

1

Rumiantsev, Andrej. "Verification Methods for On-Wafer Calibration." In On-Wafer Calibration Techniques Enabling Accurate Characterization of High-Performance Silicon Devices at the mm-Wave Range and Beyond, 89–96. New York: River Publishers, 2022. http://dx.doi.org/10.1201/9781003338994-7.

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2

Rumiantsev, Andrej. "Design of On-Wafer Calibration Standards." In On-Wafer Calibration Techniques Enabling Accurate Characterization of High-Performance Silicon Devices at the mm-Wave Range and Beyond, 51–67. New York: River Publishers, 2022. http://dx.doi.org/10.1201/9781003338994-5.

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3

Rumiantsev, Andrej. "Addressing Issues of On-Wafer Standards." In On-Wafer Calibration Techniques Enabling Accurate Characterization of High-Performance Silicon Devices at the mm-Wave Range and Beyond, 109–17. New York: River Publishers, 2022. http://dx.doi.org/10.1201/9781003338994-9.

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4

Heuermann, Holger, and Andrej Rumiantsev. "The Modified Ripple Test for On-Wafer S-Parameter Measurements." In On-Wafer Calibration Techniques Enabling Accurate Characterization of High-Performance Silicon Devices at the mm-Wave Range and Beyond, 234–38. New York: River Publishers, 2022. http://dx.doi.org/10.1201/9781003338994-32.

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5

Heuermann, Holger, Andrej Rumiantsev, and Steffen Schott. "Advanced On-Wafer Multiport Calibration Methods for Mono- and Mixed-Mode Device Characterization." In On-Wafer Calibration Techniques Enabling Accurate Characterization of High-Performance Silicon Devices at the mm-Wave Range and Beyond, 170–75. New York: River Publishers, 2022. http://dx.doi.org/10.1201/9781003338994-16.

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6

Rumiantsev, Andrej, Holger Heuermann, and Steffen Schott. "A Robust Broadband Calibration Method for Wafer-Level Characterization of Multiport Devices." In On-Wafer Calibration Techniques Enabling Accurate Characterization of High-Performance Silicon Devices at the mm-Wave Range and Beyond, 176–80. New York: River Publishers, 2022. http://dx.doi.org/10.1201/9781003338994-17.

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7

Rumiantsev, Andrej, Susan L. Sweeney, and Phillip L. Corson. "Comparison of On-Wafer Multiline TRL and LRM+ Calibrations for RF CMOS Applications." In On-Wafer Calibration Techniques Enabling Accurate Characterization of High-Performance Silicon Devices at the mm-Wave Range and Beyond, 194–98. New York: River Publishers, 2022. http://dx.doi.org/10.1201/9781003338994-22.

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8

Kukreja, R. S., and Raj N. Singh. "Synthesis and Characterization of C-N Thin Films Deposited on Si (100) Wafer by MPCVD." In Ceramic Transactions Series, 89–94. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2012. http://dx.doi.org/10.1002/9781118408162.ch9.

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9

Rumiantsev, A., G. Fisher, and R. Doerner. "Sensitivity Analysis of Wafer-Level Over-Temperature RF Calibration." In On-Wafer Calibration Techniques Enabling Accurate Characterization of High-Performance Silicon Devices at the mm-Wave Range and Beyond, 224–27. New York: River Publishers, 2022. http://dx.doi.org/10.1201/9781003338994-29.

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10

Rumiantsev, Andrej, and Ralf Doerner. "Verification of Wafer-Level Calibration Accuracy at High Temperatures." In On-Wafer Calibration Techniques Enabling Accurate Characterization of High-Performance Silicon Devices at the mm-Wave Range and Beyond, 219–23. New York: River Publishers, 2022. http://dx.doi.org/10.1201/9781003338994-28.

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Тези доповідей конференцій з теми "On-Wafer characterization":

1

Maya, Carmen, Antonio Lazaro, and Lluis Pradell. "On-wafer noise source characterization." In Second International Symposium on Fluctuations and Noise, edited by Francois Danneville, Fabrizio Bonani, M. Jamal Deen, and Michael E. Levinshtein. SPIE, 2004. http://dx.doi.org/10.1117/12.546375.

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2

Teodorescu, L., F. Drăghici, I. Rusu, and G. Brezeanu. "On-wafer high temperature characterization system." In Advanced Topics in Optoelectronics, Microelectronics, and Nanotechnologies 2016, edited by Marian Vladescu, Razvan Tamas, and Ionica Cristea. SPIE, 2016. http://dx.doi.org/10.1117/12.2247062.

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3

Galatro, L., and M. Spirito. "Calibration and characterization techniques for on-wafer device characterization." In 2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS). IEEE, 2015. http://dx.doi.org/10.1109/newcas.2015.7181978.

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4

Bodermann, Bernd, Egbert Buhr, Hans-Ulrich Danzebrink, Markus Bär, Frank Scholze, Michael Krumrey, Matthias Wurm, et al. "Joint Research on Scatterometry and AFM Wafer Metrology." In FRONTIERS OF CHARACTERIZATION AND METROLOGY FOR NANOELECTRONICS: 2011. AIP, 2011. http://dx.doi.org/10.1063/1.3657910.

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5

Messick, C. R., and T. E. Turner. "A Generic Test Structure Heater Design And Characterization." In International Report on Wafer Level Reliability Workshop. IEEE, 1992. http://dx.doi.org/10.1109/iwlr.1992.657988.

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6

Pham, A., J. Laskar, and J. Schappacher. "Development of On-Wafer Microstrip Characterization Techniques." In 47th ARFTG Conference Digest. IEEE, 1996. http://dx.doi.org/10.1109/arftg.1996.327168.

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Randa, J., D. Walker, L. Dunleavy, R. Billinger, and J. Rice. "Characterization of On-Wafer Diode Noise Sources." In 51st ARFTG Conference Digest. IEEE, 1998. http://dx.doi.org/10.1109/arftg.1998.327277.

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8

Bitincka, E., and M. K. Smit. "Novel On-wafer Technique for Loss Characterization." In Integrated Photonics Research, Silicon and Nanophotonics. Washington, D.C.: OSA, 2014. http://dx.doi.org/10.1364/iprsn.2014.im3a.4.

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Tsidilkovski, E., A. Bertuch, Erik M. Secula, David G. Seiler, Rajinder P. Khosla, Dan Herr, C. Michael Garner, Robert McDonald, and Alain C. Diebold. "The Effect of Surface Conditioning on Silicon Wafer Resistivity Monitoring." In FRONTIERS OF CHARACTERIZATION AND METROLOGY FOR NANOELECTRONICS: 2009. AIP, 2009. http://dx.doi.org/10.1063/1.3251246.

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10

Wang, Jason. "Controlling Wafer Contamination Using Automated On-Line Metrology during Wet Chemical Cleaning." In CHARACTERIZATION AND METROLOGY FOR ULSI TECHNOLOGY: 2003 International Conference on Characterization and Metrology for ULSI Technology. AIP, 2003. http://dx.doi.org/10.1063/1.1622486.

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