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Статті в журналах з теми "On-chip redundancy"
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Rozanov, V. V., and E. A. Suvorova. "VLSI AND SYSTEM-ON-CHIP REDUNDANT COMPONENTS SYNTHESIS." Issues of radio electronics, no. 8 (August 20, 2018): 33–39. http://dx.doi.org/10.21778/2218-5453-2018-8-33-39.
Повний текст джерелаАнотація:
Redundancy - mostly used method to increase fault tolerance of the system. Fault tolerance in modern embedded systems is important feature due to accelerating aging and manufacturing defects, which diagnosis during the chip testing at fabric is impossible. In addition, different ways of system using may need different degree of fault tolerance. From Application Specified Integrated Circuit (ASIC) design point of view redundancy means area and power increasing. On early design stages, it is necessary to see the correlation between the components hardware description and its synthesized equivalent. The article considers several variants of synthesized redundant components that show the effect on area and power regarding to their architecture. The main goal of presented research is to describe RTL and Synthesis correlation.
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Zhou, Xiaofeng, Lu Liu, and Zhangming Zhu. "A Fault-Tolerant Deflection Routing for Network-on-Chip." Journal of Circuits, Systems and Computers 26, no. 03 (2016): 1750037. http://dx.doi.org/10.1142/s0218126617500372.
Повний текст джерелаАнотація:
Network-on-Chip (NoC) has become a promising design methodology for the modern on-chip communication infrastructure of many-core system. To guarantee the reliability of traffic, effective fault-tolerant scheme is critical to NoC systems. In this paper, we propose a fault-tolerant deflection routing (FTDR) to address faults on links and router by redundancy technique. The proposed FTDR employs backup links and a redundant fault-tolerant unit (FTU) at router-level to sustain the traffic reliability of NoC. Experimental results show that the proposed FTDR yields an improvement of routing performance and fault-tolerant capability over the reported fault-tolerant routing schemes in average flit deflection rate, average packet latency, saturation throughput and reliability by up to 13.5%, 9.8%, 10.6% and 17.5%, respectively. The layout area and power consumption are increased merely 3.5% and 2.6%.
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Yu, Qiaoyan, Meilin Zhang, and Paul Ampadu. "Addressing network-on-chip router transient errors with inherent information redundancy." ACM Transactions on Embedded Computing Systems 12, no. 4 (2013): 1–21. http://dx.doi.org/10.1145/2485984.2485993.
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Li, Ran, Rui Ding, Zi Jian Min, and Hui Mei Yuan. "Design of Redundant Parallel Power Supply Based on Integrated DC/DC Modules." Applied Mechanics and Materials 229-231 (November 2012): 1568–71. http://dx.doi.org/10.4028/www.scientific.net/amm.229-231.1568.
Повний текст джерелаАнотація:
Taking into account the efficiency, cost-effectiveness and reliability of power supply, redundant parallel power supply controlled by microcontroller could be a good solution for us. This paper analyzes principles and traits of parallel current sharing structure. Then a design of redundancy parallel current sharing structure is introduced, which is based on integrated buck chip LM2678 and microcontroller MSP430. The design has good fault-tolerant ability, and its output voltage can be adjusted easily. The capability and feasibility of this design has been verified by the simulation and experiment.
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Cai, Bai-gen, Cheng-ming Jin, Lian-chuan Ma, Yuan Cao, and Hideo Nakamura. "Analysis on the application of on-chip redundancy in the safety-critical system." IEICE Electronics Express 11, no. 9 (2014): 20140153. http://dx.doi.org/10.1587/elex.11.20140153.
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Mohammed, Hala, Wameedh Flayyih, and Fakhrul Rokhani. "Tolerating Permanent Faults in the Input Port of the Network on Chip Router." Journal of Low Power Electronics and Applications 9, no. 1 (2019): 11. http://dx.doi.org/10.3390/jlpea9010011.
Повний текст джерелаАнотація:
Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of processing elements and memory modules to be integrated on a single chip forming multi/many-processor systems-on-chip (MPSoCs). Network on chip (NoC) arose as an interconnection for this large number of processing modules. However, the aggressive scaling of transistors makes NoC more vulnerable to both permanent and transient faults. Permanent faults persistently affect the circuit functionality from the time of their occurrence. The router represents the heart of the NoC. Thus, this research focuses on tolerating permanent faults in the router’s input buffer component, particularly the virtual channel state fields. These fields track packets from the moment they enter the input component until they leave to the next router. The hardware redundancy approach is used to tolerate the faults in these fields due to their crucial role in managing the router operation. A built-in self-test logic is integrated into the input port to periodically detect permanent faults without interrupting router operation. These approaches make the NoC router more reliable than the unprotected NoC router with a maximum of 17% and 16% area and power overheads, respectively. In addition, the hardware redundancy approach preserves the network performance in the presence of a single fault by avoiding the virtual channel closure.
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UPADHYAYA, SHAMBHU J., and I.-SHYAN HWANG. "DESIGN OF A MULTI-LEVEL FAULT-TOLERANT MESH (MFTM) FOR HIGH RELIABILITY APPLICATIONS." International Journal of Reliability, Quality and Safety Engineering 02, no. 04 (1995): 419–29. http://dx.doi.org/10.1142/s0218539395000290.
Повний текст джерелаАнотація:
This paper presents a novel technique for the enhancement of operational reliability of processor arrays by a multi-level fault-tolerant design approach. The key idea of the design is based on the well known hierarchical design paradigm. The proposed fault-tolerant architecture uses a flexible reconfiguration of redundant nodes, thereby offering a better spare utilization than existing two-level redundancy schemes. A variable number of spares is provided at each level of redundancy which enables a flexible reconfiguration as well as area efficient layouts and better spare utilization. The spare nodes at each level can replace any of the failed primary nodes, not only at the same level but also those at the lower levels. The architecture can be adopted to increase the system reliability in Multi Chip Modules (MCMs). The main contributions of our work are the higher degree of fault tolerance, higher overall reliability, flexibility, and a better spare utilization.
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Nasimi, Fahimeh, Mohammad Reza Khayyambashi, and Naser Movahhedinia. "Redundancy cancellation of compressed measurements by QRS complex alignment." PLOS ONE 17, no. 2 (2022): e0262219. http://dx.doi.org/10.1371/journal.pone.0262219.
Повний текст джерелаАнотація:
The demand for long-term continuous care has led healthcare experts to focus on development challenges. On-chip energy consumption as a key challenge can be addressed by data reduction techniques. In this paper, the pseudo periodic nature of ElectroCardioGram(ECG) signals has been used to completely remove redundancy from frames. Compressing aligned QRS complexes by Compressed Sensing (CS), result in highly redundant measurement vectors. By removing this redundancy, a high cluster of near zero samples is gained. The efficiency of the proposed algorithm is assessed using the standard MIT-BIH database. The results indicate that by aligning ECG frames, the proposed technique can achieve superior reconstruction quality compared to state-of-the-art techniques for all compression ratios. This study proves that by aligning ECG frames with a 0.05% unaligned frame rate(R-peak detection error), more compression could be gained for PRD > 5% when 5-bit non-uniform quantizer is used. Furthermore, analysis done on power consumption of the proposed technique, indicates that a very good recovery performance can be gained by only consuming 4.9μW more energy per frame compared to traditional CS.
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Sun, H., Q. Sun, S. Biereigel, et al. "A radiation tolerant clock generator for the CMS endcap timing layer readout chip." Journal of Instrumentation 17, no. 03 (2022): C03038. http://dx.doi.org/10.1088/1748-0221/17/03/c03038.
Повний текст джерелаАнотація:
Abstract We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low Power Gigabit Transceiver (lpGBT) project. The ljCDR is tested in its PLL mode. An automatic frequency calibration (AFC) block with the Triple Modular Redundancy (TMR) register is developed for the LC-oscillator calibration. The chip was manufactured in a 65 nm CMOS process with 10 metal layers. The chip has been extensively tested, including Total Ionizing Dose (TID) testing up to 300 Mrad and Single Event Upset (SEU) testing with heavy ions possessing a Linear Energy Transfer (LET) from 1.3 to 62.5 MeV × cm2/mg.
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Fei, Ji You, Hua Li, and Bin Gao. "Based on the Single Chip Microcomputer Atmega168 Robot Control System Design." Applied Mechanics and Materials 341-342 (July 2013): 700–703. http://dx.doi.org/10.4028/www.scientific.net/amm.341-342.700.
Повний текст джерелаАнотація:
based on the single chip microcomputer atmega168 robot control system design This paper introduces using micro controller, many sensors, such as ultrasonic distance measuring sensor, infrared range sensor, infrared obstacle avoidance sensor, and also using motor driving module and dc motor design a robot which can operate independently, The robot can detect its own attitude, obstacles, competition venues edge automatically, then according to signal which the sensor feedback to micro controller controlling the motor produce pushing or avoid action. In the design of the robot, we using the sensor redundancy design positioning obstacles in front of robot, we take full advantage of the proximity detector features in order to make the robot highly efficient and stable operation. The robot in the experiment operating in good condition, and it has reference significance for robot design.
Дисертації з теми "On-chip redundancy"
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Keller, Andrew Mark. "Using On-Chip Error Detection to Estimate FPGA Design Sensitivity to Configuration Upsets." BYU ScholarsArchive, 2017. https://scholarsarchive.byu.edu/etd/6302.
Повний текст джерелаАнотація:
SRAM-based FPGAs provide valuable computation resources and reconfigurability; however, ionizing radiation can cause designs operating on these devices to fail. The sensitivity of an FPGA design to configuration upsets, or its SEU sensitivity, is an indication of a design's failure rate. SEU mitigation techniques can reduce the SEU sensitivity of FPGA designs in harsh radiation environments. The reliability benefits of these techniques must be determined before they can be used in mission-critical applications and can be determined by comparing the SEU sensitivity of an FPGA design with and without these techniques applied to it. Many approaches can be taken to evaluate the SEU sensitivity of an FPGA design. This work describes a low-cost easier-to-implement approach for evaluating the SEU sensitivity of an FPGA design. This approach uses additional logic resources on the same FPGA as the design under test to determine when the design has failed, or deviated from its specified behavior. Three SEU mitigation techniques were evaluated using this approach: triple modular redundancy (TMR), configuration scrubbing, and user-memory scrubbing. Significant reduction in SEU sensitivity is demonstrated through fault injection and radiation testing. Two LEON3 processors operating in lockstep are compared against each other using on-chip error detection logic on the same FPGA. The design SEU sensitivity is reduced by 27x when TMR and configuration scrubbing are applied, and by approximately 50x when TMR, configuration scrubbing, and user-memory scrubbing are applied together. Using this approach, an SEU sensitivity comparison is made of designs implemented on both an Altera Stratix V FPGA and a Xilinx Kintex 7 FPGA. Several instances of a finite state machine are compared against each other and a set of golden output vectors, all on the same FPGA. Instances of an AES cryptography core are chained together and the output of two chains are compared using on-chip error detection. Fault injection and neutron radiation testing reveal several similarities between the two FPGA architectures. SEU mitigation techniques reduce the SEU sensitivity of the two designs between 4x and 728x. Protecting on-chip functional error detection logic with TMR and duplication with compare (DWC) is compared. Fault injection results suggest that it is more favorable to protect on-chip functional error detection logic with DWC than it is to protect it with TMR for error detection.
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Chenet, Cristiano Pegoraro. "Análise de soft errors em conversores analógico-digitais e mitigação utilizando redundância e diversidade." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/127693.
Повний текст джерелаАнотація:
Este trabalho aborda os soft errors em conversores de dados analógico-digitais e a mitigação usando redundância e diversidade. Nas tecnologias CMOS recentes, os efeitos singulares (SEEs, Single Event Effects) são um grupo de efeitos da radiação espacial que afetam a confiabilidade e disponibilidade dos sistemas. Os soft errors são SEEs que não danificam diretamente o sistema e podem ser posteriormente corrigidos. Seus principais subgrupos são o Single Event Upset (SEU), o Single Event Transient (SET) e o Single Event Functional Interrupt (SEFI). Uma das técnicas em nível de sistema amplamente usadas para proteger os circuitos eletrônicos desses efeitos é a Redundância Modular Tripla (TMR, Triple Modular Redundancy), que pode ainda ser melhorada com a adição da técnica de diversidade. Nesse contexto, esse trabalho adota um esquema baseado nessas duas técnicas para a implementação de um sistema de aquisição de dados (SAD) analógico-digital. Seus objetivos são observar o comportamento dos conversores de dados frente aos soft errors e avaliar a eficácia de um sistema baseado em TMR e diversidade espacial-temporal contra esses efeitos da radiação. A implementação desse SAD em um SoC (System-on-Chip) da Cypress Semiconductor, chamado PSoC 5LP e fabricado em tecnologia CMOS de 130 nm, propiciou a realização de dois estudos: no primeiro, é realizada a irradiação com nêutrons, caso de particular interesse para os equipamentos eletrônicos embarcados em aviões; e no segundo, são realizadas injeções de falhas por software e em tempo de execução nos registradores de controle dos periféricos e na SRAM do PSoC 5LP. O resultado da irradiação do primeiro estudo foi a não observância de erros, o que impediu cumprir os objetivos propostos para esse teste. Essa situação permitiu duas observações principais: primeiro, o fluxo de nêutrons do experimento é uma característica fundamental que impacta na capacidade de se observar os efeitos da radiação, principalmente quando a seção de choque do circuito em análise é baixa; e segundo, de que a probabilidade de ocorrerem mascaramentos de SETs nos circuitos combinacionais e analógicos é elevada, o que contribui significativamente para reduzir a sensibilidade desses circuitos. Para avaliar a eficácia do sistema baseado em TMR e diversidade espacial-temporal foi então realizada uma investigação teórica baseada em análise combinatória, e os resultados mostraram que a adição de diversidade temporal gera, em comparação ao TMR clássico, um ganho significativo na tolerância de falhas duplas e múltiplas, ao preço de um aumento do atraso do circuito. Os resultados das injeções de falhas por software e em tempo de execução nos registradores de controle dos periféricos e na SRAM mostraram que apenas um baixo percentual das falhas injetadas é detectado na forma de erros, convergindo para a justificativa de que os mascaramentos foram determinantes para a não observância de erros no primeiro estudo, de injeção de falhas por radiação. Também verificou-se que os registradores de controle dos periféricos são mais importantes no nível de aplicação do que os dados da memória SRAM. Considerações sobre a auto injeção de falhas e auto monitoramento sugerem que a utilização desses conceitos pode trazer diversas limitações e complicadores aos testes.<br>The present thesis addresses the soft errors in analog-to-digital data converters and mitigation of such errors using redundancy and diversity. In modern CMOS technologies, the Single Event Effects (SEEs) comprises an important group of space radiation effects that influence the reliability and availability of the systems. Soft errors are SEEs that do not directly damage the system and that can be further corrected. Their main subgroups are the Single Event Upset (SEU), the Single Event Transient (SET) and the Single Event Functional Interrupt (SEFI). One of the system level techniques broadly used to protect the electronic circuits against these effects is the Triple Modular Redundancy (TMR), which may be improved with the addition of the diversity technique. In this context, this work proposes a scheme based on these two techniques to implement a tolerant analog-to-digital data acquisition system (DAS). The main objectives are to observe the behavior of the data converters under soft errors, and evaluate the effectiveness of a system based on TMR and spatial-temporal diversity on mitigating these radiation effects. The implementation of this DAS in a Programmable SoC (System-on-Chip) from Cypress Semiconductor (PSoC 5LP) manufactured in 130 nm CMOS, allowed the development of two studies. In the first one, an irradiation with neutrons is performed, case of particular interest to electronic equipment embedded on planes. In the second study, runtime software fault injections are performed at the peripheral control registers and SRAM of the studied device. As a result from irradiation on the first study no errors were found, what does not allowed meet the objectives of this test. This situation allow two main observations: first, the neutron flux of the experiment is a key feature that influences the ability to observe the radiation effects, mainly when the cross section of the circuit in analysis is low; and second, the probability of occurring SETs masking in combinational and analog circuits is high, which contributes significantly to reduce the sensibility of these circuits. To evaluate the effectiveness of a system based on TMR and spatial-temporal diversity then was performed a theoretical investigation based on combinatorial analysis, and the results show that the addition of temporal diversity generates a significant gain in tolerating double and multiple faults, if compared to the classical TMR, at the price of an increase in the circuit delay. The results of the second study, performed by runtime software fault injections at the peripheral control registers and SRAM, showed that only a low percentage of injected faults is detected as errors, according to the justification that no errors were found on irradiation of neutrons due to masking. Also was verified that at the application level the peripheral control registers are more important than the data stored in the SRAM memory. Considerations for faults self-injection and self-monitoring were done, suggesting that the use of these concepts may bring numerous limitations to the test.
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Aguilera, Carlos Julio González. "Avaliação de conversores AD sob efeitos de radiação e mitigação utilizando redundância com diversidade." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2018. http://hdl.handle.net/10183/179530.
Повний текст джерелаАнотація:
Este trabalho aborda um sistema de aquisição de dados (SAD) analógico-digital, baseado em um esquema redundante com diversidade de projeto, que é testado em dois ambientes diferentes de radiação. O primeiro experimento considera um teste de dose total ionizante (Total Ioninzig Dose - TID) sob irradiação gama, e o segundo experimento considera os efeitos de eventos singulares (Single Event Effects - SEE) sob irradiação por íons pesados. O SAD é composto, principalmente, por três conversores analógicos-digitais (ADCs) e dois votadores. A técnica usada é a Redundância Modular Tripla (Triple Modular Redundancy - TMR), com implementação em diferentes níveis de diversidade (temporal e arquitetural). O sistema é construído em um System-on-Chip programável (PSoC 5LP) da Cypress Semiconductor, fabricado em tecnologia CMOS de 130nm. Para a irradiação com TID, se utiliza o PSoC de part number CY8CKIT-050 sob uma fonte de radiação gama de 60Co (cobalto-60), com uma taxa de dose efetiva de 1 krad(Si)/h por 10 dias, atingindo uma dose total de 242 krad(Si) Para SEE se utiliza o protótipo PSoC de part number CY8CKIT-059 (sem encapsulamento) em um acelerador de partículas 8UD Pelletron usando 16O (oxigeno-16) ao vácuo, com energia de 36 MeV em um LET aproximado de 5.5 MeV/mg/cm2 e uma penetração no silício de 25 mm, resultando em um fluxo de 354 p/cm2.s, e uma fluência de 5077915 p/cm2 depois de 14755 segundos (4h 09min). Observou-se com o resultado do primeiro estudo que um (1) dos módulos do sistema apresentou uma degradação significativa na sua linearidade durante a irradiação, enquanto os outros tiveram uma degradação menos grave, mantendo assim a funcionalidade e confiabilidade do sistema. Durante o tempo de irradiação do segundo estudo, foram observadas 139 falhas: 53 SEFIs (Single Events Funtional Interrupt), 29 falhas críticas e 57 falhas SDC (Silent Data Corruption), atingindo as diferentes copias do sistema e um dos votadores do mesmo, mas sempre mantendo a saída esperada. Nos dois experimentos se evidencia a vantagem de usar a diversidade de projeto, além do TMR, para melhorar a resiliência e confiabilidade em sistemas críticos redundantes que trabalham com sinais mistos.<br>This work presents an analog-to-digital data acquisition system (DAS) based on a redundant scheme with design diversity, being tested in two different radiation environments. The first experiment is a Total Ionizing Dose (TID) essay and the second one considers Single Event Effects (SEE) under heavy ion irradiation. The DAS is mainly composed of three analog-todigital converters (ADCs) and two voters. The used technique was the Triple Modular Redundancy (TMR) implementing different levels of diversity (temporal and architectural). The circuit was built in a programmable System-on-Chip (PSoC 5LP) from Cypress Semiconductor, fabricated in a 130nm CMOS technology process. For the irradiation with TID the part number CY8CKIT-050 PSoC was used under a 60Co (cobalt-60) gamma radiation source, with an effective dose rate of 1 krad(Si)/h during 10 days, reaching a total dose of 242 krad(Si). For SEE experiments the part number CY8CKIT-059 (without encapsulation) PSoC prototype under a 8UD Pelletron particle accelerator using 16O (oxigen-16) under vacuum, with an energy of 36 MeV, resulting in a flux of 354p/cm2.s and a fluence of 5077915p/cm2 after 14755 seconds (4h 09min). As result of the first study it was observed that one of the system’s modules presented a significant degradation in its linearity during the irradiation, while degradations in the other modules were not as deep, maintaining the system’s functionality and reliability. During the period of the radiation of the second study, 139 faults were observed, 82 of them were critical and 57 were SDC (Silent Data Corruption), reaching the different system copies and one of the voters, while always maintaining the correct output. The advantage of using diversity, besides TMR, to improve resilience and reliability in redundant systems working with mixed signals was demonstrated in both experiments.
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Djedidi, Oussama. "Modélisation incrémentale des processeurs embarqués pour l'estimation des caractéristiques et le diagnostic." Electronic Thesis or Diss., Aix-Marseille, 2019. http://www.theses.fr/2019AIXM0639.
Повний текст джерелаАнотація:
Les systèmes-sur-puce (Systems on Chip, SoC) sont de plus en plus embarqués dans des systèmes à risque comme les systèmes aéronautiques et les équipements de production d’énergie. Cette évolution technologique permet un gain de temps et de performance, mais présente des limites en termes de fiabilité et de sécurité. Ainsi, le développement d’outils de surveillance et de diagnostic des systèmes électroniques embarqués, en particuliers les SoC, est devenu l’un des verrous scientifiques à lever pour assurer une large utilisation de ces systèmes dans les équipements à risque en toute sécurité. Ce travail de thèse s’inscrit dans ce contexte, et a pour objectif le développement d’une approche de détection et identification des dérives des performances des SoC embarqués. L’approche proposée est basée sur un modèle incrémental, construit à partir de modules réutilisables et échangeables pour correspondre à la large gamme de SoC existants sur le marché. Le modèle est ensuite utilisé pour estimer un ensemble de caractéristiques relatives à l’état de fonctionnement du SoC. L’algorithme de diagnostic développé dans ce travail consiste à générer des indices de dérives par la comparaison en ligne des caractéristiques estimées à celles mesurées. L’évaluation des résidus et la prise de décision sont réalisées par des méthodes statistiques appropriées à la nature de chaque indice de dérive. L’approche développée a été validée expérimentalement sur des SoC différents, ainsi que sur un démonstrateur développé dans le cadre de ce travail. Les résultats expérimentaux obtenus, montrent l’efficacité et la robustesse de l’approche développée<br>Systems on Chip are increasingly embedded in safety-critical systems, such as aeronautical systems and energy production equipment. Such technological evolution allows for significant improvements in performance but presents limits in terms of reliability and security. Therefore, the development of new tools for the monitoring and diagnosis of embedded electronic systems, Systems on Chip, in particular is currently one of the scientific challenges to overcome, in order to ensure a broader and safer use of these systems in safety-critical equipment. The work presented in this thesis aims to develop an approach for detecting and identifying drifts in embedded Systems of Chips characteristics and performance. The proposed approach is based on an incremental model built from reusable and exchangeable modules able to adapt and accommodate the broad range of Systems on Chips available on the market. This model is then used to estimate a set of characteristics relating to the state of operation of the SoC. The diagnostic algorithm developed in this work consists of generating drift signals though the online comparison of the estimated characteristics to those measured. Then, the assessment of residuals and decision making are performed by statistical methods appropriate to the nature of each drift. The developed approach has been experimentally validated on different Systems on Chip, as well as on a demonstrator developed as part of this work. The obtained experimental results validate and show the efficiency and robustness of the incremental model and the monitoring algorithm
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Перепелицин, Артем Євгенович. "Методи і засоби розроблення мультипараметризовних проектів програмованої логіки для вбудованих систем". Thesis, Національний аерокосмічний університет ім. М. Є. Жуковського "Харківський авіаційний інститут", 2018. http://repository.kpi.kharkov.ua/handle/KhPI-Press/38557.
Повний текст джерелаАнотація:
Дисертація на здобуття наукового ступеня кандидата технічних наук (доктора філософії) за спеціальністю 05.13.05 "Комп'ютерні системи та компоненти". – Національний технічний університет "Харківський політехнічний інститут", Харків, 2018 р.
Дисертаційна робота присвячена розв'язанню важливої науково-технічної задачі, яка полягає в розробленні методів і засобів створення мультипараметризовних проектів програмованої логіки для вбудованих систем. Метою роботи є скорочення кількості необхідних ресурсів, підвищення продуктивності або підвищення надійності вбудованих систем на програмовної логіці з урахуванням заданої пріоритетної характеристики. У дисертаційній роботі вперше запропоновано модель мультипараметризовних проектів програмованої логіки, яка враховує можливість зміни розрядності і інтерпретації вхід-вихідних даних, функцій та архітектур компонентів і проектів на їх основі, що дозволяє сформувати множину варіантів для реалізації з потрібною продуктивністю і надійністю при обмежених апаратних ресурсах кристала. Вдосконалено метод розроблення мультипараметризовних проектів програмованої логіки для вбудованих систем який відрізняється від відомих можливістю вибору архітектури і паралельної або послідовної реалізації компонентів проекту, що дозволяє підвищити продуктивність або скоротити обсяг апаратних ресурсів. Отримав подальший розвиток метод підвищення надійності вбудованих систем на програмовній логіці який відрізняється від відомих можливістю конфігурації різних варіантів відмовостійких архітектур, що дозволяє підвищити стійкість до збоїв та відмов. Проведено експериментальне дослідження кількості необхідних ресурсів програмовної логіки для мультипараметризовної реалізації арифметичних операцій, в тому числі реалізацію параметризовних суматорів і помножувачів.<br>PhD Thesis for scientific degree candidate of technical sciences in the specialty 05.13.05 – computer systems and components. – National Technical University "Kharkіv Polytechnic Institute", Ministry of Education and Science of Ukraine, Kharkіv 2018.
The dissertation solves scientific and technical tasks – developing of methods and tools of multiparametrized PLD-based projects prototyping for embedded systems. The goal of the work is to reduce the number of required resources, to increase the productivity or to increase the reliability of FPGA-based embedded systems depending on the provided priority characteristic. In PhD thesis the model of multiparametrized FPGA-based projects is proposed, which takes into account the possibility of changing the bit depth and interpretation of input-output information, functions and architectures of components and projects based on them, which allows to generate many variants for implementation with the required performance and reliability within limited hardware resources of the chip. The method for developing of multiparametrized FPGA-based projects for embedded systems has been improved and now, unlike known ones, provides the ability to choice of architecture and parallel or sequential way of project components implementation, which allows to increase productivity or reduce the amount of hardware resources. The method of reliability improvement of FPGA-based embedded systems has been further developed and now, unlike known ones, provides possibility of various pre developed redundant architectures configuring, which increases the tolerance to SEU and failures. The suggested model, methods and tools have been implemented during development of FPGA based embedded systems in aviation ice-protection system for plane AN-140, medical systems, for RS-codes, cryptographic hash functions and 5 algorithms of block ciphers, including AES, DES and IDEA.
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Перепелицин, Артем Євгенович. "Методи і засоби розроблення мультипараметризовних проектів програмованої логіки для вбудованих систем". Thesis, Національний технічний університет "Харківський політехнічний інститут", 2018. http://repository.kpi.kharkov.ua/handle/KhPI-Press/38548.
Повний текст джерелаАнотація:
Дисертація на здобуття наукового ступеня кандидата технічних наук (доктора філософії) за спеціальністю 05.13.05 "Комп'ютерні системи та компоненти". – Національний технічний університет "Харківський політехнічний інститут", Харків, 2018 р.
Дисертаційна робота присвячена розв'язанню важливої науково-технічної задачі, яка полягає в розробленні методів і засобів створення мультипараметризовних проектів програмованої логіки для вбудованих систем. Метою роботи є скорочення кількості необхідних ресурсів, підвищення продуктивності або підвищення надійності вбудованих систем на програмовної логіці з урахуванням заданої пріоритетної характеристики. У дисертаційній роботі вперше запропоновано модель мультипараметризовних проектів програмованої логіки, яка враховує можливість зміни розрядності і інтерпретації вхід-вихідних даних, функцій та архітектур компонентів і проектів на їх основі, що дозволяє сформувати множину варіантів для реалізації з потрібною продуктивністю і надійністю при обмежених апаратних ресурсах кристала. Вдосконалено метод розроблення мультипараметризовних проектів програмованої логіки для вбудованих систем який відрізняється від відомих можливістю вибору архітектури і паралельної або послідовної реалізації компонентів проекту, що дозволяє підвищити продуктивність або скоротити обсяг апаратних ресурсів. Отримав подальший розвиток метод підвищення надійності вбудованих систем на програмовній логіці який відрізняється від відомих можливістю конфігурації різних варіантів відмовостійких архітектур, що дозволяє підвищити стійкість до збоїв та відмов. Проведено експериментальне дослідження кількості необхідних ресурсів програмовної логіки для мультипараметризовної реалізації арифметичних операцій, в тому числі реалізацію параметризовних суматорів і помножувачів.<br>PhD Thesis for scientific degree candidate of technical sciences in the specialty 05.13.05 – computer systems and components. – National Technical University "Kharkіv Polytechnic Institute", Ministry of Education and Science of Ukraine, Kharkіv 2018.
The dissertation solves scientific and technical tasks – developing of methods and tools of multiparametrized PLD-based projects prototyping for embedded systems. The goal of the work is to reduce the number of required resources, to increase the productivity or to increase the reliability of FPGA-based embedded systems depending on the provided priority characteristic. In PhD thesis the model of multiparametrized FPGA-based projects is proposed, which takes into account the possibility of changing the bit depth and interpretation of input-output information, functions and architectures of components and projects based on them, which allows to generate many variants for implementation with the required performance and reliability within limited hardware resources of the chip. The method for developing of multiparametrized FPGA-based projects for embedded systems has been improved and now, unlike known ones, provides the ability to choice of architecture and parallel or sequential way of project components implementation, which allows to increase productivity or reduce the amount of hardware resources. The method of reliability improvement of FPGA-based embedded systems has been further developed and now, unlike known ones, provides possibility of various pre developed redundant architectures configuring, which increases the tolerance to SEU and failures. The suggested model, methods and tools have been implemented during development of FPGA based embedded systems in aviation ice-protection system for plane AN-140, medical systems, for RS-codes, cryptographic hash functions and 5 algorithms of block ciphers, including AES, DES and IDEA.
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Vasudevan, Siddarth. "Design and Development of a CubeSat Hardware Architecture with COTS MPSoC using Radiation Mitigation Techniques." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-285577.
Повний текст джерелаАнотація:
CubeSat missions needs components that are tolerant against the radiation in space. The hardware components must be reliable, and it must not compromise the functionality on-board during the mission. At the same time, the cost of hardware and its development should not be high. Hence, this thesis discusses the design and development of a CubeSat architecture using a Commercial Off-The- Shelf (COTS) Multi-Processor System on Chip (MPSoC). The architecture employs an affordable Rad-Hard Micro-Controller Unit as a Supervisor for the MPSoC. Also, it uses several radiation mitigation techniques such as the Latch-up protection circuit to protect it against Single-Event Latch-ups (SELs), Readback scrubbing for Non- Volatile Memories (NVMs) such as NOR Flash and Configuration scrubbing for the FPGA present in the MPSoC to protect it against Single-Event Upset (SEU)s, reliable communication using Cyclic Redundancy Check (CRC) and Space packet protocol. Apart from such functionalities, the Supervisor executes tasks such as Watchdog that monitors the liveliness of the applications running in the MPSoC, data logging, performing Over-The-Air Software/Firmware update. The thesis work implements functionalities such as Communication, Readback memory scrubbing, Configuration scrubbing using SEM-IP, Watchdog, and Software/Firmware update. The execution times of the functionalities are presented for the application done in the Supervisor. As for the Configuration scrubbing that was implemented in Programmable Logic (PL)/FPGA, results of area and latency are reported.<br>CubeSat-uppdrag behöver komponenter som är toleranta mot strålningen i rymden. Maskinvarukomponenterna måste vara pålitliga och funktionaliteten ombord får inte äventyras under uppdraget. Samtidigt bör kostnaden för hårdvara och dess utveckling inte vara hög. Därför diskuterar denna avhandling design och utveckling av en CubeSatarkitektur med hjälp av COTS (eng. Custom-off-The-Shelf) MPSoC (eng. Multi Processor System-on-Chip). Arkitekturen använder en prisvärd strålningshärdad (eng. Rad-Hard) Micro-Controller Unit(MCU) som Övervakare för MPSoC:en och använder också flera tekniker för att begränsa strålningens effekter såsom kretser för att skydda kretsen från s.k. Single Event Latch-Ups (SELs), återläsningsskrubbning för icke-volatila minnen (eng. Non-Volatile Memories) NVMs som NOR Flash och skrubbning av konfigurationsminnet skrubbning för FPGA:er i MPSoC:en för att skydda dem mot Single-Event Upsets (SEUs), och tillhandahålla pålitlig kommunikation mha CRC och Space Packet Protocol. Bortsett från sådana funktioner utför Övervakaren uppgifter som Watchdog för att övervaka att applikationerna som körs i MPSoC:en fortfarande är vid liv, dataloggning, och Over- the-Air-uppdateringar av programvaran/Firmware. Examensarbetet implementerar funktioner såsom kommunikation, återläsningsskrubbning av minnet, konfigurationsminnesskrubbning mha SEM- IP, Watchdog och uppdatering av programvara/firmware. Exekveringstiderna för utförandet av funktionerna presenteras för den applikationen som körs i Övervakaren. När det gäller konfigurationsminnesskrubbningen som implementerats i den programmerbara logiken i FPGA:n, rapporteras area och latens.
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Hsun-Chieh, Yu. "Is More Redundancy Better For On-Chip Bus Encoding." 2005. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0009-0112200611322913.
Повний текст джерела
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Yu, Hsun-Chieh, and 游訓傑. "Is More Redundancy Better For On-Chip Bus Encoding." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/75609640278846016691.
Повний текст джерелаАнотація:
碩士<br>元智大學<br>資訊工程學系<br>93<br>Due to the presence of significant capacitive coupling between two adjacent lines in deep submicron process technologies, many bus encoding methods have been proposed to reduce self-transition activities, coupling-transition activities, or worst-case crosstalk delay. However these methods were shown not viable for energy reduction based on same wire-pitch assumption. In this thesis, we revisit this issue not only from the energy but also from the delay and codec overhead perspectives. We focus on the methods employing many redundant lines for eliminating crosstalk delay. Our study is made based on that all encoded buses use the same routing area. To guarantee a fair comparison, we propose a simple method to find the wire width that achieves minimal delay for a given wire pitch. We also tailor the circuit model for each encoded bus in terms of its crosstalk avoidance capability so that the noise induced delay can manifests itself on a victim wire. Our analysis shows that all investigated methods including those using more redundant wires for crosstalk avoidance are not viable for an on-chip bus from all perspectives. It also shows that a wrong conclusion would be made if our study is made based on same wire-pitch premise.
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Moriam, Sadia. "On Fault Resilient Network-on-Chip for Many Core Systems." Doctoral thesis, 2018. https://tud.qucosa.de/id/qucosa%3A34064.
Повний текст джерелаАнотація:
Rapid scaling of transistor gate sizes has increased the density of on-chip integration and paved the way for heterogeneous many-core systems-on-chip, significantly improving the speed of on-chip processing. The design of the interconnection network of these complex systems is a challenging one and the network-on-chip (NoC) is now the accepted scalable and bandwidth efficient interconnect for multi-processor systems on-chip (MPSoCs). However, the performance enhancements of technology scaling come at the cost of reliability as on-chip components particularly the network-on-chip become increasingly prone to faults. In this thesis, we focus on approaches to deal with the errors caused by such faults. The results of these approaches are obtained not only via time-consuming cycle-accurate simulations but also by analytical approaches, allowing for faster and accurate evaluations, especially for larger networks.
Redundancy is the general approach to deal with faults, the mode of which varies according to the type of fault. For the NoC, there exists a classification of faults into transient, intermittent and permanent faults. Transient faults appear randomly for a few cycles and may be caused by the radiation of particles. Intermittent faults are similar to transient faults, however, differing in the fact that they occur repeatedly at the same location, eventually leading to a permanent fault. Permanent faults by definition are caused by wires and transistors being permanently short or open. Generally, spatial redundancy or the use of redundant components is used for dealing with permanent faults. Temporal redundancy deals with failures by re-execution or by retransmission of data while information redundancy adds redundant information to the data packets allowing for error detection and correction. Temporal and information redundancy methods are useful when dealing with transient and intermittent faults.
In this dissertation, we begin with permanent faults in NoC in the form of faulty links and routers. Our approach for spatial redundancy adds redundant links in the diagonal direction to the standard rectangular mesh topology resulting in the hexagonal and octagonal NoCs. In addition to redundant links, adaptive routing must be used to bypass faulty components. We develop novel fault-tolerant deadlock-free adaptive routing algorithms for these topologies based on the turn model without the use of virtual channels. Our results show that the hexagonal and octagonal NoCs can tolerate all 2-router and 3-router faults, respectively, while the mesh has been shown to tolerate all 1-router faults. To simplify the restricted-turn selection process for achieving deadlock freedom, we devised an approach based on the channel dependency matrix instead of the state-of-the-art Duato's method of observing the channel dependency graph for cycles. The approach is general and can be used for the turn selection process for any regular topology.
We further use algebraic manipulations of the channel dependency matrix to analytically assess the fault resilience of the adaptive routing algorithms when affected by permanent faults. We present and validate this method for the 2D mesh and hexagonal NoC topologies achieving very high accuracy with a maximum error of 1%. The approach is very general and allows for faster evaluations as compared to the generally used cycle-accurate simulations. In comparison, existing works usually assume a limited number of faults to be able to analytically assess the network reliability. We apply the approach to evaluate the fault resilience of larger NoCs demonstrating the usefulness of the approach especially compared to cycle-accurate simulations.
Finally, we concentrate on temporal and information redundancy techniques to deal with transient and intermittent faults in the router resulting in the dropping and hence loss of packets. Temporal redundancy is applied in the form of ARQ and retransmission of lost packets. Information redundancy is applied by the generation and transmission of redundant linear combinations of packets known as random linear network coding. We develop an analytic model for flexible evaluation of these approaches to determine the network performance parameters such as residual error rates and increased network load. The analytic model allows to evaluate larger NoCs and different topologies and to investigate the advantage of network coding compared to uncoded transmissions.
We further extend the work with a small insight to the problem of secure communication over the NoC. Assuming large heterogeneous MPSoCs with components from third parties, the communication is subject to active attacks in the form of packet modification and drops in the NoC routers. Devising approaches to resolve these issues, we again formulate analytic models for their flexible and accurate evaluations, with a maximum estimation error of 7%.
Частини книг з теми "On-chip redundancy"
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Salehi, Mohammad, Florian Kriebel, Semeen Rehman, and Muhammad Shafique. "Power-Aware Fault-Tolerance for Embedded Systems." In Dependable Embedded Systems. Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_24.
Повний текст джерелаАнотація:
AbstractPower-constrained fault-tolerance has emerged as a key challenge in the deep sub-micron technology. Multi-/many-core chips can support different hardening modes considering variants of redundant multithreading (RMT). In dark silicon chips, the maximum number of cores that can simultaneously be powered-on (at the full performance level) is constrained by the thermal design power (TDP). The rest of the cores have to be power-gated (i.e., stay “dark”), or the cores have to operate at a lower performance level. It has been predicted that about 25–50% of a many-core chip can potentially be “dark.” In this chapter, a system-level power–reliability management technique is presented. The technique jointly considers multiple hardening modes at the software and hardware levels, each offering distinct power, reliability, and performance properties. Also, a framework for the system-level optimization is introduced which considers different power–reliability–performance management problems for many-core processors depending upon the target system and user constraints.
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Hahn, Eike, Dominik Kalinowski, Waldemar Mueller, Mohamed Abdelawwad, and Josef Boercsoek. "RISC-V Based Safety System-on-Chip with Hardware Comparator." In Proceedings of CECNet 2021. IOS Press, 2021. http://dx.doi.org/10.3233/faia210423.
Повний текст джерелаАнотація:
In this paper, a Safety System-on-Chip based on the open-source RISC-V processor SweRV EH1 from Western Digital is presented. A hardware comparator concept is followed. The SSoC is implemented on a Xilinx FPGA system and extended with standard peripherals from the Xilinx IP library and from Cobham Gaisler, so that the overall system has an Ethernet interface in addition to GPIO and UART. The goal is to create a complete redundancy approach with a hardware fault tolerance of nearly 1 from input to output based on the freely available RISC-V instruction set and prove its feasibility.
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Guang, Liang, Juha Plosila, and Hannu Tenhunen. "Self-Adaptive SoCs for Dependability." In Advances in Systems Analysis, Software Engineering, and High Performance Computing. IGI Global, 2014. http://dx.doi.org/10.4018/978-1-4666-6034-2.ch001.
Повний текст джерелаАнотація:
Dependability is a primary concern for emerging billion-transistor SoCs (Systems-on-Chip), especially when the constant technology scaling introduces an increasing rate of faults and errors. Considering the time-dependent device degradation (e.g. caused by aging and run-time voltage and temperature variations), self-adaptive circuits and architectures to improve dependability is promising and very likely inevitable. This chapter extensively surveys existing works on monitoring, decision-making, and reconfiguration addressing different dependability threats to Very Large Scale Integration (VLSI) chips. Centralized, distributed, and hierarchical fault management, utilizing various redundancy schemes and exploiting logical or physical reconfiguration methods, are all examined. As future research directions, the challenge of integrating different error management schemes to account for multifold threats and the great promise of error resilient computing are identified. This chapter provides, for chip designers, much needed insights on applying a self-adaptive computing paradigm to approach dependability on error-prone, cost-sensitive SoCs.
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Venkatesha, Shashikiran, and Ranjani Parthasarathi. "Design of Low-Cost Reliable and Fault-Tolerant 32-Bit One Instruction Core for Multi-Core Systems." In Fault Tolerance [Working Title]. IntechOpen, 2022. http://dx.doi.org/10.5772/intechopen.102823.
Повний текст джерелаАнотація:
Billions of transistors on a chip have led to integration of many cores leading to many challenges such as increased power dissipation, thermal dissipation, occurrence of faults in the circuits, and reliability issues. Existing approaches explore the usage of redundancy-based solutions for fault tolerance at core level, thread level, micro-architectural level, and software level. Core-level techniques improve the lifetime reliability of multi-core systems with asymmetric cores (large and small cores), which have gained momentum and focus among a large number of researchers. Based on the above implications, multi-core system using one instruction cores (MCS-OIC) factoring its features are proposed in this chapter. The MCS-OIC is an asymmetric multi-core architecture with MIPS core as the conventional core and OICs as the warm standby-redundant core. OIC executes only one instruction named ‘subleq _ subtract if less than or equal to zero’. When there is one of the functional units (i.e., ALU) of any conventional core fails, the opcode of the instruction is sent to the OIC. The OIC decodes the instruction opcode and emulates the faulty instruction by repeated execution of the ‘subleq’ instruction, thus providing fault tolerance. To evaluate the idea, the OIC is synthesized using ASIC and FPGA. Performance implications due to OICs at instruction and application level are evaluated. Yield analysis is estimated for various configurations of multi-core system using OICs.
Тези доповідей конференцій з теми "On-chip redundancy"
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Heyrman, Kris, and Peter Veelaert. "Useful-state encoding: Network control with minimal redundancy." In 2010 International Symposium on System-on-Chip - SOC. IEEE, 2010. http://dx.doi.org/10.1109/issoc.2010.5625552.
Повний текст джерела
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Jung, Jongpil, Kyungsu Kang, Jae-Jin Lee, Youngjun Yoon, and Chong-Min Kyung. "Cost-effective TSV redundancy configuration." In 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC). IEEE, 2012. http://dx.doi.org/10.1109/vlsi-soc.2012.6379042.
Повний текст джерела
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Jung, Jongpil, Kyungsu Kang, Jae-Jin Lee, Youngjun Yoon, and Chong-Min Kyung. "Cost-effective TSV redundancy configuration." In 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC). IEEE, 2012. http://dx.doi.org/10.1109/vlsi-soc.2012.7332113.
Повний текст джерела
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Miedema, Lukas, Benjamin Rouxel, and Clemens Grelck. "Task-level Redundancy vs Instruction-level Redundancy against Single Event Upsets in Real-time DAG scheduling." In 2021 IEEE 14th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC). IEEE, 2021. http://dx.doi.org/10.1109/mcsoc51149.2021.00062.
Повний текст джерела
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Sim, Mong Tee, and Yanyan Zhuang. "A SpaceWire PHY with Double Data Rate and Fallback Redundancy." In 2020 IEEE 33rd International System-on-Chip Conference (SOCC). IEEE, 2020. http://dx.doi.org/10.1109/socc49529.2020.9524763.
Повний текст джерела
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Wang, Shuo, and Lei Wang. "Exploiting soft redundancy for error-resilient on-chip memory design." In the 2006 IEEE/ACM international conference. ACM Press, 2006. http://dx.doi.org/10.1145/1233501.1233610.
Повний текст джерела
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Bhattacharya, K., S. Kim, and N. Ranganathan. "Improving the reliability of on-chip L2 cache using redundancy." In 2007 25th International Conference on Computer Design ICCD 2007. IEEE, 2007. http://dx.doi.org/10.1109/iccd.2007.4601906.
Повний текст джерела
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Wang, Shuo, and Lei Wang. "Exploiting Soft Redundancy for Error-Resilient On-Chip Memory Design." In 2006 IEEE/ACM International Conference on Computer Aided Design. IEEE, 2006. http://dx.doi.org/10.1109/iccad.2006.320170.
Повний текст джерела
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Oszwald, Florian, Philipp Obergfell, Matthias Traub, and Juergen Becker. "Reliable Fail-Operational Automotive E/E-Architectures by Dynamic Redundancy and Reconfiguration." In 2019 32nd IEEE International System-on-Chip Conference (SOCC). IEEE, 2019. http://dx.doi.org/10.1109/socc46988.2019.1570547977.
Повний текст джерела
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Kim, Jeong Hoon, In Jung Lyu, Hyun June Lyu, and Jun Rim Choi. "Minimizing redundancy-based motion estimation design for high-definition." In 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip (VLSI-SoC). IEEE, 2011. http://dx.doi.org/10.1109/vlsisoc.2011.6081662.
Повний текст джерела