Статті в журналах: "Non-Volatile Main Memory (NVMM)"

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OMORI, Yu, and Keiji KIMURA. "Non-Volatile Main Memory Emulator for Embedded Systems Employing Three NVMM Behaviour Models." IEICE Transactions on Information and Systems E104.D, no. 5 (May 1, 2021): 697–708. http://dx.doi.org/10.1587/transinf.2020edp7092.

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Cheng, Wen, Chunyan Li, Lingfang Zeng, Yingjin Qian, Xi Li, and André Brinkmann. "NVMM-Oriented Hierarchical Persistent Client Caching for Lustre." ACM Transactions on Storage 17, no. 1 (February 2, 2021): 1–22. http://dx.doi.org/10.1145/3404190.

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In high-performance computing (HPC), data and metadata are stored on special server nodes and client applications access the servers’ data and metadata through a network, which induces network latencies and resource contention. These server nodes are typically equipped with (slow) magnetic disks, while the client nodes store temporary data on fast SSDs or even on non-volatile main memory (NVMM). Therefore, the full potential of parallel file systems can only be reached if fast client side storage devices are included into the overall storage architecture. In this article, we propose an NVMM-based hierarchical persistent client cache for the Lustre file system (NVMM-LPCC for short). NVMM-LPCC implements two caching modes: a read and write mode (RW-NVMM-LPCC for short) and a read only mode (RO-NVMM-LPCC for short). NVMM-LPCC integrates with the Lustre Hierarchical Storage Management (HSM) solution and the Lustre layout lock mechanism to provide consistent persistent caching services for I/O applications running on client nodes, meanwhile maintaining a global unified namespace of the entire Lustre file system. The evaluation results presented in this article show that NVMM-LPCC can increase the average read throughput by up to 35.80 times and the average write throughput by up to 9.83 times compared with the native Lustre system, while providing excellent scalability.

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3

Kawata, Hirotaka, Gaku Nakagawa, and Shuichi Oikawa. "Using DRAM as Cache for Non-Volatile Main Memory Swapping." International Journal of Software Innovation 4, no. 1 (January 2016): 61–71. http://dx.doi.org/10.4018/ijsi.2016010105.

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The performance of mobile devices such as smartphones and tablets has been rapidly improving in recent years. However, these improvements have been seriously affecting power consumption. One of the greatest challenges is to achieve efficient power management for battery-equipped mobile devices. To solve this problem, the authors focus on the emerging non-volatile memory (NVM), which has been receiving increasing attention in recent years. Since its performance is comparable with that of DRAM, it is possible to replace the main memory with NVM, thereby reducing power consumption. However, the price and capacity of NVM are problematic. Therefore, the authors provide a large memory space without performance degradation by combining NVM with other memory devices. In this study, they propose a design for non-volatile main memory systems that use DRAM as a swap space. This enables both high performance and energy efficient memory management through dynamic power management in NVM and DRAM.

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Haywood Dadzie, Thomas, Jiwon Lee, Jihye Kim, and Hyunok Oh. "NVM-Shelf: Secure Hybrid Encryption with Less Flip for Non-Volatile Memory." Electronics 9, no. 8 (August 13, 2020): 1304. http://dx.doi.org/10.3390/electronics9081304.

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The Non-Volatile Memory (NVM), such as PRAM or STT-MRAM, is often adopted as the main memory in portable embedded systems. The non-volatility triggers a security issue against physical attacks, which is a vulnerability caused by memory extraction and snapshots. However, simply encrypting the NVM degrades the performance of the memory (high energy consumption, short lifetime), since typical encryption causes an avalanche effect while most NVMs suffer from the memory-write operation. In this paper, we propose NVM-shelf: Secure Hybrid Encryption with Less Flip (shelf) for Non-Volatile Memory (NVM), which is hybrid encryption to reduce the flip penalty. The main idea is that a stream cipher, such as block cipher CTR mode, is flip-tolerant when the keystream is reused. By modifying the CTR mode in AES block cipher, we let the keystream updated in a short period and reuse the keystream to achieve flip reduction while maintaining security against physical attacks. Since the CTR mode requires additional storage for the nonce, we classify write-intensive cache blocks and apply our CTR mode to the write-intensive blocks and apply the ECB mode for the rest of the blocks. To extend the cache-based NVM-shelf implementation toward SPM-based systems, we also propose an efficient compiler for SA-SPM: Security-Aware Scratch Pad Memory, which ensures the security of main memories in SPM-based embedded systems. Our compiler is the first approach to support full encryption of memory regions (i.e., stack, heap, code, and static variables) in an SPM-based system. By integrating the NVM-shelf framework to the SA-SPM compiler, we obtain the NVM-shelf implementation for both cache-based and SPM-based systems. The cache-based experiment shows that the NVM-shelf achieves encryption flip penalty less than 3%, and the SPM-based experiment shows that the NVM-shelf reduces the flip penalty by 31.8% compared to the whole encryption.

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Khan, Mohammad Nasim Imtiaz, and Swaroop Ghosh. "Comprehensive Study of Security and Privacy of Emerging Non-Volatile Memories." Journal of Low Power Electronics and Applications 11, no. 4 (September 24, 2021): 36. http://dx.doi.org/10.3390/jlpea11040036.

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Several promising non-volatile memories (NVMs) such as magnetic RAM (MRAM), spin-transfer torque RAM (STTRAM), ferroelectric RAM (FeRAM), resistive RAM (RRAM), and phase-change memory (PCM) are being investigated to keep the static leakage within a tolerable limit. These new technologies offer high density and consume zero leakage power and can bridge the gap between processor and memory. The desirable properties of emerging NVMs make them suitable candidates for several applications including replacement of conventional memories. However, their unique characteristics introduce new data privacy and security issues. Some of them are already available in the market as discrete chips or a part of full system implementation. They are considered to become ubiquitous in future computing devices. Therefore, it is important to ensure their security/privacy issues. Note that these NVMs can be considered for cache, main memory, or storage application. They are also suitable to implement in-memory computation which increases system throughput and eliminates von Neumann bottleneck. Compute-capable NVMs impose new security and privacy challenges that are fundamentally different than their storage counterpart. This work identifies NVM vulnerabilities and attack vectors originating from the device level all the way to circuits and systems, considering both storage and compute applications. We also summarize the circuit/system-level countermeasures to make the NVMs robust against security and privacy issues.

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Li, Xiaochang, and Zhengjun Zhai. "UHNVM: A Universal Heterogeneous Cache Design with Non-Volatile Memory." Electronics 10, no. 15 (July 22, 2021): 1760. http://dx.doi.org/10.3390/electronics10151760.

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During the recent decades, non-volatile memory (NVM) has been anticipated to scale up the main memory size, improve the performance of applications, and reduce the speed gap between main memory and storage devices, while supporting persistent storage to cope with power outages. However, to fit NVM, all existing DRAM-based applications have to be rewritten by developers. Therefore, the developer must have a good understanding of targeted application codes, so as to manually distinguish and store data fit for NVM. In order to intelligently facilitate NVM deployment for existing legacy applications, we propose a universal heterogeneous cache hierarchy which is able to automatically select and store the appropriate data of applications for non-volatile memory (UHNVM), without compulsory code understanding. In this article, a program context (PC) technique is proposed in the user space to help UHNVM to classify data. Comparing to the conventional hot or cold files categories, the PC technique can categorize application data in a fine-grained manner, enabling us to store them either in NVM or SSDs efficiently for better performance. Our experimental results using a real Optane dual-inline-memory-module (DIMM) card show that our new heterogeneous architecture reduces elapsed times by about 11% compared to the conventional kernel memory configuration without NVM.

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7

Wang, Tse-Yuan, Chun-Feng Wu, Che-Wei Tsao, Yuan-Hao Chang, Tei-Wei Kuo, and Xue Liu. "Rethinking the Interactivity of OS and Device Layers in Memory Management." ACM Transactions on Embedded Computing Systems 21, no. 4 (July 31, 2022): 1–21. http://dx.doi.org/10.1145/3530876.

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In the big data era, a huge number of services has placed a fast-growing demand on the capacity of DRAM-based main memory. However, due to the high hardware cost and serious leakage power/energy consumption, the growth rate of DRAM capacity cannot meet the increased rate of the required main memory space when the energy or hardware cost is a critical concern. To tackle this issue, hybrid main-memory devices/modules have been proposed to replace the pure DRAM main memory with a hybrid main memory module that provides a large main memory space by integrating a small-sized DRAM and a large-sized non-volatile memory (NVM) into the same memory module. Although NVMs have high-density and low-cost features, they suffer from the low read/write performance and low endurance issue, compared to DRAM. Thus, inside the hybrid main-memory module, it also includes a memory management design to use DRAM as the cache of NVMs to enhance its performance and lifetime. However, it also introduces new design challenges in both the OS and the memory module. In this work, we rethink the interactivity of OS and hybrid main-memory module, and propose a cross-layer cache design that (1) utilizes the information from the operating system to optimize the hit ratio of the DRAM cache inside the memory module, and (2) takes advantage of the bulk-size (or block-based) read/write feature of NVM to minimize the time overhead on the data movement between DRAM and NVM. At the same time, this cross-layer cache design is very lightweight and only introduces limited runtime management overheads. A series of experiments was conducted to evaluate the effectiveness of the proposed cross-layer cache design. The results show that the proposed design could improve access performance for up to 88%, compared to the investigated well-known page replacement algorithms.

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8

Bez, Roberto, Emilio Camerlenghi, and Agostino Pirovano. "Materials and Processes for Non-Volatile Memories." Materials Science Forum 608 (December 2008): 111–32. http://dx.doi.org/10.4028/www.scientific.net/msf.608.111.

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The development of the semiconductor industry through the CMOS technology has been possible thanks to the unique properties of the silicon and silicon dioxide material. Nevertheless the continuous scaling of the device dimension and the increase of the integration level, i.e. the capability to follow for more than 20 years the so-called Moore’s law, has been enabled not only by the Si-SiO2 system, but also by the use of other materials. The introduction of new materials every generation has allowed the integration of sub-micron and now of nanometer scale devices: different types of dielectrics, like Si3N4 or doped-SiO2, to form spacer, barrier and separation layers; conductive films, like WSi2, TiSi2, CoSi2 and NiSi2, to build low resistive gates; metals, like W, Ti, TiN, to have low resistive contacts, or like Al or Cu, to have low resistive interconnects. Although the technology development has been mainly driven by the CMOS transistor downscaling, other devices and most of all Non-Volatile Memories (NVM) have been able to evolve due to the large exploitation of these materials. NVM today represent a large portion of the overall semiconductor market and one of the most important technologies for the mobile application segment. In particular the main technology line in the NVM field is represented by the Flash Memory. Flash memory cell is based on the concept of a MOS transistor with a Floating-Gate (FG). The writing/reading operations of the cell are possible thanks again to the unique properties of the SiO2 system, being a quasi-ideal dielectric at low electric field, enabling the Flash memory to store electrons for several years, and becoming a fair conductor at higher electric field by tunnel effect, thus allowing reaching fast programming speeds. Flash have now reached the integration of many billions of bits in one monolithic component with cell dimension of 0.008um2 at 45nm technology node, always based on the FG concept. Nevertheless Flash have technological and physical constraint that will make more difficult their further scaling, even if the scaling limits are still under debate. In this contest there is the industrial interest for alternative technologies that exploit new materials and concepts to go beyond the Flash technology, to allow better scaling, and to enlarge the memory performance. Hence other technologies, alternative to floating gate devices, have been proposed and are under investigation. These new proposals exploit different physical mechanisms and different materials to store the information: magnetism and magnetoresistive materials (e.g. Co, Ni, Fe, Mn) in magnetic memories or MRAM; ferroelectricity and perovskite materials (e.g. PbTixZr1-xO3 or SrBi2Ta2O9 or BaxSr1-xTiO3) in ferroelectric memories or FeRAM; phase change and chalcogenide materials (e.g. Ge2Sb2Te5 or AsInSbTe) in phase-change memory or PCM. Among these alternative NVM, PCM are one of the most promising candidates to become a mainstream NVM, having the potentiality to improve the performance compared to Flash - random access time, read throughput, direct write, bit granularity, endurance - as well as to be scalable beyond Flash technology.

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Shen, Zongjie, Chun Zhao, Yanfei Qi, Ivona Z. Mitrovic, Li Yang, Jiacheng Wen, Yanbo Huang, Puzhuo Li, and Cezhou Zhao. "Memristive Non-Volatile Memory Based on Graphene Materials." Micromachines 11, no. 4 (March 25, 2020): 341. http://dx.doi.org/10.3390/mi11040341.

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Resistive random access memory (RRAM), which is considered as one of the most promising next-generation non-volatile memory (NVM) devices and a representative of memristor technologies, demonstrated great potential in acting as an artificial synapse in the industry of neuromorphic systems and artificial intelligence (AI), due its advantages such as fast operation speed, low power consumption, and high device density. Graphene and related materials (GRMs), especially graphene oxide (GO), acting as active materials for RRAM devices, are considered as a promising alternative to other materials including metal oxides and perovskite materials. Herein, an overview of GRM-based RRAM devices is provided, with discussion about the properties of GRMs, main operation mechanisms for resistive switching (RS) behavior, figure of merit (FoM) summary, and prospect extension of GRM-based RRAM devices. With excellent physical and chemical advantages like intrinsic Young’s modulus (1.0 TPa), good tensile strength (130 GPa), excellent carrier mobility (2.0 × 105 cm2∙V−1∙s−1), and high thermal (5000 Wm−1∙K−1) and superior electrical conductivity (1.0 × 106 S∙m−1), GRMs can act as electrodes and resistive switching media in RRAM devices. In addition, the GRM-based interface between electrode and dielectric can have an effect on atomic diffusion limitation in dielectric and surface effect suppression. Immense amounts of concrete research indicate that GRMs might play a significant role in promoting the large-scale commercialization possibility of RRAM devices.

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10

Liu, Gang, Leying Chen, and Shimin Chen. "Zen." Proceedings of the VLDB Endowment 14, no. 5 (January 2021): 835–48. http://dx.doi.org/10.14778/3446095.3446105.

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Emerging Non-Volatile Memory (NVM) technologies like 3DX-point promise significant performance potential for OLTP databases. However, transactional databases need to be redesigned because the key assumptions that non-volatile storage is orders of magnitude slower than DRAM and only supports blocked-oriented access have changed. NVMs are byte-addressable and almost as fast as DRAM. The capacity of NVM is much (4-16x) larger than DRAM. Such NVM characteristics make it possible to build OLTP database entirely in NVM main memory. This paper studies the structure of OLTP engines with hybrid NVM and DRAM memory. We observe three challenges to design an OLTP engine for NVM: tuple metadata modifications, NVM write redundancy, and NVM space management. We propose Zen, a high-throughput log-free OLTP engine for NVM. Zen addresses the three design challenges with three novel techniques: metadata enhanced tuple cache, log-free persistent transactions, and light-weight NVM space management. Experimental results on a real machine equipped with Intel Optane DC Persistent Memory show that Zen achieves up to 10.1x improvement compared with existing solutions to run an OLTP database as large as the size of NVM while achieving fast failure recovery.

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Kim, Jeong-Geun, Shin-Dug Kim, and Su-Kyung Yoon. "Q-Selector-Based Prefetching Method for DRAM/NVM Hybrid Main Memory System." Electronics 9, no. 12 (December 16, 2020): 2158. http://dx.doi.org/10.3390/electronics9122158.

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This research is to design a Q-selector-based prefetching method for a dynamic random-access memory (DRAM)/ Phase-change memory (PCM)hybrid main memory system for memory-intensive big data applications generating irregular memory accessing streams. Specifically, the proposed method fully exploits the advantages of two-level hybrid memory systems, constructed as DRAM devices and non-volatile memory (NVM) devices. The Q-selector-based prefetching method is based on the Q-learning method, one of the reinforcement learning algorithms, which determines a near-optimal prefetcher for an application’s current running phase. For this, our model analyzes real-time performance status to set the criteria for the Q-learning method. We evaluate the Q-selector-based prefetching method with workloads from data mining and data-intensive benchmark applications, PARSEC-3.0 and graphBIG. Our evaluation results show that the system achieves approximately 31% performance improvement and increases the hit ratio of the DRAM-cache layer by 46% on average compared to a PCM-only main memory system. In addition, it achieves better performance results compared to the state-of-the-art prefetcher, access map pattern matching (AMPM) prefetcher, by 14.3% reduction of execution time and 12.89% of better CPI enhancement.

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Ievtukh, V. A., A. N. Nazarov, V. I. Turchanikov, and V. S. Lysenko. "Nanocluster NVM Cells Metrology: Window Formation, Relaxation and Charge Retention Measurements." Advanced Materials Research 718-720 (July 2013): 1118–23. http://dx.doi.org/10.4028/www.scientific.net/amr.718-720.1118.

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In the paper a measurement technique for study main technical and physical parameters of nanocluster non-volatile memory capacitance cell is presented. The charging/discharging process features associated with nanoclusters (nanocrystals) incorporated into gate dielectric are discussed. Original equipment for fast capacitance measurements based on computer interfaces is considers.

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13

Bahn, Hyokyung, and Kyungwoon Cho. "Implications of NVM Based Storage on Memory Subsystem Management." Applied Sciences 10, no. 3 (February 3, 2020): 999. http://dx.doi.org/10.3390/app10030999.

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Recently, non-volatile memory (NVM) has advanced as a fast storage medium, and legacy memory subsystems optimized for DRAM (dynamic random access memory) and HDD (hard disk drive) hierarchies need to be revisited. In this article, we explore the memory subsystems that use NVM as an underlying storage device and discuss the challenges and implications of such systems. As storage performance becomes close to DRAM performance, existing memory configurations and I/O (input/output) mechanisms should be reassessed. This article explores the performance of systems with NVM based storage emulated by the RAMDisk under various configurations. Through our measurement study, we make the following findings. (1) We can decrease the main memory size without performance penalties when NVM storage is adopted instead of HDD. (2) For buffer caching to be effective, judicious management techniques like admission control are necessary. (3) Prefetching is not effective in NVM storage. (4) The effect of synchronous I/O and direct I/O in NVM storage is less significant than that in HDD storage. (5) Performance degradation due to the contention of multi-threads is less severe in NVM based storage than in HDD. Based on these observations, we discuss a new PC configuration consisting of small memory and fast storage in comparison with a traditional PC consisting of large memory and slow storage. We show that this new memory-storage configuration can be an alternative solution for ever-growing memory demands and the limited density of DRAM memory. We anticipate that our results will provide directions in system software development in the presence of ever-faster storage devices.

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14

Zhang, Zhou, Zhaole Chu, Peiquan Jin, Yongping Luo, Xike Xie, Shouhong Wan, Yun Luo, et al. "PLIN." Proceedings of the VLDB Endowment 16, no. 2 (October 2022): 243–55. http://dx.doi.org/10.14778/3565816.3565826.

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Non-Volatile Memory (NVM) has emerged as an alternative to next-generation main memories. Although many tree indices have been proposed for NVM, they generally use B+-tree-like structures. To further improve the performance of NVM-aware indices, we consider integrating learned indexes into NVM. The challenges of such an integration are two fold: (1) existing NVM indices rely on small nodes to accelerate insertions with crash consistency, but learned indices use huge nodes to obtain a flat structure. (2) the node structure of learned indices is not NVM friendly, meaning that accessing a learned node will cause multiple NVM block misses. Thus, in this paper, we propose a new persistent learned index called PLIN. The novelty of PLIN lies in four aspects: an NVM-aware data placement strategy, locally unordered and globally ordered leaf nodes, a model copy mechanism, and a hierarchical insertion strategy. In addition, PLIN is proposed for the NVM-only architecture, which can support instant recovery. We also present optimistic concurrency control and fine-grained locking mechanisms to make PLIN scalable to concurrent requests. We conduct experiments on real persistent memory with various workloads and compare PLIN with APEX, PACtree, ROART, TLBtree, and Fast&Fair. The results show that PLIN achieves 2.08x higher insertion performance and 4.42x higher query performance than its competitors on average. Meanwhile, PLIN only needs ~30 μs to recover from a system crash.

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15

Zhuge, Qingfeng, Hao Zhang, Edwin Hsing-Mean Sha, Rui Xu, Jun Liu, and Shengyu Zhang. "Exploring Efficient Architectures on Remote In-Memory NVM over RDMA." ACM Transactions on Embedded Computing Systems 20, no. 5s (October 31, 2021): 1–20. http://dx.doi.org/10.1145/3477004.

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Efficiently accessing remote file data remains a challenging problem for data processing systems. Development of technologies in non-volatile dual in-line memory modules (NVDIMMs), in-memory file systems, and RDMA networks provide new opportunities towards solving the problem of remote data access. A general understanding about NVDIMMs, such as Intel Optane DC Persistent Memory (DCPM), is that they expand main memory capacity with a cost of multiple times lower performance than DRAM. With an in-depth exploration presented in this paper, however, we show an interesting finding that the potential of NVDIMMs for high-performance, remote in-memory accesses can be revealed through careful design. We explore multiple architectural structures for accessing remote NVDIMMs in a real system using Optane DCPM, and compare the performance of various structures. Experiments are conducted to show significant performance gaps among different ways of using NVDIMMs as memory address space accessible through RDMA interface. Furthermore, we design and implement a prototype of user-level, in-memory file system, RIMFS, in the device DAX mode on Optane DCPM. By comparing against the DAX-supported Linux file system, Ext4-DAX, we show that the performance of remote reads on RIMFS over RDMA is 11.44 higher than that on a remote Ext4-DAX on average. The experimental results also show that the performance of remote accesses on RIMFS is maintained on a heavily loaded data server with CPU utilization as high as 90%, while the performance of remote reads on Ext4-DAX is significantly reduced by 49.3%, and the performance of local reads on Ext4-DAX is even more significantly reduced by 90.1%. The performance comparisons of writes exhibit the same trends.

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16

Zou, Yu, Amro Awad, and Mingjie Lin. "DirectNVM: Hardware-accelerated NVMe SSDs for High-performance Embedded Computing." ACM Transactions on Embedded Computing Systems 21, no. 1 (January 31, 2022): 1–24. http://dx.doi.org/10.1145/3463911.

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With data-intensive artificial intelligence (AI) and machine learning (ML) applications rapidly surging, modern high-performance embedded systems, with heterogeneous computing resources, critically demand low-latency and high-bandwidth data communication. As such, the newly emerging NVMe (Non-Volatile Memory Express) protocol, with parallel queuing, access prioritization, and optimized I/O arbitration, starts to be widely adopted as a de facto fast I/O communication interface. However, effectively leveraging the potential of modern NVMe storage proves to be nontrivial and demands fine-grained control, high processing concurrency, and application-specific optimization. Fortunately, modern FPGA devices, capable of efficient parallel processing and application-specific programmability, readily meet the underlying physical layer requirements of the NVMe protocol, therefore providing unprecedented opportunities to implementing a rich-featured NVMe middleware to benefit modern high-performance embedded computing. In this article, we present how to rethink existing accessing mechanisms of NVMe storage and devise innovative hardware-assisted solutions to accelerating NVMe data access performance for the high-performance embedded computing system. Our key idea is to exploit the massively parallel I/O queuing capability, provided by the NVMe storage system, through leveraging FPGAs’ reconfigurability and native hardware computing power to operate transparently to the main processor. Specifically, our DirectNVM system aims at providing effective hardware constructs for facilitating high-performance and scalable userspace storage applications through (1) hardening all the essential NVMe driver functionalities, therefore avoiding expensive OS syscalls and enabling zero-copy data access from the application, (2) relying on hardware for the I/O communication control instead of relying on OS-level interrupts that can significantly reduce both total I/O latency and its variance, and (3) exposing cutting-edge and application-specific weighted-round-robin I/O traffic scheduling to the userspace. To validate our design methodology, we developed a complete DirectNVM system utilizing the Xilinx Zynq MPSoC architecture that incorporates a high-performance application processor (APU) equipped with DDR4 system memory and a hardened configurable PCIe Gen3 block in its programmable logic part. We then measured the storage bandwidth and I/O latency of both our DirectNVM system and a conventional OS-based system when executing the standard FIO benchmark suite [ 2 ]. Specifically, compared against the PetaLinux built-in kernel driver code running on a Zynq MPSoC, our DirectNVM has shown to achieve up to 18.4× higher throughput and up to 4.5× lower latency. To ensure the fairness of our performance comparison, we also measured our DirectNVM system against the Intel SPDK [ 26 ], a highly optimized userspace asynchronous NVMe I/O framework running on a X86 PC system. Our experiment results have shown that our DirectNVM, even running on a considerably less powerful embedded ARM processor than a full-scale AMD processor, achieved up to 2.2× higher throughput and 1.3× lower latency. Furthermore, by experimenting with a multi-threading test case, we have demonstrated that our DirectNVM’s weighted-round-robin scheduling can significantly optimize the bandwidth allocation between latency-constraint frontend applications and other backend applications in real-time systems. Finally, we have developed a theoretical framework of performance modeling with classic queuing theory that can quantitatively define the relationship between a system’s I/O performance and its I/O implementation.

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17

Yu, Songping, Nong Xiao, Mingzhu Deng, Fang Liu, and Wei Chen. "Redesign the Memory Allocator for Non-Volatile Main Memory." ACM Journal on Emerging Technologies in Computing Systems 13, no. 3 (May 13, 2017): 1–26. http://dx.doi.org/10.1145/2997651.

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18

Chen, Shimin, and Qin Jin. "Persistent B + -trees in non-volatile main memory." Proceedings of the VLDB Endowment 8, no. 7 (February 2015): 786–97. http://dx.doi.org/10.14778/2752939.2752947.

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19

Chen, Jie, Ron C. Chiang, H. Howie Huang, and Guru Venkataramani. "Energy-aware writes to non-volatile main memory." ACM SIGOPS Operating Systems Review 45, no. 3 (January 11, 2012): 48–52. http://dx.doi.org/10.1145/2094091.2094104.

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20

SHU, Jiwu, Youmin CHEN, Qingda HU, and Youyou LU. "Development of system software on non-volatile main memory." SCIENTIA SINICA Informationis 51, no. 6 (May 13, 2021): 869. http://dx.doi.org/10.1360/ssi-2019-0128.

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21

Hou, Fangyong, and Hongjun He. "Ultra simple way to encrypt non-volatile main memory." Security and Communication Networks 8, no. 7 (August 4, 2014): 1155–68. http://dx.doi.org/10.1002/sec.1071.

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22

Wang, Ying, Wen-Qing Jia, De-Jun Jiang, and Jin Xiong. "A Survey of Non-Volatile Main Memory File Systems." Journal of Computer Science and Technology 38, no. 2 (March 30, 2023): 348–72. http://dx.doi.org/10.1007/s11390-023-1054-3.

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23

Walden, Candace, Devesh Singh, Meenatchi Jagasivamani, Shang Li, Luyi Kang, Mehdi Asnaashari, Sylvain Dubois, Bruce Jacob, and Donald Yeung. "Monolithically Integrating Non-Volatile Main Memory over the Last-Level Cache." ACM Transactions on Architecture and Code Optimization 18, no. 4 (December 31, 2021): 1–26. http://dx.doi.org/10.1145/3462632.

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Many emerging non-volatile memories are compatible with CMOS logic, potentially enabling their integration into a CPU’s die. This article investigates such monolithically integrated CPU–main memory chips. We exploit non-volatile memories employing 3D crosspoint subarrays, such as resistive RAM (ReRAM), and integrate them over the CPU’s last-level cache (LLC). The regular structure of cache arrays enables co-design of the LLC and ReRAM main memory for area efficiency. We also develop a streamlined LLC/main memory interface that employs a single shared internal interconnect for both the cache and main memory arrays, and uses a unified controller to service both LLC and main memory requests. We apply our monolithic design ideas to a many-core CPU by integrating 3D ReRAM over each core’s LLC slice. We find that co-design of the LLC and ReRAM saves 27% of the total LLC–main memory area at the expense of slight increases in delay and energy. The streamlined LLC/main memory interface saves an additional 12% in area. Our simulation results show monolithic integration of CPU and main memory improves performance by 5.3× and 1.7× over HBM2 DRAM for several graph and streaming kernels, respectively. It also reduces the memory system’s energy by 6.0× and 1.7×, respectively. Moreover, we show that the area savings of co-design permits the CPU to have 23% more cores and main memory, and that streamlining the LLC/main memory interface incurs a small 4% performance penalty.

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Alshboul, Mohammad, Hussein Elnawawy, Reem Elkhouly, Keiji Kimura, James Tuck, and Yan Solihin. "Efficient Checkpointing with Recompute Scheme for Non-volatile Main Memory." ACM Transactions on Architecture and Code Optimization 16, no. 2 (June 2019): 1–27. http://dx.doi.org/10.1145/3323091.

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Hakert, Christian, Kuan-Hsun Chen, Horst Schirmeier, Lars Bauer, Paul R. Genssler, Georg von der Brüggen, Hussam Amrouch, Jörg Henkel, and Jian-Jia Chen. "Software-Managed Read and Write Wear-Leveling for Non-Volatile Main Memory." ACM Transactions on Embedded Computing Systems 21, no. 1 (January 31, 2022): 1–24. http://dx.doi.org/10.1145/3483839.

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In-memory wear-leveling has become an important research field for emerging non-volatile main memories over the past years. Many approaches in the literature perform wear-leveling by making use of special hardware. Since most non-volatile memories only wear out from write accesses, the proposed approaches in the literature also usually try to spread write accesses widely over the entire memory space. Some non-volatile memories, however, also wear out from read accesses, because every read causes a consecutive write access. Software-based solutions only operate from the application or kernel level, where read and write accesses are realized with different instructions and semantics. Therefore different mechanisms are required to handle reads and writes on the software level. First, we design a method to approximate read and write accesses to the memory to allow aging aware coarse-grained wear-leveling in the absence of special hardware, providing the age information. Second, we provide specific solutions to resolve access hot-spots within the compiled program code (text segment) and on the application stack. In our evaluation, we estimate the cell age by counting the total amount of accesses per cell. The results show that employing all our methods improves the memory lifetime by up to a factor of 955×.

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26

Du, Jiayi, Yan Wang, Qingfeng Zhuge, Jingtong Hu, and Edwin H. M. Sha. "Efficient Loop Scheduling for Chip Multiprocessors with Non-Volatile Main Memory." Journal of Signal Processing Systems 71, no. 3 (October 12, 2012): 261–73. http://dx.doi.org/10.1007/s11265-012-0703-5.

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27

Ou, Qiao-Feng, Bang-Shu Xiong, Lei Yu, Jing Wen, Lei Wang, and Yi Tong. "In-Memory Logic Operations and Neuromorphic Computing in Non-Volatile Random Access Memory." Materials 13, no. 16 (August 10, 2020): 3532. http://dx.doi.org/10.3390/ma13163532.

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Recent progress in the development of artificial intelligence technologies, aided by deep learning algorithms, has led to an unprecedented revolution in neuromorphic circuits, bringing us ever closer to brain-like computers. However, the vast majority of advanced algorithms still have to run on conventional computers. Thus, their capacities are limited by what is known as the von-Neumann bottleneck, where the central processing unit for data computation and the main memory for data storage are separated. Emerging forms of non-volatile random access memory, such as ferroelectric random access memory, phase-change random access memory, magnetic random access memory, and resistive random access memory, are widely considered to offer the best prospect of circumventing the von-Neumann bottleneck. This is due to their ability to merge storage and computational operations, such as Boolean logic. This paper reviews the most common kinds of non-volatile random access memory and their physical principles, together with their relative pros and cons when compared with conventional CMOS-based circuits (Complementary Metal Oxide Semiconductor). Their potential application to Boolean logic computation is then considered in terms of their working mechanism, circuit design and performance metrics. The paper concludes by envisaging the prospects offered by non-volatile devices for future brain-inspired and neuromorphic computation.

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Kuznetsov, Sergey Dmitrievich. "In anticipation of native DBMS architectures based on non-volatile main memory." Proceedings of the Institute for System Programming of the RAS 32, no. 1 (2020): 153–80. http://dx.doi.org/10.15514/ispras-2020-32(1)-9.

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29

Luo, Huizhang, Qingfeng Zhuge, Liang Shi, Jian Li, and Edwin H. M. Sha. "Accurate age counter for wear leveling on non-volatile based main memory." Design Automation for Embedded Systems 17, no. 3-4 (September 2013): 543–64. http://dx.doi.org/10.1007/s10617-014-9141-x.

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Barbon, Claudio, Vitaliy Bilovol, Emiliano Javier Di Liscia, and Bibiana Arcondo. "Eutectic Sb7.4Te92.6 thin film for non-volatile phase-change memories." Microelectronics International 36, no. 4 (October 7, 2019): 171–75. http://dx.doi.org/10.1108/mi-03-2019-0016.

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Purpose The purpose of this paper is to investigate the structure and electrical properties of eutectic Sb7.4Te92.6 as made thin films to evaluate their potentiality for application to non-volatile phase-change memories. Design/methodology/approach The films were prepared by the pulsed laser deposition technique. The films were characterized by using X-ray diffraction in grazing-incident geometry, differential scanning calorimetry, Raman spectroscopy and transversal current–voltage curves. Findings The memory effect state, characteristic of a typical phase-change memory material, was observed. The temperature of crystallization was about 100ºC. Research limitations/implications Further studies on endurance, scaling and SET/RESET operations are needed. Practical implications One of the main characteristic values, the hold voltage and the threshold voltage values, were about 0.85 and 1.2 V, respectively, in a line with those of Ge2Sb2Te5, GeTe and Sb2Te being considered to date as the main compounds for phase-change memory devices. Originality/value The conduction mechanism in the amorphous regime is highly agreed with the Poole–Frenkel effect in deep traps.

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Wu, Kai, and Dong Li. "Unimem: Runtime Data Management on Non-Volatile Memory-Based Heterogeneous Main Memory for High Performance Computing." Journal of Computer Science and Technology 36, no. 1 (January 2021): 90–109. http://dx.doi.org/10.1007/s11390-020-0942-z.

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Pan, Chen, Shouzhen Gu, Mimi Xie, Yongpan Liu, Chun Jason Xue, and Jingtong Hu. "Wear-Leveling Aware Page Management for Non-Volatile Main Memory on Embedded Systems." IEEE Transactions on Multi-Scale Computing Systems 2, no. 2 (April 1, 2016): 129–42. http://dx.doi.org/10.1109/tmscs.2016.2525999.

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Rehman, Shania, Muhammad Farooq Khan, Sikandar Aftab, Honggyun Kim, Jonghwa Eom, and Deok-kee Kim. "Thickness-dependent resistive switching in black phosphorus CBRAM." Journal of Materials Chemistry C 7, no. 3 (2019): 725–32. http://dx.doi.org/10.1039/c8tc04538k.

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34

Huang, Yazhi, Tiantian Liu, and Chun Jason Xue. "Register allocation for write activity minimization on non-volatile main memory for embedded systems." Journal of Systems Architecture 58, no. 1 (January 2012): 13–23. http://dx.doi.org/10.1016/j.sysarc.2011.09.001.

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Fanciulli, Marco, Michele Perego, Caroline Bonafos, A. Mouti, S. Schamm, and G. Benassayag. "Nanocrystals in High-k Dielectric Stacks for Non-Volatile Memory Applications." Advances in Science and Technology 51 (October 2006): 156–66. http://dx.doi.org/10.4028/www.scientific.net/ast.51.156.

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The possibility to use semiconducting or metallic nanocrystals (ncs) embedded in a SiO2 matrix as charge storage elements in novel non volatile memory devices has been widely explored in the last ten years. The replacement of the continuous polysilicon layer of a conventional flash memory device by a 2-dimensional nanoparticle array presents several advantages but the fundamental trade-off between programming and data retention characteristics has not been overcome yet. The main problem is the limited retention time basically due to charge loss by leakage current through the ultra-thin SiO2 tunnelling dielectric. A longer retention time can be achieved by increasing the tunnel oxide thickness. This however implies higher operating voltages and consequently a reduced write/erase speed. Using high-k materials for tunnel and/or gate oxide it is in principle possible to achieve the goal of a low voltage non volatile memory device. The high dielectric constant of these materials allows using thicker tunnel oxide reducing leakage current. Several approaches have been explored to synthesise ordered arrays of ncs in SiO2 but the transfer of these methodologies to the synthesis of 2-d array of ncs in high-k materials is not trivial. In this work we address the material science issues related to the synthesis of metallic and semiconducting ncs in high-k materials using different techniques. A detailed review of the state of the art in the field is presented and further research strategies are suggested.

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36

Saranti, Konstantina, and Shashi Paul. "Two-Terminal Non-Volatile Memory Devices Using Silicon Nanowires as the Storage Medium." Advances in Science and Technology 95 (October 2014): 78–83. http://dx.doi.org/10.4028/www.scientific.net/ast.95.78.

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In the recent years a notable progress in the miniaturisation of electronic devices has been achieved in which the main component that has shown great interest is electronic memory. However, miniaturisation is reaching its limit. Alternative materials, manufacturing equipment and architectures for the storage devices are considered. In this work, an investigation on the suitability of silicon nanowires as the charge storage medium in two-terminal non-volatile memory devices is presented. Silicon nanostructures have attracted attention due to their small size, interesting properties and their potential integration into electronic devices. The two-terminal memory devices presented in this work, have a simple structure of silicon nanowires sandwiched between dielectric layers (silicon nitride) on glass substrate with thermally evaporated aluminium bottom and top contacts. The silicon nanostructures and the dielectric layer were deposited by Plasma Enhanced Chemical Vapour Deposition (PECVD) technique. The electrical behaviour of the memory cell was examined by Current-Voltage (I-V), data retention time (Current-time) and write-read-erase-read measurements. Metal-Insulator-Semiconductor (MIS) structures were also prepared for further analysis. The same silicon nanowires were embedded into the MIS capacitors and Capacitance-Voltage (C-V) analysis was conducted. Strong I-V and C-V hysteresis as well as an electrical bistability were detected. The memory effect is observed by this electrical bistability of the device that was able to switch between high and low conductivity states.

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37

Zanotti, Tommaso, Francesco Maria Puglisi, and Paolo Pavan. "Energy-Efficient Non-Von Neumann Computing Architecture Supporting Multiple Computing Paradigms for Logic and Binarized Neural Networks." Journal of Low Power Electronics and Applications 11, no. 3 (July 6, 2021): 29. http://dx.doi.org/10.3390/jlpea11030029.

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Different in-memory computing paradigms enabled by emerging non-volatile memory technologies are promising solutions for the development of ultra-low-power hardware for edge computing. Among these, SIMPLY, a smart logic-in-memory architecture, provides high reconfigurability and enables the in-memory computation of both logic operations and binarized neural networks (BNNs) inference. However, operation-specific hardware accelerators can result in better performance for a particular task, such as the analog computation of the multiply and accumulate operation for BNN inference, but lack reconfigurability. Nonetheless, a solution providing the flexibility of SIMPLY while also achieving the high performance of BNN-specific analog hardware accelerators is missing. In this work, we propose a novel in-memory architecture based on 1T1R crossbar arrays, which enables the coexistence on the same crossbar array of both SIMPLY computing paradigm and the analog acceleration of the multiply and accumulate operation for BNN inference. We also highlight the main design tradeoffs and opportunities enabled by different emerging non-volatile memory technologies. Finally, by using a physics-based Resistive Random Access Memory (RRAM) compact model calibrated on data from the literature, we show that the proposed architecture improves the energy delay product by >103 times when performing a BNN inference task with respect to a SIMPLY implementation.

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Kappert, Holger, Sebastian Braun, Michael Alfring, Norbert Kordas, Andreas Kelberer, Stefan Dreiner, and Rainer Kokozinski. "High Temperature EEPROM Using a Differential Approach for High Reliability." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, HiTEN (July 1, 2017): 000042–0000045. http://dx.doi.org/10.4071/2380-4491.2017.hiten.42.

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Abstract Various applications require the storage of program code or calibration data inside a non-volatile memory. In many cases data is programmed one time e.g. during initial test or calibration and needs to be stored and readable over the whole lifetime of a product. The expected lifetime is a few thousand hours to ten years or even more depending on the application. Due to its ease of use and reprogramming capability EEPROM based memory is very common in this field in comparison to e.g. fuses which are only one time programmable and consume considerable silicon area. High reliability especially with respect to data retention is the main constraint for these non-volatile memories. Considering the degrading mechanisms which are mainly accelerated by thermal energy, storage and operation temperature have a strong impact on EEPROM reliability. Especially at very high temperatures of 250 °C and above data retention is limited to a few thousand hours or less with further increase of temperature, which makes EEPROM hard to use as a long time non-volatile memory. Nevertheless the increasing complexity of high temperature electronics and its use in high temperature applications like data acquisition systems create a demand for reliable non-volatile memories. In this paper a differential approach is presented, with the focus on increasing the reliability of EEPROM based memories especially with respect to data retention. The circuitry has been realized in a 0.35μm high temperature SOI-CMOS technology.

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39

Liu, Hai-Kun, Di Chen, Hai Jin, Xiao-Fei Liao, Binsheng He, Kan Hu, and Yu Zhang. "A Survey of Non-Volatile Main Memory Technologies: State-of-the-Arts, Practices, and Future Directions." Journal of Computer Science and Technology 36, no. 1 (January 2021): 4–32. http://dx.doi.org/10.1007/s11390-020-0780-z.

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40

Mittal, Sparsh, and Jeffrey S. Vetter. "A Survey of Software Techniques for Using Non-Volatile Memories for Storage and Main Memory Systems." IEEE Transactions on Parallel and Distributed Systems 27, no. 5 (May 1, 2016): 1537–50. http://dx.doi.org/10.1109/tpds.2015.2442980.

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41

Makarova, E. E., V. V. Amelichev, D. V. Kostyuk, D. V. Vasilyev, Y. V. Kazakov, and E. P. Orlov. "Research of Test Cells of Power-independent Magnetoresistive Memory." Nano- i Mikrosistemnaya Tehnika 23, no. 3 (June 22, 2022): 154–58. http://dx.doi.org/10.17587/nmst.24.154-158.

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The new generation non-volatile memory devices are actively developed and researched. The MRAM test cell was manufactured by the Scientific-Manufacturing Complex "Technological Center". The control measuring system (CMS) was developed and manufactured for research. The article presents an algorithm for the operation of the CMS, which makes it possible to study spin-tunnel magnetoresistive (STMR) elements of a non-volatile MRAM test cell. The main investigated characteristics of the MRAM test cell are the currents at which the cell is magnetized. Methods for measuring resistance in a changing magnetic field created by the buses and determining currents for the magnetization reversal of an STMR element are presented in this article. The recording current of STMR element for the line was 40 mA, for the column was 67 mA. The next stage of the study was writing and reading of the STMR elements. The resistance of the STMR element with "0" logical state is 6,8 Q and with "1" logical state is 13,4 Q. The stability of the MRAM element is confirmed by performing switch operations while maintaining the levels of logical states.

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42

Tsoy, M. O., and D. M. Alfonso. "Developing modules for local storage and handling of cache memory defects information in a processor with non-volatile memory." Radio industry (Russia) 30, no. 4 (December 23, 2020): 111–18. http://dx.doi.org/10.21778/2413-9599-2020-30-4-111-118.

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Problem statement. Due to the downsizing of technological process in microprocessor manufacturing, the number of possible manufacturing defects in the microprocessor chip increases, some types of which can only appear during the main operation of the microprocessor. The hardware implementation of the module for storing and processing information on cache memory defects of the processor with non-volatile memory is considered to neutralize such defects and, as a result, increase the number of usable microprocessors.Objective. Research of various implementation options for such a module, identification of related problems and methods for their solution, synthesis of the described implementation options using computer-aided engineering (CAD) and comparison of the obtained characteristics.Results. The implementation that occupies the smallest area on the chip, intended for implementation in the Elbrus-12C microprocessor under development, was found based on the synthesis results analysis.Practical implications. The paper describes the issues and the way of their solution, taking into account modern requirements for development to increase the number of usable processors.

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Tang, Peng, Junlong Chen, Tian Qiu, Honglong Ning, Xiao Fu, Muyun Li, Zuohui Xu, Dongxiang Luo, Rihui Yao, and Junbiao Peng. "Recent Advances in Flexible Resistive Random Access Memory." Applied System Innovation 5, no. 5 (September 21, 2022): 91. http://dx.doi.org/10.3390/asi5050091.

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Flexible electronic devices have received great attention in the fields of foldable electronic devices, wearable electronic devices, displays, actuators, synaptic bionics and so on. Among them, high-performance flexible memory for information storage and processing is an important part. Due to its simple structure and non-volatile characteristics, flexible resistive random access memory (RRAM) is the most likely flexible memory to achieve full commercialization. At present, the minimum bending radius of flexible RRAM can reach 2 mm and the maximum ON/OFF ratio (storage window) can reach 108. However, there are some defects in reliability and durability. In the bending process, the cracks are the main cause of device failure. The charge trap sites provided by appropriate doping or the use of amorphous nanostructures can make the conductive filaments of flexible RRAM steadier. Flexible electrodes with high conductivity and flexible dielectric with stable storage properties are the main development directions of flexible RRAM materials in the future.

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Abad, Pablo, Pablo Prieto, Valentin Puente, and Jose-Angel Gregorio. "AC-WAR: Architecting the Cache Hierarchy to Improve the Lifetime of a Non-Volatile Endurance-Limited Main Memory." IEEE Transactions on Parallel and Distributed Systems 27, no. 1 (January 1, 2016): 66–77. http://dx.doi.org/10.1109/tpds.2015.2390225.

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Buhari, Bello Alhaji, Afolayan Ayodele Obiniyi, Sahalu B. Junaidu, and Armand F. Donfack Kana. "Trends in Remote User Authentication Based on Smart Card and External Memory." International Journal of Security and Privacy in Pervasive Computing 14, no. 1 (January 1, 2022): 1–10. http://dx.doi.org/10.4018/ijsppc.307148.

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This research performs a literature survey of remote user authentication researches based on smart card and external memory. The main security confidence of smart card based schemes is temper-resistance property. Other reasons are small physical size, portability, convenience of non-volatile memory, and security provided by a single chip computer embedded in a plastic card. The most efficient schemes are those that used hash function or ECC. The high cost of the cards and readers and their deployment remains a burden to issuers or users. This is what motivates the use of external memory instead of smart card. But the problem of non-temper resistance property associated with external memory limited researches in that direction. There are also, absence of other activities that are essential in user authentication such as forgot/reset password and re-registration in case the external memory or smart card is stolen or lost in all the reviewed researches.

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46

Asifuzzaman, Kazi, Rommel Sánchez Verdejo, and Petar Radojković. "Performance and Power Estimation of STT-MRAM Main Memory with Reliable System-level Simulation." ACM Transactions on Embedded Computing Systems 21, no. 1 (January 31, 2022): 1–25. http://dx.doi.org/10.1145/3476838.

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Анотація:

It is questionable whether DRAM will continue to scale and will meet the needs of next-generation systems. Therefore, significant effort is invested in research and development of novel memory technologies. One of the candidates for next-generation memory is Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM). STT-MRAM is an emerging non-volatile memory with a lot of potential that could be exploited for various requirements of different computing systems. Being a novel technology, STT-MRAM devices are already approaching DRAM in terms of capacity, frequency, and device size. Although STT-MRAM technology got significant attention of various major memory manufacturers, academic research of STT-MRAM main memory remains marginal. This is mainly due to the unavailability of publicly available detailed timing and current parameters of this novel technology, which are required to perform a reliable main memory simulation on performance and power estimation. This study demonstrates an approach to perform a cycle accurate simulation of STT-MRAM main memory, being the first to release detailed timing and current parameters of this technology from academia—essentially enabling researchers to conduct reliable system-level simulation of STT-MRAM using widely accepted existing simulation infrastructure. The results show a fairly narrow overall performance deviation in response to significant variations in key timing parameters, and the power consumption experiments identify the key power component that is mostly affected with STT-MRAM.

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47

BYUN, SIWOO, MOONHAENG HUH, and HOYOUNG HWANG. "FLASH MEMORY LOCK MANAGEMENT FOR PORTABLE INFORMATION SYSTEMS." International Journal of Cooperative Information Systems 15, no. 03 (September 2006): 461–79. http://dx.doi.org/10.1142/s0218843006001438.

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Flash memory is becoming a major database storage in building embedded systems or portable devices because of its non-volatile, shock-resistant, power-economic nature, and fast access time for read operations. Flash memory, however, should be erased before it can be rewritten and the erase and write operations are very slow as compared to main memory. Due to this drawback, traditional database management schemes are not easy to apply directly to flash memory database for portable devices. Therefore, we improve the traditional schemes and propose a new scheme called Flash Two Phase Locking (F2PL) scheme for efficient transaction processing in a flash memory database environment. F2PL achieves high transaction performance by exploiting the notion of the Alternative Version Coordination which allows previous version reads and efficiently handles slow write/erase operations in lock management processes. We also propose a simulation model to show the performance of F2PL. Based on the results of the performance evaluation, we conclude that F2PL scheme outperforms the traditional schemes.

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48

Vindum, Simon Friis, and Lars Birkedal. "Spirea: A Mechanized Concurrent Separation Logic for Weak Persistent Memory." Proceedings of the ACM on Programming Languages 7, OOPSLA2 (October 16, 2023): 632–57. http://dx.doi.org/10.1145/3622820.

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Weak persistent memory (a.k.a. non-volatile memory) is an emerging technology that offers fast byte-addressable durable main memory. A wealth of algorithms and libraries has been developed to explore this exciting technology. As noted by others, this has led to a significant verification gap. Towards closing this gap, we present Spirea, the first concurrent separation logic for verification of programs under a weak persistent memory model. Spirea is based on the Iris and Perennial verification frameworks, and by combining features from these logics with novel techniques it supports high-level modular reasoning about crash-safe and thread-safe programs and libraries. Spirea is fully mechanized in the Coq proof assistant and allows for interactive development of proofs with the Iris Proof Mode. We use Spirea to verify several challenging examples with modular specifications. We show how our logic can verify thread-safety and crash-safety of non-blocking durable data structures with null-recovery, in particular the Treiber stack and the Michael-Scott queue adapted to persistent memory. This is the first time durable data structures have been verified with a program logic.

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Khan, Asif. "(Invited) Ferroelectric Field-Effect Transistors as High-Density, Ultra-fast, Embedded Non-Volatile Memories." ECS Meeting Abstracts MA2022-02, no. 15 (October 9, 2022): 805. http://dx.doi.org/10.1149/ma2022-0215805mtgabs.

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Анотація:

Ferroelectric field-effect transistors (FEFETs) are receiving significant attention from the microelectronics community for next-generation memory technologies, especially as embedded non-volatile elements for data-centric applications. The main attractive features of FEFETs are that write energy and speed of FEFETs are within an order of magnitude of respective metrics for SRAMs (FEFET ~1 fJ and 1-10 ns vs. SRAM: <1 fJ and <1 ns), all the while requiring a significantly smaller cell size (FEFET 50-60F2 vs. SRAM 120-150F2) and close-to-zero standby leakage power – provided that FEFETs are integrated at the same advanced technology nodes as SRAMs [1]. In this talk, we will discuss the potential path for FEFET toward fulfilling this vision, by addressing the outstanding technological challenges: ultra-fast read-after write, reliability, voltage scaling and variation. To that end, our recent exposition on the trap and reliability physics of FEFETs will highlighted. We will highlight, based on newly developed experimental schemes, how the simultaneous capture and emission of electrons and holes in write cycles occur at the interface and the grain boundaries in the time domain, where in the band-diagram, these traps (acceptors and donors) are located and how exactly they result in the degradation of the read speed and reliability with continued write cycling. Based on these insights, we move on show how engineering the interfacial layer and the ferroelectric grain structure can enable ultra-fast read-after write and write voltage and dramatic improvements in reliability and variation, towards achieving a high-density, ultra-high speed memory technology. This research is supported by the National Science Foundation, the Defense Advanced Research Program Agency (DARPA), the Semiconductor Research Corporation (SRC) - Global Research Collaboration (GRC) program, the Applications and Systems-Driven Center for Energy-Efficient Integrated Nano Technologies (ASCENT), one of six centers in the Joint University Microelectronics Program (JUMP), a SRC program sponsored by the DARPA, and an Intel Rising Star award. [1] Mikolajick, T., Schroeder, U. & Slesazeck, S. The past, the present, and the future of ferroelectric memories. IEEE Trans. Electron Devices 67, 1434–1443 (2020). [2] Asif Islam Khan, Ali Keshavarzi, and Suman Datta. “The future of ferroelectric field-effect transistor technology." Nature Electronics 3.10 (2020): 588-597.

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Claverie, A., Caroline Bonafos, G. Ben Assayag, S. Schamm, N. Cherkashin, V. Paillard, P. Dimitrakis, et al. "Materials Science Issues for the Fabrication of Nanocrystal Memory Devices by Ultra Low Energy Ion Implantation." Defect and Diffusion Forum 258-260 (October 2006): 531–41. http://dx.doi.org/10.4028/www.scientific.net/ddf.258-260.531.

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Анотація:

Nanocrystal memories are attractive candidate for the development of non volatile memory devices for deep submicron technologies. In a nanocrystal memory device, a 2D network of isolated nanocrystals is buried in the gate dielectric of a MOS and replaces the classical polysilicon layer used in floating gate (flash) memories. Recently, we have demonstrated a route to fabricate these devices at low cost by using ultra low energy ion implantation. Obviously, all the electrical characteristics of the device depend on the characteristics of the nanocrystal population (sizes and densities) but also on their exact location with respect to the gate and channel of the MOS transistor. It is the goal of this paper to report on the main materials science aspects of the fabrication of 2D arrays of Si nanocrystals in thin SiO2 layers and at tunable distances from their SiO2/interfaces.

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Статті в журналах з теми "Non-Volatile Main Memory (NVMM)"

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