Статті в журналах з теми "NM TECHNOLOGY NODE"
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Itani, Toshiro. "157 nm Lithography for 70 nm Technology Node." Japanese Journal of Applied Physics 41, Part 1, No. 6B (June 30, 2002): 4033–36. http://dx.doi.org/10.1143/jjap.41.4033.
Повний текст джерелаThompson, K., J. H. Booske, Y. B. Gianchandani, and R. F. Cooper. "Electromagnetic annealing for the 100 nm technology node." IEEE Electron Device Letters 23, no. 3 (March 2002): 127–29. http://dx.doi.org/10.1109/55.988813.
Повний текст джерелаOgawa, Yoshihiro. "Cleaning Technology for Advanced Devices beyond 20 nm Node." Solid State Phenomena 195 (December 2012): 7–12. http://dx.doi.org/10.4028/www.scientific.net/ssp.195.7.
Повний текст джерелаSHAHIDI, GHAVAM G. "ARE WE AT THE END OF CMOS SCALING?" International Journal of High Speed Electronics and Systems 16, no. 01 (March 2006): 3–8. http://dx.doi.org/10.1142/s0129156406003503.
Повний текст джерелаFeudel, Thomas. "Advanced Annealing Schemes for High-Performance SOI Logic Technologies." Materials Science Forum 573-574 (March 2008): 387–400. http://dx.doi.org/10.4028/www.scientific.net/msf.573-574.387.
Повний текст джерелаLi, Zongru, Christopher Jarrett Elash, Chen Jin, Li Chen, Jiesi Xing, Zhiwu Yang, and Shuting Shi. "Comparison of Total Ionizing Dose Effects in 22-nm and 28-nm FD SOI Technologies." Electronics 11, no. 11 (June 1, 2022): 1757. http://dx.doi.org/10.3390/electronics11111757.
Повний текст джерелаSuganaga, Toshifumi. "157 nm lithography with high numerical aperture lens for the 70 nm technology node." Journal of Micro/Nanolithography, MEMS, and MOEMS 1, no. 3 (October 1, 2002): 206. http://dx.doi.org/10.1117/1.1501565.
Повний текст джерелаAllgair, John, Benjamin Bunday, Aaron Cordes, Pete Lipscomb, Milt Godwin, Victor Vartanian, Michael Bishop, Doron Arazi, and Kye-Weon Kim. "Metrology Requirements for the 32 nm Technology Node and Beyond." ECS Transactions 18, no. 1 (December 18, 2019): 151–60. http://dx.doi.org/10.1149/1.3096443.
Повний текст джерелаWakabayashi, H., G. S. Samudra, I. J. Djomehri, H. Nayfeh, and D. A. Antoniadis. "Supply-voltage optimization for below-70-nm technology-node MOSFETs." IEEE Transactions on Semiconductor Manufacturing 15, no. 2 (May 2002): 151–56. http://dx.doi.org/10.1109/66.999586.
Повний текст джерелаTakeda, Eiji, Eiichi Murakami, Kazuyoshi Torii, Yutaka Okuyama, Eishi Ebe, Kenji Hinode, and Shin'ichiro Kimura. "Reliability issues of silicon LSIs facing 100-nm technology node." Microelectronics Reliability 42, no. 4-5 (April 2002): 493–506. http://dx.doi.org/10.1016/s0026-2714(02)00029-x.
Повний текст джерелаSaxena, Shubhangi, and Kamsali Manjunathachari. "Novel Nanoelectronic Materials and Devices: For Future Technology Node." ECS Transactions 107, no. 1 (April 24, 2022): 15701–11. http://dx.doi.org/10.1149/10701.15701ecst.
Повний текст джерелаTomita, Hiroshi, Yuji Yamada, Hidenobu Nagashima, Norio Ishikawa, and Yumiko Taniguchi. "New FEOL Cleaning Technology for Advanced Devices beyond 45 nm Node." Solid State Phenomena 134 (November 2007): 185–88. http://dx.doi.org/10.4028/www.scientific.net/ssp.134.185.
Повний текст джерелаKim, Juhyun, Myunggon Kang, Jongwook Jeon, and Hyungcheol Shin. "Device Optimization of Nano-Plate Transistors for 3.5 nm Technology Node." Journal of Nanoscience and Nanotechnology 19, no. 10 (October 1, 2019): 6771–75. http://dx.doi.org/10.1166/jnn.2019.17108.
Повний текст джерелаBerry, C., J. Warnock, J. Badar, D. G. Bair, E. Behnen, B. Bell, A. Buyuktosunoglu, et al. "IBM z14 design methodology enhancements in the 14-nm technology node." IBM Journal of Research and Development 62, no. 2/3 (March 1, 2018): 9:1–9:12. http://dx.doi.org/10.1147/jrd.2018.2800218.
Повний текст джерелаJang, Doyoung, Dmitry Yakimets, Geert Eneman, Pieter Schuddinck, Marie Garcia Bardon, Praveen Raghavan, Alessio Spessot, Diederik Verkest, and Anda Mocuta. "Device Exploration of NanoSheet Transistors for Sub-7-nm Technology Node." IEEE Transactions on Electron Devices 64, no. 6 (June 2017): 2707–13. http://dx.doi.org/10.1109/ted.2017.2695455.
Повний текст джерелаXu, Peng, Yinghua Piao, Liang Ge, Cheng Hu, Lun Zhu, Zhiwei Zhu, David Wei Zhang, and Dongping Wu. "Investigation of Novel Junctionless MOSFETs for Technology Node Beyond 22 nm." ECS Transactions 44, no. 1 (December 15, 2019): 33–39. http://dx.doi.org/10.1149/1.3694293.
Повний текст джерелаHolmes, Steven. "22-nm-node technology active-layer patterning for planar transistor devices." Journal of Micro/Nanolithography, MEMS, and MOEMS 9, no. 1 (January 1, 2010): 013001. http://dx.doi.org/10.1117/1.3302125.
Повний текст джерелаVandervorst, Wilfried, Trudo Clarysse, and Pierre Eyben. "Spreading resistance roadmap towards and beyond the 70 nm technology node." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 20, no. 1 (2002): 451. http://dx.doi.org/10.1116/1.1446455.
Повний текст джерелаNagase, Masatoshi, Takuya Maruyama, and Makoto Sekine. "Advanced CD Control Technology for 65-nm Node Dual Damascene Process." IEEE Transactions on Semiconductor Manufacturing 20, no. 3 (August 2007): 245–51. http://dx.doi.org/10.1109/tsm.2007.901842.
Повний текст джерелаLazzaz, Abdelaziz, Khaled Bousbahi, and Mustapha Ghamnia. "Performance analysis of FinFET based inverter, NAND and NOR circuits at 10 NM,7 NM and 5 NM node technologies." Facta universitatis - series: Electronics and Energetics 36, no. 1 (2023): 1–16. http://dx.doi.org/10.2298/fuee2301001l.
Повний текст джерелаHussain, Inamul, and Saurabh Chaudhury. "CNFET Based Low Power Full Adder Circuit for VLSI Applications." Nanoscience & Nanotechnology-Asia 10, no. 3 (June 17, 2020): 286–91. http://dx.doi.org/10.2174/2210681209666190220122553.
Повний текст джерелаŠedivý, Josef, Petr Průša, Jiří Čejka, and Ladislav Bartuška. "Utilization of the Capacitated Vehicle Routing Problem with the Capacity Limitation of Nodes in Water Transportation." Naše more 69, no. 3 (November 2022): 149–58. http://dx.doi.org/10.17818/nm/2022/3.5.
Повний текст джерелаBonifacio, Cecile, Michael Campin, Kevin McIlwrath, and Paul Fischione. "Post-FIB Cleaning of TEM Specimens from 14 nm and Other FinFETs by Concentrated Argon Ion Milling." EDFA Technical Articles 21, no. 4 (November 1, 2019): 4–12. http://dx.doi.org/10.31399/asm.edfa.2019-4.p004.
Повний текст джерелаDash, T. P., S. Dey, S. Das, J. Jena, E. Mahapatra, and C. K. Maiti. "Source/Drain Stressor Design for Advanced Devices at 7 nm Technology Node." Nanoscience & Nanotechnology-Asia 10, no. 4 (August 26, 2020): 447–56. http://dx.doi.org/10.2174/2210681209666190809101307.
Повний текст джерелаHuang, Zhengfeng, Di Cao, Jianguo Cui, Yingchun Lu, Yiming Ouyang, Haochen Qi, Qi Xu, Huaguo Liang, and Tianming Ni. "Design of Multiple Node Upset Tolerant Latch in 32 nm CMOS Technology." Journal of Computer-Aided Design & Computer Graphics 33, no. 3 (March 1, 2021): 346–55. http://dx.doi.org/10.3724/sp.j.1089.2021.18385.
Повний текст джерелаZhu, Jinlong, Jiamin Liu, Tianlai Xu, Shuai Yuan, Zexu Zhang, Hao Jiang, Honggang Gu, Renjie Zhou, and Shiyuan Liu. "Optical wafer defect inspection at the 10 nm technology node and beyond." International Journal of Extreme Manufacturing 4, no. 3 (April 21, 2022): 032001. http://dx.doi.org/10.1088/2631-7990/ac64d7.
Повний текст джерелаHuang, Zhengfeng, Yang Guo, Shangjie Pan, Yingchun Lu, Huaguo Liang, Haochen Qi, Yiming Ouyang, Tianming Ni, and Qi Xu. "Tri-Node Upsets Self-Recovery Latch Design in 32 nm CMOS Technology." Journal of Computer-Aided Design & Computer Graphics 32, no. 12 (December 1, 2020): 2013–20. http://dx.doi.org/10.3724/sp.j.1089.2020.18160.
Повний текст джерелаKANG, Yesung, and Youngmin KIM. "Intra-Gate Length Biasing for Leakage Optimization in 45 nm Technology Node." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E96.A, no. 5 (2013): 947–52. http://dx.doi.org/10.1587/transfun.e96.a.947.
Повний текст джерелаSANDHYA, KESHARWANI, and DEDHE VAIBHAV. "DOUBLE NODE UPSET RADIATION IMMUNE LATCH DESIGN IN 65 NM CMOS TECHNOLOGY." i-manager's Journal on Circuits and Systems 6, no. 3 (2018): 21. http://dx.doi.org/10.26634/jcir.6.3.14624.
Повний текст джерелаBaklanov, Mikhail R., Evgeny A. Smirnov, and Larry Zhao. "Ultra Low Dielectric Constant Materials for 22 nm Technology Node and Beyond." ECS Transactions 35, no. 4 (December 16, 2019): 717–28. http://dx.doi.org/10.1149/1.3572315.
Повний текст джерелаHook, Terence B. "Power and Technology Scaling into the 5 nm Node with Stacked Nanosheets." Joule 2, no. 1 (January 2018): 1–4. http://dx.doi.org/10.1016/j.joule.2017.10.014.
Повний текст джерелаDash, Tara Prasanna, Suprava Dey, Sanghamitra Das, Eleena Mohapatra, Jhansirani Jena, and Chinmay Kumar Maiti. "Strain-engineering in nanowire field-effect transistors at 3 nm technology node." Physica E: Low-dimensional Systems and Nanostructures 118 (April 2020): 113964. http://dx.doi.org/10.1016/j.physe.2020.113964.
Повний текст джерелаOboňa, Jozef Vincenc, Tomáš Hrnčíř, Sharang, Marek Šikula, and Andrey Denisyuk. "Xe plasma FIB Delayering of IC based on 14 nm node technology." Microscopy and Microanalysis 22, S3 (July 2016): 56–57. http://dx.doi.org/10.1017/s1431927616001136.
Повний текст джерелаOno, Kazuo, Kenzo Kurotsuchi, Yoshihisa Fujisaki, Riichiro Takemura, Motoyasu Terao, and Norikatsu Takaura. "Resistive Switching Ion-Plug Memory for 32-nm Technology Node and Beyond." Japanese Journal of Applied Physics 48, no. 4 (April 20, 2009): 04C160. http://dx.doi.org/10.1143/jjap.48.04c160.
Повний текст джерелаLin, Jen-Chieh, Teng-Chun Tsai, Chia-Lin Hsu, Welch Lin, Chien-Chung Huang, Chih-Hsien Chen, and J. Y. Wu. "Advanced Rework Process Development for Cu-CMP at 28 nm Technology Node." ECS Transactions 33, no. 10 (December 17, 2019): 175–80. http://dx.doi.org/10.1149/1.3489058.
Повний текст джерелаBroussous, Lucile, D. Krejcirova, K. Courouble, S. Zoll, A. Iwasaki, H. Ishikawa, F. Buisine, A. Lamaury, and D. Fuard. "TiN Hard Mask Cleans with SC1 Solutions, for 64nm Pitch BEOL Patterning." Solid State Phenomena 219 (September 2014): 209–12. http://dx.doi.org/10.4028/www.scientific.net/ssp.219.209.
Повний текст джерелаJain, Amitabh. "Ultra-Shallow Junction Formation Using Rapid Thermal Processing." Materials Science Forum 573-574 (March 2008): 305–18. http://dx.doi.org/10.4028/www.scientific.net/msf.573-574.305.
Повний текст джерелаLamy, Magali, Marc de la Bardonnie, Frederic Lorut, Ryan Ross, Christophe Wyon, and Laurens F. Tz Kwakman. "How Effective Are Failure Analysis Methods for the 65 nm CMOS Technology Node?" EDFA Technical Articles 8, no. 2 (May 1, 2006): 14–20. http://dx.doi.org/10.31399/asm.edfa.2006-2.p014.
Повний текст джерелаDe, Indranil, Deepak Johri, Anadi Srivastava, and C. M. Osburn. "Impact of gate workfunction on device performance at the 50 nm technology node." Solid-State Electronics 44, no. 6 (June 2000): 1077–80. http://dx.doi.org/10.1016/s0038-1101(99)00323-8.
Повний текст джерелаGao, Weimin, Ivan Ciofi, Yves Saad, Philippe Matagne, Michael Bachmann, Werner Gillijns, Kevin Lucas, Wolfgang Demmerle, and Thomas Schmoeller. "Rigorous assessment of patterning solution of metal layer in 7 nm technology node." Journal of Micro/Nanolithography, MEMS, and MOEMS 15, no. 1 (February 19, 2016): 013505. http://dx.doi.org/10.1117/1.jmm.15.1.013505.
Повний текст джерелаOrlowski, Marius, and Andreas Wild. "Can 3-D Devices Extend Moore's Law Beyond the 32 nm Technology Node?" ECS Transactions 3, no. 6 (December 21, 2019): 3–17. http://dx.doi.org/10.1149/1.2357050.
Повний текст джерелаPark, Dae-Gyu, Mike Chudzik, and Haizhou Yin. "Challenges in FEOL Logic Device Integration for 32 nm Technology Node and Beyond." ECS Transactions 11, no. 6 (December 19, 2019): 371–77. http://dx.doi.org/10.1149/1.2778394.
Повний текст джерелаYan, Jhih-Yang, Sun-Rong Jan, Yi-Chung Huang, Huang-Siang Lan, Y. H. Huang, Bigchoug Hung, K. T. Chan, Michael Huang, M. T. Yang, and C. W. Liu. "Asymmetric Keep-Out Zone of Through-Silicon Via Using 28-nm Technology Node." IEEE Electron Device Letters 36, no. 9 (September 2015): 938–40. http://dx.doi.org/10.1109/led.2015.2456179.
Повний текст джерелаRezgui, Houssem, Faouzi Nasri, Giovanni Nastasi, Mohamed Fadhel Ben Aissa, Salah Rahmouni, Vittorio Romano, Hafedh Belmabrouk, and Amen Allah Guizani. "Design optimization of nanoscale electrothermal transport in 10 nm SOI FinFET technology node." Journal of Physics D: Applied Physics 53, no. 49 (September 25, 2020): 495103. http://dx.doi.org/10.1088/1361-6463/abaf7c.
Повний текст джерелаNoguchi, J., K. Sato, N. Konishi, S. Uno, T. Oshima, K. Ishikawa, H. Ashihara, et al. "Process and Reliability of Air-Gap Cu Interconnect Using 90-nm Node Technology." IEEE Transactions on Electron Devices 52, no. 3 (March 2005): 352–59. http://dx.doi.org/10.1109/ted.2005.843886.
Повний текст джерелаHuang, Zhengfeng, Yan Zhang, Wenhui Wu, Lanxi Duan, Huaguo Liang, Yiming Ouyang, Aibin Yan, and Tai Song. "A high-speed quadruple-node-upset-tolerant latch in 22 nm CMOS technology." Microelectronics Reliability 147 (August 2023): 115032. http://dx.doi.org/10.1016/j.microrel.2023.115032.
Повний текст джерелаLu, Peng, Can Yang, Yifei Li, Bo Li, and Zhengsheng Han. "Three-Dimensional TID Hardening Design for 14 nm Node SOI FinFETs." Eng 2, no. 4 (December 3, 2021): 620–31. http://dx.doi.org/10.3390/eng2040039.
Повний текст джерелаMo, Fabrizio, Chiara Elfi Spano, Yuri Ardesi, Massimo Ruo Roch, Gianluca Piccinini, and Marco Vacca. "NS-GAAFET Compact Modeling: Technological Challenges in Sub-3-nm Circuit Performance." Electronics 12, no. 6 (March 21, 2023): 1487. http://dx.doi.org/10.3390/electronics12061487.
Повний текст джерелаIwasaki, Akihisa, Kristell Courouble, Steven Lippy, Fabrice Buisine, Hidekazu Ishikawa, Emanuel Cooper, Evelyn Kennedy, Stephane Zoll, and Lucile Broussous. "Industrial Challenges of TiN Hard Mask Wet Removal Process for 14nm Technology Node." Solid State Phenomena 219 (September 2014): 213–16. http://dx.doi.org/10.4028/www.scientific.net/ssp.219.213.
Повний текст джерелаChenyun Pan, Praveen Raghavan, Ahmet Ceyhan, Francky Catthoor, Zsolt Tokei, and Azad Naeemi. "Technology/Circuit/System Co-Optimization and Benchmarking for Multilayer Graphene Interconnects at Sub-10-nm Technology Node." IEEE Transactions on Electron Devices 62, no. 5 (May 2015): 1530–36. http://dx.doi.org/10.1109/ted.2015.2409875.
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