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Статті в журналах з теми "Neuromorphic technologies":
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Okazaki, Atsuya. "Hardware Technologies for Neuromorphic Computing." Journal of the Robotics Society of Japan 35, no. 3 (2017): 209–14. http://dx.doi.org/10.7210/jrsj.35.209.
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Argyris, Apostolos. "Photonic neuromorphic technologies in optical communications." Nanophotonics 11, no. 5 (January 19, 2022): 897–916. http://dx.doi.org/10.1515/nanoph-2021-0578.
Анотація:
Abstract Machine learning (ML) and neuromorphic computing have been enforcing problem-solving in many applications. Such approaches found fertile ground in optical communications, a technological field that is very demanding in terms of computational speed and complexity. The latest breakthroughs are strongly supported by advanced signal processing, implemented in the digital domain. Algorithms of different levels of complexity aim at improving data recovery, expanding the reach of transmission, validating the integrity of the optical network operation, and monitoring data transfer faults. Lately, the concept of reservoir computing (RC) inspired hardware implementations in photonics that may offer revolutionary solutions in this field. In a brief introduction, I discuss some of the established digital signal processing (DSP) techniques and some new approaches based on ML and neural network (NN) architectures. In the main part, I review the latest neuromorphic computing proposals that specifically apply to photonic hardware and give new perspectives on addressing signal processing in optical communications. I discuss the fundamental topologies in photonic feed-forward and recurrent network implementations. Finally, I review the photonic topologies that were initially tested for channel equalization benchmark tasks, and then in fiber transmission systems, for optical header recognition, data recovery, and modulation format identification.
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Kim, Chul-Heung, Suhwan Lim, Sung Yun Woo, Won-Mook Kang, Young-Tak Seo, Sung-Tae Lee, Soochang Lee, et al. "Emerging memory technologies for neuromorphic computing." Nanotechnology 30, no. 3 (November 13, 2018): 032001. http://dx.doi.org/10.1088/1361-6528/aae975.
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Varshika, M. Lakshmi, Federico Corradi, and Anup Das. "Nonvolatile Memories in Spiking Neural Network Architectures: Current and Emerging Trends." Electronics 11, no. 10 (May 18, 2022): 1610. http://dx.doi.org/10.3390/electronics11101610.
Анотація:
A sustainable computing scenario demands more energy-efficient processors. Neuromorphic systems mimic biological functions by employing spiking neural networks for achieving brain-like efficiency, speed, adaptability, and intelligence. Current trends in neuromorphic technologies address the challenges of investigating novel materials, systems, and architectures for enabling high-integration and extreme low-power brain-inspired computing. This review collects the most recent trends in exploiting the physical properties of nonvolatile memory technologies for implementing efficient in-memory and in-device computing with spike-based neuromorphic architectures.
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Della Rocca, Mattia. "Of the Artistic Nude and Technological Behaviorism." Nuncius 32, no. 2 (2017): 376–411. http://dx.doi.org/10.1163/18253911-03202006.
Анотація:
Neuromorphic technologies lie at the core of 21st century neuroscience, especially in the “big brain science” projects started in 2013 – i.e. the BRAIN Initiative and the Human Brain Project. While neuromorphism and the “reverse engineering” of the brain are often presented as a “methodological revolution” in the brain sciences, these concepts have a long history which is strongly interconnected with the developments in neuroscience and the related field of bioengineering since the end of World War II. In this paper I provide a short review of the first generation of “neuromorphic devices” created in the 1960s, by focusing on the work of Leon Harmon and his “neuromime,” whose material history overlapped in a very interesting sense with the visual and artistic culture of the second half of the 20th century.
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Rajendran, Bipin, and Fabien Alibart. "Neuromorphic Computing Based on Emerging Memory Technologies." IEEE Journal on Emerging and Selected Topics in Circuits and Systems 6, no. 2 (June 2016): 198–211. http://dx.doi.org/10.1109/jetcas.2016.2533298.
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Woo, Jiyong, Jeong Hun Kim, Jong‐Pil Im, and Seung Eon Moon. "Recent Advancements in Emerging Neuromorphic Device Technologies." Advanced Intelligent Systems 2, no. 10 (August 23, 2020): 2000111. http://dx.doi.org/10.1002/aisy.202000111.
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Woo, Jiyong, Jeong Hun Kim, Jong‐Pil Im, and Seung Eon Moon. "Recent Advancements in Emerging Neuromorphic Device Technologies." Advanced Intelligent Systems 2, no. 10 (October 2020): 2070101. http://dx.doi.org/10.1002/aisy.202070101.
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Kurshan, Eren, Hai Li, Mingoo Seok, and Yuan Xie. "A Case for 3D Integrated System Design for Neuromorphic Computing and AI Applications." International Journal of Semantic Computing 14, no. 04 (December 2020): 457–75. http://dx.doi.org/10.1142/s1793351x20500063.
Анотація:
Over the last decade, artificial intelligence (AI) has found many applications areas in the society. As AI solutions have become more sophistication and the use cases grew, they highlighted the need to address performance and energy efficiency challenges faced during the implementation process. To address these challenges, there has been growing interest in neuromorphic chips. Neuromorphic computing relies on non von Neumann architectures as well as novel devices, circuits and manufacturing technologies to mimic the human brain. Among such technologies, three-dimensional (3D) integration is an important enabler for AI hardware and the continuation of the scaling laws. In this paper, we overview the unique opportunities 3D integration provides in neuromorphic chip design, discuss the emerging opportunities in next generation neuromorphic architectures and review the obstacles. Neuromorphic architectures, which relied on the brain for inspiration and emulation purposes, face grand challenges due to the limited understanding of the functionality and the architecture of the human brain. Yet, high-levels of investments are dedicated to develop neuromorphic chips. We argue that 3D integration not only provides strategic advantages to the cost-effective and flexible design of neuromorphic chips, it may provide design flexibility in incorporating advanced capabilities to further benefit the designs in the future.
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Orii, Yasumitsu, Akihiro Horibe, Kuniaki Sueoka, Keiji Matsumoto, Toyohiro Aoki, Hirokazu Noma, Sayuri Kohara, et al. "PERSPECTIVE ON REQUIRED PACKAGING TECHNOLOGIES FOR NEUROMORPHIC DEVICES." International Symposium on Microelectronics 2015, no. 1 (October 1, 2015): 000561–66. http://dx.doi.org/10.4071/isom-2015-tha15.
Анотація:
Cognitive computing has capability of machine learning, recognition and proposal. It is essential to make human life richer, more productive and more intelligent. For the realization of the cognitive computing, an efficient and scalable non-von Neumann architecture inspired by the human brain structure has been developed and a device which demonstrates the concept was also built. This device mimics the signal processing of the human brain, packing one million neuron circuits in 4,096 cores. It consumes almost 1,000 times less energy per event compared with a state-of-the-art multiprocessor. However, one million neurons only correspond to those of the bee's brain, and to mimic the brains of higher order animals, the inter-chip wiring becomes much more important, because this kind of neuromorphic device requires a large number of parallel signal lines for massive parallel signal operations. 3D chip stacking is, of course, a crucial technology in achieving the device. Technologies associated with 3D stacking such as low cost TSV formation and fine-pitch interconnection, smaller than 10μm pitch technology are required. From the reliability point of view, the optimization of solder composition is also important. Injection Molded Solder (IMS) is well fit to this fine pitch interconnection, in terms of material optimization and low cost joints. As for the interposer, the build-up organic interposer is the most attractive candidates for the cost issue, but in the most top layer, ultra-fine pitch wiring with the line and space widths smaller than 1μm should be prepared. Lots of material and process innovations are necessary for the inter-chip connection for neuromorphic devices.
Дисертації з теми "Neuromorphic technologies":
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Hock, Matthias [Verfasser], and Karlheinz [Akademischer Betreuer] Meier. "Modern Semiconductor Technologies for Neuromorphic Hardware / Matthias Hock ; Betreuer: Karlheinz Meier." Heidelberg : Universitätsbibliothek Heidelberg, 2014. http://d-nb.info/1180031628/34.
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Jackson, Thomas C. "Building Efficient Neuromorphic Networks in Hardware with Mixed Signal Techniques and Emerging Technologies." Research Showcase @ CMU, 2017. http://repository.cmu.edu/dissertations/1096.
Анотація:
In recent years, neuromorphic architectures have been an increasingly effective tool used to solve big data problems. Hardware neural networks have not been able to fully exploit the power efficient properties of the neural paradigm, however, due to limitations in standard CMOS. One of the largest challenges is the quadratic scaling of the synapses in a neural network. There has been some work in using post CMOS technology as synapses to overcome this limitation, but systems to date have not been scalable due to the design of their neurons. This dissertation aims to design and build scalable neural network architectures that can use emerging resistive memory technology as synapses. Using analog computing techniques to build networks is promising, especially due to the development of dense, CMOS compatible analog resistive memories. Building functional analog networks in advanced technology nodes, however, is challenging due to the relatively poor performance of analog components in these nodes. This work explores oscillatory neural networks (ONNs), which use phase as the analog state variable instead of voltage or current, reducing the number of traditional analog components required and making the networks better-suited for advanced nodes. This thesis develops additional ONN theory with regard to hardware networks, since previous work did not consider the effect of transmission delay on network dynamics. Transmission delay is proven to cause desynchronization in unmodified ONNs, and the theoretical analysis suggests ways to build networks which do synchronize. Conclusions from the theoretical development are used to build a PLL-based ONN in hardware. The PLL-based ONN is more energy efficient than comparable systems implemented in digital CMOS, although the neuron area is somewhat larger. The measurement of the PLL-based ONN also reveals additional poorly-studied facets of ONN dynamics. Using the knowledge gained from the PLL-based ONN, a larger, PLL-free ONN is built in the same technology. Removing the PLL in each neuron reduces the power and area consumption without sacrificing any functionality.This dissertation demonstrates that ONNs are well-suited to take advantage of emerging resistive memory technology to build efficient hardware neural networks.
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Calayir, Vehbi. "Neurocomputing and Associative Memories Based on Emerging Technologies: Co-optimization of Technology and Architecture." Research Showcase @ CMU, 2014. http://repository.cmu.edu/dissertations/422.
Анотація:
Neurocomputers offer a massively parallel computing paradigm by mimicking the human brain. Their efficient use in statistical information processing has been proposed to overcome critical bottlenecks with traditional computing schemes for applications such as image and speech processing, and associative memory. In neural networks information is generally represented by phase (e.g., oscillatory neural networks) or amplitude (e.g., cellular neural networks). Phase-based neurocomputing is constructed as a network of coupled oscillatory neurons that are connected via programmable phase elements. Representing each neuron circuit with one oscillatory device and implementing programmable phases among neighboring neurons, however, are not clearly feasible from circuits perspective if not impossible. In contrast to nascent oscillatory neurocomputing circuits, mature amplitude-based neural networks offer more efficient circuit solutions using simpler resistive networks where information is carried via voltage- and current-mode signals. Yet, such circuits have not been efficiently realized by CMOS alone due to the needs for an efficient summing mechanism for weighted neural signals and a digitally-controlled weighting element for representing couplings among artificial neurons. Large power consumption and high circuit complexity of such CMOS-based implementations have precluded adoption of amplitude-based neurocomputing circuits as well, and have led researchers to explore the use of emerging technologies for such circuits. Although they provide intriguing properties, previously proposed neurocomputing components based on emerging technologies have not offered a complete and practical solution to efficiently construct an entire system. In this thesis we explore the generalized problem of co-optimization of technology and architecture for such systems, and develop a recipe for device requirements and target capabilities. We describe four plausible technologies, each of which could potentially enable the implementation of an efficient and fully-functional neurocomputing system. We first investigate fully-digital neural network architectures that have been tried before using CMOS technology in which many large-size logic gates such as D flip-flops and look-up tables are required. Using a newly-proposed all-magnetic non-volatile logic family, mLogic, we demonstrate the efficacy of digitizing the oscillators and phase relationships for an oscillatory neural network by exploiting the inherent storage as well as enabling an all-digital cellular neural network hardware with simplified programmability. We perform system-level comparisons of mLogic and 32nm CMOS for both networks consisting of 60 neurons. Although digital implementations based on mLogic offer improvements over CMOS in terms of power and area, analog neurocomputing architectures seem to be more compatible with the greatest portion of emerging technologies and devices. For this purpose in this dissertation we explore several emerging technologies with unique device configurations and features such as mCell devices, ovenized aluminum nitride resonators, and tunable multi-gate graphene devices to efficiently enable two key components required for such analog networks – that is, summing function and weighting with compact D/A (digital-to-analog) conversion capability. We demonstrate novel ways to implement these functions and elaborate on our building blocks for artificial neurons and synapses using each technology. We verify the functionality of each proposed implementation using various image processing applications based on compact circuit simulation models for such post-CMOS devices. Finally, we design a proof-of-concept neurocomputing circuitry containing 20 neurons using 65nm CMOS technology that is based on the primitives that we define for our analog neurocomputing scheme. This allows us to fully recognize the inefficiencies of an all-CMOS implementation for such specific applications. We share our experimental results that are in agreement with circuit simulations for the same image processing applications based on proposed architectures using emerging technologies. Power and area comparisons demonstrate significant improvements for analog neurocomputing circuits when implemented using beyond- CMOS technologies, thereby promising huge opportunities for future energy-efficient computing.
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Garbin, Daniele. "Etude de la variabilité des technologies PCM et OxRAM pour leur utilisation en tant que synapses dans les systèmes neuromorphiques." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT133/document.
Анотація:
Le cerveau humain est composé d’un grand nombre de réseaux neuraux interconnectés, dont les neurones et les synapses en sont les briques constitutives. Caractérisé par une faible consommation de puissance, de quelques Watts seulement, le cerveau humain est capable d’accomplir des tâches qui sont inaccessibles aux systèmes de calcul actuels, basés sur une architecture de type Von Neumann. La conception de systèmes neuromorphiques vise à réaliser une nouvelle génération de systèmes de calcul qui ne soit pas de type Von Neumann. L’utilisation de mémoire non-volatile innovantes en tant que synapses artificielles, pour application aux systèmes neuromorphiques, est donc étudiée dans cette thèse. Deux types de technologies de mémoires sont examinés : les mémoires à changement de phase (Phase-Change Memory, PCM) et les mémoires résistives à base d’oxyde (Oxide-based resistive Random Access Memory, OxRAM). L’utilisation des dispositifs PCM en tant que synapses de type binaire et probabiliste est étudiée pour l’extraction de motifs visuels complexes, en évaluant l’impact des conditions de programmation sur la consommation de puissance au niveau du système. Une nouvelle stratégie de programmation, qui permet de réduire l’impact du problème de la dérive de la résistance des dispositifs PCM est ensuite proposée. Il est démontré qu’en utilisant des dispositifs de tailles réduites, il est possible de diminuer la consommation énergétique du système. La variabilité des dispositifs OxRAM est ensuite évaluée expérimentalement par caractérisation électrique, en utilisant des méthodes statistiques, à la fois sur des dispositifs isolés et dans une matrice complète de mémoire. Un modèle qui permets de reproduire la variabilité depuis le niveau faiblement résistif jusqu’au niveau hautement résistif est ainsi développé. Une architecture de réseau de neurones de type convolutionnel est ensuite proposée sur la base de ces travaux éxperimentaux. La tolérance du circuit neuromorphique à la variabilité des OxRAM est enfin démontrée grâce à des tâches de reconnaissance de motifs visuels complexes, comme par exemple des caractères manuscrits ou des panneaux de signalisations routièresThe human brain is made of a large number of interconnected neural networks which are composed of neurons and synapses. With a low power consumption of only few Watts, the human brain is able to perform computational tasks that are out of reach for today’s computers, which are based on the Von Neumann architecture. Neuromorphic hardware design, taking inspiration from the human brain, aims to implement the next generation, non-Von Neumann computing systems. In this thesis, emerging non-volatile memory devices, specifically Phase-Change Memory (PCM) and Oxide-based resistive memory (OxRAM) devices, are studied as artificial synapses in neuromorphic systems. The use of PCM devices as binary probabilistic synapses is studied for complex visual pattern extraction applications, evaluating the impact of the PCM programming conditions on the system-level power consumption.A programming strategy is proposed to mitigate the impact of PCM resistance drift. It is shown that, using scaled devices, it is possible to reduce the synaptic power consumption. The OxRAM resistance variability is evaluated experimentally through electrical characterization, gathering statistics on both single memory cells and at array level. A model that allows to reproduce OxRAM variability from low to high resistance state is developed. An OxRAM-based convolutional neural network architecture is then proposed on the basis of this experimental work. By implementing the computation of convolution directly in memory, the Von Neumann bottleneck is avoided. Robustness to OxRAM variability is demonstrated with complex visual pattern recognition tasks such as handwritten characters and traffic signs recognition
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Ly, Denys. "Mémoires résistives et technologies 3D monolithiques pour processeurs neuromorphiques impulsionnels et reconfigurables." Thesis, Université Grenoble Alpes, 2020. http://www.theses.fr/2020GRALT016.
Анотація:
Le cerveau humain est un système computationnel complexe mais énergétiquement efficace qui excelle aux applications cognitives grâce à sa capacité naturelle à faire de l'inférence. À l'inverse, les systèmes de calculs traditionnels reposant sur la classique architecture de Von Neumann exigent des consommations de puissance importantes pour exécuter de telles tâches. Ces considérations ont donné naissance à la fameuse approche neuromorphique, qui consiste à construire des systèmes de calculs inspirés du cerveau. Dans cette thèse, nous examinons l'utilisation de technologies novatrices, à savoir les mémoires résistives (RRAMs) et les technologies tridimensionnelles (3D) monolithiques, pour permettre l'implémentation matérielle compacte de processeurs neuromorphiques impulssionnels (SNNs) et reconfigurables à faible puissance. Dans un premier temps, nous fournirons une étude détaillée sur l'impact des propriétés électriques des RRAMs dans les SNNs utilisant des synapses à base de RRAMs, et entraînés avec des méthodes d'apprentissage non-supervisées (plasticité fonction du temps d'occurence des impulsions, STDP). Notamment, nous clarifierons le rôle de la variabilité synaptique provenant de la variabilité résistive des RRAMs. Dans un second temps, nous étudierons l'utilisation de matrices de mémoires ternaires adressables par contenu (TCAMs) à base de RRAMs en tant que tables de routage synaptique dans les processeurs SNNs, afin de permettre la reconfigurabilité de la topologie du réseau. Pour ce faire, nous présenterons des caractérisations électriques approfondies de deux circuits TCAMs à base de RRAMs: (i) la structure TCAM la plus courante avec deux-transistors/deux-RRAMs (2T2R), et (ii) une nouvelle structure TCAM avec un-transistor/deux-RRAMs/un-transistor (1T2R1T), toutes deux dotées de la plus petite surface silicium à l'heure actuelle. Nous comparerons les deux structures en termes de performances, fiabilité et endurance. Pour finir, nous explorerons le potentiel des technologies 3D monolithiques en vue d'améliorer l'efficacité en surface. En plus de la classique intégration monolithique des RRAMs dans le retour en fin de ligne (back-end-of-line) des technologies CMOS, nous analyserons l'empilement vertical de transistors CMOS les uns au-dessus des autres. Pour cela, nous démontrerons la possibilité d'intégrer monolithiquement deux niveaux de transistors CMOS avec un niveau de dispositifs RRAMs. Cette preuve de concept sera appuyée par des caractérisations électriques effectuées sur les dispositifs fabriquésThe human brain is a complex, energy-efficient computational system that excels at cognitive tasks thanks to its natural capability to perform inference. By contrast, conventional computing systems based on the classic Von Neumann architecture require large power budget to execute such assignments. Herein comes the idea to build brain-inspired electronic computing systems, the so-called neuromorphic approach. In this thesis, we explore the use of novel technologies, namely Resistive Memories (RRAMs) and three-dimensional (3D) monolithic technologies, to enable the hardware implementation of compact, low-power reconfigurable Spiking Neural Network (SNN) processors. We first provide a comprehensive study of the impact of RRAM electrical properties on SNNs with RRAM synapses and trained with unsupervised learning (Spike-Timing-Dependent Plasticity (STDP)). In particular, we clarify the role of synaptic variability originating from RRAM resistance variability. Second, we investigate the use of RRAM-based Ternary Content-Addressable Memory (TCAM) arrays as synaptic routing tables in SNN processors to enable on-the-fly reconfigurability of network topology. For this purpose, we present in-depth electrical characterisations of two RRAM-based TCAM circuits: (i) the most common two-transistors/two-RRAMs (2T2R) RRAM-based TCAM, and (ii) a novel one-transistor/two-RRAMs/one-transistor (1T2R1T) RRAM-based TCAM, both featuring the smallest silicon area up-to-date. We compare both structures in terms of performance, reliability, and endurance. Finally, we explore the potential of 3D monolithic technologies to improve area-efficiency. In addition to the conventional monolithic integration of RRAMs in the back-end-of-line of CMOS technology, we examine the vertical stacking of CMOS over CMOS transistors. To this end, we demonstrate the full 3D monolithic integration of two tiers of CMOS transistors with one tier of RRAM devices, and present electrical characterisations performed on the fabricated devices
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Suri, Manan. "Technologies émergentes de mémoire résistive pour les systèmes et application neuromorphique." Phd thesis, Université de Grenoble, 2013. http://tel.archives-ouvertes.fr/tel-00935190.
Анотація:
La recherche dans le domaine de l'informatique neuro-inspirée suscite beaucoup d'intérêt depuis quelques années. Avec des applications potentielles dans des domaines tels que le traitement de données à grande échelle, la robotique ou encore les systèmes autonomes intelligents pour ne citer qu'eux, des paradigmes de calcul bio-inspirés sont étudies pour la prochaine génération solutions informatiques (post-Moore, non-Von Neumann) ultra-basse consommation. Dans ce travail, nous discutons les rôles que les différentes technologies de mémoire résistive non-volatiles émergentes (RRAM), notamment (i) Phase Change Memory (PCM), (ii) Conductive-Bridge Memory (CBRAM) et de la mémoire basée sur une structure Metal-Oxide (OXRAM) peuvent jouer dans des dispositifs neuromorphiques dédies. Nous nous concentrons sur l'émulation des effets de plasticité synaptique comme la potentialisation à long terme (Long Term Potentiation, LTP), la dépression à long terme (Long Term Depression, LTD) et la théorie STDP (Spike-Timing Dependent Plasticity) avec des synapses RRAM. Nous avons développé à la fois de nouvelles architectures de faiblement énergivore, des méthodologies de programmation ainsi que des règles d'apprentissages simplifiées inspirées de la théorie STDP spécifiquement optimisées pour certaines technologies RRAM. Nous montrons l'implémentation de systèmes neuromorphiques a grande échelle et efficace énergétiquement selon deux approches différentes: (i) des synapses multi-niveaux déterministes et (ii) des synapses stochastiques binaires. Des prototypes d'applications telles que l'extraction de schéma visuel et auditif complexe sont également montres en utilisant des réseaux de neurones impulsionnels (Feed-forward Spiking Neural Network, SNN). Nous introduisons également une nouvelle méthodologie pour concevoir des neurones stochastiques très compacts qui exploitent les caractéristiques physiques intrinsèques des appareils CBRAM.
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Janzakova, Kamila. "Développement de dendrites polymères organiques en 3D comme dispositif neuromorphique." Electronic Thesis or Diss., Université de Lille (2022-....), 2023. http://www.theses.fr/2023ULILN017.
Анотація:
Les technologies neuromorphiques constituent une voie prometteuse pour le développement d'une informatique plus avancée et plus économe en énergie. Elles visent à reproduire les caractéristiques attrayantes du cerveau, telles qu'une grande efficacité de calcul et une faible consommation d'énergie au niveau des logiciels et du matériel. À l'heure actuelle, les implémentations logicielles inspirées du cerveau (telles que ANN et SNN) ont déjà démontré leur efficacité dans différents types de tâches (reconnaissance d'images et de la parole). Toutefois, pour tirer un meilleur parti des algorithmes inspirés du cerveau, il est possible de les combiner avec une implémentation materielle appropriée qui s'appuierait également sur une architecture et des processus inspirés du cerveau. L'ingénierie neuromorphique s'est principalement appuyée sur les technologies conventionnelles (CMOS circuits, memristor) pour le développement de circuits inspirés du cerveau. Néanmoins, ces implémentations sont fabriquées suivant une approche top-down. En revanche, l'informatique cérébrale repose sur des processus bottom-up tels que l'interconnectivité entre les cellules et la formation de voies de communication neuronales.À la lumière de ce qui précède, ce travail de thèse porte sur le développement de dispositifs neuromorphiques organiques programmables en 3D qui, contrairement à la plupart des technologies neuromorphiques actuelles, peuvent être créés de manière bottom-up. Cela permet de rapprocher les technologies neuromorphiques du niveau de programmation du cerveau, où les chemins neuronaux nécessaires sont établis uniquement en fonction des besoins.Tout d'abord, nous avons découvert que les interconnexions 3D à base de PEDOT:PSS peuvent être formées au moyen d'électropolymérisation bipolaire en courant alternatif, permettant d'imiter la croissance des cellules neuronales. En réglant individuellement les paramètres de la forme d'onde (tension d'amplitude de crête - VP, fréquence - f, duty cycle- dc et tension de décalage - Voff), une large gamme de structures semblables à des dendrites a été observée avec différents degrés de ramification, volumes, surfaces, asymétries et dynamiques de croissance.Ensuite, nous avons montré que les morphologies dendritiques obtenues à différentes fréquences sont conductrices. De plus, chaque structure présente une valeur de conductance qui peut être interprétée comme un poids synaptique. Plus important encore, la capacité des dendrites à fonctionner comme OECT a été révélée. Différentes morphologies de dendrites ont présenté des performances différentes en tant qu'OECT. De plus, la capacité des dendrites en PEDOT:PSS à modifier leur conductivité en réponse à la tension de grille a été utilisée pour imiter les fonctions de mémoire du cerveau (plasticité à court terme -STP et plasticité à long terme -LTP). Les réponses à la STP varient en fonction de la structure dendritique. En outre, l'émulation de la LTP a été démontrée non seulement au moyen d'un fil de grille Ag/AgCl, mais aussi au moyen d'une grille dendritique en polymère développée par électropolymérisation.Enfin, la plasticité structurelle a été démontrée par la croissance dendritique, où le poids de la connexion finale est régi par les règles d'apprentissage de type Hebbien (plasticité dépendante du moment de l'impulsion - STDP et plasticité dépendante du rythme de l'impulsion - SRDP). En utilisant les deux approches, une variété de topologies dendritiques avec des états de conductance programmables (c'est-à-dire le poids synaptique) et diverses dynamiques de croissance ont été observées. Finalement, en utilisant la même plasticité structurelle dendritique, des caractéristiques cérébrales plus complexes telles que l'apprentissage associatif et les tâches de classification ont été émulées.En outre, les perspectives futures de ces technologies basées sur des objets dendritiques polymères ont été discutéesNeuromorphic technologies is a promising direction for development of more advanced and energy-efficient computing. They aim to replicate attractive brain features such as high computational efficiency at low power consumption on a software and hardware level. At the moment, brain-inspired software implementations (such as ANN and SNN) have already shown their successful application for different types of tasks (image and speech recognition). However, to benefit more from the brain-like algorithms, one may combine them with appropriate hardware that would also rely on brain-like architecture and processes and thus complement them. Neuromorphic engineering has already shown the utilization of solid-state electronics (CMOS circuits, memristor) for the development of brain-inspired devices. Nevertheless, these implementations are fabricated through top-down methods. In contrast, brain computing relies on bottom-up processes such as interconnectivity between cells and the formation of neural communication pathways.In the light of mentioned above, this work reports on the development of programmable 3D organic neuromorphic devices, which, unlike most current neuromorphic technologies, can be created in a bottom-up manner. This allows bringing neuromorphic technologies closer to the level of brain programming, where necessary neural paths are established only on the need.First, we found out that PEDOT:PSS based 3D interconnections can be formed by means of AC-bipolar electropolymerization and that they are capable of mimicking the growth of neural cells. By tuning individually the parameters of the waveform (peak amplitude voltage -VP, frequency - f, duty cycle - dc and offset voltage - Voff), a wide range of dendrite-like structures was observed with various branching degrees, volumes, surface areas, asymmetry of formation, and even growth dynamics.Next, it was discovered that dendritic morphologies obtained at various frequencies are conductive. Moreover, each structure exhibits an individual conductance value that can be interpreted as synaptic weight. More importantly, the ability of dendrites to function as OECT was revealed. Different dendrites exhibited different performances as OECT. Further, the ability of PEDOT:PSS dendrites to change their conductivity in response to gate voltage was used to mimic brain memory functions (short-term plasticity -STP and long-term plasticity -LTP). STP responses varied depending on the dendritic structure. Moreover, emulation of LTP was demonstrated not only by means of an Ag/AgCl gate wire but as well by means of a self-developed polymer dendritic gate.Finally, structural plasticity was demonstrated through dendritic growth, where the weight of the final connection is governed according to Hebbian learning rules (spike-timing-dependent plasticity - STDP and spike-rate-dependent plasticity - SRDP). Using both approaches, a variety of dendritic topologies with programmable conductance states (i.e., synaptic weight) and various dynamics of growth have been observed. Eventually, using the same dendritic structural plasticity, more complex brain features such as associative learning and classification tasks were emulated.Additionally, future perspectives of such technologies based on self-propagating polymer dendritic objects were discussed
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Haessig, Germain. "Neuromorphic computation using event-based sensors : from algorithms to hardware implementations." Thesis, Sorbonne université, 2018. http://www.theses.fr/2018SORUS422/document.
Анотація:
Cette thèse porte sur l’implémentation d’algorithmes événementiels, en utilisant, dans un premier temps, des données provenant d’une rétine artificielle, mimant le fonctionnement de la rétine humaine, pour ensuite évoluer vers tous types de signaux événementiels. Ces signaux événementiels sont issus d’un changement de paradigme dans la représentation du signal, offrant une grande plage dynamique de fonctionnement, une résolution temporelle importante ainsi qu’une compression native du signal. Sera notamment étudiée la réalisation d’un dispositif de création de cartes de profondeur monoculaires à haute fréquence, un algorithme de tri cellulaire en temps réel, ainsi que l’apprentissage non supervisé pour de la reconnaissance de formes. Certains de ces algorithmes (détection de flot optique, construction de cartes de profondeur en stéréovision) seront développés en parallèle sur des plateformes de simulation neuromorphiques existantes (SpiNNaker, TrueNorth), afin de proposer une chaîne de traitement de l’information entièrement neuromorphique, du capteur au calcul, à faible coût énergétiqueThis thesis is about the implementation of neuromorphic algorithms, using, as a first step, data from a silicon retina, mimicking the human eye’s behavior, and then evolve towards all kind of event-based signals. These eventbased signals are coming from a paradigm shift in the data representation, thus allowing a high dynamic range, a precise temporal resolution and a sensor-level data compression. Especially, we will study the development of a high frequency monocular depth map generator, a real-time spike sorting algorithm for intelligent brain-machine interfaces, and an unsupervised learning algorithm for pattern recognition. Some of these algorithms (Optical flow detection, depth map construction from stereovision) will be in the meantime developed on available neuromorphic platforms (SpiNNaker, TrueNorth), thus allowing a fully neuromorphic pipeline, from sensing to computing, with a low power budget
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Bedecarrats, Thomas. "Etude et intégration d’un circuit analogique, basse consommation et à faible surface d'empreinte, de neurone impulsionnel basé sur l’utilisation du BIMOS en technologie 28 nm FD-SOI." Thesis, Université Grenoble Alpes (ComUE), 2019. http://www.theses.fr/2019GREAT045.
Анотація:
Avec la fin annoncée de la loi de Moore, les acteurs de la microélectronique cherchent de nouveaux paradigmes sur lesquels s’appuyer pour alimenter les développements futurs de notre société de l’information. En s’inspirant des systèmes nerveux biologiques, l’ingénierie neuromorphique offre des perspectives nouvelles qui révolutionnent d’ores et déjà l’intelligence artificielle. Pour que leurs performances permettent leur généralisation, les processeurs neuronaux se doivent d’intégrer des circuits de neurones les plus petits et les moins énergivores possible afin que les réseaux de neurones artificiels qu’ils implémentent atteignent une taille critique. Dans ce travail, nous montrons qu’il est possible de réduire le nombre de composants nécessaires à la conception d’un circuit analogique de neurone impulsionnel par la fonctionnalisation des courants de génération parasites dans un transistor BIMOS intégré en technologie 28 nm FD-SOI et dimensionné aux tailles minimales autorisées par la technologie. Après une caractérisation systématique des ces courants par des mesures quasi-statiques du FD-SOI BIMOS à température ambiante sous différentes polarisations, une modélisation compacte de ce composant adaptée à partir du modèle CEA-LETI UTSOI est proposée. Le circuit analogique de neurone impulsionnel à fuite, intégration et déclenchement basé sur le BIMOS (« BIMOS-based leaky, integrate-and-fire spiking neuron » : BB-LIF SN) est ensuite décrit. L’influence des différentes dimensions caractéristiques et polarisations de contrôle sur son fonctionnement observée lors des mesures sur des démonstrateurs fabriqués sur silicium est expliquée en détail. Un modèle analytique simple de ses limites de fonctionnement est proposé. La cohérence entre les résultats de mesures, ceux de simulations compactes et les prédictions du modèle analytique simple atteste la pertinence des analyses proposées. Dans sa version la plus aboutie, le BB-LIF SN occupe une surface de 15 µm², consomme environ 2 pJ/spike, fonctionne à des fréquences de déclenchement comprises entre 3 et 75 kHz pour des courant synaptique compris entre 600 pA et 25 nA sous une tension d’alimentation de 3 VWhile Moore’s law reaches its limits, microelectronics actors are looking for new paradigms to ensure future developments of our information society. Inspired by biologic nervous systems, neuromorphic engineering is providing new perspectives which have already enabled breakthroughs in artificial intelligence. To achieve sufficient performances to allow their spread, neural processors have to integrate neuron circuits as small and as low power(ed) as possible so that artificial neural networks they implement reach a critical size. In this work, we show that it is possible to reduce the number of components necessary to design an analogue spiking neuron circuit thanks to the functionalisation of parasitic generation currents in a BIMOS transistor integrated in 28 nm FD-SOI technology and sized with the minimum dimensions allowed by this technology. After a systematic characterization of the FD-SOI BIMOS currents under several biases through quasi-static measurements at room temperature, a compact model of this component, adapted from the CEA-LETI UTSOI one, is proposed. The BIMOS-based leaky, integrate-and-fire spiking neuron (BB-LIF SN) circuit is described. Influence of the different design and bias parameters on its behaviour observed during measurements performed on a demonstrator fabricated in silicon is explained in detail. A simple analytic model of its operating boundaries is proposed. The coherence between measurement and compact simulation results and predictions coming from the simple analytic model attests to the relevance of the proposed analysis. In its most successful achievement, the BB-LIF SN circuit is 15 µm², consumes around 2 pJ/spike, triggers at a rate between 3 and 75 kHz for 600 pA to 25 nA synaptic currents under a 3 V power supply
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Cohen, Gregory Kevin. "Event-Based Feature Detection, Recognition and Classification." Thesis, Paris 6, 2016. http://www.theses.fr/2016PA066204/document.
Анотація:
La detection, le suivi de cible et la reconnaissance de primitives visuelles constituent des problèmes fondamentaux de la vision robotique. Ces problématiques sont réputés difficiles et sources de défis. Malgré les progrès en puissance de calcul des machines, le gain en résolution et en fréquence des capteurs, l’état-de-l’art de la vision robotique peine à atteindre des performances en coût d’énergie et en robustesse qu’offre la vision biologique. L’apparition des nouveaux capteurs, appelés "rétines de silicium” tel que le DVS (Dynamic Vision Sensor) et l’ATIS (Asynchronous Time-based Imaging Sensor) reproduisant certaines fonctionnalités des rétines biologiques, ouvre la voie à de nouveaux paradigmes pour décrire et modéliser la perception visuelle, ainsi que pour traiter l’information visuelle qui en résulte. Les tâches de suivi et de reconnaissance de formes requièrent toujours la caractérisation et la mise en correspondance de primitives visuelles. La détection de ces dernières et leur description nécessitent des approches fondamentalement différentes de celles employées en vision robotique traditionnelle. Cette thèse développe et formalise de nouvelles méthodes de détection et de caractérisation de primitives spatio-temporel des signaux acquis par les rétines de silicium (plus communément appelés capteurs “event-based”). Une structure théorique pour les tâches de détection, de suivi, de reconnaissance et de classification de primitives est proposée. Elle est ensuite validée par des données issues de ces capteurs “event-based”,ainsi que par des bases données standard du domaine de la reconnaissance de formes, convertit au préalable à un format compatible avec la representation “événement”. Les résultats présentés dans cette thèse démontrent les potentiels et l’efficacité des systèmes "event-based”. Ce travail fournit une analyse approfondie de différentes méthodes de reconnaissance de forme et de classification “event-based". Cette thèse propose ensuite deux solutions basées sur les primitives. Deux mécanismes d’apprentissage, un purement événementiel et un autre, itératif, sont développés puis évalués pour leur capacité de classification et de robustesse. Les résultats démontrent la validité de la classification “event-based” et souligne l’importance de la dynamique de la scène dans les tâches primordiales de définitions des primitives et de leur détection et caractétisationOne of the fundamental tasks underlying much of computer vision is the detection, tracking and recognition of visual features. It is an inherently difficult and challenging problem, and despite the advances in computational power, pixel resolution, and frame rates, even the state-of-the-art methods fall far short of the robustness, reliability and energy consumption of biological vision systems. Silicon retinas, such as the Dynamic Vision Sensor (DVS) and Asynchronous Time-based Imaging Sensor (ATIS), attempt to replicate some of the benefits of biological retinas and provide a vastly different paradigm in which to sense and process the visual world. Tasks such as tracking and object recognition still require the identification and matching of local visual features, but the detection, extraction and recognition of features requires a fundamentally different approach, and the methods that are commonly applied to conventional imaging are not directly applicable. This thesis explores methods to detect features in the spatio-temporal information from event-based vision sensors. The nature of features in such data is explored, and methods to determine and detect features are demonstrated. A framework for detecting, tracking, recognising and classifying features is developed and validated using real-world data and event-based variations of existing computer vision datasets and benchmarks. The results presented in this thesis demonstrate the potential and efficacy of event-based systems. This work provides an in-depth analysis of different event-based methods for object recognition and classification and introduces two feature-based methods. Two learning systems, one event-based and the other iterative, were used to explore the nature and classification ability of these methods. The results demonstrate the viability of event-based classification and the importance and role of motion in event-based feature detection
Книги з теми "Neuromorphic technologies":
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Pearce, Tim C. Chemosensation. Oxford University Press, 2018. http://dx.doi.org/10.1093/oso/9780199674923.003.0017.
Анотація:
Olfaction in animals still surpasses any technological solution to chemical sensing yet conceived. While certain classes of molecular detection technologies may be capable of high sensitivity to a restricted number of compounds, unique to the biological system is its astonishing dynamic range (over 10 orders of magnitude), combining both extreme levels of sensitivity to certain key compounds of behavioural importance and varying levels of discrimination between an almost infinite variety of ligands, presented both individually and in complex combinations. For over 30 years the olfactory system of insects and mammals has provided biological sensing factors, rich inspiration, and processing principles for use in developing chemical sensing technologies. Here we focus on three such technological translations: recent rapid progress in measuring directly from olfactory binding/receptor proteins and chemosensory neurons as a biohybrid solution to chemical sensing; olfactory system based processing principles and architectures that have been applied to existing chemosensor technologies to achieve real-world sensing performance gains; and full-blown neuromorphic implementations of the olfactory pathways of animals.
Частини книг з теми "Neuromorphic technologies":
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Saïghi, Sylvain. "Neuromorphic Technologies, Memristors." In Encyclopedia of Computational Neuroscience, 2001–3. New York, NY: Springer New York, 2015. http://dx.doi.org/10.1007/978-1-4614-6675-8_116.
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Saïghi, Sylvain. "Neuromorphic Technologies, Memristors." In Encyclopedia of Computational Neuroscience, 1–3. New York, NY: Springer New York, 2014. http://dx.doi.org/10.1007/978-1-4614-7320-6_116-1.
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Lim, Gerard Joseph, Calvin Ching Ian Ang, and Wen Siang Lew. "Spintronics for Neuromorphic Engineering." In Emerging Non-volatile Memory Technologies, 297–315. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-15-6912-8_9.
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Dananjaya, Putu Andhita, Roshan Gopalakrishnan, and Wen Siang Lew. "RRAM-Based Neuromorphic Computing Systems." In Emerging Non-volatile Memory Technologies, 383–414. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-15-6912-8_12.
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Narduzzi, Simon, Loreto Mateu, Petar Jokic, Erfan Azarkhish, and Andrea Dunbar. "Benchmarking Neuromorphic Computing for Inference." In Industrial Artificial Intelligence Technologies and Applications, 1–19. New York: River Publishers, 2023. http://dx.doi.org/10.1201/9781003377382-1.
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Li, Zheng, Chenchen Liu, Hai Li, and Yiran Chen. "Neuromorphic Hardware Acceleration Enabled by Emerging Technologies." In Emerging Technology and Architecture for Big-data Analytics, 217–44. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-54840-1_10.
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Molendijk, Maarten, Kanishkan Vadivel, Federico Corradi, Gert-Jan van Schaik, Amirreza Yousefzadeh, and Henk Corporaal. "Benchmarking the Epiphany Processor as a Reference Neuromorphic Architecture." In Industrial Artificial Intelligence Technologies and Applications, 21–34. New York: River Publishers, 2023. http://dx.doi.org/10.1201/9781003377382-2.
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Sengupta, Abhronil, Aayush Ankit, and Kaushik Roy. "Efficient Neuromorphic Systems and Emerging Technologies: Prospects and Perspectives." In Emerging Technology and Architecture for Big-data Analytics, 261–74. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-54840-1_12.
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Asad, Arghavan, and Farah Mohammadi. "NeuroTower: A 3D Neuromorphic Architecture with Low-Power TSVs." In Proceedings of the Future Technologies Conference (FTC) 2022, Volume 3, 227–36. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-18344-7_14.
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Narduzzi, Simon, Dorvan Favre, Nuria Pazos Escudero, and L. Andrea Dunbar. "Deploying a Convolutional Neural Network on Edge MCU and Neuromorphic Hardware Platforms." In Industrial Artificial Intelligence Technologies and Applications, 129–39. New York: River Publishers, 2023. http://dx.doi.org/10.1201/9781003377382-10.
Тези доповідей конференцій з теми "Neuromorphic technologies":
1
Kirkland, Paul, Gaetano Di Caterina, John Soraghan, and George Matich. "Neuromorphic technologies for defence and security." In Emerging Imaging and Sensing Technologies for Security and Defence V; Advanced Manufacturing Technologies for Micro- and Nanosystems in Security and Defence III, edited by Maria Farsari, John G. Rarity, Francois Kajzar, Attila Szep, Richard C. Hollins, Gerald S. Buller, Robert A. Lamb, et al. SPIE, 2020. http://dx.doi.org/10.1117/12.2575978.
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Strukov, D. "Emerging Memory Technologies for Neuromorphic Computing." In 2016 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2016. http://dx.doi.org/10.7567/ssdm.2016.b-7-02.
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Ielmini, Daniele. "Embedded memory technologies for neuromorphic computing." In Neuronics Conference. València: FUNDACIO DE LA COMUNITAT VALENCIANA SCITO, 2023. http://dx.doi.org/10.29363/nanoge.neuronics.2024.029.
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Narayanan, Pritish, Geoffrey W. Burr, Stefano Ambrogio, and Robert M. Shelby. "Neuromorphic Technologies for Next-Generation Cognitive Computing." In 2017 IEEE International Memory Workshop (IMW). IEEE, 2017. http://dx.doi.org/10.1109/imw.2017.7939095.
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Shelby, Robert M., Pritish Narayanan, Stefano Ambrogio, Hsinyu Tsai, Kohji Hosokawa, Scott C. Lewis, and Geoffrey W. Burr. "Neuromorphic technologies for next-generation cognitive computing." In 2017 IEEE Electron Devices Technology and Manufacturing Conference (EDTM). IEEE, 2017. http://dx.doi.org/10.1109/edtm.2017.7947500.
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Andrishak, Artur, Tiago L. Alves, Ricardo M. R. Adão, Christian Maibohm, Bruno Romeira, and Jana B. Nieder. "3D Polymer Interconnects for Neuromorphic Photonics Technologies." In 2023 Conference on Lasers and Electro-Optics Europe & European Quantum Electronics Conference (CLEO/Europe-EQEC). IEEE, 2023. http://dx.doi.org/10.1109/cleo/europe-eqec57999.2023.10232683.
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Stark, P., J. Weiss, R. Dangel, F. Horst, J. Geler-Kremer, and B. J. Offrein. "High-Performance Neuromorphic Computing Based on Photonic Technologies." In Optical Fiber Communication Conference. Washington, D.C.: OSA, 2021. http://dx.doi.org/10.1364/ofc.2021.tu5h.4.
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Hai Li. "Conventional and neuromorphic systems leveraging emerging memory technologies." In 2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT). IEEE, 2017. http://dx.doi.org/10.1109/vlsi-dat.2017.7939673.
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Offrein, Bert Jan, Tommaso Stecconi, Donato Francesco Falcone, Elger Anne Vlieg, Felix Hermann, Laura Bégon-Lours, Daniel Jubin, et al. "Photonic and electronic integrated technologies for neuromorphic computing." In 2023 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2023. http://dx.doi.org/10.7567/ssdm.2023.h-2-01.
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Mishra, Vishwas, Abhishek Kumar, and Shyam Akashe. "New Non-Volatile Memory Technologies and Neuromorphic Computing." In 2023 IEEE World Conference on Applied Intelligence and Computing (AIC). IEEE, 2023. http://dx.doi.org/10.1109/aic57670.2023.10263872.