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Статті в журналах з теми "Neuromorphic computer systems"

Автор: Grafiati

Опубліковано: 30 травня 2022

Оновлено: 31 травня 2022

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1

Dunham, Christopher S., Sam Lilak, Joel Hochstetter, Alon Loeffler, Ruomin Zhu, Charles Chase, Adam Z. Stieg, Zdenka Kuncic, and James K. Gimzewski. "Nanoscale neuromorphic networks and criticality: a perspective." Journal of Physics: Complexity 2, no. 4 (December 1, 2021): 042001. http://dx.doi.org/10.1088/2632-072x/ac3ad3.

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Abstract Numerous studies suggest critical dynamics may play a role in information processing and task performance in biological systems. However, studying critical dynamics in these systems can be challenging due to many confounding biological variables that limit access to the physical processes underpinning critical dynamics. Here we offer a perspective on the use of abiotic, neuromorphic nanowire networks as a means to investigate critical dynamics in complex adaptive systems. Neuromorphic nanowire networks are composed of metallic nanowires and possess metal-insulator-metal junctions. These networks self-assemble into a highly interconnected, variable-density structure and exhibit nonlinear electrical switching properties and information processing capabilities. We highlight key dynamical characteristics observed in neuromorphic nanowire networks, including persistent fluctuations in conductivity with power law distributions, hysteresis, chaotic attractor dynamics, and avalanche criticality. We posit that neuromorphic nanowire networks can function effectively as tunable abiotic physical systems for studying critical dynamics and leveraging criticality for computation.

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2

Ferreira de Lima, Thomas, Alexander N. Tait, Armin Mehrabian, Mitchell A. Nahmias, Chaoran Huang, Hsuan-Tung Peng, Bicky A. Marquez, et al. "Primer on silicon neuromorphic photonic processors: architecture and compiler." Nanophotonics 9, no. 13 (August 10, 2020): 4055–73. http://dx.doi.org/10.1515/nanoph-2020-0172.

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AbstractMicroelectronic computers have encountered challenges in meeting all of today’s demands for information processing. Meeting these demands will require the development of unconventional computers employing alternative processing models and new device physics. Neural network models have come to dominate modern machine learning algorithms, and specialized electronic hardware has been developed to implement them more efficiently. A silicon photonic integration industry promises to bring manufacturing ecosystems normally reserved for microelectronics to photonics. Photonic devices have already found simple analog signal processing niches where electronics cannot provide sufficient bandwidth and reconfigurability. In order to solve more complex information processing problems, they will have to adopt a processing model that generalizes and scales. Neuromorphic photonics aims to map physical models of optoelectronic systems to abstract models of neural networks. It represents a new opportunity for machine information processing on sub-nanosecond timescales, with application to mathematical programming, intelligent radio frequency signal processing, and real-time control. The strategy of neuromorphic engineering is to externalize the risk of developing computational theory alongside hardware. The strategy of remaining compatible with silicon photonics externalizes the risk of platform development. In this perspective article, we provide a rationale for a neuromorphic photonics processor, envisioning its architecture and a compiler. We also discuss how it can be interfaced with a general purpose computer, i.e. a CPU, as a coprocessor to target specific applications. This paper is intended for a wide audience and provides a roadmap for expanding research in the direction of transforming neuromorphic photonics into a viable and useful candidate for accelerating neuromorphic computing.

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3

Jang, Taejin, Suhyeon Kim, Jeesoo Chang, Kyung Kyu Min, Sungmin Hwang, Kyungchul Park, Jong-Ho Lee, and Byung-Gook Park. "3D AND-Type Stacked Array for Neuromorphic Systems." Micromachines 11, no. 9 (August 31, 2020): 829. http://dx.doi.org/10.3390/mi11090829.

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NOR/AND flash memory was studied in neuromorphic systems to perform vector-by-matrix multiplication (VMM) by summing the current. Because the size of NOR/AND cells exceeds those of other memristor synaptic devices, we proposed a 3D AND-type stacked array to reduce the cell size. Through a tilted implantation method, the conformal sources and drains of each cell could be formed, with confirmation by a technology computer aided design (TCAD) simulation. In addition, the cell-to-cell variation due to the etch slope could be eliminated by controlling the deposition thickness of the cells. The suggested array can be beneficial in simple program/inhibit schemes given its use of Fowler–Nordheim (FN) tunneling because the drain lines and source lines are parallel. Therefore, the conductance of each synaptic device can be updated at low power level.

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4

Liu, Te-Yuan, Ata Mahjoubfar, Daniel Prusinski, and Luis Stevens. "Neuromorphic computing for content-based image retrieval." PLOS ONE 17, no. 4 (April 6, 2022): e0264364. http://dx.doi.org/10.1371/journal.pone.0264364.

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Neuromorphic computing mimics the neural activity of the brain through emulating spiking neural networks. In numerous machine learning tasks, neuromorphic chips are expected to provide superior solutions in terms of cost and power efficiency. Here, we explore the application of Loihi, a neuromorphic computing chip developed by Intel, for the computer vision task of image retrieval. We evaluated the functionalities and the performance metrics that are critical in content-based visual search and recommender systems using deep-learning embeddings. Our results show that the neuromorphic solution is about 2.5 times more energy-efficient compared with an ARM Cortex-A72 CPU and 12.5 times more energy-efficient compared with NVIDIA T4 GPU for inference by a lightweight convolutional neural network when batch size is 1 while maintaining the same level of matching accuracy. The study validates the potential of neuromorphic computing in low-power image retrieval, as a complementary paradigm to the existing von Neumann architectures.

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5

Bhat, Pranava. "Analysis of Neuromorphic Computing Systems and its Applications in Machine Learning." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (June 30, 2021): 5309–12. http://dx.doi.org/10.22214/ijraset.2021.35601.

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The domain of engineering has always taken inspiration from the biological world. Understanding the functionalities of the human brain is one of the key areas of interest over time and has caused many advancements in the field of computing systems. The computational capability per unit power per unit volume of the human brain exceeds the current best supercomputers. Mimicking the physics of computations used by the nervous system and the brain can bring a paradigm shift to the computing systems. The concept of bridging computing and neural systems can be termed as neuromorphic computing and it is bringing revolutionary changes in the computing hardware. Neuromorphic computing systems have seen swift progress in the past decades. Many organizations have introduced a variety of designs, implementation methodologies and prototype chips. This paper discusses the parameters that are considered in the advanced neuromorphic computing systems and the tradeoffs between them. There have been attempts made to make computer models of neurons. Advancements in the hardware implementation are fuelling the applications in the field of machine learning. This paper presents the applications of these modern computing systems in Machine Learning.

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6

Choi, Hyun-Seok, Yu Jeong Park, Jong-Ho Lee, and Yoon Kim. "3-D Synapse Array Architecture Based on Charge-Trap Flash Memory for Neuromorphic Application." Electronics 9, no. 1 (December 30, 2019): 57. http://dx.doi.org/10.3390/electronics9010057.

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In order to address a fundamental bottleneck of conventional digital computers, there is recently a tremendous upsurge of investigations on hardware-based neuromorphic systems. To emulate the functionalities of artificial neural networks, various synaptic devices and their 2-D cross-point array structures have been proposed. In our previous work, we proposed the 3-D synapse array architecture based on a charge-trap flash (CTF) memory. It has the advantages of high-density integration of 3-D stacking technology and excellent reliability characteristics of mature CTF device technology. This paper examines some issues of the 3-D synapse array architecture. Also, we propose an improved structure and programming method compared to the previous work. The synaptic characteristics of the proposed method are closely examined and validated through a technology computer-aided design (TCAD) device simulation and a system-level simulation for the pattern recognition task. The proposed technology will be the promising solution for high-performance and high-reliability of neuromorphic hardware systems.

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7

Varshika, M. Lakshmi, Federico Corradi, and Anup Das. "Nonvolatile Memories in Spiking Neural Network Architectures: Current and Emerging Trends." Electronics 11, no. 10 (May 18, 2022): 1610. http://dx.doi.org/10.3390/electronics11101610.

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A sustainable computing scenario demands more energy-efficient processors. Neuromorphic systems mimic biological functions by employing spiking neural networks for achieving brain-like efficiency, speed, adaptability, and intelligence. Current trends in neuromorphic technologies address the challenges of investigating novel materials, systems, and architectures for enabling high-integration and extreme low-power brain-inspired computing. This review collects the most recent trends in exploiting the physical properties of nonvolatile memory technologies for implementing efficient in-memory and in-device computing with spike-based neuromorphic architectures.

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8

Young, Aaron R., Mark E. Dean, James S. Plank, and Garrett S. Rose. "A Review of Spiking Neuromorphic Hardware Communication Systems." IEEE Access 7 (2019): 135606–20. http://dx.doi.org/10.1109/access.2019.2941772.

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9

Chung, Jaeyong, Taehwan Shin, and Joon-Sung Yang. "Simplifying Deep Neural Networks for FPGA-Like Neuromorphic Systems." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 38, no. 11 (November 2019): 2032–42. http://dx.doi.org/10.1109/tcad.2018.2877016.

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10

Kang, Yongshin, Joon-Sung Yang, and Jaeyong Chung. "Weight Partitioning for Dynamic Fixed-Point Neuromorphic Computing Systems." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 38, no. 11 (November 2019): 2167–71. http://dx.doi.org/10.1109/tcad.2018.2878167.

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11

Kurshan, Eren, Hai Li, Mingoo Seok, and Yuan Xie. "A Case for 3D Integrated System Design for Neuromorphic Computing and AI Applications." International Journal of Semantic Computing 14, no. 04 (December 2020): 457–75. http://dx.doi.org/10.1142/s1793351x20500063.

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Анотація:

Over the last decade, artificial intelligence (AI) has found many applications areas in the society. As AI solutions have become more sophistication and the use cases grew, they highlighted the need to address performance and energy efficiency challenges faced during the implementation process. To address these challenges, there has been growing interest in neuromorphic chips. Neuromorphic computing relies on non von Neumann architectures as well as novel devices, circuits and manufacturing technologies to mimic the human brain. Among such technologies, three-dimensional (3D) integration is an important enabler for AI hardware and the continuation of the scaling laws. In this paper, we overview the unique opportunities 3D integration provides in neuromorphic chip design, discuss the emerging opportunities in next generation neuromorphic architectures and review the obstacles. Neuromorphic architectures, which relied on the brain for inspiration and emulation purposes, face grand challenges due to the limited understanding of the functionality and the architecture of the human brain. Yet, high-levels of investments are dedicated to develop neuromorphic chips. We argue that 3D integration not only provides strategic advantages to the cost-effective and flexible design of neuromorphic chips, it may provide design flexibility in incorporating advanced capabilities to further benefit the designs in the future.

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12

Hughes, Mark A., Mike J. Shipston, and Alan F. Murray. "Towards a ‘siliconeural computer’: technological successes and challenges." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 373, no. 2046 (July 28, 2015): 20140217. http://dx.doi.org/10.1098/rsta.2014.0217.

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Electronic signals govern the function of both nervous systems and computers, albeit in different ways. As such, hybridizing both systems to create an iono-electric brain–computer interface is a realistic goal; and one that promises exciting advances in both heterotic computing and neuroprosthetics capable of circumventing devastating neuropathology. ‘Neural networks’ were, in the 1980s, viewed naively as a potential panacea for all computational problems that did not fit well with conventional computing. The field bifurcated during the 1990s into a highly successful and much more realistic machine learning community and an equally pragmatic, biologically oriented ‘neuromorphic computing’ community. Algorithms found in nature that use the non-synchronous, spiking nature of neuronal signals have been found to be (i) implementable efficiently in silicon and (ii) computationally useful. As a result, interest has grown in techniques that could create mixed ‘siliconeural’ computers. Here, we discuss potential approaches and focus on one particular platform using parylene-patterned silicon dioxide.

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13

Yang, Chaofei, Ximing Qiao, and Yiran Chen. "Neuromorphic Computing Systems: From CMOS To Emerging Nonvolatile Memory." IPSJ Transactions on System LSI Design Methodology 12 (2019): 53–64. http://dx.doi.org/10.2197/ipsjtsldm.12.53.

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14

Jeong, YeonJoo, Mohammed A. Zidan, and Wei D. Lu. "Parasitic Effect Analysis in Memristor-Array-Based Neuromorphic Systems." IEEE Transactions on Nanotechnology 17, no. 1 (January 2018): 184–93. http://dx.doi.org/10.1109/tnano.2017.2784364.

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15

Bieszczad, Andrzej, and Bernard Pagurek. "Neurosolver: Neuromorphic general problem solver." Information Sciences 105, no. 1-4 (March 1998): 239–77. http://dx.doi.org/10.1016/s0020-0255(97)10027-5.

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16

Bhattacharya, Tinish, Sai Li, Yangqi Huang, Wang Kang, Weisheng Zhao, and Manan Suri. "Low-Power (1T1N) Skyrmionic Synapses for Spiking Neuromorphic Systems." IEEE Access 7 (2019): 5034–44. http://dx.doi.org/10.1109/access.2018.2886854.

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17

McOWAN, PETER W., CHRISTOPHER BENTON, JASON DALE, and ALAN JOHNSTON. "A MULTI-DIFFERENTIAL NEUROMORPHIC APPROACH TO MOTION DETECTION." International Journal of Neural Systems 09, no. 05 (October 1999): 429–34. http://dx.doi.org/10.1142/s0129065799000435.

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This paper presents a multi-differential neuromorphic approach to motion detection. The model is based evidence for a differential operators interpretation of the properties of the cortical motion pathway. We discuss how this strategy, which provides a robusl measure of speed for a range of types of image motion using a single compulational mechanism, forms a usful framework in which to develop future neuromorphic motion systems. We also discuss both our approaches to developing computational motion models, and constraints in the design strategy for transferring motion models to other domains of early visual processing.

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18

Kotov, V. B., and F. A. Yudkin. "Modeling and Characterization of Resistor Elements for Neuromorphic Systems." Optical Memory and Neural Networks 28, no. 4 (October 2019): 271–82. http://dx.doi.org/10.3103/s1060992x19040040.

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19

Serrano-Gotarredona, T., T. Prodromakis, and B. Linares-Barranco. "A Proposal for Hybrid Memristor-CMOS Spiking Neuromorphic Learning Systems." IEEE Circuits and Systems Magazine 13, no. 2 (2013): 74–88. http://dx.doi.org/10.1109/mcas.2013.2256271.

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20

Qi, Meng, Tianquan Fu, Huadong Yang, Ye Tao, Chunran Li, and Xiaoming Xiu. "Reliable analog resistive switching behaviors achieved using memristive devices in AlO _x /HfO _x bilayer structure for neuromorphic systems." Semiconductor Science and Technology 37, no. 3 (January 31, 2022): 035018. http://dx.doi.org/10.1088/1361-6641/ac3cc7.

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Abstract Human brain synaptic memory simulation based on resistive random access memory (RRAM) has enormous potential to replace the traditional von Neumann digital computer thanks to several advantages, including its simple structure, its high-density integration, and its capabilities regarding information storage and neuromorphic computing. Herein, the reliable resistive switching (RS) behaviors of RRAM are demonstrated by engineering the AlO x /HfO x bilayer structure. This allows for uniform multibit information storage. Further, the analog switching behaviors are capable of imitating several synaptic learning functions, including learning experience behaviors, short-term plasticity, long-term plasticity transition, and spike-timing-dependent plasticity (STDP). In addition, the memristor based on STDP learning rules is implemented in image pattern recognition. These results may show the potential of HfO x -based memristors for future information storage and neuromorphic computing applications.

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21

Hazan, Avi, and Elishai Ezra Tsur. "Neuromorphic Neural Engineering Framework-Inspired Online Continuous Learning with Analog Circuitry." Applied Sciences 12, no. 9 (April 29, 2022): 4528. http://dx.doi.org/10.3390/app12094528.

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Neuromorphic hardware designs realize neural principles in electronics to provide high-performing, energy-efficient frameworks for machine learning. Here, we propose a neuromorphic analog design for continuous real-time learning. Our hardware design realizes the underlying principles of the neural engineering framework (NEF). NEF brings forth a theoretical framework for the representation and transformation of mathematical constructs with spiking neurons, thus providing efficient means for neuromorphic machine learning and the design of intricate dynamical systems. Our analog circuit design implements the neuromorphic prescribed error sensitivity (PES) learning rule with OZ neurons. OZ is an analog implementation of a spiking neuron, which was shown to have complete correspondence with NEF across firing rates, encoding vectors, and intercepts. We demonstrate PES-based neuromorphic representation of mathematical constructs with varying neuron configurations, the transformation of mathematical constructs, and the construction of a dynamical system with the design of an inducible leaky oscillator. We further designed a circuit emulator, allowing the evaluation of our electrical designs on a large scale. We used the circuit emulator in conjunction with a robot simulator to demonstrate adaptive learning-based control of a robotic arm with six degrees of freedom.

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22

Chen, Guang, Hu Cao, Muhammad Aafaque, Jieneng Chen, Canbo Ye, Florian Röhrbein, Jörg Conradt, et al. "Neuromorphic Vision Based Multivehicle Detection and Tracking for Intelligent Transportation System." Journal of Advanced Transportation 2018 (December 2, 2018): 1–13. http://dx.doi.org/10.1155/2018/4815383.

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Neuromorphic vision sensor is a new passive sensing modality and a frameless sensor with a number of advantages over traditional cameras. Instead of wastefully sending entire images at fixed frame rate, neuromorphic vision sensor only transmits the local pixel-level changes caused by the movement in a scene at the time they occur. This results in advantageous characteristics, in terms of low energy consumption, high dynamic range, sparse event stream, and low response latency, which can be very useful in intelligent perception systems for modern intelligent transportation system (ITS) that requires efficient wireless data communication and low power embedded computing resources. In this paper, we propose the first neuromorphic vision based multivehicle detection and tracking system in ITS. The performance of the system is evaluated with a dataset recorded by a neuromorphic vision sensor mounted on a highway bridge. We performed a preliminary multivehicle tracking-by-clustering study using three classical clustering approaches and four tracking approaches. Our experiment results indicate that, by making full use of the low latency and sparse event stream, we could easily integrate an online tracking-by-clustering system running at a high frame rate, which far exceeds the real-time capabilities of traditional frame-based cameras. If the accuracy is prioritized, the tracking task can also be performed robustly at a relatively high rate with different combinations of algorithms. We also provide our dataset and evaluation approaches serving as the first neuromorphic benchmark in ITS and hopefully can motivate further research on neuromorphic vision sensors for ITS solutions.

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23

Wang, Ye-Guo. "Applications of Memristors in Neural Networks and Neuromorphic Computing: A Review." International Journal of Machine Learning and Computing 11, no. 5 (September 2021): 350–56. http://dx.doi.org/10.18178/ijmlc.2021.11.5.1060.

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24

Trik, Mohammad, Saadat Pour Mozaffari, and Amir Massoud Bidgoli. "Providing an Adaptive Routing along with a Hybrid Selection Strategy to Increase Efficiency in NoC-Based Neuromorphic Systems." Computational Intelligence and Neuroscience 2021 (September 15, 2021): 1–8. http://dx.doi.org/10.1155/2021/8338903.

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Effective and efficient routing is one of the most important parts of routing in NoC-based neuromorphic systems. In fact, this communication structure connects different units through the packets routed by routers and switches embedded in the network on a chip. With the help of this capability, not only high scalability and high development can be created, but by decreasing the global wiring to the chip level, power consumption can be reduced. In this paper, an adaptive routing algorithm for NoC-based neuromorphic systems is proposed along with a hybrid selection strategy. Accordingly, a traffic analyzer is first used to determine the type of local or nonlocal traffic depending on the number of hops. Then, considering the type of traffic, the RCA and NoP selection strategies are used for the nonlocal and local strategies, respectively. Finally, using the experiments that performed in the simulator environment, it has been shown that this solution can well reduce the average delay time and power consumption.

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25

Yu, Cho, and Park. "A Silicon-Compatible Synaptic Transistor Capable of Multiple Synaptic Weights toward Energy-Efficient Neuromorphic Systems." Electronics 8, no. 10 (September 30, 2019): 1102. http://dx.doi.org/10.3390/electronics8101102.

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In order to resolve the issue of tremendous energy consumption in conventional artificial intelligence, hardware-based neuromorphic system is being actively studied. Although various synaptic devices for the system have been proposed, they have shown limits in terms of endurance, reliability, energy efficiency, and Si processing compatibility. In this work, we design a synaptic transistor with short-term and long-term plasticity, high density, high reliability and energy efficiency, and Si processing compatibility. The synaptic characteristics of the device are closely examined and validated through technology computer-aided design (TCAD) device simulation. Consequently, full synaptic functions with high energy efficiency have been realized.

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26

Partzsch, Johannes, Christian Mayr, Massimiliano Giulioni, Marko Noack, Stefan Hänzsche, Stefan Scholze, Sebastian Höppner, Paolo Del Giudice, and Rene Schüffny. "Mean Field Approach for Configuring Population Dynamics on a Biohybrid Neuromorphic System." Journal of Signal Processing Systems 92, no. 11 (June 27, 2020): 1303–21. http://dx.doi.org/10.1007/s11265-020-01556-9.

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Abstract Real-time coupling of cell cultures to neuromorphic circuits necessitates a neuromorphic network that replicates biological behaviour both on a per-neuron and on a population basis, with a network size comparable to the culture. We present a large neuromorphic system composed of 9 chips, with overall 2880 neurons and 144M conductance-based synapses. As they are realized in a robust switched-capacitor fashion, individual neurons and synapses can be configured to replicate with high fidelity a wide range of biologically realistic behaviour. In contrast to other exploration/heuristics-based approaches, we employ a theory-guided mesoscopic approach to configure the overall network to a range of bursting behaviours, thus replicating the statistics of our targeted in-vitro network. The mesoscopic approach has implications beyond our proposed biohybrid, as it allows a targeted exploration of the behavioural space, which is a non-trivial task especially in large, recurrent networks.

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27

Sánchez Quintana, Carlos, Francisco Moreno Arcas, David Albarracín Molina, José David Fernández Rodriguez, and Francisco J. Vico. "Melomics: A Case-Study of AI in Spain." AI Magazine 34, no. 3 (September 15, 2013): 99–103. http://dx.doi.org/10.1609/aimag.v34i3.2464.

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Traditionally focused on good old-fashioned AI and robotics, the Spanish AI community holds a vigorous computational intelligence substrate. Neuromorphic, evolutionary, or fuzzylike systems have been developed by many research groups in the Spanish computer sciences. It is no surprise, then, that these naturegrounded efforts start to emerge, enriching the AI catalogue of research projects and publications and, eventually, leading to new directions of basic or applied research. In this article, we review the contribution of Melomics in computational creativity.

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28

Grübl, Andreas, Sebastian Billaudelle, Benjamin Cramer, Vitali Karasenko, and Johannes Schemmel. "Verification and Design Methods for the BrainScaleS Neuromorphic Hardware System." Journal of Signal Processing Systems 92, no. 11 (July 9, 2020): 1277–92. http://dx.doi.org/10.1007/s11265-020-01558-7.

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Abstract This paper presents verification and implementation methods that have been developed for the design of the BrainScaleS-2 65 nm ASICs. The 2nd generation BrainScaleS chips are mixed-signal devices with tight coupling between full-custom analog neuromorphic circuits and two general purpose microprocessors (PPU) with SIMD extension for on-chip learning and plasticity. Simulation methods for automated analysis and pre-tapeout calibration of the highly parameterizable analog neuron and synapse circuits and for hardware-software co-development of the digital logic and software stack are presented. Accelerated operation of neuromorphic circuits and highly-parallel digital data buses between the full-custom neuromorphic part and the PPU require custom methodologies to close the digital signal timing at the interfaces. Novel extensions to the standard digital physical implementation design flow are highlighted. We present early results from the first full-size BrainScaleS-2 ASIC containing 512 neurons and 130 K synapses, demonstrating the successful application of these methods. An application example illustrates the full functionality of the BrainScaleS-2 hybrid plasticity architecture.

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Slavova, Angela, and Ventsislav Ignatov. "Edge of Chaos in Memristor Cellular Nonlinear Networks." Mathematics 10, no. 8 (April 12, 2022): 1288. http://dx.doi.org/10.3390/math10081288.

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Information processing in the brain takes place in a dense network of neurons connected through synapses. The collaborative work between these two components (Synapses and Neurons) allows for basic brain functions such as learning and memorization. The so-called von Neumann bottleneck, which limits the information processing capability of conventional systems, can be overcome by the efficient emulation of these computational concepts. To this end, mimicking the neuronal architectures with silicon-based circuits, on which neuromorphic engineering is based, is accompanied by the development of new devices with neuromorphic functionalities. We shall study different memristor cellular nonlinear networks models. The rigorous mathematical analysis will be presented based on local activity theory, and the edge of chaos domain will be determined in the models under consideration. Simulations of these models working on the edge of chaos will show the generation of static and dynamic patterns.

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30

Brüderle, Daniel, Mihai A. Petrovici, Bernhard Vogginger, Matthias Ehrlich, Thomas Pfeil, Sebastian Millner, Andreas Grübl, et al. "A comprehensive workflow for general-purpose neural modeling with highly configurable neuromorphic hardware systems." Biological Cybernetics 104, no. 4-5 (May 2011): 263–96. http://dx.doi.org/10.1007/s00422-011-0435-9.

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31

Folgheraiter, Michele, Amina Keldibek, Bauyrzhan Aubakir, Giuseppina Gini, Alessio Mauro Franchi, and Matteo Bana. "A neuromorphic control architecture for a biped robot." Robotics and Autonomous Systems 120 (October 2019): 103244. http://dx.doi.org/10.1016/j.robot.2019.07.014.

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32

Vu, The H., Ogbodo Mark Ikechukwu, and Abderazek Ben Abdallah. "Fault-Tolerant Spike Routing Algorithm and Architecture for Three Dimensional NoC-Based Neuromorphic Systems." IEEE Access 7 (2019): 90436–52. http://dx.doi.org/10.1109/access.2019.2925085.

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33

Reichel, Lukas, David Liechti, Karl Presser, and Shih-Chii Liu. "Range estimation on a robot using neuromorphic motion sensors." Robotics and Autonomous Systems 51, no. 2-3 (May 2005): 167–74. http://dx.doi.org/10.1016/j.robot.2004.10.005.

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34

Alimisis, Vassilis, Marios Gourdouparis, Georgios Gennis, Christos Dimas, and Paul P. Sotiriadis. "Analog Gaussian Function Circuit: Architectures, Operating Principles and Applications." Electronics 10, no. 20 (October 17, 2021): 2530. http://dx.doi.org/10.3390/electronics10202530.

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Анотація:

This review paper explores existing architectures, operating principles, performance metrics and applications of analog Gaussian function circuits. Architectures based on the translinear principle, the bulk-controlled approach, the floating gate approach, the use of multiple differential pairs, compositions of different fundamental blocks and others are considered. Applications involving analog implementations of Machine Learning algorithms, neuromorphic circuits, smart sensor systems and fuzzy/neuro-fuzzy systems are discussed, focusing on the role of the Gaussian function circuit. Finally, a general discussion and concluding remarks are provided.

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35

Qiu, Qinru, Zhe Li, Khadeer Ahmed, Wei Liu, Syed Faisal Habib, Hai (Helen) Li, and Miao Hu. "A Neuromorphic Architecture for Context Aware Text Image Recognition." Journal of Signal Processing Systems 84, no. 3 (November 4, 2015): 355–69. http://dx.doi.org/10.1007/s11265-015-1067-4.

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36

Abad Peraza, Viviana, José Manuel Ferrández Vicente, and Ernesto Arturo Martínez Rams. "Bioinspired Auditory Model for Vowel Recognition." Electronics 10, no. 18 (September 18, 2021): 2304. http://dx.doi.org/10.3390/electronics10182304.

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In this work, a bioinspired or neuromorphic model to replicate the vowel recognition process for an auditory system is presented. A bioinspired peripheral and central auditory system model is implemented and a neuromorphic higher auditory system model based on artificial neuronal nets for vowel recognition is proposed. For their verification, ten Hispanic Spanish language-speaking adults (five males and five females) were used. With the proposed bioinspired model based on artificial neuronal nets it is possible to recognize with high levels of accuracy and sensibility the vowels phonemes of speech signals and the assessment of cochlear implant stimulation strategies in terms of vowel recognition.

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37

Pérez-Bosch Quesada, Emilio, Rocío Romero-Zaliz, Eduardo Pérez, Mamathamba Kalishettyhalli Mahadevaiah, John Reuben, Markus Andreas Schubert, Francisco Jiménez-Molinos, Juan Bautista Roldán, and Christian Wenger. "Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems." Electronics 10, no. 6 (March 11, 2021): 645. http://dx.doi.org/10.3390/electronics10060645.

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In this work, three different RRAM compact models implemented in Verilog-A are analyzed and evaluated in order to reproduce the multilevel approach based on the switching capability of experimental devices. These models are integrated in 1T-1R cells to control their analog behavior by means of the compliance current imposed by the NMOS select transistor. Four different resistance levels are simulated and assessed with experimental verification to account for their multilevel capability. Further, an Artificial Neural Network study is carried out to evaluate in a real scenario the viability of the multilevel approach under study.

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38

Balaji, Adarsha, Thibaut Marty, Anup Das, and Francky Catthoor. "Run-time Mapping of Spiking Neural Networks to Neuromorphic Hardware." Journal of Signal Processing Systems 92, no. 11 (July 28, 2020): 1293–302. http://dx.doi.org/10.1007/s11265-020-01573-8.

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39

Khan, Nabeel, Khurram Iqbal, and Maria G. Martini. "Time-Aggregation-Based Lossless Video Encoding for Neuromorphic Vision Sensor Data." IEEE Internet of Things Journal 8, no. 1 (January 1, 2021): 596–609. http://dx.doi.org/10.1109/jiot.2020.3007866.

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40

Pérez, Eduardo, Antonio Javier Pérez-Ávila, Rocío Romero-Zaliz, Mamathamba Kalishettyhalli Mahadevaiah, Emilio Pérez-Bosch Quesada, Juan Bautista Roldán, Francisco Jiménez-Molinos, and Christian Wenger. "Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing." Electronics 10, no. 9 (May 3, 2021): 1084. http://dx.doi.org/10.3390/electronics10091084.

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Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by tuning the programming parameters of the multi-level incremental step pulse with verify algorithm (M-ISPVA). The optimized set of parameters was assessed by comparing its results with a non-optimized one. The optimized set of parameters proved to be an effective way to define non-overlapped conductive levels due to the strong reduction of the device-to-device variability as well as of the cycle-to-cycle variability, assessed by inter-levels switching tests and during 1k reset-set cycles. In order to evaluate this improvement in real scenarios, the experimental characteristics of the RRAM devices were captured by means of a behavioral model, which was used to simulate two different neuromorphic systems: an 8×8 vector-matrix-multiplication (VMM) accelerator and a 4-layer feedforward neural network for MNIST database recognition. The results clearly showed that the optimization of the programming parameters improved both the precision of VMM results as well as the recognition accuracy of the neural network in about 6% compared with the use of non-optimized parameters.

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41

Malavena, Gerardo, Alessandro Sottocornola Spinelli, and Christian Monzio Compagnoni. "A Noise-Resilient Neuromorphic Digit Classifier Based on NOR Flash Memories with Pulse–Width Modulation Scheme." Electronics 10, no. 22 (November 13, 2021): 2784. http://dx.doi.org/10.3390/electronics10222784.

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In this work, we investigate the implementation of a neuromorphic digit classifier based on NOR Flash memory arrays as artificial synaptic arrays and exploiting a pulse-width modulation (PWM) scheme. Its performance is compared in presence of various noise sources against what achieved when a classical pulse-amplitude modulation (PAM) scheme is employed. First, by modeling the cell threshold voltage (VT) placement affected by program noise during a program-and-verify scheme based on incremental step pulse programming (ISPP), we show that the classifier truthfulness degradation due to the limited program accuracy achieved in the PWM case is considerably lower than that obtained with the PAM approach. Then, a similar analysis is carried out to investigate the classifier behavior after program in presence of cell VT instabilities due to random telegraph noise (RTN) and to temperature variations, leading again to results in favor of the PWM approach. In light of these results, the present work suggests a viable solution to overcome some of the more serious reliability issues of NOR Flash-based artificial neural networks, paving the way to the implementation of highly-reliable, noise-resilient neuromorphic systems.

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42

Kwon, Kyuahn, and Jaeyong Chung. "Reducing Parameters of Neural Networks via Recursive Tensor Approximation." Electronics 11, no. 2 (January 11, 2022): 214. http://dx.doi.org/10.3390/electronics11020214.

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Large-scale neural networks have attracted much attention for surprising results in various cognitive tasks such as object detection and image classification. However, the large number of weight parameters in the complex networks can be problematic when the models are deployed to embedded systems. In addition, the problems are exacerbated in emerging neuromorphic computers, where each weight parameter is stored within a synapse, the primary computational resource of the bio-inspired computers. We describe an effective way of reducing the parameters by a recursive tensor factorization method. Applying the singular value decomposition in a recursive manner decomposes a tensor that represents the weight parameters. Then, the tensor is approximated by algorithms minimizing the approximation error and the number of parameters. This process factorizes a given network, yielding a deeper, less dense, and weight-shared network with good initial weights, which can be fine-tuned by gradient descent.

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43

D'Angelo, Robert, Richard Wood, Nathan Lowry, Geremy Freifeld, Haiyao Huang, Christopher D. Salthouse, Brent Hollosi, et al. "A Computationally Efficient Visual Saliency Algorithm Suitable for an Analog CMOS Implementation." Neural Computation 30, no. 9 (September 2018): 2439–71. http://dx.doi.org/10.1162/neco_a_01106.

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Computer vision algorithms are often limited in their application by the large amount of data that must be processed. Mammalian vision systems mitigate this high bandwidth requirement by prioritizing certain regions of the visual field with neural circuits that select the most salient regions. This work introduces a novel and computationally efficient visual saliency algorithm for performing this neuromorphic attention-based data reduction. The proposed algorithm has the added advantage that it is compatible with an analog CMOS design while still achieving comparable performance to existing state-of-the-art saliency algorithms. This compatibility allows for direct integration with the analog-to-digital conversion circuitry present in CMOS image sensors. This integration leads to power savings in the converter by quantizing only the salient pixels. Further system-level power savings are gained by reducing the amount of data that must be transmitted and processed in the digital domain. The analog CMOS compatible formulation relies on a pulse width (i.e., time mode) encoding of the pixel data that is compatible with pulse-mode imagers and slope based converters often used in imager designs. This letter begins by discussing this time-mode encoding for implementing neuromorphic architectures. Next, the proposed algorithm is derived. Hardware-oriented optimizations and modifications to this algorithm are proposed and discussed. Next, a metric for quantifying saliency accuracy is proposed, and simulation results of this metric are presented. Finally, an analog synthesis approach for a time-mode architecture is outlined, and postsynthesis transistor-level simulations that demonstrate functionality of an implementation in a modern CMOS process are discussed.

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44

Grübl, Andreas, Sebastian Billaudelle, Benjamin Cramer, Vitali Karasenko, and Johannes Schemmel. "Correction to: Verification and Design Methods for the BrainScaleS Neuromorphic Hardware System." Journal of Signal Processing Systems 92, no. 11 (August 13, 2020): 1345. http://dx.doi.org/10.1007/s11265-020-01584-5.

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45

Fayyazi, Arash, Mohammad Ansari, Mehdi Kamal, Ali Afzali-Kusha, and Massoud Pedram. "An Ultra Low-Power Memristive Neuromorphic Circuit for Internet of Things Smart Sensors." IEEE Internet of Things Journal 5, no. 2 (April 2018): 1011–22. http://dx.doi.org/10.1109/jiot.2018.2799948.

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46

Liu, Xiangyong, Guang Chen, Xuesong Sun, and Alois Knoll. "Ground Moving Vehicle Detection and Movement Tracking Based on the Neuromorphic Vision Sensor." IEEE Internet of Things Journal 7, no. 9 (September 2020): 9026–39. http://dx.doi.org/10.1109/jiot.2020.3001167.

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47

Woo, Sung Yun, Dongseok Kwon, Nagyong Choi, Won-Mook Kang, Young-Tak Seo, Min-Kyu Park, Jong-Ho Bae, Byung-Gook Park, and Jong-Ho Lee. "Low-Power and High-Density Neuron Device for Simultaneous Processing of Excitatory and Inhibitory Signals in Neuromorphic Systems." IEEE Access 8 (2020): 202639–47. http://dx.doi.org/10.1109/access.2020.3036088.

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48

Panin, Gennady N. "Low-Dimensional Layered Light-Sensitive Memristive Structures for Energy-Efficient Machine Vision." Electronics 11, no. 4 (February 17, 2022): 619. http://dx.doi.org/10.3390/electronics11040619.

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Layered two-dimensional (2D) and quasi-zero-dimensional (0D) materials effectively absorb radiation in the wide ultraviolet, visible, infrared, and terahertz ranges. Photomemristive structures made of such low-dimensional materials are of great interest for creating optoelectronic platforms for energy-efficient storage and processing of data and optical signals in real time. Here, photosensor and memristor structures based on graphene, graphene oxide, bismuth oxyselenide, and transition metal dichalcogenides are reviewed from the point of view of application in broadband image recognition in artificial intelligence systems for autonomous unmanned vehicles, as well as the compatibility of the formation of layered neuromorphic structures with CMOS technology.

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49

Nwakanma, Cosmas Ifeanyi, Jae-Woo Kim, Jae-Min Lee, and Dong-Seong Kim. "Edge AI prospect using the NeuroEdge computing system: Introducing a novel neuromorphic technology." ICT Express 7, no. 2 (June 2021): 152–57. http://dx.doi.org/10.1016/j.icte.2021.05.003.

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50

Habu, Yasushi, Keiichiro Uta, and Yasuhiro Fukuoka. "Three-dimensional walking of a simulated muscle-driven quadruped robot with neuromorphic two-level central pattern generators." International Journal of Advanced Robotic Systems 16, no. 6 (November 1, 2019): 172988141988528. http://dx.doi.org/10.1177/1729881419885288.

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We aim to design a neuromorphic controller for the locomotion of a quadruped robot with muscle-driven leg mechanisms. To this end, we use a simulated cat model; each leg of the model is equipped with three joints driven by six muscle models incorporating two-joint muscles. For each leg, we use a two-level central pattern generator consisting of a rhythm generation part to produce basic rhythms and a pattern formation part to synergistically activate a different set of muscles in each of the four sequential phases (swing, touchdown, stance, and liftoff). Conventionally, it was difficult for a quadruped model with such realistic neural systems and muscle-driven leg mechanisms to walk even on flat terrain, but because of our improved neural and mechanical components, our quadruped model succeeds in reproducing motoneuron activations and leg trajectories similar to those in cats and achieves stable three-dimensional locomotion at a variety of speeds. Moreover, the quadruped is capable of walking upslope and over irregular terrains and adapting to perturbations, even without adjusting the parameters.

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