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Статті в журналах з теми "Multiply and accumulate"

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Автор: Grafiati

Опубліковано: 14 березня 2023

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1

Pawar, Roshani, and Dr S. S. Shriramwar. "Review on Multiply-Accumulate Unit." International Journal of Engineering Research and Applications 07, no. 06 (June 2017): 09–13. http://dx.doi.org/10.9790/9622-0706040913.

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2

Lee, Young Seo, Kyung Min Kim, Ji Heon Lee, Young-Ho Gong, Seon Wook Kim, and Sung Woo Chung. "Monolithic 3D stacked multiply-accumulate units." Integration 76 (January 2021): 183–89. http://dx.doi.org/10.1016/j.vlsi.2020.10.006.

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3

Mohammaden, Amr, Mohammed Fouda, Ihsen Alouani, Lobna A. Said, and Ahmed Radwan. "CNTFET-Based Ternary Multiply-and-Accumulate Unit." Electronics 11, no. 9 (April 30, 2022): 1455. http://dx.doi.org/10.3390/electronics11091455.

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Анотація:

Multiply-Accumulate (MAC) is one of the most commonly used operations in modern computing systems due to its use in matrix multiplication, signal processing, and in new applications such as machine learning and deep neural networks. Ternary number system offers higher information processing within the same number of digits when compared to binary systems. In this paper, a MAC is proposed using a CNTFET-based ternary logic number. Specifically, we build a 5-trit multiplier and 10-trit adder as building blocks of two ternary MAC unit designs. The first is a basic MAC which has two methods to implement, serial and pipeline. The second is an improved MAC design that optimizes the number of transistors, offers higher performance and lower power consumption. The designed MAC unit can operate up to 300MHz. Finally, a comparative study in terms of power, delay, and area variations is conducted under different supply voltages and temperature levels.

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4

Nahmias, Mitchell A., Thomas Ferreira de Lima, Alexander N. Tait, Hsuan-Tung Peng, Bhavin J. Shastri, and Paul R. Prucnal. "Photonic Multiply-Accumulate Operations for Neural Networks." IEEE Journal of Selected Topics in Quantum Electronics 26, no. 1 (January 2020): 1–18. http://dx.doi.org/10.1109/jstqe.2019.2941485.

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5

HG, Rangaraju, Arpitha H S, and Muralidhara K N. "Design of Efficient Reversible Multiply Accumulate (MAC) Unit." International Journal of Computer Applications 85, no. 16 (January 16, 2014): 1–12. http://dx.doi.org/10.5120/14922-3338.

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6

Kashfi, Fatemeh, S. Mehdi Fakhraie, and Saeed Safari. "Designing an ultra-high-speed multiply-accumulate structure." Microelectronics Journal 39, no. 12 (December 2008): 1476–84. http://dx.doi.org/10.1016/j.mejo.2008.07.006.

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7

Israel, Scott, Steven C. Gustafson, and Edmond S. Cooley. "Asynchronous integrated optical multiply accumulate with sideways summer." Applied Optics 25, no. 14 (July 15, 1986): 2284. http://dx.doi.org/10.1364/ao.25.002284.

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8

Nielsen, Christian D., and Alain J. Martin. "Design of a delay-insensitive multiply-accumulate unit." Integration 15, no. 3 (October 1993): 291–311. http://dx.doi.org/10.1016/0167-9260(93)90034-a.

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9

Bhuvaneswary, N., S. Prabu, K. Tamilselvan, and K. G. Parthiban. "Efficient Implementation of Multiply Accumulate Operation Unit Using an Interlaced Partition Multiplier." Journal of Computational and Theoretical Nanoscience 18, no. 4 (April 1, 2021): 1321–26. http://dx.doi.org/10.1166/jctn.2021.9398.

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Анотація:

A new strategy for quick multiplication of two numbers is introduced. Inputs are separated into segments, and one segment is replaced by two with zeros interlocking in each alternative segments. With zero carries between segments the product are computed, within the time needed to multiply the short partitions and add the partial sums. The multiplication of two numbers generated and adds that product to an accumulator by multiply accumulate operation (MAC unit). This operation is performed within the MAC unit. MAC is an advanced co-processor that plays a vital role in FFT, DFT, etc. The MAC unit is utilized for additional execution and its input is given to the proposed multiplier that provides a trivial speed increment over the array multiplier designs. This paper is utilized to design speed enhanced multiply Accumulate Unit by an Interlaced Partition Multiplier. This new multiplier design simulation is optimized with existing method.

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10

Liu, Xu, Xudong Zhu, Chunqing Wang, Yifan Cao, Baihang Wang, Hanwen Ou, Yizheng Wu, et al. "Silicon-Based Metastructure Optical Scattering Multiply–Accumulate Computation Chip." Nanomaterials 12, no. 13 (June 21, 2022): 2136. http://dx.doi.org/10.3390/nano12132136.

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Optical neural networks (ONN) have become the most promising solution to replacing electronic neural networks, which have the advantages of large bandwidth, low energy consumption, strong parallel processing ability, and super high speed. Silicon-based micro-nano integrated photonic platforms have demonstrated good compatibility with complementary metal oxide semiconductor (CMOS) processing. Therefore, without completely changing the existing silicon-based fabrication technology, optoelectronic hybrid devices or all-optical devices of better performance can be achieved on such platforms. To meet the requirements of smaller size and higher integration for silicon photonic computing, the topology of a four-channel coarse wavelength division multiplexer (CWDM) and an optical scattering unit (OSU) are inversely designed and optimized by Lumerical software. Due to the random optical power splitting ratio and incoherency, the intensities of different input signals from CWDM can be weighted and summed directly by the subsequent OSU to accomplish arbitrary multiply–accumulate (MAC) operations, therefore supplying the core foundation for scattering ONN architecture.

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11

Kuang, S. R., and J. P. Wang. "Low-error configurable truncated multipliers for multiply-accumulate applications." Electronics Letters 42, no. 16 (2006): 904. http://dx.doi.org/10.1049/el:20061812.

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12

Kataeva, Irina, Henrik Engseth, and Anna Kidiyarova-Shevchenko. "New design of an RSFQ parallel multiply–accumulate unit." Superconductor Science and Technology 19, no. 5 (March 16, 2006): S381—S386. http://dx.doi.org/10.1088/0953-2048/19/5/s45.

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13

Rathore, Mallika, Peter Milder, and Emre Salman. "Error Probability Models for Voltage-Scaled Multiply-Accumulate Units." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28, no. 7 (July 2020): 1665–75. http://dx.doi.org/10.1109/tvlsi.2020.2988204.

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14

Chen, Jia, Jiancong Li, Yi Li, and Xiangshui Miao. "Multiply accumulate operations in memristor crossbar arrays for analog computing." Journal of Semiconductors 42, no. 1 (January 1, 2021): 013104. http://dx.doi.org/10.1088/1674-4926/42/1/013104.

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15

Chikkani, Rajyalakshmi. "VLSI Implementation of Multiply and Accumulate Unit Using Distributed Arithmetic." Bioscience Biotechnology Research Communications 13, no. 15 (December 25, 2020): 212–17. http://dx.doi.org/10.21786/bbrc/13.15/37.

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16

Irwin, D. "A multiply-and-accumulate selection algorithm for dynamic entropy coding." ACM SIGCOMM Computer Communication Review 16, no. 1 (February 1986): 5–12. http://dx.doi.org/10.1145/15703.15704.

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17

Danysh, A., and D. Tan. "Architecture and implementation of a vector/SIMD multiply-accumulate unit." IEEE Transactions on Computers 54, no. 3 (March 2005): 284–93. http://dx.doi.org/10.1109/tc.2005.41.

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18

Bunyk, P. I., Q. P. Herr, and M. W. Johnson. "Demonstration of Multiply-Accumulate Unit for Programmable Band-Pass ADC." IEEE Transactions on Appiled Superconductivity 15, no. 2 (June 2005): 392–95. http://dx.doi.org/10.1109/tasc.2005.849858.

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19

Masadeh, Mahmoud, Osman Hasan, and Sofiene Tahar. "Input-Conscious Approximate Multiply-Accumulate (MAC) Unit for Energy-Efficiency." IEEE Access 7 (2019): 147129–42. http://dx.doi.org/10.1109/access.2019.2946513.

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20

Mohamed Asan Basiri, M., and S. k. Noor Mohammad. "Quadruple throughput fixed point quarter precision multiply accumulate circuit design." IET Computers & Digital Techniques 11, no. 5 (August 7, 2017): 183–89. http://dx.doi.org/10.1049/iet-cdt.2017.0051.

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21

Dinah, Shalo Thanga, and V. Jeyalakshm. "High Performance Multiply Accumulate (MAC) Unit Based FIR Filter Design." International Journal of Applied Engineering Research 17, no. 6 (December 30, 2022): 565–72. http://dx.doi.org/10.37622/ijaer/17.6.2022.565-572.

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22

Zhang, Hao, Dongdong Chen, and Seok-Bum Ko. "New Flexible Multiple-Precision Multiply-Accumulate Unit for Deep Neural Network Training and Inference." IEEE Transactions on Computers 69, no. 1 (January 1, 2020): 26–38. http://dx.doi.org/10.1109/tc.2019.2936192.

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23

Sarma, Rajkumar, Cherry Bhargava, and Ketan Kotecha. "An Evolutionary Normalization Algorithm for Signed Floating-Point Multiply-Accumulate Operation." Computers, Materials & Continua 72, no. 1 (2022): 481–95. http://dx.doi.org/10.32604/cmc.2022.024516.

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24

S, Saravanan, and Madheswaran M. "MODIFIED MULTIPLY-ACCUMULATE ARCHITECTURE WITH THE SWITCHING POWER SWIFTNESS IMPROVEMENT TECHNIQUE." International Journal on Intelligent Electronic Systems 2, no. 1 (2008): 80–85. http://dx.doi.org/10.18000/ijies.30029.

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25

Garland, James, and David Gregg. "Low Complexity Multiply Accumulate Unit for Weight-Sharing Convolutional Neural Networks." IEEE Computer Architecture Letters 16, no. 2 (July 1, 2017): 132–35. http://dx.doi.org/10.1109/lca.2017.2656880.

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26

McGovern, B. P., R. F. Woods, and C. McAllister. "Optimised multiply/accumulate architecture for very high throughput rate digital filters." Electronics Letters 31, no. 14 (1995): 1135. http://dx.doi.org/10.1049/el:19950823.

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27

Chen, Ke, Linbin Chen, Pedro Reviriego, and Fabrizio Lombardi. "Efficient Implementations of Reduced Precision Redundancy (RPR) Multiply and Accumulate (MAC)." IEEE Transactions on Computers 68, no. 5 (May 1, 2019): 784–90. http://dx.doi.org/10.1109/tc.2018.2885044.

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28

Chhajed, Harsh, Gopal Raut, Narendra Dhakad, Sudheer Vishwakarma, and Santosh Kumar Vishvakarma. "BitMAC: Bit-Serial Computation-Based Efficient Multiply-Accumulate Unit for DNN Accelerator." Circuits, Systems, and Signal Processing 41, no. 4 (January 8, 2022): 2045–60. http://dx.doi.org/10.1007/s00034-021-01873-9.

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29

Ryu, Sungju, Naebeom Park, and Jae-Joon Kim. "Feedforward-Cutset-Free Pipelined Multiply–Accumulate Unit for the Machine Learning Accelerator." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27, no. 1 (January 2019): 138–46. http://dx.doi.org/10.1109/tvlsi.2018.2873716.

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30

Smith, S. C., R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson. "NULL convention multiply and accumulate unit with conditional rounding, scaling, and saturation." Journal of Systems Architecture 47, no. 12 (June 2002): 977–98. http://dx.doi.org/10.1016/s1383-7621(02)00060-7.

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31

Garland, James, and David Gregg. "Low Complexity Multiply-Accumulate Units for Convolutional Neural Networks with Weight-Sharing." ACM Transactions on Architecture and Code Optimization 15, no. 3 (October 8, 2018): 1–24. http://dx.doi.org/10.1145/3233300.

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32

Cai, Fuxi, Justin M. Correll, Seung Hwan Lee, Yong Lim, Vishishtha Bothra, Zhengya Zhang, Michael P. Flynn, and Wei D. Lu. "A fully integrated reprogrammable memristor–CMOS system for efficient multiply–accumulate operations." Nature Electronics 2, no. 7 (July 2019): 290–99. http://dx.doi.org/10.1038/s41928-019-0270-x.

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33

Cho, Mannhee, and Youngmin Kim. "FPGA-Based Convolutional Neural Network Accelerator with Resource-Optimized Approximate Multiply-Accumulate Unit." Electronics 10, no. 22 (November 19, 2021): 2859. http://dx.doi.org/10.3390/electronics10222859.

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Анотація:

Convolutional neural networks (CNNs) are widely used in modern applications for their versatility and high classification accuracy. Field-programmable gate arrays (FPGAs) are considered to be suitable platforms for CNNs based on their high performance, rapid development, and reconfigurability. Although many studies have proposed methods for implementing high-performance CNN accelerators on FPGAs using optimized data types and algorithm transformations, accelerators can be optimized further by investigating more efficient uses of FPGA resources. In this paper, we propose an FPGA-based CNN accelerator using multiple approximate accumulation units based on a fixed-point data type. We implemented the LeNet-5 CNN architecture, which performs classification of handwritten digits using the MNIST handwritten digit dataset. The proposed accelerator was implemented, using a high-level synthesis tool on a Xilinx FPGA. The proposed accelerator applies an optimized fixed-point data type and loop parallelization to improve performance. Approximate operation units are implemented using FPGA logic resources instead of high-precision digital signal processing (DSP) blocks, which are inefficient for low-precision data. Our accelerator model achieves 66% less memory usage and approximately 50% reduced network latency, compared to a floating point design and its resource utilization is optimized to use 78% fewer DSP blocks, compared to general fixed-point designs.

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34

Lyakhov, Pavel, Maria Valueva, Georgii Valuev, and Nikolai Nagornov. "A Method of Increasing Digital Filter Performance Based on Truncated Multiply-Accumulate Units." Applied Sciences 10, no. 24 (December 18, 2020): 9052. http://dx.doi.org/10.3390/app10249052.

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Анотація:

This paper proposes new digital filter architecture based on a modified multiply-accumulate (MAC) unit architecture called truncated MAC (TMAC), with the aim of increasing the performance of digital filtering. This paper provides a theoretical analysis of the proposed TMAC units and their hardware simulation. Theoretical analysis demonstrated that replacing conventional MAC units with modified TMAC units, as the basis for the implementation of digital filters, can theoretically reduce the filtering time by 29.86%. Hardware simulation showed that TMAC units increased the performance of digital filters by up to 10.89% compared to digital filters using conventional MAC units, but were associated with increased hardware costs. The results of this research can be used in the theory of digital signal processing to solve practical problems such as noise reduction, amplification and suppression of the frequency spectrum, interpolation, decimation, equalization and many others.

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35

Smith, S. C. "Development of a large word-width high-speed asynchronous multiply and accumulate unit." Integration 39, no. 1 (September 2005): 12–28. http://dx.doi.org/10.1016/j.vlsi.2004.11.001.

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36

Ezilarasan, M. R., J. Britto Pari, and Man-Fai Leung. "Reconfigurable Architecture for Noise Cancellation in Acoustic Environment Using Single Multiply Accumulate Adaline Filter." Electronics 12, no. 4 (February 6, 2023): 810. http://dx.doi.org/10.3390/electronics12040810.

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Анотація:

The creation of multiple applications with a higher level of complexity has been made possible by the usage of artificial neural networks (ANNs). In this research, an efficient flexible finite impulse response (FIR) filter structure called ADALINE (adaptive linear element) that makes use of a MAC (multiply accumulate) core is proposed. The least mean square (LMS) and recursive least square (RLS) algorithms are the most often used methods for maximizing filter coefficients. Despite outperforming the LMS, the RLS approach has not been favored for real-time applications due to its higher design arithmetic complexity. To achieve less computation, the fundamental filter has utilized an LMS-based tapping delay line filter, which is practically a workable option for an adaptive filtering algorithm. To discover the undiscovered system, the adjustable coefficient filters have been developed in the suggested work utilizing an optimal LMS approach. The 10-tap filter being considered here has been analyzed and synthesized utilizing field programmable gate array (FPGA) devices and programming in hardware description language. In terms of how well the resources were used, the placement and postrouting design performed well. If the implemented filter architecture is compared with the existing filter architecture, it reveals a 25% decrease in resources from the existing one and an increase in clock frequency of roughly 20%.

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37

Yuyun Liao and D. B. Roberts. "A high-performance and low-power 32-bit multiply-accumulate unit with single-instruction-multiple-data (SIMD) feature." IEEE Journal of Solid-State Circuits 37, no. 7 (July 2002): 926–31. http://dx.doi.org/10.1109/jssc.2002.1015692.

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38

S, Rakesh, and K. S. Vijula Grace. "Power Efficient Multiply Accumulate Architectures using Modified Parallel Prefix Adders for Low Power Applications." International Journal of Computing and Digital Systems 9, no. 4 (July 1, 2020): 615–23. http://dx.doi.org/10.12785/ijcds/090409.

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39

Nakahara, Yasuhiro, Yuta Masuda, Masato Kiyama, Motoki Amagasaki, and Masahiro Iida. "A Posit Based Multiply-accumulate Unit with Small Quire Size for Deep Neural Networks." IPSJ Transactions on System LSI Design Methodology 15 (2022): 16–19. http://dx.doi.org/10.2197/ipsjtsldm.15.16.

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40

Srikanth, I., and S. Aunmetha. "High Level Synchronization and Computations of Feed Forward Cut-Set based Multiply Accumulate Unit." Journal of Physics: Conference Series 1804, no. 1 (February 1, 2021): 012201. http://dx.doi.org/10.1088/1742-6596/1804/1/012201.

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41

Lyakhov, Pavel, Maria Valueva, Georgii Valuev, and Nikolai Nagornov. "High-Performance Digital Filtering on Truncated Multiply-Accumulate Units in the Residue Number System." IEEE Access 8 (2020): 209181–90. http://dx.doi.org/10.1109/access.2020.3038496.

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42

Jeon, Dong-Ik, Kyeong-Bin Park, and Ki-Seok Chung. "HMC-MAC: Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube." IEEE Computer Architecture Letters 17, no. 1 (January 1, 2018): 5–8. http://dx.doi.org/10.1109/lca.2017.2700298.

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43

Parameswar, A., H. Hara, and T. Sakurai. "A swing restored pass-transistor logic-based multiply and accumulate circuit for multimedia applications." IEEE Journal of Solid-State Circuits 31, no. 6 (June 1996): 804–9. http://dx.doi.org/10.1109/4.509866.

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44

Tatas, K., G. Koutroumpezis, D. Soudris, and A. Thanailakis. "Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications." Integration 40, no. 2 (February 2007): 74–93. http://dx.doi.org/10.1016/j.vlsi.2006.02.011.

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45

La Guia de Solaz, Manuel, and Richard Conway. "Razor Based Programmable Truncated Multiply and Accumulate, Energy-Reduction for Efficient Digital Signal Processing." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23, no. 1 (January 2015): 189–93. http://dx.doi.org/10.1109/tvlsi.2014.2300173.

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46

Demasius, Kai-Uwe, Aron Kirschen, and Stuart Parkin. "Energy-efficient memcapacitor devices for neuromorphic computing." Nature Electronics 4, no. 10 (October 2021): 748–56. http://dx.doi.org/10.1038/s41928-021-00649-y.

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Анотація:

AbstractData-intensive computing operations, such as training neural networks, are essential for applications in artificial intelligence but are energy intensive. One solution is to develop specialized hardware onto which neural networks can be directly mapped, and arrays of memristive devices can, for example, be trained to enable parallel multiply–accumulate operations. Here we show that memcapacitive devices that exploit the principle of charge shielding can offer a highly energy-efficient approach for implementing parallel multiply–accumulate operations. We fabricate a crossbar array of 156 microscale memcapacitor devices and use it to train a neural network that could distinguish the letters ‘M’, ‘P’ and ‘I’. Modelling these arrays suggests that this approach could offer an energy efficiency of 29,600 tera-operations per second per watt, while ensuring high precision (6–8 bits). Simulations also show that the devices could potentially be scaled down to a lateral size of around 45 nm.

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47

Giacomin, Edouard, Sumanth Gudaparthi, Juergen Boemmels, Rajeev Balasubramonian, Francky Catthoor, and Pierre-Emmanuel Gaillardon. "A Multiply-and-Accumulate Array for Machine Learning Applications Based on a 3D Nanofabric Flow." IEEE Transactions on Nanotechnology 20 (2021): 873–82. http://dx.doi.org/10.1109/tnano.2021.3132224.

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48

Kao, J. T., M. Miyazaki, and A. R. Chandrakasan. "A 175-MV multiply-accumulate unit using an adaptive supply voltage and body bias architecture." IEEE Journal of Solid-State Circuits 37, no. 11 (November 2002): 1545–54. http://dx.doi.org/10.1109/jssc.2002.803957.

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49

Camus, Vincent, Linyan Mei, Christian Enz, and Marian Verhelst. "Review and Benchmarking of Precision-Scalable Multiply-Accumulate Unit Architectures for Embedded Neural-Network Processing." IEEE Journal on Emerging and Selected Topics in Circuits and Systems 9, no. 4 (December 2019): 697–711. http://dx.doi.org/10.1109/jetcas.2019.2950386.

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50

KENNEDY, MICHAEL PETER, CHAI WAH WU, STANLEY PAU, and JAMES TOW. "DIGITAL SIGNAL PROCESSOR-BASED INVESTIGATION OF CHUA'S CIRCUIT FAMILY." Journal of Circuits, Systems and Computers 03, no. 02 (June 1993): 269–92. http://dx.doi.org/10.1142/s0218126693000204.

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Анотація:

This paper is concerned with exploiting the architecture of a single-chip digital signal processor for integrating piecewise-linear ODEs. We show that DSPs can be usefully applied in the study of Chua's circuit family provided that one chooses a multistep integration algorithm which exploits their unique single-instruction multiply-and-accumulate feature.

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