Дисертації з теми "Multiply and accumulate"
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Duppils, Mattias. "Digitally controlled analog multiply-accumulate units /." Linköping : Univ, 2002. http://www.bibl.liu.se/liupubl/disp/disp2002/tek792s.pdf.
Повний текст джерелаNatter, William. "Design and implementation of digit-serial online multiply-accumulate arithmetic operations." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/MQ60479.pdf.
Повний текст джерелаLindahl, Erik. "Design and implementation of a decimation filter using a multi-precision multiply and accumulate unit for an audio range delta sigma analog to digital converter." Thesis, Linköping University, Department of Electrical Engineering, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-11261.
Повний текст джерелаThis work presents the design and implementation of a decimation filter for a three bits sigma delta analog to digital converter. The input is audio with a oversampling ratio of 32. Filter optimization and tradeoffs concerning the design is described. The filter is a multistage filter consisting of two cascaded FIR filters. The arithmetic unit is a multi-precision unit that can handle three or 24 bits MAC operations. The designed decimation filter is synthesized on standard cells of a 0.13 μm CMOS library.
Bowlyn, Kevin Nathaniel. "IMPLEMENTATION OF A NOVEL INTEGRATED DISTRIBUTED ARITHMETIC AND COMPLEX BINARY NUMBER SYSTEM IN FAST FOURIER TRANSFORM ALGORITHM." OpenSIUC, 2017. https://opensiuc.lib.siu.edu/dissertations/1470.
Повний текст джерелаKamp, William Hermanus Michael. "Redundant Number Systems for Optimising Digital Signal Processing Performance in Field Programmable Gate Array." Thesis, University of Canterbury. Electrical and Computer Engineering, 2010. http://hdl.handle.net/10092/4623.
Повний текст джерелаOlano, Jimmy Fernando Tarrillo. "Exploring the use of multiple modular redundancies for masking accumulated faults in SRAM-based FPGAs." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/103895.
Повний текст джерелаSoft errors in the configuration memory bits of SRAM-based FPGAs are an important issue due to the persistence effect and its possibility of generating functional failures in the implemented circuit. Whenever a configuration memory bit cell is flipped, the soft error will be corrected only by reloading the correct configuration memory bitstream. If the correct bitstream is not loaded, persistent soft errors can accumulate in the configuration memory bits provoking a system functional failure in the user’s design, and consequently can cause a catastrophic situation. This scenario gets worse in the event of multi-bit upset, whose probability of occurrence is increasing in new nano-metric technologies. Traditional strategies to deal with soft errors in configuration memory are based on the use of any type of triple modular redundancy (TMR) and the scrubbing of the memory to repair and avoid the accumulation of faults. The high reliability of this technique has been demonstrated in many studies, however TMR is aimed at masking single faults. The technology trend makes lower the dimensions of the transistors, and this leads to increased susceptibility to faults. In this new scenario, it is commoner to have multiple to single faults in the configuration memory of the FPGA, so that the use of TMR is inappropriate in high reliability applications. Furthermore, since the fault rate is increasing, scrubbing rate also needs to be incremented, leading to the increase in power consumption. Aiming at coping with massive upsets between sparse scrubbing, this work proposes the use of a multiple redundancy system composed of n identical modules, known as nmodular redundancy (nMR), operating in tandem and an innovative self-adaptive voter to be able to mask multiple upsets in the system. The main drawback of using modular redundancy is its high cost in terms of area and power consumption. However, area overhead is less and less problem due the higher density in new technologies. On the other hand, the high power consumption has always been a handicap of FPGAs. In this work we also propose a model to prevent power overhead caused by the use of multiple redundancy in SRAM-based FPGAs. The capacity of the proposal to tolerate multiple faults has been evaluated by radiation experiments and fault injection campaigns of study case circuits implemented in a 65nm technology commercial FPGA. Finally we demonstrate that the power overhead generated by the use of nMR in FPGAs is much lower than it is discussed in the literature.
Ghodrati, Ashkan, and Ahmed Rashid. "Modelling and Simulation of a Power Take-off in Connection with Multiple Wave Energy Converters." Thesis, Blekinge Tekniska Högskola, Institutionen för tillämpad signalbehandling, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-3396.
Повний текст джерела+46736290781
Teng, Sin Yong. "Intelligent Energy-Savings and Process Improvement Strategies in Energy-Intensive Industries." Doctoral thesis, Vysoké učení technické v Brně. Fakulta strojního inženýrství, 2020. http://www.nusl.cz/ntk/nusl-433427.
Повний текст джерелаTavares, Lucas Alves. "O envolvimento da proteína adaptadora 1 (AP-1) no mecanismo de regulação negativa do receptor CD4 por Nef de HIV-1." Universidade de São Paulo, 2016. http://www.teses.usp.br/teses/disponiveis/17/17136/tde-06012017-113215/.
Повний текст джерелаThe Human Immunodeficiency Virus (HIV) is the etiologic agent of Acquired Immunodeficiency Syndrome (AIDS). AIDS is a disease which has a global distribution, and it is estimated that there are currently at least 36.9 million people infected with the virus. During the replication cycle, HIV promotes several changes in the physiology of the host cell to promote their survival and enhance replication. The fast progression of HIV-1 in humans and animal models is closely linked to the function of an accessory protein Nef. Among several actions of Nef, one is the most important is the down-regulation of proteins from the immune response, such as the CD4 receptor. It is known that this action causes CD4 degradation in lysosome, but the molecular mechanisms are still incompletely understood. Nef forms a tripartite complex with the cytosolic tail of the CD4 and adapter protein 2 (AP-2) in clathrin-coated vesicles, inducing CD4 internalization and lysosome degradation. Previous research has demonstrated that CD4 target to lysosomes by Nef involves targeting of this receptor to multivesicular bodies (MVBs) pathway by an atypical mechanism because, although not need charging ubiquitination, depends on the proteins from ESCRTs (Endosomal Sorting Complexes Required for Transport) machinery and the action of Alix, an accessory protein ESCRT machinery. It has been reported that Nef interacts with subunits of AP- 1, AP-2, AP-3 complexes and Nef does not appear to interact with AP-4 and AP-5 subunits. However, the role of Nef interaction with AP-1 or AP-3 in CD4 down-regulation is poorly understood. Furthermore, AP-1, AP-2 and AP-3 are potentially heterogeneous due to the existence of multiple subunits isoforms encoded by different genes. However, there are few studies to demonstrate if the different combinations of APs isoforms are form and if they have distinct functional properties. This study aim to identify and characterize cellular factors involved on CD4 down-modulation induced by Nef from HIV-1. More specifically, this study aimed to characterize the involvement of AP-1 complex in the down-regulation of CD4 by Nef HIV-1 through the functional study of the two isoforms of ?-adaptins, AP-1 subunits. By pull-down technique, we showed that Nef is able to interact with ?2. In addition, our data from immunoblots indicated that ?2- adaptin, not ?1-adaptin, is required in Nef-mediated targeting of CD4 to lysosomes and the ?2 participation in this process is conserved by Nef from different viral strains. Furthermore, by flow cytometry assay, ?2 depletion, but not ?1 depletion, compromises the reduction of surface CD4 levels induced by Nef. Immunofluorescence microscopy analysis also revealed that ?2 depletion impairs the redistribution of CD4 by Nef to juxtanuclear region, resulting in CD4 accumulation in primary endosomes. Knockdown of ?1A, another subunit of AP-1, resulted in decreased cellular levels of ?1 and ?2 and, compromising the efficient CD4 degradation by Nef. Moreover, upon artificially stabilizing ESCRT-I in early endosomes, via overexpression of HRS, internalized CD4 accumulates in enlarged HRS-GFP positive endosomes, where co-localize with ?2. Together, the results indicate that ?2-adaptin is a molecule that is essential for CD4 targeting by Nef to ESCRT/MVB pathway, being an important protein in the endo-lysosomal system. Furthermore, the results indicate that ?-adaptins isoforms not only have different functions, but also seem to compose AP-1 complex with distinct cell functions, and only the AP-1 variant comprising ?2, but not ?1, acts in the CD4 down-regulation induced by Nef. These studies contribute to a better understanding on the molecular mechanisms involved in Nef activities, which may also help to improve the understanding of the HIV pathogenesis and the related syndrome. In addition, this work contributes with the understanding of primordial process regulation on intracellular trafficking of transmembrane proteins.
Liu, Albert Y. M., and 劉元明. "A Multiply-And-Accumulate Module Generator." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/31258642337837389545.
Повний текст джерела國立清華大學
資訊工程學系
88
Multiply-And-Accumulate (MAC) is the most frequently used operation in many DSP applications. We propose a software method that can generate high-performance MAC units in synthesizable HDL format. Our tool integrates several novel techniques including a modified radix-4 Booth encoding, a three dimensional Wallace tree, a sign-extension prevention scheme , and a hybrid carry-select/carry-look-ahead adder. It allows users to specify the number of bits in both inputs and output, the number system (signed or unsigned or decided by command inputs), the number of pipeline stages, saturation option on overflow, accumulator type (“addition only” or “addition and subtraction”), and pipeline stall as well as accumulator initialization capability. A typical MAC unit (16x16 inputs, 40-bit Accumulation , 2-stage pipeline) can be generated within seconds and run at over 280 MHz in post-layout simulation typical case when targeted toward a TSMC 0.35μm CMOS cell library.
YE, YI-HAO, and 葉儀皓. "A new design approach of CMOS floating point multiply/accumulate chip." Thesis, 1986. http://ndltd.ncl.edu.tw/handle/70572211987483505163.
Повний текст джерелаSu, Yu-Yi, and 蘇育毅. "Dynamic Early Terminating of Multiply-Accumulate Operation for Convolutional Neural Networks." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/j6vujt.
Повний текст джерела國立清華大學
資訊工程學系所
106
Deep learning has been attracting enormous attention from academia as well as industry due to its great success in many artificial intelligence applications. As more applications are developed, the need for implementing a complex neural network model on an energy-limited edge device becomes more critical. Thus, this paper proposes a new optimization method for saving the computations of convolutional neural networks (CNNs). The method takes advantage of the fact that some convolutional operations are actually wasteful since their outputs are pruned by the following activation or pooling layers. Basically, a convolutional filter conducts a series of multiply-accumulate (MAC) operations. We propose to set a series of checkpoints in the MAC operations to determine whether a filter could terminate early according to the intermediate result. Furthermore, a fine-tuning process is conducted to recover the accuracy loss due to the applied checkpoints. The experimental results show that the proposed method can save approximately 50% MAC operations with only 1% accuracy loss for two classic CNN models and it is competitive with previous methods.
WU, JI-LI, and 吳基立. "A study of high speed CMOS floating point multiply/accumulate chip based on redundant binary representation." Thesis, 1989. http://ndltd.ncl.edu.tw/handle/14874956461527063537.
Повний текст джерелаLi, June-Yi, and 李峻毅. "A Non-volatile Computing-In-Memory ReRAM Macro with Multiply-and-Accumulate for Binary DNN AI Edge Processors." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/gnarhb.
Повний текст джерелаLin, Wei-En, and 林暐恩. "A Non-volatile ReRAM Based Macro with Computing-In-Memory Multiply-and-Accumulate for Binary DNN AI Edge Processors." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/473g54.
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