Дисертації з теми "MULTIPLIER CIRCUIT"
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1
Tang, Wing Ho Aaron. "Optimum MESFET frequency multiplier design." Thesis, Queen's University Belfast, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.239221.
Повний текст джерела
2
Comerma, Montells Albert. "Development of a multichannel integrated circuit for Silicon Photo-Multiplier arrays readout." Doctoral thesis, Universitat de Barcelona, 2014. http://hdl.handle.net/10803/134876.
Повний текст джерелаАнотація:
The aim of this thesis is to present a solution for the readout of Silicon Photo-Multipliers (SiPMs) arrays improving currently implemented systems. Using as a starting point previous designs with similar objectives a novel current mode input stage has been designed and tested. To start with the design a valid model has been used to generate realistic output from the SiPMs depending on light input. Design has been performed in first place focusing in general applications for medical imaging Positron Emission Tomography (PET) and then using the same topology for a more constrained design in particle detectors (upgrade of Tracker detector at LHCb experiment).
A 16 channel ASIC for PET applications including the novel input stage has demonstrated an excellent timing measurement with good energy resolution measurement and pile-up detection. This document starts with the analysis of the requirements needed to fit such a system, followed by a detailed description of the input stage and analog processing. Signal is divided in the input stage into three different signal paths: timing, energy and pileup. Every channel performs different signal analysis to deliver; a fast time signal output (digital edge), energy output (a linear time over threshold digital output) and a digital bit to signal pile-up. The time information is then ORed between all channels to generate a single timing output. All the pile-up bits are combined in a digital word ready to be readout for the 16 channels. Design has been optimized for reduced power consumption and no components needed to interface inputs and outputs. Digital slow control to tune the circuit behaviour is also included. The prototype measurements have proved to be a valid option for integration in a full system scanner.
An adapted prototype of the input stage using different technology and adapted to the different constraints from a particle detector is also presented. Only simulation results are available since device is still under production. An analysis of the different requirements needed by the SciFi tracker design is summarized. Current specifications are still evolving since final sensor is still not defined, but other requirements and some tunable elements permits to design such prototypes.L’objectiu d’aquesta tesi és presentar una solució per a la lectura de matrius de fotomultiplicadors de silici (SiPM) millorant les característiques de sistemes actuals. Amb aquesta finalitat s’ha dissenyat i provat el circuit d’una nova etapa d’entrada. En primer lloc s’ha dissenyat pensant en aplicacions genèriques i per a imatge mèdica, concretament per a escàners PET (Positron Emission Tomography). Però més endavant s’aplica la mateixa topologia per a una aplicació més concreta i específica com és un detector de partícules (l’actualització del Tracker a l’experiment LHCb). Els SiPM són uns dispositius electrònics relativament nous amb la possibilitat de comptar fotons i millorant algunes característiques dels sensors actuals, com serien la tensió d’operació més baixa, més guany o immunitat a camps magn`etics, mentre manté unes prestacions excel•lents respecte el guany, resolució temporal i rang dinàmic. Aquest tipus de dispositius es troben en constant evolució encara i una gran varietat de fabricants intenten millorar les prestacions, sobretot respecte la eficiència en la detecció de llum, reduir el corrent d’obscuritat, construir matrius més grans i augmentar l’espectre al qual són sensibles. En aquest document es presenta el disseny d’un circuit integrat específic amb les següents característiques: gran rang dinàmic, alta velocitat, multicanal, amb entrada en corrent i baixa impedància d’entrada, baix consum, control de la tensió de polarització del SiPM i amb les sortides de; temps, càrrega i apilament.
3
Srinivasan, Venkataramanujam. "Gigahertz-Range Multiplier Architectures Using MOS Current Mode Logic (MCML)." Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/9643.
Повний текст джерелаАнотація:
The tremendous advancement in VLSI technologies in the past decade has fueled the need for intricate tradeoffs among speed, power dissipation and area. With gigahertz range microprocessors becoming commonplace, it is a typical design requirement to push the speed to its extreme while minimizing power dissipation and die area. Multipliers are critical components of many computational intensive circuits such as real time signal processing and arithmetic systems. The increasing demand in speed for floating-point co-processors, graphic processing units, CDMA systems and DSP chips has shaped the need for high-speed multipliers.
The focus of our research for modern digital systems is two fold. The first one is to analyze a relatively unexplored logic style called MOS Current Mode Logic (MCML), which is a promising logic technique for the design of high performance arithmetic circuits with minimal power dissipation. The second one is to design high-speed arithmetic circuits, in particular, gigahertz-range multipliers that exploit the many attractive features of the MCML logic style. A small library of MCML gates that form the core components of the multiplier were designed and optimized for high-speed operation. The three 8-bit MCML multiplier architectures designed and simulated in TSMC 0.18 mm CMOS technology are: 3-2-tree architecture with ripple carry adder (Architecture I), 4-2-tree design with ripple carry adder (Architecture II) and 4-2-tree architecture with carry look-ahead adders (Architecture III). Architecture I operates with a maximum throughput of 4.76 GHz (4.76 Billion multiplications per second) and a latency of 3.78 ns. Architecture II has a maximum throughput of 3.3 GHz and a latency of 3 ns and Architecture III has a maximum throughput of 2 GHz and a latency of 3 ns. Architecture I achieves the highest throughput among the three multipliers, but it incurs the largest area and latency, in terms of clock cycle count as well as absolute delay. Although it is difficult to compare the speed of our multipliers with existing ones, due to the use of different technologies and different optimization goals, we believe our multipliers are among the fastest found in contemporary literature.Master of Science
4
Ramasamy, Lakshminarayanan. "First Order Mobility Independent ASIC for a Point-of-Care In-Vitro Diagnostic Device." University of Cincinnati / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1326296847.
Повний текст джерела
5
El, Hassan Bachar. "Architecture VLSI asynchrone utilisant la logique différentielle à précharge : application aux opérateurs arithmétiques." Grenoble INPG, 1995. http://www.theses.fr/1995INPG0099.
Повний текст джерелаАнотація:
La complexite et la vitesse de fonctionnement des circuits integres, atteignent un seuil ou les systemes asynchrones deviennent une laternative interessante pour resoudre certains problemes des systemes synchrones. Apres une etude generale sur les differents types de systemes asynchrones nous sommes passes a l'etude de la circuiterie asynchrone: differentes logiques ont ete etudiees et nous avons choisi la logique dcvs (differential cascode voltage switch logic) pour la suite de l'etude. Nous sommes ensuite passes a l'etude et la conception des operateurs arithmetiques asynchrones, premiere experience d'utilisation de la logique dcvs. Nous avons etudie quatre architectures d'additionneurs-soustracteurs et plusieurs types de multiplieurs parallele-parallele. Puis nous avons concu et fabrique un multiplieur-accumulateur 18 12 + 30 bits, utilisant un arbre a retenue bloquee (carry-save) et un additionneur rapide, capable de fonctionner en modes synchrone et asynchrone. L'etude des pipelines asynchrones a ete ensuite abordee. Nous avons etudie plusieurs methodes pour realiser ces pipelines et nous avons propose quelques modifications a certaines d'entre elles. Ces modifications ont permis a ces pipelines de devenir plus rapides. L'etude des operateurs et du pipeline asynchrone nous a fait sentir le besoin d'une bibliotheque de cellules standards asynchrone et nous a donne les grandes lignes pour concevoir cette bibliotheque, en logique dcvs. La derniere partie de notre travail a ete consacree a l'etude des anneaux autosequences (self timed rings). Apres une etude general de ces anneaux nous y avons introduit la meme modification introduite au pipeline asynchrone. Ceci a permis de diminuer les nombres d'etages minimal et optimal de ces anneaux. La conception de la multiplication parallele-serie ainsi que la division en anneau a ensuite ete etudiee. Quatre diviseurs implementes en anneaux ont finalement ete concus en utilisant les cellules de la bibliotheque asynchrone
6
Remund, Craig Timothy. "Design of CMOS Four-Quadrant Gilbert Cell Multiplier Circuits in Weak and Moderate Inversion." Diss., CLICK HERE for online access, 2004. http://contentdm.lib.byu.edu/ETD/image/etd611.pdf.
Повний текст джерела
7
Ozalevli, Erhan. "Exploiting Floating-Gate Transistor Properties in Analog and Mixed-Signal Circuit Design." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/14048.
Повний текст джерелаАнотація:
With the downscaling trend in CMOS technology, it has been possible to utilize the advantages of high element densities in VLSI circuits and systems. This trend has readily allowed digital circuits to predominate VLSI implementations due to their ease of scaling. However, high element density in integrated circuit technology has also entailed a decrease in the power consumption per functional circuit cell for the use of low-power and reconfigurable systems in portable equipment.
Analog circuits have the advantage over digital circuits in designing low-power and compact VLSI circuits for signal processing systems. Also, analog circuits have been employed to utilize the wide dynamic range of the analog domain to meet the stringent signal-to-noise-and-distortion requirements of some signal processing applications. However, the imperfections and mismatches of CMOS devices can easily deteriorate the performance of analog circuits when they are used to realize precision and highly linear elements in the analog domain. This is mainly due to the lack of tunability of the analog circuits that necessitates the use of special trimming or layout techniques.
These problems can be alleviated by making use of the analog storage and capacitive coupling capabilities of floating-gate transistors. In this research, tunable resistive elements and analog storages are built using floating-gate transistors to be incorporated into signal processing applications. Tunable linearized resistors are designed and implemented
in CMOS technology, and are employed in building a highly linear amplifier, a transconductance multiplier, and a binary-weighted resistor digital-to-analog converter. Moreover, a tunable voltage reference is designed by utilizing the analog storage feature of the floating-gate transistor. This voltage reference is used to build low-power, compact, and tunable/reconfigurable voltage-output digital-to-analog converter and distributed arithmetic
architecture.
8
Normand, Guy. "Les circuits translineaires : contribution a leur etude et a leur mise en oeuvre dans les domaines analogique et logique." Nantes, 1987. http://www.theses.fr/1987NANT2056.
Повний текст джерелаАнотація:
Les circuits translineaires sont des circuits constitues d'un certain nombre de jonctions bipolaires, organisees en mailles translineaires. Le processus translineaires conduit a la realisation de nombreuses fonctions electroniques lineaires ou non lineaires, analogiques ou logiques. Les structures translineaires sont destinees a commander electroniquement le facteur transfert des reseaux lineaires
9
Choudens, Philippe de. "Test intégré de processeur facilement testable." Grenoble INPG, 1985. http://tel.archives-ouvertes.fr/tel-00319265.
Повний текст джерелаАнотація:
Un test permet d'assurer la sécurité de fonctionnement des circuits VLSI. La première partie montre l'intérêt dans un tel contexte d'un processeur facilement testable; la deuxième partie développe pour de tels microprocesseurs une stratégie de test. Dans la troisième partie est traité le problème de la définition des vecteurs de test des circuits logiques programmables. Développement d'un test pour multiplieur itératif
10
Tang, Guang-ming. "Studies on Datapath Circuits for Superconductor Bit-Slice Microprocessors." 京都大学 (Kyoto University), 2016. http://hdl.handle.net/2433/217208.
Повний текст джерела
11
Chaour, Issam, Ahmed Fakhfakh, and Olfa Kanoun. "Enhanced Passive RF-DC Converter Circuit Efficiency for Low RF Energy Harvesting." Universitätsbibliothek Chemnitz, 2017. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-224264.
Повний текст джерелаАнотація:
For radio frequency energy transmission, the conversion efficiency of the receiver is decisive not only for reducing sending power, but also for enabling energy transmission over long and variable distances. In this contribution, we present a passive RF-DC converter for energy harvesting at ultra-low input power at 868 MHz. The novel converter consists of a reactive matching circuit and a combined voltage multiplier and rectifier. The stored energy in the input inductor and capacitance, during the negative wave, is conveyed to the output capacitance during the positive one. Although Dickson and Villard topologies have principally comparable efficiency for multi-stage voltage multipliers, the Dickson topology reaches a better efficiency within the novel ultra-low input power converter concept. At the output stage, a low-pass filter is introduced to reduce ripple at high frequencies in order to realize a stable DC signal. The proposed rectifier enables harvesting energy at even a low input power from −40 dBm for a resistive load of 50 kΩ. It realizes a significant improvement in comparison with state of the art solutions
12
Vácha, Petr. "Křížení v kartézském genetickém programování." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2012. http://www.nusl.cz/ntk/nusl-235481.
Повний текст джерелаАнотація:
Optimization of digital circuits still attracts much attention not only of researchers but mainly chip producers. One of new the methods for the optimization of digital circuits is cartesian genetic programming. This Master's thesis describes a new crossover operator and its implementation for cartesian genetic programming. Experimental evaluation was performed in the task of three-bit multiplier and five-bit parity circuit design.
13
Oliveira, Vlademir de Jesus Silva [UNESP]. "Sintetizador analógico de sinais ortogonais: projeto e construção usando tecnologia CMOS." Universidade Estadual Paulista (UNESP), 2004. http://hdl.handle.net/11449/90796.
Повний текст джерелаАнотація:
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Nesse trabalho, propõe-se o projeto e implementação de um sintetizador de sinais ortogonais utilizando técnicas de circuito integrado e processo CMOS. O circuito do sintetizador baseia-se em um modelo matemático que utiliza multiplicadores e integradores analógicos, para geração de bases de funções ortogonais, tais como os polinômios de Legendre, as funções de base coseno e seno, a smoothed-cosine basis e os polinômios de Hermite. Funções ortogonais são bastante empregadas em processamento de sinais, e a implementação deste método matemático é capaz de gerar vários tipos de funções em um mesmo circuito integrado. O projeto proposto utiliza blocos analógicos funcionais para implementar o sintetizador. Os blocos que compõem o sintetizador foram projetados utilizando circuitos diferenciais, processamento em modo de corrente e técnicas de low-voltage. Algumas topologias utilizadas estão descritas na literatura, sendo que algumas foram adaptadas e mesmo modificadas, como no caso do multiplicador de corrente. Outras tiveram que ser propostas. As simulações e os resultados experimentais mostraram que o sintetizador é capaz de gerar funções ortogonais com amplitude e distorções satisfatórias. O sintetizador pode ser alimentado em 3V, tal qual foi projetado, tem faixa de entrada de ±20 μA e apresenta DHT (distorção harmônica total) inferior a 4% no quinto e último estágio em cascata.
In this work, a design and implementation of a synthesizer of orthogonal signals using CMOS technology and design technique for integrated circuits is proposed. The synthesizer circuit used analog multipliers and integrators for produce orthogonal functions such as Legendre polynomials, cosine and sine basis of functions, smoothed-cosine basis and Hermite polynomials. Orthogonal functions can be employed in signal processing and the implementation proposed can generate several kinds of functions in the same integrated circuit. In the synthesizer design building blocks was employed. The synthesizer’s blocks were design using differential circuits, low-voltage and current-mode techniques. Some topologies from papers were adapted or modified, as in the case of the current multiplier. Other topologies had to be proposed. The simulation and experimental results have shown that the synthesizer is able to produce orthogonal functions with satisfactory quality in distortions and amplitude. The synthesizer has a 3V supply voltage, a input current range of ±20 μA and it presents less than 4% of THD (Total Harmonic Distortion) in the last output in cascade.
14
Oliveira, Vlademir de Jesus Silva. "Sintetizador analógico de sinais ortogonais : projeto e construção usando tecnologia CMOS /." Ilha Solteira : [s.n.], 2004. http://hdl.handle.net/11449/90796.
Повний текст джерелаАнотація:
Orientador: Nobuo OkiBanca: Saulo Finco
Banca: Cláudio Kitano
Resumo: Nesse trabalho, propõe-se o projeto e implementação de um sintetizador de sinais ortogonais utilizando técnicas de circuito integrado e processo CMOS. O circuito do sintetizador baseia-se em um modelo matemático que utiliza multiplicadores e integradores analógicos, para geração de bases de funções ortogonais, tais como os polinômios de Legendre, as funções de base coseno e seno, a smoothed-cosine basis e os polinômios de Hermite. Funções ortogonais são bastante empregadas em processamento de sinais, e a implementação deste método matemático é capaz de gerar vários tipos de funções em um mesmo circuito integrado. O projeto proposto utiliza blocos analógicos funcionais para implementar o sintetizador. Os blocos que compõem o sintetizador foram projetados utilizando circuitos diferenciais, processamento em modo de corrente e técnicas de low-voltage. Algumas topologias utilizadas estão descritas na literatura, sendo que algumas foram adaptadas e mesmo modificadas, como no caso do multiplicador de corrente. Outras tiveram que ser propostas. As simulações e os resultados experimentais mostraram que o sintetizador é capaz de gerar funções ortogonais com amplitude e distorções satisfatórias. O sintetizador pode ser alimentado em 3V, tal qual foi projetado, tem faixa de entrada de ±20 μA e apresenta DHT (distorção harmônica total) inferior a 4% no quinto e último estágio em cascata.
Abstract: In this work, a design and implementation of a synthesizer of orthogonal signals using CMOS technology and design technique for integrated circuits is proposed. The synthesizer circuit used analog multipliers and integrators for produce orthogonal functions such as Legendre polynomials, cosine and sine basis of functions, smoothed-cosine basis and Hermite polynomials. Orthogonal functions can be employed in signal processing and the implementation proposed can generate several kinds of functions in the same integrated circuit. In the synthesizer design building blocks was employed. The synthesizer's blocks were design using differential circuits, low-voltage and current-mode techniques. Some topologies from papers were adapted or modified, as in the case of the current multiplier. Other topologies had to be proposed. The simulation and experimental results have shown that the synthesizer is able to produce orthogonal functions with satisfactory quality in distortions and amplitude. The synthesizer has a 3V supply voltage, a input current range of ±20 μA and it presents less than 4% of THD (Total Harmonic Distortion) in the last output in cascade.
Mestre
15
Chvátlina, Pavel. "Laboratorní přípravek pro testování tranzistorů IGBT." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-217920.
Повний текст джерелаАнотація:
This master’s thesis describes the function and realization of the laboratory test equipment designed for measuring and analysing of collector current iC and voltage uCE courses during the opening and closing process of a power IGBT transistor. The opening and closing times toff and ton of the new power transistor IGBT are changing in the range from tenths to the ones s, so the reading of current iC and voltage uCE proceeds in a very short time. The measuring circuit of this test equipment is based on a short-time discharging of a condenser battery to the inductive load over the measured transistor. Consequently it is possible to replace the power supply whose maximum output power would otherwise have to be in the range of ones MW. In the final part of this thesis there are described properties and design of a high-frequency sensor with the Rogowski coil, which can be used for reading collector current course during opening and closing time of the measured transistor IGBT. Collector current iC and voltage uCE courses can be analysed with a storage oscilloscope.
16
Vašíček, Zdeněk. "Acceleration Methods for Evolutionary Design of Digital Circuits." Doctoral thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2012. http://www.nusl.cz/ntk/nusl-261257.
Повний текст джерелаАнотація:
Ačkoliv můžeme v literatuře nalézt řadu příkladů prezentujících evoluční návrh jakožto zajímavou a slibnou alternativu k tradičním návrhovým technikám používaným v oblasti číslicových obvodů, praktické nasazení je často problematické zejména v důsledku tzv. problému škálovatelnosti, který se projevuje např. tak, že evoluční algoritmus je schopen poskytovat uspokojivé výsledky pouze pro malé instance řešeného problému. Vážný problém představuje tzv. problém škálovatelnosti evaluace fitness funkce, který je markantní zejména v oblasti syntézy kombinačních obvodů, kde doba potřebná pro ohodnocení kandidátního řešení typicky roste exponenciálně se zvyšujícím se počtem primárních vstupů. Tato disertační práce se zabývá návrhem několika metod umožňujících redukovat problem škálovatelnosti evaluace v oblasti evolučního návrhu a optimalizace číslicových systémů. Cílem je pomocí několika případových studií ukázat, že s využitím vhodných akceleračních technik jsou evoluční techniky schopny automaticky navrhovat inovativní/kompetitivní řešení praktických problémů. Aby bylo možné redukovat problém škálovatelnosti v oblasti evolučního návrhu číslicových filtrů, byl navržen doménově specifický akcelerátor na bázi FPGA. Tato problematika reprezentuje případ, kdy je nutné ohodnotit velké množství trénovacích dat a současně provést mnoho generací. Pomocí navrženého akcelerátoru se podařilo objevit efektivní implementace různých nelineárních obrazových filtrů. S využitím evolučně navržených filtrů byl vytvořen robustní nelineární filtr implusního šumu, který je chráněn užitným vzorem. Navržený filtr vykazuje v porovnání s konvenčními řešeními vysokou kvalitu filtrace a nízkou implementační cenu. Spojením evolučního návrhu a technik známých z oblasti formální verifikace se podařilo vytvořit systém umožňující výrazně redukovat problém škálovatelnosti evoluční syntézy kombinačních obvodů na úrovni hradel. Navržená metoda dovoluje produkovat komplexní a přesto kvalitní řešení, která jsou schopna konkurovat komerčním nástrojům pro logickou syntézu. Navržený algoritmus byl experimentálně ověřen na sadě několika benchmarkových obvodů včetně tzv. obtížně syntetizovatelných obvodů, kde dosahoval v průměru o 25% lepších výsledků než dostupné akademické i komerční nástroje. Poslední doménou, kterou se práce zabývá, je akcelerace evolučního návrhu lineárních systémů. Na příkladu evolučního návrhu násobiček s vícenásobnými konstantními koeficienty bylo ukázáno, že čas potřebný k evaluaci kandidátního řešení lze výrazně redukovat (defacto na ohodocení jediného testovacího vektoru), je-li brán v potaz charakter řešeného problému (v tomto případě linearita).
17
RIZZO, ROBERTO GIORGIO. "Energy-Accuracy Scaling in Digital ICs: Static and Adaptive Design Methods and Tools." Doctoral thesis, Politecnico di Torino, 2019. http://hdl.handle.net/11583/2743228.
Повний текст джерела
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Najafi, Syed Ahmed Ali. "Energy Harvesting From Overhead Transmission Line Magnetic Fields." University of Akron / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=akron1548448189459464.
Повний текст джерела
19
Subramanian, Shyam. "Methods for synthesis of multiple-input translinear element networks." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/22591.
Повний текст джерелаАнотація:
Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.Committee Chair: Anderson, David; Committee Member: Habetler, Thomas; Committee Member: Hasler, Paul; Committee Member: McClellan, James; Committee Member: Minch, Bradley.
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Fernandez, Alexandre Marino. "Circuito alterado em três atos: abrir, tatear e multiplicar." Universidade de São Paulo, 2013. http://www.teses.usp.br/teses/disponiveis/27/27157/tde-28012014-161653/.
Повний текст джерелаАнотація:
Nesta pesquisa analiso as metodologias de luteria experimental chamadas Circuit-Bending e Hardware Hacking, as quais englobo no termo Circuito Alterado, criado especificamente para este trabalho. Tais metodologias baseiam-se na construção de aparelhos musicais a partir da reutilização de componentes eletrônicos descartados. O principal objetivo desta dissertação é estabelecer relações contextuais entre os três atos fundamentais envolvidos na alteração de circuitos - abrir o circuito, tateá-lo em busca de sonoridades interessantes e multiplicar a metodologia, através de concertos, blogs e/ou oficinas - e questões culturais relacionadas a cada ato.On this research I analyze the experimental luthier methodologies called Circuit-Bending and Hardware Hacking, which I call Circuito Alterado (Altered Circuits). This methodologies are based in the construction of musical instruments from the reuse of obsolete electronic components. The main goal of this dissertation is to establish contextual relationships between the tree acts involved in the methodologies - to open-up the circuit, to touch it, in the search of interesting sonorities and to multiply it, through concerts, blogs and/or workshops - and cultural issues related to each act.
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Kwon, Ohsang. "On high performance multiplier design using dynamic CMOS circuits /." Full text (PDF) from UMI/Dissertation Abstracts International, 2000. http://wwwlib.umi.com/cr/utexas/fullcit?p3004310.
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Sabade, Sagar Suresh. "Integrated circuit outlier identification by multiple parameter correlation." Diss., Texas A&M University, 2004. http://hdl.handle.net/1969.1/267.
Повний текст джерелаАнотація:
Semiconductor manufacturers must ensure that chips conform to their specifications before they are shipped to customers. This is achieved by testing various parameters of a chip to determine whether it is defective or not. Separating defective chips from fault-free ones is relatively straightforward for functional or other Boolean tests that produce a go/no-go type of result. However, making this distinction is extremely challenging for parametric tests. Owing to continuous distributions of parameters, any pass/fail threshold results in yield loss and/or test escapes. The continuous advances in process technology, increased process variations and inaccurate fault models all make this even worse. The pass/fail thresholds for such tests are usually set using prior experience or by a combination of visual inspection and engineering judgment. Many chips have parameters that exceed certain thresholds but pass Boolean tests. Owing to the imperfect nature of tests, to determine whether these chips (called "outliers") are indeed defective is nontrivial. To avoid wasted investment in packaging or further testing it is important to screen defective chips early in a test flow. Moreover, if seemingly strange behavior of outlier chips can be explained with the help of certain process parameters or by correlating additional test data, such chips can be retained in the test flow before they are proved to be fatally flawed. In this research, we investigate several methods to identify true outliers (defective chips, or chips that lead to functional failure) from apparent outliers (seemingly defective, but fault-free chips). The outlier identification methods in this research primarily rely on wafer-level spatial correlation, but also use additional test parameters. These methods are evaluated and validated using industrial test data. The potential of these methods to reduce burn-in is discussed.
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Topcu, Ali. "Multiple Devices Open Circuit Fault Diagnosis for Multilevel Inverters." University of Akron / OhioLINK, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=akron1603745813645294.
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Maikowski, Leo M. "Toleranced multiple fault diagnosis of analogue circuits." Thesis, University of Brighton, 1995. https://research.brighton.ac.uk/en/studentTheses/61464794-ec3e-4bcb-b091-fd3d69ec8ecf.
Повний текст джерелаАнотація:
The implementation of an automatic fault diagnosis approach for analogue circuits is facing a number of problem areas. They are typically: component and measurement tolerances, circuit size, limited observability constraints, multiple fault conditions, non-linear behaviour, speed and generic applicability. Since such fault finding techniques utilize circuit simulations sometime during the diagnostic process, the preferred form of classification amongst researchers is a taxonomy of Simulationbefore-Test (SbT) and Simulation-after-Test (SaT) methods. A survey of related work following these two strategies has been carried out, which concludes: The main advantage of the SaT strategy is their diagnostic power to cope with above problem areas, their main disadvantage is the often considerable computational on-line effort. The main advantage of the SbT strategy is on-line speed, but diagnostic power is often limited. What is needed is a workable solution to combine the advantages of the two strategies, whilst minimizing their disadvantages. The thesis is focused on this need. Subject of the research programme was therefore to look into the feasibility of a Simulation-before-Test approach for diagnosing toleranced analogue non-linear networks in the presence of multiple faults and from there to research the concepts, strategies and algorithms required to form a diagnostic approach.
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Clarke, Christopher T. "The implementation and applications of multiple-valued logic." Thesis, University of Warwick, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.386944.
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Guerreiro, Inês. "Cholinergic and multiple-circuit mechanisms of hippocampal theta-rhythm generation." Electronic Thesis or Diss., Université Paris sciences et lettres, 2021. http://www.theses.fr/2021UPSLE074.
Повний текст джерелаАнотація:
Les oscillations thêta sont un rythme proéminent de 4 à 12 Hz observé dans l'hippocampe et ses structures associées chez tous les mammifères. Outre l'hippocampe, deux autres structures du cerveau sont reconnues comme essentielles à la génération in vivo du rythme thêta de l’hippocampe - le septum médian (MS) et le cortex entorhinal (EC). Cependant, après plusieurs décennies de recherche, les mécanismes produisant ces oscillations restent mal connus. Dans cette thèse, on étudiera le rôle que les trois régions du cerveau citées précédemment (MS, EC et l'hippocampe) jouent dans la génération et l'entretien des oscillations thêta. Dans la première partie de cette thèse, on étudiera comment les entrées septales cholinergiques, en agissant sur les neurones hippocampaux GABAergique, contrôlent l'excitabilité et la plasticité de l'hippocampe. Dans la seconde partie, on analysera les mécanismes du circuit qui permettent la génération du rythme thêta dans le EC et la propagation de l'activité oscillatoire jusqu'à l'hippocampe. À cette fin, on commencera par étudier comment la connectivité du réseau du cortex enthorhinal, fait de cellules stellaires, de cellules pyramidales et d'interneurones à dynamique rapide, module la réponse du circuit vers les entrées excitatrices de l'hippocampe. Ensuite, on examinera comment les entrées oscillatoires enthorhinales vers un réseau de cellules OLM, d'interneurones à dynamique rapide et de cellules pyramidales, peuvent conduire le système dans un état de résonance thêta. En résumé, on proposera un mécanisme multi-circuit pour la génération des oscillations thêta dans un réseau septal-hippocampal-entorhinal, dans lequel trois régions du cerveau jouent un rôle actif dans la production et l'expression du rythme thêta. Les entrées cholinergiques contrôlent l'excitabilité hippocampale, ce qui permet la génération des oscillations thêta dans le circuit du EC et leur propagation dans l'hippocampe, et ferme ainsi la boucle enthorhinale-hippocampaleHippocampal theta oscillations are a prominent 4-12 Hz rhythm observed in the hippocampal local field potential and its associated structures of all mammals. Besides the hippocampus, two other brain structures are known to be essential for in vivo hippocampal theta generation - the medial septum (MS) and entorhinal cortex (EC). However, after decades of research, the mechanisms through which these oscillations arise remain elusive. In this thesis, we address the role that each of the three mentioned brain regions (MS, EC and hippocampus) play in the generation and maintenance of theta oscillations. In the first part of the dissertation, we study how septal cholinergic inputs acting on hippocampal GABAergic interneurons through α7 nicotinic receptors regulate the excitability and plasticity of the hippocampus. In the second part, we investigate the circuit mechanisms that enable the generation of theta oscillations in the EC and the propagation of the rhythmic activity to the hippocampus. To this aim, we start by studying how the connectivity of the entorhinal cortex network made of stellate cells, pyramidal cells and fast-spiking interneurons modulates the circuit's response to hippocampal excitatory inputs. Next, we address how entorhinal oscillatory inputs onto a hippocampal network of OLM cells, fast-spiking interneurons and pyramidal cells can drive the system into a theta resonant state. In summary, we propose a multi-circuit mechanism for the generation of theta oscillations in a septal-hippocampalentorhinal network, where the three brain regions play an active role in the induction and expression of the theta rhythm. Cholinergic inputs regulate hippocampal excitability, which acts as a gate that permits theta oscillations to arise in the EC circuit and spread to the hippocampus, thus closing the entorhinal-hippocampal loop
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SamadiBoroujeni, MohammadReza. "High performance CMOS integrated circuits for optical receivers." [College Station, Tex. : Texas A&M University, 2006. http://hdl.handle.net/1969.1/ETD-TAMU-1108.
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Grist, Darren. "The design of high speed multipliers and their implementation in differential logic." Thesis, University of Kent, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.311228.
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Shawcross, Anna. "Infant multiple breath washout using a novel open-closed circuit system." Thesis, University of Manchester, 2018. https://www.research.manchester.ac.uk/portal/en/theses/infant-multiple-breath-washout-using-a-novel-openclosed-circuit-system(06f61a8a-f731-4a60-b0fe-ad330582d7bd).html.
Повний текст джерелаАнотація:
Background: Lung clearance index (LCI), obtained by multiple breath washout testing (MBW), is a sensitive measure of lung disease in infants. It has been identified as a particularly suitable endpoint for clinical trials in cystic fibrosis (CF), but has potential applications in many other conditions. However, MBW in infants presents a number of technical challenges. Conventional MBW is based on simultaneous measurement of flow and gas. These two signals are then aligned and combined to derive expired gas volumes and measures of ventilation inhomogeneity: this process becomes increasingly vulnerable to errors in gas signal alignment at rapid respiratory rates. At present, no existing system for infant MBW meets all the criteria set out in international guidelines, and there is no simple method of assessing lung function outside research laboratories in this population. This thesis describes an alternative method of performing MBW in infants. In this method, expired gas is collected and analysed to derive functional residual capacity (FRC) and LCI. There is no need to simultaneously measure flow, and therefore no need for the complicated step of integrating flow and gas signals. Dead space is also significantly reduced by removing the flowmeter. Methods: In the first phase of testing, an existing lung model was modified to generate realistic infant breathing parameters with high accuracy. The prototype system was modified to improve accuracy and subsequently tested at FRC of 100-250mls with respiratory rates of 20-60min-1. In the second phase, testing proceeded to an in vivo pilot study of the novel method in children with cystic fibrosis and healthy controls. Practical applicability of the system was determined by the number of successful duplicate tests, and within-subject repeatability. Comparison was made with LCI measurements obtained using a respiratory mass spectrometer, currently considered the gold standard for infant LCI. Results: In a total of 103 tests performed in the lung model, overall mean error (standard deviation) of FRC measurement was -1.0(3.3)%, with 90% of tests falling within +/-5%. 13 patients were excluded from the clinical study due to being unsedated or inadequately sedated and therefore failing to tolerate the test. A total of 25 patients (7 children with CF, 18 healthy control children) were deemed to be adequately sedated at the start of the test, of these 20 patients (7 with CF) successfully underwent duplicate testing (80% success rate). Mean FRC for healthy controls was 19.5ml/kg, and mean LCI 6.45. For children with CF, mean FRC was 21.8ml/kg and mean LCI 6.98. Mean within-subject coefficient of variation for FRC was 7.18% and for LCI 5.94%. Of 4 infants assessed with both the novel method and the respiratory mass spectrometer, there was good correlation in FRC measurement (mean difference -8.1%). Comparison of LCI with the mass spectrometer was affected by technical difficulties with the test; in those patients who underwent technically adequate tests with both methods, mean difference in LCI between the two methods was 1.65%. Discussion: FRC measurement using the novel method has superior accuracy in vitro than previously described systems. Data from the pilot study suggest that this is a feasible and reproducible method of performing LCI in infants and young children, as long as they are adequately sedated. Results in both children with CF and controls fall within the expected range, and well within accuracy limits set by international guidelines. However, the system and testing protocol could be further improved to reduce the number of technically inadequate tests having to be excluded. This could provide a more accessible alternative to previously described systems for infant MBW.
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Silva, Ricardo Cunha Gonçalves da. "Lógica quaternária de alto desempenho e baixo consumo para circuitos VLSI." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2007. http://hdl.handle.net/10183/13121.
Повний текст джерелаАнотація:
Desde a década de 60, o aprimoramento das técnicas de fabricação de circuitos integrados que usam lógica binária tem levado ao aumento exponencial na densidade de dispositivos, melhoria do desempenho, redução da energia consumida e redução dos custos de fabricação dos circuitos integrados no estado da arte. Esse avanço tem sido alcançado historicamente pela miniaturização dos dispositivos que, já em escala nanométrica, começam a encontrar limites físicos para a sua redução. Com o intuito de dar continuidade ao avanço tecnológico, muitos trabalhos têm proposto a compactação da informação através do uso de lógica não binária como solução alternativa para a melhoria de desempenho de circuitos no estado da arte. Nesse sentido, diversos trabalhos foram desenvolvidos em diferentes tecnologias que vão de circuitos bipolares a dispositivos quânticos, entretanto, até o presente momento, nenhuma tecnologia demonstrou ao mesmo tempo os requisitos de desempenho, consumo, área e confiabilidade, necessários à aplicação em circuitos de alta escala de integração. Este trabalho apresenta uma nova família de circuitos de lógica quaternária com alto desempenho, baixos consumo e área e que usa tecnologia CMOS. Os circuitos desenvolvidos neste trabalho fazem uso de três fontes de alimentação e até oito diferentes transistores com diferentes tensões de limiar para realizar a lógica quaternária. São apresentados circuitos elementares como inversores e circuitos literais e com eles construídos circuitos aritméticos e multiplexadores. Os circuitos são simulados com a ferramenta SPICE usando a tecnologia TSMC 0,18 μm e os resultados são comparados com circuitos equivalentes em lógica binária. Na comparação de um somador completo quaternário de quatro bits, por exemplo, com o circuito equivalente em lógica binária, a implementação quaternária apresenta melhoria 55% na velocidade, 63% no consumo de potência e utiliza pouco mais de duas vezes o número de transistores. Este trabalho também propõe o uso de lógica quaternária em FPGA e são desenvolvidos blocos lógicos programáveis quaternários. Resultados de mapeamento lógico de circuitos aritméticos em blocos lógicos programáveis apresentam grande redução em área e consumo de potência na implementação quaternária quando comparado aos equivalentes binários. Em alguns circuitos quaternários, o consumo de potência e o número de transistores usados são reduzidos a 3% do consumo e do número de transistores usados nos circuitos equivalentes binários, enquanto o atraso crítico é duas vezes maior do que o atraso crítico binário.Since the decade of 60, the improvement of techniques for manufacturing integrated circuits that use binary logic has led to the exponential increase in the density of devices, improving performance, reducing energy consumption and reducing costs of manufacture of integrated circuits in the state of the art. This breakthrough has been achieved historically by the miniaturization of devices, already in nano, starting to reach physical limits to their reduction. In order to give continuity to technological advancement, many studies have proposed the compaction of information through the use of non-binary logic as an alternative for the performance improvement of the state of the art circuits. Accordingly, several studies have been developed in different technologies ranging from bipolar circuits to quantum devices, however, at the moment, no technology demonstrated at the same time the performance requirements, consumption, area and reliability necessary for the application in very large scale of integration. This paper presents a new family of quaternary logic circuits with high performance, low consumption and area, which uses CMOS technology. The circuits developed in this work make use of three power supplies and up to eight different transistors with different threshold voltages, to perform the quaternary logic. Elementary circuits such as inverters and literal circuits are presented and used to implement multiplexers and arithmetic circuits. The circuits are simulated with the SPICE tool using TSMC 0.18 μm technology and the results are compared with equivalent circuits in binary logic. Comparison of a quaternary full adder of four bits, for example, with the equivalent circuit in binary logic shows 55% improvement in speed and 63% in the power consumption for the quaternary implementation and it uses little more than twice the number of transistors. This paper also proposes the use of quaternary logic in FPGA and quaternary configurable logic blocks are developed. Logical mapping results of arithmetic circuits in configurable logic blocks show great reduction in area and power consumption of the quaternary implementation compared to the equivalent binary. In some quaternary circuits, the consumption of power and the number of transistors used are reduced to 3% of consumption and the number of transistors used in the binary equivalent circuits, while the critical delay is two times higher than the binary critical delay.
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Alam, Mohammed S. "Fabrication and characterization of multiple flexible magnetic windings." [Gainesville, Fla.] : University of Florida, 2001. http://purl.fcla.edu/fcla/etd/UFE0000301.
Повний текст джерелаАнотація:
Thesis (M.S.)--University of Florida, 2001.Title from title page of source document. Document formatted into pages; contains ix, 55 p.; also contains graphics. Includes vita. Includes bibliographical references (p. 53-54).
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Lustrac, André de. "Conception de circuits Josephson ultrarapides : modélisation de la jonction tunnel Josephson ayant une constante de temps de l'ordre de la picoseconde : conception d'une famille logique à couplage direct adaptée aux jonctions Josephson picosecondes : application à un circuit additionneur et à un circuit multiplieur." Paris 11, 1986. http://www.theses.fr/1986PA112283.
Повний текст джерелаАнотація:
Un modèle adapté aux jonctions tunnel Josephson ayant des constantes de temps de l’ordre de la picoseconde est défini à partir d’un développement limité de l’expression du courant Josephson dépendant du temps, dite équation de Werthamer. Il se compose des composantes de l’expression adiabatique augmenté d’un terme supplémentaire qui dépend de la phase et de la tension aux bornes de la jonction et apparait comme un terme capacitif. Des expressions analytiques des temps caractéristiques d’une jonction (retard à la commutation, temps de montée) sont proposées pour les principales conditions de charge. Les principes de l’optimisation de la conception des circuits logique à couplage direct mettant en œuvre ces jonctions sont ensuite étudiés. Une famille de portes à hautes performances en vitesse et en consommation est proposée. Cette famille comprend un OU, un ET, un OU exclusif synchrone ainsi qu’une porte Majorité 2/3 et un NON. La conception optimisée, les marges et les délais logiques de ces portes sont déterminés. Enfin nous étudions deux circuits de complexité croissante : un additionneur 2+2 bits (20 ps/bit) et un multiplieur 4x4 bits (temps de multiplication : 100 ps)A Josephson tunnel junction model adapted to junction dynamics in the 1 picosecond range is derived from a series expansion of the time dependent Josephson current (Werthamer equation). The model consists of the terms of the adiabatic approximation and an added term depending on the phase and voltage across the junction which appears as an added capacitance. Analytical expressions of the junction characteristic times (turn of delay, rise time) are derived in the main junction load conditions. Then the principles of optimum design of direct coupled logic circuits implemented with these junctions are studied. It is found that circuits with heavily loaded junctions do not improve significantly if faster switching junctions are used. Therefore a new logic family (OR, AND, EXOR, Majority 2/3, NOT) is proposed which avoids heavily loaded junctions are used. The optimum designs, margins and logic delays of such circuits are determined. Two circuits of increasing complexity are finally studied using this logic family: a 2+2 bit adder (20 ps/bit) and a 4x4 bit multiplier (multiplication time: 100ps)
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Chen, Chao-Wu. "Design and NMOS implementation of parallel pipelined multiplier." Ohio : Ohio University, 1988. http://www.ohiolink.edu/etd/view.cgi?ohiou1182779741.
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Lynn, Michael (Michael Benjamin). "Generation and tuning of learned sensorimotor behavior by multiple neural circuit architectures." Thesis, Massachusetts Institute of Technology, 2015. http://hdl.handle.net/1721.1/100876.
Повний текст джерелаАнотація:
Thesis: S.M., Massachusetts Institute of Technology, Department of Brain and Cognitive Sciences, 2015.Cataloged from PDF version of thesis.
Includes bibliographical references (pages 25-26).
Organisms have a remarkable ability to respond to complex sensory inputs with intricate, tuned motor patterns. How does the brain organize and tune these motor responses, and are certain circuit architectures, or connectivity patterns, optimally suited for certain sensorimotor applications? This thesis presents progress towards this particular problem in three subprojects. The first section re-analyzes a large data set of single-unit recordings in zebra finch area HVC during singing. While HVC is known to be essential for proper expression of adult vocalization, its circuit architecture is contentious. Evidence is presented against the recently postulated gesture-trajectory extrema hypothesis for the organization of area HVC. Instead, the data suggest that the synaptic chain model of HVC organization is a better fit for the data, where chains of RA-projecting HVC neurons are synaptically connected to walk the bird through each time-step of the song. The second section examines how optimal sensorimotor estimation using a Bayesian inference framework could be implemented in a cerebellar circuit. Two novel behavioral paradigms are developed to assess how rats might tune their motor output to the statistics of the sensory inputs, and whether their behavior might be consistent with the use of a Bayesian inference paradigm. While neither behavior generated stable behavior, evidence indicates that rats may use a spinal circuit to rapidly and dynamically adjust motor output. The third section addresses the formation of habitual behaviors in a cortico-striatal network using rats. Stress and depression are known to significantly alter decision-making abilities, but the neural substrate of this is poorly understood. Towards this goal, rats are trained on a panel of decision-making tasks in a forced-choice T-maze, and it is shown that a chronic stress procedure produces a dramatic shift in behavior in a subset of these tasks but not the rest. This behavioral shift is reversed by optogenetic stimulation of prelimbic input to striatum, pinpointing a circuit element which may control stress-induced behavioral changes. Furthermore, a circuit hypothesis is presented to explain why sensitivity to changing reward values diminishes with overtraining.
by Michael Lynn.
S.M.
35
Hill, David T. "Removal of trace elements from coal using a multiple-property processing circuit." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-01242009-063125/.
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Zhang, Duo. "DYNAMIC CMOS MIMO CIRCUITS WITH FEEDBACK INVERTER LOOP AND PULL-DOWN BRIDGE." Wright State University / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=wright1377210272.
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37
Chuah, Kia Liang. "A multiple delay switch-level simulator for MOS/LSI circuits." Thesis, University of Ottawa (Canada), 1985. http://hdl.handle.net/10393/4606.
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Lee, Hoon S. "A CAD tool for current-mode multiple-valued CMOS circuits." Thesis, Monterey, California. Naval Postgraduate School, 1988. http://hdl.handle.net/10945/22935.
Повний текст джерелаАнотація:
Approved for public release; distribution is unlimitedThe contribution of this thesis is the development of a CAD (computer aided design) tool for current mode multiple-valued logic (MVL) CMOS circuits. It is only the second known MVL CAD tool and the first CAD tool for MVL CMOS. The tool accepts a specification of the function to be realized by the user, produces a minimal or near-minimal realization (if such a realization is possible), and produces a layout of a programmable logic array (PLA) integrated circuit that realizes the given function. The layout is in MAGIC format, suitable for submission to a chip manufacturer. The CAD tool also allows the user to simulate the realized function so that he/she can verify correctness of design. The CAD tool is designed also to be an analysis tool for heuristic minimization algorithms. As part of this thesis, a random function generator and statistics gathering package were developed. In the present tool, two heuristics are provided and the user can choose one or both. In the latter case, the better realization is output to the user. The CAD tool is designed to be flexible, so that future improvements can be made in the heuristic algorithms, as well as the layout generator. Thus, the tool can be used to accommodate new technologies, for example, a voltage mode CMOS PLA rather than the current mode CMOS currently implemented.
http://archive.org/details/cadtoolforcurren00leeh
Lieutenant, Republic of Korea Navy
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Kim, Jae Hong. "Wide-Band and Scalable Equivalent Circuit Model for Multiple Quantum Well Laser Diodes." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7129.
Повний текст джерелаАнотація:
This dissertation presents a wide-band lumped element equivalent circuit model and a building block-based scalable circuit model for multiple quantum well laser diodes. The wide-band multiple-resonance model expresses two important laser diode characteristics such as input reflection and electrical-to-optical transmission together. Additionally, it demonstrates good agreements with the measurement results of the selected commercial discrete laser diodes. The proposed building block-based modeling approach proves its validity using a numerically derived scalable rate equation. Since success in a circuit design depends largely on the availability of accurate device models, the practical application of the proposed models provides improved accuracy, simple implementation and a short design time.
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Nechma, Tarek. "Parallel sparse matrix solution for direct circuit simulation on a multiple FPGA system." Thesis, University of Southampton, 2012. https://eprints.soton.ac.uk/347886/.
Повний текст джерелаАнотація:
SPICE, from the University of California, at Berkeley, is the de facto world standard for circuit simulation. SPICE is used to model the behaviour of electronic circuits prior to manufacturing to decrease defects and hence reduce costs. However, accurate SPICE simulations of today's sub micron circuits can often take days or weeks on conventional processors. In a nutshell, a SPICE simulation is an iterative process that consists of two phases per iteration, namely, model evaluation followed by a matrix solution. The model evaluation phase has been found to be easily parallelisable unlike the subsequent phase, which involves the solution of highly sparse and asymmetric matrices. In this thesis, we present an FPGA implementation of a sparse matrix solver hardware,geared towards matrices that arise in SPICE circuit simulations. As such, we demonstrate how we extract parallelism at di�erent granularities to accelerate the solution process. Our approach combines static pivoting with symbolic analysis to compute an accurate task ow-graph which e�ciently exploits parallelism at multiple granularities and sustains high oating-point data rates. We also present a quantitative comparison between the performance of our hardware protrotype and state-of-the-art software package running on a general purpose PC equipped with a 2.67 GHz six-core 12 thread Intel Core Xeon X5650 microprocessor and 6 GB memory. We report average speedups of 9.65�, 11.83�, 17.21� against UMFPACK, KLU, and Kundert Sparse matrix packages respectively. We also detail our approach to adapt our sparse LU hardware prototype from a single-FPGA architecture to a multi-FPGA system to achieve higher acceleration ratios up to 38� for certain circuit matrices.
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Rakkarn, Sakchai. "OPERATION ASSIGNMENT WITH BOARD SPLITTING AND MULTIPLE MACHINES IN PRINTED CIRCUIT BOARD ASSEMBLY." Case Western Reserve University School of Graduate Studies / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=case1201021027.
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Dongre, Sidhartha. "Investigating through multiple experimental approaches how early visual circuit functions affect Drosophila behaviour." Thesis, University of Sheffield, 2015. http://etheses.whiterose.ac.uk/11156/.
Повний текст джерелаАнотація:
Drosophila melanogaster has become a versatile model organism, with high genetic tractability and ease of manipulability, mixed with low cost and low space constraints. Genetic tools with which to modify flies in myriad ways are constantly developed and updated, whilst physical tools have also become more apt for access to various biological systems. In this thesis I have used several such tools, such as the Drosophila flight simulator, High Pressure Freezing and Transmission Electron Microscopy to test visual behaviour and synaptic function, respectively. In Drosophila’s early visual system, R1-R6 and R7/R8 information channels carry visual information to the visual brain. These channels have been thought separated on the basis of their structure and function, however it is our hypothesis that these channels can functionally inform each other and that this occurs at an early stage of the visual pathway. Here I have used the flight simulator to show that the absence of ‘chromatic’ photoreceptors adversely affects visually-driven optomotor behaviour. In conjunction with other electrophysiological data, I have helped to support the idea that this influence may result from functional connection between R1-R6 and R7/R8 photoreceptors. Similarly, I have used the flight simulator to show that Ca2+-activated K+ channel mutations in post-synaptic Large Monopolar Cells can affect visual behaviour, but that these effects are often managed by homeostatic mechanisms that serve to maintain biologically-relevant function. Additionally, I have shown that the absence of dietary Polyunsaturated Fatty Acids can influence visual behaviour. Pre- and post-synaptic information at Drosophila photoreceptor synapses has been shown to adapt in accordance with changing visual conditions. I used programmes of light- and dark-adaptation, along with High Pressure Freezing and Transmission Electron Microscopy to test how these adaptations are translated at the synapse. All of these conclusions are discussed alongside electrophysiological findings acquired from the early visual system.
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Huang, Chu-Hsin, and 黃祝欣. "VLSI Circuit Design of Karatsuba’s Multiplier." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/63066797664531748877.
Повний текст джерелаАнотація:
碩士逢甲大學
資訊工程所
92
In the last few years, VLSI circuit design using hardware description languages (HDLs) becomes more and more popular. With these high-level HDLs, a circuit designer can realize a design easily and efficiently. Moreover, the thesis uses mathematical formulas to describe computational problems, and generate partial or full HDL codes. In fact, the process of code generation could be full automatic. In this thesis, we present a methodology to translate tensor product formulas to Verifying Logic HDL (VeriLog) programs. Additionally, we use pipeline and some compiler technologies to optimize Verilog programs. Tensor product formulas are used to represent block recursive algorithms. Operations of tensor product formulas can be mapped to programming language structures. The main goal of this thesis is to present a VLSI circuit design of long-bit Karatsuba’s multiplier and a design methodology.
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Hung, Chin-Chung, and 洪志忠. "A CMOS Multiplier Circuit using a 1.5V CMOS Logic Circuit." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/66188657075161112912.
Повний текст джерелаАнотація:
碩士國立臺灣大學
電機工程學系
85
This thesis reports a 1.5V high-speed 8X8 multiplier circuit usingthe Wallace tree reduction architecture and true-single- phase bootstrappeddyanmic and static circuit techniques. Based on a 0.8um CMOS technology, the CLA circuit speed performance of this 8X8 dynamic multiplier circuit is improved by 39% as compared to the CMOS Manchester carry look-aheadcircuit without using the bootstrapped technique. In the whole dynamicmultiplier circuit, it is improved by 15.5%. The proposed Modified- Manchester CLA circuit speed performance of this 8X8 static multiplier circuit is improved by 60.8% as compared to thhe conventional static CLA circuit whithout using bootstrapped technique. The whole static multiplier circuit is improvedby 35.5%.
45
Yeh, Shiou-Ting, and 葉修廷. "Integrated Circuit Design of a Logarithmic Conversion System Based Multiplier." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/9gp27b.
Повний текст джерелаАнотація:
碩士國立金門大學
電子工程學系碩士班
102
Digital Signal Processing(DSP) applications have been widely used in video,3-D graphics, telecommunication and smart Information Technology(IT) consumer electronics products. Many complex arithmetic calculations such as multiplication, division, reciprocal, square-root and power operations are required in DSP technology. Nowadays, logarithmic number system(LNS) can be used to simplify these complex operations using simple shift-and-add operations. LNS-based computing system contains logarithmic conversion unit, simple calculation unit and antilogarithmic conversion unit to the binary values. Many methods about logarithmic conversion to binary system and antilogarithmic converter have been presented in recent years. Logarithmic conversion system includes a Logarithmic converter and Anti-Logarithmic converter. Linear approximation of logarithmic converter and Anti-Logarithmic converter approach will be proposed in this paper, and the error value of our proposed method is smaller than other literature. In hardware area, compared with the previous literature, our proposed approach of the six nonsymmetric region logarithmic conversion module is only required to pay an additional 33% of the hardware costs, and to get 183% of the error reduced. In Anti-Logarithmic converter, our proposed method of the four region Anti-logarithmic conversion module compared with previous literature, we can only have to pay an additional 29.7% of the hardware cost to get 170% error reduced. The integrated circuit design of a logarithmic conversion system based multipliers and designed under TSMC 0.18um process.
46
Jian, Duan-Zuo, and 簡端佐. "A design of 8X8 multiplier circuit by Tanner Tools Pro." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/47526830724949464538.
Повний текст джерелаАнотація:
碩士南榮科技大學
工程科技研究所碩士班
102
In the paper, a new structure of 8X8 multiplier circuit is proposed by using Tanner Tools Pro. First, the logical circuit and functional diagram of the multiplier are edited in S-Edit mode. Using T-Spice, the circuit functional analysis and simulation are simulated to reveal correctly. In L-Edit mode, the circuit layout of the 8X8 multiplier is generated using auto place and route technology. Finally, the layout of mask layers are adopted to agree with design rule check. Also, the proposed 8X8 multiplier circuit is compared with the traditional one. The analyses reveal that the new circuit of the proposed multiplier simplies the complexity of the circuit, decreases the delay time of the circuit, and improve the efficiency of the multiplier.
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Ann, Jiang, and 安正. "Development of Ion Fan Electrodes using adjustable voltage multiplier circuit." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/36212773267454012547.
Повний текст джерелаАнотація:
碩士國立臺灣大學
機械工程學研究所
101
A ion fan is consisted of a pair of electrodes between which generated ions with applied high voltages can drive the air flow. Most study use pin-to-plate or pin-to-ring as its electrodes to generate ion wind, which the pin is at high potential. However, it has been studied that if one put a ring near the high potential pin can increase the velocity of ion wind. This study investigate the high potential electrode’s shape by using multi-pin circle arrangement instead of single pin in the middle. Additionally, a high voltage power supply (HVPS) is necessary of the ion fan, this study use voltage multiplier circuit as the HVPS which consist of 50 electrolytic capacitors and diodes. The experiment showing that using different capacitance of electrolytic capacitors can decrease the voltage drop which appears in using single capacitance of electrolytic capacitors. Finally, the multi-pin circle arrangement using 3 pins has a velocity of 1.21 m/s which is larger than 0.85 m/s when using 6 pins and is slightly smaller than single pin in the middle which is 1.23 m/s while the supplying voltage was in 10.5kV.
48
Huang, Po-Chun, and 黃柏鈞. "Analog Multiplier for Boundary Conduction Mode Boost Power Factor Correction Circuit." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/10298047996209696947.
Повний текст джерелаАнотація:
碩士國立臺灣大學
電子工程學研究所
97
In recent years, harmonic distortion problem has been emphasized. To achieve the standards which were made by each country, power factor correctors have played an important role in switching power supplies. In current architecture of active power factor corrector, input current is controlled by input voltage which multiplies feedback control signal to become sinusoidal wave; hence analog multipliers are the heart of the control circuits. This thesis mainly discusses on an analog multiplier which can be applied to power factor corrector, and purposes a method by shifting input voltage up one threshold voltage, improving the analog multiplier using linear variable resistor applies in non-inverting amplifier. The linear variable resistor is composed of two MOS in parallel. One is operated in linear region, and the other is operated in saturation region. The value of linear variable resistance will change by input; therefore change the gain of non-inverting amplifier to realize multiplier. In this thesis, a complete boundary conduction mode boost PFC circuit is built with the proposed multiplier. Finally, simulation outcomes of Hspice verify that the purposed multiplier can be used for PFC circuit.
49
SHEKHAR, CHANDRA. "DESIGN OF LOW POWER LOW VOLTAGE GILBERT CELL BASED MULTIPLIER CIRCUIT." Thesis, 2011. http://dspace.dtu.ac.in:8080/jspui/handle/repository/13864.
Повний текст джерелаАнотація:
M.TECHThis thesis presents four quadrant analog multiplier circuit using CMOS and NMOS based on the Gilbert Cell multiplier architecture. Both the multipliers operate in saturation region. Analog multipliers are used in communication circuits, neural networks as well as frequency doublers, RMS circuits and phase detectors. High linearity is the prime issue for multipliers in conventional applications like modulation circuits. Initially, different multiplier architectures are reviewed. Multiplier using CMOS and NMOS is designed and simulated. The input power supply for the multipliers is ±1.5V with the input signal range ±10mV. The multiplier circuit is simulated on PSPICE using 180nm technology Level 7 provided by Mosis. The bandwidth of NMOS multiplier is 38.99 GHz and power dissipation is .35mW. The bandwidth of CMOS multiplier is 26.72 GHz and power dissipation is .07255mW.
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Lin, Shu-Hsuan, and 林書玄. "High-Speed and Low-Power Multiplier-Accumulator Micro-Architecture and Circuit Design." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/68062221088208250298.
Повний текст джерелаАнотація:
碩士國立交通大學
電子工程系所
93
A power-speed optimization technique of circuit level for a datapath of processors is proposed in this thesis. By using efficient multiplication algorithms, a high-speed multiplier-accumulator micro-architecture is designed in this thesis. According to this high-speed micro-architecture design, a low-power transistor level multiplier-accumulator is also implemented. Take the transistor size, the supply voltage, and the threshold voltage as tuning variables which are optimized jointly in terms of power and speed in this thesis which can reduce the dynamic power to one half and can increase the speed to 20%. Design techniques of leakage current suppression are discussed in chapter 4. The micro-architecture optimization methods in terns of power and speed are also examined in chapter 5. All the results are simulated in TSMC 0.13 μm CMOS technology. Making use of micro-architecture and circuit level design techniques, the critical path of a 16X16+32 multiplier-accumulator operation is within 2ns, the dynamic power consumption is below 10 mW.