Увійти

Готові списки джерел за темами / Multilinear Depth 3 Circuits / Статті в журналах

Статті в журналах з теми "Multilinear Depth 3 Circuits"

Щоб переглянути інші типи публікацій з цієї теми, перейдіть за посиланням: Multilinear Depth 3 Circuits.

Автор: Grafiati

Опубліковано: 6 вересня 2023

Оформте джерело за APA, MLA, Chicago, Harvard та іншими стилями

Оберіть тип джерела:

Ознайомтеся з топ-50 статей у журналах для дослідження на тему "Multilinear Depth 3 Circuits".

Біля кожної праці в переліку літератури доступна кнопка «Додати до бібліографії». Скористайтеся нею – і ми автоматично оформимо бібліографічне посилання на обрану працю в потрібному вам стилі цитування: APA, MLA, «Гарвард», «Чикаго», «Ванкувер» тощо.

Також ви можете завантажити повний текст наукової публікації у форматі «.pdf» та прочитати онлайн анотацію до роботи, якщо відповідні параметри наявні в метаданих.

Переглядайте статті в журналах для різних дисциплін та оформлюйте правильно вашу бібліографію.

1

Ghosal, Purnata, and B. V. Raghavendra Rao. "On Proving Parameterized Size Lower Bounds for Multilinear Algebraic Models." Fundamenta Informaticae 177, no. 1 (December 18, 2020): 69–93. http://dx.doi.org/10.3233/fi-2020-1980.

Повний текст джерела

Анотація:

We consider the problem of obtaining parameterized lower bounds for the size of arithmetic circuits computing polynomials with the degree of the polynomial as the parameter. We consider the following special classes of multilinear algebraic branching programs: 1) Read Once Oblivious Branching Programs (ROABPs), 2) Strict interval branching programs, 3) Sum of read once formulas with restricted ordering. We obtain parameterized lower bounds (i.e., nΩ(t(k)) lower bound for some function t of k) on the size of the above models computing a multilinear polynomial that can be computed by a depth four circuit of size g(k)nO(1) for some computable function g. Further, we obtain a parameterized separation between ROABPs and read-2 ABPs. This is obtained by constructing a degree k polynomial that can be computed by a read-2 ABP of small size such that the rank of the partial derivative matrix under any partition of the variables is large.

Стилі APA, Harvard, Vancouver, ISO та ін.

2

Saraf, Shubhangi, and Ilya Volkovich. "Black-Box Identity Testing of Depth-4 Multilinear Circuits." Combinatorica 38, no. 5 (December 9, 2017): 1205–38. http://dx.doi.org/10.1007/s00493-016-3460-4.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

3

Raz, Ran, and Amir Yehudayoff. "Lower Bounds and Separations for Constant Depth Multilinear Circuits." computational complexity 18, no. 2 (June 2009): 171–207. http://dx.doi.org/10.1007/s00037-009-0270-8.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

4

Chillara, Suryajith. "On Computing Multilinear Polynomials Using Multi- r -ic Depth Four Circuits." ACM Transactions on Computation Theory 13, no. 3 (September 30, 2021): 1–21. http://dx.doi.org/10.1145/3460952.

Повний текст джерела

Анотація:

In this article, we are interested in understanding the complexity of computing multilinear polynomials using depth four circuits in which the polynomial computed at every node has a bound on the individual degree of r ≥ 1 with respect to all its variables (referred to as multi- r -ic circuits). The goal of this study is to make progress towards proving superpolynomial lower bounds for general depth four circuits computing multilinear polynomials, by proving better bounds as the value of r increases. Recently, Kayal, Saha and Tavenas (Theory of Computing, 2018) showed that any depth four arithmetic circuit of bounded individual degree r computing an explicit multilinear polynomial on n O (1) variables and degree d must have size at least ( n / r 1.1 ) Ω(√ d / r ) . This bound, however, deteriorates as the value of r increases. It is a natural question to ask if we can prove a bound that does not deteriorate as the value of r increases, or a bound that holds for a larger regime of r . In this article, we prove a lower bound that does not deteriorate with increasing values of r , albeit for a specific instance of d = d ( n ) but for a wider range of r . Formally, for all large enough integers n and a small constant η, we show that there exists an explicit polynomial on n O (1) variables and degree Θ (log 2 n ) such that any depth four circuit of bounded individual degree r ≤ n η must have size at least exp(Ω(log 2 n )). This improvement is obtained by suitably adapting the complexity measure of Kayal et al. (Theory of Computing, 2018). This adaptation of the measure is inspired by the complexity measure used by Kayal et al. (SIAM J. Computing, 2017).

Стилі APA, Harvard, Vancouver, ISO та ін.

5

Karnin, Zohar S., Partha Mukhopadhyay, Amir Shpilka, and Ilya Volkovich. "Deterministic Identity Testing of Depth-4 Multilinear Circuits with Bounded Top Fan-in." SIAM Journal on Computing 42, no. 6 (January 2013): 2114–31. http://dx.doi.org/10.1137/110824516.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

6

Kayal, Neeraj, Vineet Nair, and Chandan Saha. "Separation Between Read-once Oblivious Algebraic Branching Programs (ROABPs) and Multilinear Depth-three Circuits." ACM Transactions on Computation Theory 12, no. 1 (February 25, 2020): 1–27. http://dx.doi.org/10.1145/3369928.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

7

Gupta, Ankit, Pritish Kamath, Neeraj Kayal, and Ramprasad Saptharishi. "Arithmetic Circuits: A Chasm at Depth 3." SIAM Journal on Computing 45, no. 3 (January 2016): 1064–79. http://dx.doi.org/10.1137/140957123.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

8

Kayal, Neeraj, and Nitin Saxena. "Polynomial Identity Testing for Depth 3 Circuits." computational complexity 16, no. 2 (May 2007): 115–38. http://dx.doi.org/10.1007/s00037-007-0226-9.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

9

Fang, M., S. Fenner, F. Green, S. Homer, and Y. Zhang. "Quantum lower bounds for fanout." Quantum Information and Computation 6, no. 1 (January 2006): 46–57. http://dx.doi.org/10.26421/qic6.1-3.

Повний текст джерела

Анотація:

We consider the resource bounded quantum circuit model with circuits restricted by the number of qubits they act upon and by their depth. Focusing on natural universal sets of gates which are familiar from classical circuit theory, several new lower bounds for constant depth quantum circuits are proved. The main result is that parity (and hence fanout) requires log depth quantum circuits, when the circuits are composed of single qubit and arbitrary size Toffoli gates, and when they use only constantly many ancill\ae. Under this constraint, this bound is close to optimal. In the case of a non-constant number $a$ of ancill\ae\ and $n$ input qubits, we give a tradeoff between $a$ and the required depth, that results in a non-constant lower bound for fanout when $a = n^{1-o(1)}$. We also show that, regardless of the number of ancill\ae\, arbitrary arity Toffoli gates cannot be simulated exactly by a constant depth circuit family with gates of bounded arity.

Стилі APA, Harvard, Vancouver, ISO та ін.

10

Lovett, Shachar, and Emanuele Viola. "Bounded-Depth Circuits Cannot Sample Good Codes." computational complexity 21, no. 2 (March 30, 2012): 245–66. http://dx.doi.org/10.1007/s00037-012-0039-3.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

11

Boyar, Joan, Magnus Gausdal Find, and René Peralta. "Small low-depth circuits for cryptographic applications." Cryptography and Communications 11, no. 1 (March 24, 2018): 109–27. http://dx.doi.org/10.1007/s12095-018-0296-3.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

12

Shpilka, A., and A. Wigderson. "Depth-3 arithmetic circuits over fields of characteristic zero." Computational Complexity 10, no. 1 (November 2001): 1–27. http://dx.doi.org/10.1007/pl00001609.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

13

Yan, P. Y., and I. Parberry. "Exponential Size Lower Bounds for Some Depth 3 Circuits." Information and Computation 112, no. 1 (July 1994): 117–30. http://dx.doi.org/10.1006/inco.1994.1054.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

14

Shpilka, Amir. "Interpolation of Depth-3 Arithmetic Circuits with Two Multiplication Gates." SIAM Journal on Computing 38, no. 6 (January 2009): 2130–61. http://dx.doi.org/10.1137/070694879.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

15

Kumar, Mrinal. "On the Power of Border of Depth-3 Arithmetic Circuits." ACM Transactions on Computation Theory 12, no. 1 (February 25, 2020): 1–8. http://dx.doi.org/10.1145/3371506.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

16

Wolfovitz, Guy. "The complexity of depth-3 circuits computing symmetric Boolean functions." Information Processing Letters 100, no. 2 (October 2006): 41–46. http://dx.doi.org/10.1016/j.ipl.2006.06.008.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

17

Agrawal, Manindra, Chandan Saha, Ramprasad Saptharishi, and Nitin Saxena. "Jacobian Hits Circuits: Hitting Sets, Lower Bounds for Depth-$D$ Occur-$k$ Formulas and Depth-3 Transcendence Degree-$k$ Circuits." SIAM Journal on Computing 45, no. 4 (January 2016): 1533–62. http://dx.doi.org/10.1137/130910725.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

18

Albrecht, A., E. Hein, D. Melzer, K. Steinhöfel, M. Taupitz, and C. K. Wong. "Liver tissue classification by bounded-depth threshold circuits." International Congress Series 1230 (June 2001): 1156–57. http://dx.doi.org/10.1016/s0531-5131(01)00202-3.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

19

Fagin, Ronald, Maria M. Klawe, Nicholas J. Pippenger, and Larry Stockmeyer. "Bounded-depth, polynomial-size circuits for symmetric functions." Theoretical Computer Science 36 (1985): 239–50. http://dx.doi.org/10.1016/0304-3975(85)90045-3.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

20

Green, F., S. Homer, C. Moore, and C. Pollett. "Counting, fanout and the complexity of quantum ACC." Quantum Information and Computation 2, no. 1 (January 2002): 35–65. http://dx.doi.org/10.26421/qic2.1-3.

Повний текст джерела

Анотація:

We propose definitions of QAC^0, the quantum analog of the classical class AC^0 of constant-depth circuits with AND and OR gates of arbitrary fan-in, and QACC[q], the analog of the class ACC[q] where Mod_q gates are also allowed. We prove that parity or fanout allows us to construct quantum MOD_q gates in constant depth for any q, so QACC[2] = QACC. More generally, we show that for any q,p > 1, MOD_q is equivalent to MOD_p (up to constant depth and polynomial size). This implies that QAC^0 with unbounded fanout gates, denoted QACwf^0, is the same as QACC[q] and QACC for all q. Since \ACC[p] \ne ACC[q] whenever p and q are distinct primes, QACC[q] is strictly more powerful than its classical counterpart, as is QAC^0 when fanout is allowed. This adds to the growing list of quantum complexity classes which are provably more powerful than their classical counterparts. We also develop techniques for proving upper bounds for QACC in terms of related language classes. We define classes of languages closely related to QACC[2] and show that restricted versions of them can be simulated by polynomial-size circuits. With further restrictions, language classes related to QACC[2] operators can be simulated by classical threshold circuits of polynomial size and constant depth.

Стилі APA, Harvard, Vancouver, ISO та ін.

21

Brustmann, Bettina, and Ingo Wegener. "The complexity of symmetric functions in bounded-depth circuits." Information Processing Letters 25, no. 4 (June 1987): 217–19. http://dx.doi.org/10.1016/0020-0190(87)90163-3.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

22

Grolmusz, Vince. "A lower bound for depth-3 circuits with MOD m gates." Information Processing Letters 67, no. 2 (July 1998): 87–90. http://dx.doi.org/10.1016/s0020-0190(98)00093-3.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

23

Sergeev, Igor' S. "On the complexity of bounded-depth circuits and formulas over the basis of fan-in gates." Discrete Mathematics and Applications 29, no. 4 (August 27, 2019): 241–54. http://dx.doi.org/10.1515/dma-2019-0022.

Повний текст джерела

Анотація:

Abstract We obtain estimates for the complexity of the implementation of n-place Boolean functions by circuits and formulas built of unbounded fan-in conjunction and disjunction gates and either negation gates or negations of variables as inputs. Restrictions on the depth of circuits and formulas are imposed. In a number of cases, the estimates obtained in the paper are shown to be asymptotically sharp. In particular, for the complexity of circuits with variables and their negations on inputs, the Shannon function is asymptotically estimated as $2\cdot {{2}^{n/2}};$this estimate is attained on depth-3 circuits.

Стилі APA, Harvard, Vancouver, ISO та ін.

24

Allender, Eric, V. Arvind, Rahul Santhanam, and Fengming Wang. "Uniform derandomization from pathetic lower bounds." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 370, no. 1971 (July 28, 2012): 3512–35. http://dx.doi.org/10.1098/rsta.2011.0318.

Повний текст джерела

Анотація:

The notion of probabilistic computation dates back at least to Turing, who also wrestled with the practical problems of how to implement probabilistic algorithms on machines with, at best, very limited access to randomness. A more recent line of research, known as derandomization, studies the extent to which randomness is superfluous. A recurring theme in the literature on derandomization is that probabilistic algorithms can be simulated quickly by deterministic algorithms, if one can obtain impressive (i.e. superpolynomial, or even nearly exponential) circuit size lower bounds for certain problems. In contrast to what is needed for derandomization, existing lower bounds seem rather pathetic. Here, we present two instances where ‘pathetic’ lower bounds of the form n 1+ ϵ would suffice to derandomize interesting classes of probabilistic algorithms. We show the following: — If the word problem over S 5 requires constant-depth threshold circuits of size n 1+ ϵ for some ϵ >0, then any language accepted by uniform polynomial size probabilistic threshold circuits can be solved in subexponential time (and, more strongly, can be accepted by a uniform family of deterministic constant-depth threshold circuits of subexponential size). — If there are no constant-depth arithmetic circuits of size n 1+ ϵ for the problem of multiplying a sequence of n 3×3 matrices, then, for every constant d , black-box identity testing for depth- d arithmetic circuits with bounded individual degree can be performed in subexponential time (and even by a uniform family of deterministic constant-depth AC 0 circuits of subexponential size).

Стилі APA, Harvard, Vancouver, ISO та ін.

25

Lai, Wenxing. "The Inapproximability of k-DominatingSet for Parameterized AC 0 Circuits †." Algorithms 12, no. 11 (November 4, 2019): 230. http://dx.doi.org/10.3390/a12110230.

Повний текст джерела

Анотація:

Chen and Flum showed that any FPT-approximation of the k-Clique problem is not in para- AC 0 and the k-DominatingSet (k-DomSet) problem could not be computed by para- AC 0 circuits. It is natural to ask whether the f ( k ) -approximation of the k-DomSet problem is in para- AC 0 for some computable function f. Very recently it was proved that assuming W [ 1 ] ≠ FPT , the k-DomSet problem cannot be f ( k ) -approximated by FPT algorithms for any computable function f by S., Laekhanukit and Manurangsi and Lin, seperately. We observe that the constructions used in Lin’s work can be carried out using constant-depth circuits, and thus we prove that para- AC 0 circuits could not approximate this problem with ratio f ( k ) for any computable function f. Moreover, under the hypothesis that the 3-CNF-SAT problem cannot be computed by constant-depth circuits of size 2 ε n for some ε > 0 , we show that constant-depth circuits of size n o ( k ) cannot distinguish graphs whose dominating numbers are either ≤k or > log n 3 log log n 1 / k . However, we find that the hypothesis may be hard to settle by showing that it implies NP ⊈ NC 1 .

Стилі APA, Harvard, Vancouver, ISO та ін.

26

Kulikov, Alexander S., and Vladimir V. Podolskii. "Computing Majority by Constant Depth Majority Circuits with Low Fan-in Gates." Theory of Computing Systems 63, no. 5 (November 29, 2018): 956–86. http://dx.doi.org/10.1007/s00224-018-9900-3.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

27

Cai, Jin-yi. "Lower bounds for constant-depth circuits in the presence of help bits." Information Processing Letters 36, no. 2 (October 1990): 79–83. http://dx.doi.org/10.1016/0020-0190(90)90101-3.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

28

Dvir, Zeev, and Amir Shpilka. "Locally Decodable Codes with Two Queries and Polynomial Identity Testing for Depth 3 Circuits." SIAM Journal on Computing 36, no. 5 (January 2007): 1404–34. http://dx.doi.org/10.1137/05063605x.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

29

Jukna, Stasys. "Computing threshold functions by depth-3 threshold circuits with smaller thresholds of their gates." Information Processing Letters 56, no. 3 (November 1995): 147–50. http://dx.doi.org/10.1016/0020-0190(95)00137-2.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

30

Saxena, Nitin, and C. Seshadhri. "Blackbox Identity Testing for Bounded Top-Fanin Depth-3 Circuits: The Field Doesn't Matter." SIAM Journal on Computing 41, no. 5 (January 2012): 1285–98. http://dx.doi.org/10.1137/10848232.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

31

Ni, Xiaotong, and Maarten van den Nest. "Commuting quantum circuits: efficiently classical simulations versus hardness results." Quantum Information and Computation 13, no. 1&2 (January 2013): 54–72. http://dx.doi.org/10.26421/qic13.1-2-5.

Повний текст джерела

Анотація:

The study of quantum circuits composed of commuting gates is particularly useful to understand the delicate boundary between quantum and classical computation. Indeed, while being a restricted class, commuting circuits exhibit genuine quantum effects such as entanglement. In this paper we show that the computational power of commuting circuits exhibits a surprisingly rich structure. First we show that every 2-local commuting circuit acting on $d$-level systems and followed by single-qudit measurements can be efficiently simulated classically with high accuracy. In contrast, we prove that such strong simulations are hard for 3-local circuits. Using sampling methods we further show that all commuting circuits composed of exponentiated Pauli operators $e^{i\theta P}$ can be simulated efficiently classically when followed by single-qubit measurements. Finally, we show that commuting circuits can efficiently simulate certain non-commutative processes, related in particular to constant-depth quantum circuits. This gives evidence that the power of commuting circuits goes beyond classical computation.

Стилі APA, Harvard, Vancouver, ISO та ін.

32

Grigoriev, D., and A. Razborov. "Exponential Lower Bounds for Depth 3 Arithmetic Circuits in Algebras of Functions over Finite Fields." Applicable Algebra in Engineering, Communication and Computing 10, no. 6 (July 1, 2000): 465–87. http://dx.doi.org/10.1007/s002009900021.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

33

Uchizawa, Kei, Rodney Douglas, and Wolfgang Maass. "On the Computational Power of Threshold Circuits with Sparse Activity." Neural Computation 18, no. 12 (December 2006): 2994–3008. http://dx.doi.org/10.1162/neco.2006.18.12.2994.

Повний текст джерела

Анотація:

Circuits composed of threshold gates (McCulloch-Pitts neurons, or perceptrons) are simplified models of neural circuits with the advantage that they are theoretically more tractable than their biological counterparts. However, when such threshold circuits are designed to perform a specific computational task, they usually differ in one important respect from computations in the brain: they require very high activity. On average every second threshold gate fires (sets a 1 as output) during a computation. By contrast, the activity of neurons in the brain is much sparser, with only about 1% of neurons firing. This mismatch between threshold and neuronal circuits is due to the particular complexity measures (circuit size and circuit depth) that have been minimized in previous threshold circuit constructions. In this letter, we investigate a new complexity measure for threshold circuits, energy complexity, whose minimization yields computations with sparse activity. We prove that all computations by threshold circuits of polynomial size with entropy O(log n) can be restructured so that their energy complexity is reduced to a level near the entropy of circuit states. This entropy of circuit states is a novel circuit complexity measure, which is of interest not only in the context of threshold circuits but for circuit complexity in general. As an example of how this measure can be applied, we show that any polynomial size threshold circuit with entropy O(log n) can be simulated by a polynomial size threshold circuit of depth 3. Our results demonstrate that the structure of circuits that result from a minimization of their energy complexity is quite different from the structure that results from a minimization of previously considered complexity measures, and potentially closer to the structure of neural circuits in the nervous system. In particular, different pathways are activated in these circuits for different classes of inputs. This letter shows that such circuits with sparse activity have a surprisingly large computational power.

Стилі APA, Harvard, Vancouver, ISO та ін.

34

Dövencioğlu, Dicle, Hiroshi Ban, Andrew J. Schofield, and Andrew E. Welchman. "Perceptual Integration for Qualitatively Different 3-D Cues in the Human Brain." Journal of Cognitive Neuroscience 25, no. 9 (September 2013): 1527–41. http://dx.doi.org/10.1162/jocn_a_00417.

Повний текст джерела

Анотація:

The visual system's flexibility in estimating depth is remarkable: We readily perceive 3-D structure under diverse conditions from the seemingly random dots of a “magic eye” stereogram to the aesthetically beautiful, but obviously flat, canvasses of the Old Masters. Yet, 3-D perception is often enhanced when different cues specify the same depth. This perceptual process is understood as Bayesian inference that improves sensory estimates. Despite considerable behavioral support for this theory, insights into the cortical circuits involved are limited. Moreover, extant work tested quantitatively similar cues, reducing some of the challenges associated with integrating computationally and qualitatively different signals. Here we address this challenge by measuring fMRI responses to depth structures defined by shading, binocular disparity, and their combination. We quantified information about depth configurations (convex “bumps” vs. concave “dimples”) in different visual cortical areas using pattern classification analysis. We found that fMRI responses in dorsal visual area V3B/KO were more discriminable when disparity and shading concurrently signaled depth, in line with the predictions of cue integration. Importantly, by relating fMRI and psychophysical tests of integration, we observed a close association between depth judgments and activity in this area. Finally, using a cross-cue transfer test, we found that fMRI responses evoked by one cue afford classification of responses evoked by the other. This reveals a generalized depth representation in dorsal visual cortex that combines qualitatively different information in line with 3-D perception.

Стилі APA, Harvard, Vancouver, ISO та ін.

35

Karnin, Zohar S., and Amir Shpilka. "Black box polynomial identity testing of generalized depth-3 arithmetic circuits with bounded top fan-in." Combinatorica 31, no. 3 (May 2011): 333–64. http://dx.doi.org/10.1007/s00493-011-2537-3.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

36

Bun, Mark, Robin Kothari, and Justin Thaler. "Quantum algorithms and approximating polynomials for composed functions with shared inputs." Quantum 5 (September 16, 2021): 543. http://dx.doi.org/10.22331/q-2021-09-16-543.

Повний текст джерела

Анотація:

We give new quantum algorithms for evaluating composed functions whose inputs may be shared between bottom-level gates. Let f be an m-bit Boolean function and consider an n-bit function F obtained by applying f to conjunctions of possibly overlapping subsets of n variables. If f has quantum query complexity Q(f), we give an algorithm for evaluating F using O~(Q(f)⋅n) quantum queries. This improves on the bound of O(Q(f)⋅n) that follows by treating each conjunction independently, and our bound is tight for worst-case choices of f. Using completely different techniques, we prove a similar tight composition theorem for the approximate degree of f.By recursively applying our composition theorems, we obtain a nearly optimal O~(n1−2−d) upper bound on the quantum query complexity and approximate degree of linear-size depth-d AC0 circuits. As a consequence, such circuits can be PAC learned in subexponential time, even in the challenging agnostic setting. Prior to our work, a subexponential-time algorithm was not known even for linear-size depth-3 AC0 circuits.As an additional consequence, we show that AC0∘⊕ circuits of depth d+1 require size Ω~(n1/(1−2−d))≥ω(n1+2−d) to compute the Inner Product function even on average. The previous best size lower bound was Ω(n1+4−(d+1)) and only held in the worst case (Cheraghchi et al., JCSS 2018).

Стилі APA, Harvard, Vancouver, ISO та ін.

37

Amin, Kazi Rafsanjani, Carine Ladner, Guillaume Jourdan, Sébastien Hentz, Nicolas Roch, and Julien Renard. "Loss mechanisms in TiN high impedance superconducting microwave circuits." Applied Physics Letters 120, no. 16 (April 18, 2022): 164001. http://dx.doi.org/10.1063/5.0086019.

Повний текст джерела

Анотація:

Aluminum-based platforms have allowed to reach major milestones for superconducting quantum circuits. For the next generation of devices, materials that are able to maintain low microwave losses while providing new functionalities, such as large kinetic inductance or compatibility with CMOS platform, are needed. Here, we report on a combined direct current and microwave investigation of titanium nitride films of different thicknesses grown using CMOS compatible methods. For microwave resonators made of 3 nm thick TiN, we measured large kinetic inductance [Formula: see text] pH/sq, high mode impedance of [Formula: see text] kΩ while maintaining microwave quality factor [Formula: see text] in the single photon limit. We present an in-depth study of the microwave loss mechanisms in these devices that indicates the importance of quasiparticles and provide insight for further improvement.

Стилі APA, Harvard, Vancouver, ISO та ін.

38

Romano, A., J. Vanhellemont, A. De Keersgieter, W. Vandervorst, J. R. Morante, and J. Van Landuyt. "A novel TEM technique for junction delineation in integrated circuits." Proceedings, annual meeting, Electron Microscopy Society of America 48, no. 4 (August 1990): 748–49. http://dx.doi.org/10.1017/s0424820100176873.

Повний текст джерела

Анотація:

Ion implantation is a well established technique to dope selectively prespecified regions of silicon substrates. It has the drawback that a thermal treatment is required to activate the dopant and to reconstruct the crystal lattice. This leads to dopant diffusion in depth and also laterally, when the implantation has been preformed through a patterned mask.In this paper two different approaches to determine the doping profile using chemical etching and TEM are presented. Cross-section specimens are prepared using a technique described elsewhere, followed by preferential etching.The first approach is well established and is based on the combined action of HF and HNO3.Low concentrations of HF are used to keep the etching rate low enough. Figure 1 shows a cross-section of a boron implanted and annealed sample which has been etched using the solution HF(40%):HNO3(65%)= 1:300 at 5°C for 80 seconds. The etching rate is proportional to the doping level, as shown in figure 2 and it can be observed that the lowest level which one can delineate with this solution is of the order of 1017cm−3, which is in agreement with the delineated level of figure 1, namely 6·1017 cm−3.

Стилі APA, Harvard, Vancouver, ISO та ін.

39

Yetiş, Hasan, and Mehmet Karaköse. "A New Framework Containing Convolution and Pooling Circuits for Image Processing and Deep Learning Applications with Quantum Computing Implementation." Traitement du Signal 39, no. 2 (April 30, 2022): 501–12. http://dx.doi.org/10.18280/ts.390212.

Повний текст джерела

Анотація:

The resource need for deep learning and quantum computers' high computing power potential encourage collaboration between the two fields. Today, variational quantum circuits are used to perform the convolution operation with quantum computing. However, the results produced by variational circuits do not show a direct resemblance to the classical convolution operation. Because classical data is encoded into quantum data with their exact values in value-encoded methods, in contrast to variational quantum circuits, arithmetical operations can be applied with high accuracy. In this study, value-encoded quantum circuits for convolution and pooling operations are proposed to apply deep learning in quantum computers in a traditional and proven way. To construct the convolution and pooling operations, some modules such as addition, multiplication, division, and comparison are created. In addition, a window-based framework for quantum image processing applications is proposed. The generated convolution and pooling circuits are simulated on the IBM QISKIT simulator in parallel thanks to the proposed framework. The obtained results are verified by the expected results. Due to the limitations of quantum simulators and computers in the NISQ era, the used grayscale images are resized to 8x8 and the resolution of the images is reduced to 3 qubits. With developing the quantum technologies, the proposed approach can be applied for bigger and higher resolution images. Although the proposed method causes more qubit usage and circuit depth compared to variational convolutional circuits, the results they produce are exactly the same as the classical convolution process.

Стилі APA, Harvard, Vancouver, ISO та ін.

40

Asadpour, Ailin, Amir Sabbagh Molahosseini, and Azadeh Alsadat Emrani Zarandi. "The use of reversible logic gates in the design of residue number systems." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 2 (April 1, 2023): 2009. http://dx.doi.org/10.11591/ijece.v13i2.pp2009-2022.

Повний текст джерела

Анотація:

Reversible computing is an emerging technique to achieve ultra-low-power circuits. Reversible arithmetic circuits allow for achieving energy-efficient high-performance computational systems. Residue number systems (RNS) provide parallel and fault-tolerant additions and multiplications without carry propagation between residue digits. The parallelism and fault-tolerance features of RNS can be leveraged to achieve high-performance reversible computing. This paper proposed RNS full reversible circuits, including forward converters, modular adders and multipliers, and reverse converters used for a class of RNS moduli sets with the composite form {2<sup>k</sup>, 2<sup>p</sup>-1}. Modulo 2<sup>n</sup>-1, 2<sup>n</sup>, and 2<sup>n</sup>+1 adders and multipliers were designed using reversible gates. Besides, reversible forward and reverse converters for the 3-moduli set {2<sup>n</sup>-1, 2<sup>n+k</sup>, 2<sup>n</sup>+1} have been designed. The proposed RNS-based reversible computing approach has been applied for consecutive multiplications with an improvement of above 15% in quantum cost after the twelfth iteration, and above 27% in quantum depth after the ninth iteration. The findings show that the use of the proposed RNS-based reversible computing in convolution results in a significant improvement in quantum depth in comparison to conventional methods based on weighted binary adders and multipliers.

Стилі APA, Harvard, Vancouver, ISO та ін.

41

Kim and Choi. "Indirect Time-of-Flight Depth Sensor with Two-Step Comparison Scheme for Depth Frame Difference Detection." Sensors 19, no. 17 (August 23, 2019): 3674. http://dx.doi.org/10.3390/s19173674.

Повний текст джерела

Анотація:

A depth sensor with integrated frame difference detection is proposed. Instead of frame difference detection using light intensity, which is vulnerable to ambient light, the difference in depth between successive frames can be acquired. Because the conventional time-of-flight depth sensor requires two frames of depth-image acquisition with four-phase modulation, it has large power consumption, as well as a large area for external frame memories. Therefore, we propose a simple two-step comparison scheme for generating the depth frame difference in a single frame. With the proposed scheme, only a single frame is needed to obtain the frame difference, with less than half of the power consumption of the conventional depth sensor. Because the frame difference is simply generated by column-parallel circuits, no access of the external frame memory is involved, nor is a digital signal processor. In addition, we used an over-pixel metal–insulator–metal capacitor to store temporary signals for enhancing the area efficiency. A prototype chip was fabricated using a 90 nm backside illumination complementary metal–oxide–semiconductor (CMOS) image sensor process. We measured the depth frame difference in the range of 1–2.5 m. With a 10 MHz modulation frequency, a depth frame difference of >10 cm was successfully detected even for objects with different reflectivity. The maximum relative error from the difference of the reflectivity (white and wooden targets) was <3%.

Стилі APA, Harvard, Vancouver, ISO та ін.

42

Prihozhy, Anatoly A. "Synthesis of quantum circuits based on incompletely specified functions and if-decision diagrams." Journal of the Belarusian State University. Mathematics and Informatics, no. 3 (December 14, 2021): 84–97. http://dx.doi.org/10.33581/2520-6508-2021-3-84-97.

Повний текст джерела

Анотація:

The problem of synthesis and optimisation of logical reversible and quantum circuits from functional descriptions represented as decision diagrams is considered. It is one of the key problems being solved with the aim of creating quantum computing technology and quantum computers. A new method of stepwise transformation of the initial functional specification to a quantum circuit is proposed, which provides for the following project states: reduced ordered binary decision diagram, if-decision diagram, functional if-decision diagram, reversible circuit and quantum circuit. The novelty of the method consists in extending the Shannon and Davio expansions of a Boolean function on a single variable to the expansions of the same Boolean function on another function with obtaining decomposition products that are represented by incompletely defined Boolean functions. Uncertainty in the decomposition products gives remarkable opportunities for minimising the graph representation of the specified function. Instead of two outgoing branches of the binary diagram vertex, three outgoing branches of the if-diagram vertex are generated, which increase the level of parallelism in reversible and quantum circuits. For each transformation step, appropriate mapping rules are proposed that reduce the number of lines, gates and the depth of the reversible and quantum circuit. The comparison of new results with the results given by the known method of mapping the vertices of binary decision diagram into cascades of reversible and quantum gates shows a significant improvement in the quality of quantum circuits that are synthesised by the proposed method.

Стилі APA, Harvard, Vancouver, ISO та ін.

43

Emelyanov, V. V. "Passivation of a Conductive System of Integrated Circuits with a Layer of Aluminum Nitride." Doklady BGUIR 21, no. 3 (June 20, 2023): 12–16. http://dx.doi.org/10.35596/1729-7648-2023-21-3-12-16.

Повний текст джерела

Анотація:

Passivation of the film conductive system of integrated circuits makes it more reliable by increasing the resistance to electromigration. The problem of manufacturing a passivating layer on the formed current-conducting system of an integrated circuit, obtained in a single technological cycle, including isotropic plasma-chemical etching of an aluminum alloy layer to a depth of 8–12 nm and isotropic plasma-chemical nitriding of the surface of the obtained current-carrying tracks until the aluminum nitride thickness from 10 to 50 nm, is considered. This task makes it possible to form a dielectric film based on silicon dioxide on a silicon substrate with active regions, etch contact windows to active elements of the substrate in the dielectric film, deposit a barrier layer 0.005–0.050 µm thick, and deposit an aluminum alloy film 0.5–2.0 um and much more.

Стилі APA, Harvard, Vancouver, ISO та ін.

44

Yin, Yue-Xin, Xiao-Jie Yin, Xiao-Pei Zhang, Guan-Wen Yan, Yue Wang, Yuan-Da Wu, Jun-Ming An, Liang-Liang Wang, and Da-Ming Zhang. "High-Q-Factor Silica-Based Racetrack Microring Resonators." Photonics 8, no. 2 (February 6, 2021): 43. http://dx.doi.org/10.3390/photonics8020043.

Повний текст джерела

Анотація:

In this paper, ultrahigh-Q factor racetrack microring resonators (MRRs) are demonstrated based on silica planar lightwave circuits (PLCs) platform. A loaded ultrahigh-Q factor Qload of 1.83 × 106 is obtained. The MRRs are packaged with fiber-to-fiber loss of ~5 dB. A notch depth of 3 dB and ~137 pm FSR are observed. These MRRs show great potential in optical communications as filters. Moreover, the devices are suitable used in monolithic integration and hybrid integration with other devices, especially in external cavity lasers (ECLs) to realize ultranarrow linewidths.

Стилі APA, Harvard, Vancouver, ISO та ін.

45

Aslantas, Kubilay, Şükrü Ülker, Ömer Şahan, Danil Yu Pimenov, and Khaled Giasin. "Mechanistic modeling of cutting forces in high-speed microturning of titanium alloy with consideration of nose radius." International Journal of Advanced Manufacturing Technology 119, no. 3-4 (December 10, 2021): 2393–408. http://dx.doi.org/10.1007/s00170-021-08437-w.

Повний текст джерела

Анотація:

AbstractMicroturning is a micromechanical machining process used to produce microcylindrical or axially symmetrical parts. Microcylindrical parts are mainly used in microfluidic systems, intravenous micromotors, microsurgical applications, optical lens applications, and microinjection systems. The workpiece diameter is very small in microturning and therefore is greatly affected by the cutting forces. For this reason, it is important to predict the cutting forces when machining miniature parts. In this study, an analytical mechanistic model of microturning is used to predict the cutting forces considering the tool nose radius. In the semi-empirically developed mechanistic model, the tool radius was considered. A series of semi-orthogonal microturning cutting tests were carried out to determine the cutting and edge force coefficients. The mechanistic model was generalized depending on the cutting speed and depth of cut by performing multilinear regression analysis. In the study, the depth of cut (ap = 30–90 µm) and feed values (f = 0.5–20 µm/rev) were selected considering the nose radius and edge radius of the cutting tool. The experiments were carried out under high-cutting speeds (Vc = 150–500 m/min) and microcutting conditions. Ti6Al4V alloy was used as the workpiece material and the tests were carried out under dry cutting conditions. Validation tests for different cutting parameters were carried out to validate the accuracy of the developed mechanistic model. The results showed that the difference between the mechanistic model and the experimental data was a minimum of 3% and a maximum of 24%. The maximum difference between the experimental and the model usually occurs in forces in the tangential direction. It has been observed that the developed model gives accurate results even at a depth of cut smaller than the nose radius and at feed values smaller than the edge radius.

Стилі APA, Harvard, Vancouver, ISO та ін.

46

Simko, Steven J., and Richard A. Waldo. "Multitechnique problem solving using EDS/EPMA and surface analysis." Proceedings, annual meeting, Electron Microscopy Society of America 50, no. 2 (August 1992): 1782–83. http://dx.doi.org/10.1017/s0424820100133540.

Повний текст джерела

Анотація:

Thin films are used in a wide range of modern technologies. Examples include sensors, antiwear coatings, optical coatings, and integrated circuits. A variety of methods have evolved for characterizing thin films in the thickness range of 1 monolayer to several micrometers. Electron probe microanalysis (EPMA) or energy dispersive x-ray spectroscopy (EDS) are two methods for characterizing thicker films (>1 μm). In these techniques, the sampling depth depends on the penetration depth of the primary electron beam which can be controlled by changing the electron beam energy. Thin films can also be characterized using line scans on specimens prepared as polished cross-sections or after angle lapping. For extremely thin films (<3 nm), techniques with high surface sensitivity such as Auger electron spectroscopy (AES) and x-ray photoelectron spectroscopy (XPS) are commonly employed. Sampling depth depends on the attenuation length of the emitted photoelectrons or Auger electrons.Electron spectroscopy techniques are also used to characterize thicker films by adding a microsectioning method to the experiment, most commonly ion sputtering.

Стилі APA, Harvard, Vancouver, ISO та ін.

47

Weisse, Julietta, Heinz Mitlehner, Lothar Frey, and Tobias Erlbacher. "Design of a 4H-SiC RESURF n-LDMOS Transistor for High Voltage Integrated Circuits." Materials Science Forum 963 (July 2019): 629–32. http://dx.doi.org/10.4028/www.scientific.net/msf.963.629.

Повний текст джерела

Анотація:

In this work, a lateral 4H-SiC n-LDMOS transistor, based on the principle of a reduced surface field due to charge compensation, is investigated by numerical simulations, in order to find adequate fabrication parameters for a lightly doped p-type epitaxy in combination with a higher doped channel region. The purpose of this work is the integration into an existing technology for a 10 V 4H-SiC-CMOS process. The simulations predict in a blocking voltage of 1.3 kV in combination with an On-resistance of 17 mΩcm2 for a device with a RESURF structure with a total implanted Al concentration of 6∙1016 cm-3 and a depth of 1 μm, a field plate of 5 μm and a drift region of 20 μm. The threshold voltage varies from 5 V to 10 V, depending on the thickness of the gate oxide (50 nm to 100 nm).

Стилі APA, Harvard, Vancouver, ISO та ін.

48

TAYARI, MAHSHID, and MOHAMMAD ESHGHI. "DESIGN OF 3-INPUT REVERSIBLE PROGRAMMABLE LOGIC ARRAY." Journal of Circuits, Systems and Computers 20, no. 02 (April 2011): 283–97. http://dx.doi.org/10.1142/s0218126611007256.

Повний текст джерела

Анотація:

In this paper, for the first time a design for a Reversible Programmable Logic Array (RPLA) is introduced. This is the first RPLA design because the reversible PLA design, presented in previous research, is not a programmable circuit. In our presented RPLAs, four reversible AND array designs with different specifications are proposed. A reversible OR array, which can be programmed to generate any Boolean function, is also designed. This reversible and programmable OR array is also cascadable. That is, it produces a copy of inputted midterms at its outputs to be fed to another OR array in order to design another Boolean function, with no need for another AND array. The proposed 3-input RPLA is programmed to design three reversible circuits, a 1-bit full adder, a 1-bit full subtractor, and a 2-to-1 line multiplexer. Five figures of merit, including number of gates, number of constant inputs, number of garbage outputs, depth and quantum cost of the circuit are considered to evaluate and compare the designs. A comparison between the proposed reversible AND arrays and the same circuit presented in previous research, against these figures of merit, shows a better performance of our proposed designs. The proposed RPLAs are also evaluated, using these five figures of merit.

Стилі APA, Harvard, Vancouver, ISO та ін.

49

Theys, Tom, Pierpaolo Pani, Johannes van Loon, Jan Goffin, and Peter Janssen. "Three-dimensional Shape Coding in Grasping Circuits: A Comparison between the Anterior Intraparietal Area and Ventral Premotor Area F5a." Journal of Cognitive Neuroscience 25, no. 3 (March 2013): 352–64. http://dx.doi.org/10.1162/jocn_a_00332.

Повний текст джерела

Анотація:

Depth information is necessary for adjusting the hand to the three-dimensional (3-D) shape of an object to grasp it. The transformation of visual information into appropriate distal motor commands is critically dependent on the anterior intraparietal area (AIP) and the ventral premotor cortex (area F5), particularly the F5p sector. Recent studies have demonstrated that both AIP and the F5a sector of the ventral premotor cortex contain neurons that respond selectively to disparity-defined 3-D shape. To investigate the neural coding of 3-D shape and the behavioral role of 3-D shape-selective neurons in these two areas, we recorded single-cell activity in AIP and F5a during passive fixation of curved surfaces and during grasping of real-world objects. Similar to those in AIP, F5a neurons were either first- or second-order disparity selective, frequently showed selectivity for discrete approximations of smoothly curved surfaces that contained disparity discontinuities, and exhibited mostly monotonic tuning for the degree of disparity variation. Furthermore, in both areas, 3-D shape-selective neurons were colocalized with neurons that were active during grasping of real-world objects. Thus, area AIP and F5a contain highly similar representations of 3-D shape, which is consistent with the proposed transfer of object information from AIP to the motor system through the ventral premotor cortex.

Стилі APA, Harvard, Vancouver, ISO та ін.

50

Kim, Dongyung. "An Optimized Discrete Data Classification Method in N -Dimensional." Computational and Mathematical Methods 2022 (May 28, 2022): 1–8. http://dx.doi.org/10.1155/2022/8199872.

Повний текст джерела

Анотація:

We propose a discrete data classification method of scattered data in N -dimensional by solving the minimax problem for a set of points. The current research is extended from 2-dimensional and 3-dimensional to N -dimensional. The problem can be applied to artificial intelligence classification problems (machine learning, deep learning), point data analysis problems (data science problem), the optimized design of nanoscale circuits, and the location of facility problems, circle detection on 2D image, or sphere detection on depth image. We generalized the discrete data classification methodology in N -dimensional. Finally, we resolved to find an exact solution of the location of a manifold for our suggested problem in N -dimensional.

Стилі APA, Harvard, Vancouver, ISO та ін.

Ми пропонуємо знижки на всі преміум-плани для авторів, чиї праці увійшли до тематичних добірок літератури. Зв'яжіться з нами, щоб отримати унікальний промокод!