Добірка наукової літератури з теми "Multi-r-ic Circuits"

In this article, we are interested in understanding the complexity of computing multilinear polynomials using depth four circuits in which the polynomial computed at every node has a bound on the individual degree of r ≥ 1 with respect to all its variables (referred to as multi- r -ic circuits). The goal of this study is to make progress towards proving superpolynomial lower bounds for general depth four circuits computing multilinear polynomials, by proving better bounds as the value of r increases. Recently, Kayal, Saha and Tavenas (Theory of Computing, 2018) showed that any depth four arithmetic circuit of bounded individual degree r computing an explicit multilinear polynomial on n O (1) variables and degree d must have size at least ( n / r 1.1 ) Ω(√ d / r ) . This bound, however, deteriorates as the value of r increases. It is a natural question to ask if we can prove a bound that does not deteriorate as the value of r increases, or a bound that holds for a larger regime of r . In this article, we prove a lower bound that does not deteriorate with increasing values of r , albeit for a specific instance of d = d ( n ) but for a wider range of r . Formally, for all large enough integers n and a small constant η, we show that there exists an explicit polynomial on n O (1) variables and degree Θ (log 2 n ) such that any depth four circuit of bounded individual degree r ≤ n η must have size at least exp(Ω(log 2 n )). This improvement is obtained by suitably adapting the complexity measure of Kayal et al. (Theory of Computing, 2018). This adaptation of the measure is inspired by the complexity measure used by Kayal et al. (SIAM J. Computing, 2017).

In this study, we developed a complete flow for the design of monolithic 3D ICs. We have taken the register-transfer level netlist of a circuit as the input and synthesized it to construct the gate-level netlist. Next, we partitioned the circuit using custom-made partitioning algorithms and implemented the place and route flow of the entire 3D IC by repurposing 2D electronic design automation tools. We implemented two different partitioning algorithms, namely the min-cut and the analytical quadratic (AQ) algorithms, to assign the cells in different tiers. We applied our flow on three different benchmark circuits and compared the total power dissipation of the 3D designs with their 2D counterparts. We also compared our results with that of similar works and obtained significantly better performance. Our two-tier 3D flow with AQ partitioner obtained 37.69%, 35.06%, and 12.15% power reduction compared to its 2D counterparts on the advanced encryption standard, floating-point unit, and fast Fourier transform benchmark circuits, respectively. Finally, we analyzed the type of circuits that are more applicable for a 3D layout and the impact of increasing the number of tiers of the 3D design on total power dissipation.

The current trend in electronic-systems technology is to produce compact, lighter, low-power-dissipating, affordable, reliable, and mobile information systems. These factors favor the augmentation of interface systems that sense, source, store, display, and actuate with artificial-intelligence strategies. Herein lies the opportunity to introduce novel technologies based on integrated multi-component oxide (e.g., titanates, niobates, and tantalates) films into usable systems. In particular the oxygen octahedra class of materials (e.g., (Ba,Sr)TiO3 or BST, Pb(Zr,Ti)O3 or PZT, layered SrBi2Ta2O9 or SBT, and polytitanates) that exhibit high permittivities; large electromechanical-coupling coefficients; and pyroelectric, electro-optic, and ferroelectric effects are of interest. They are being evaluated, due to growing demand for compatibility with integrated-circuit (IC) technology, for a variety of applications. These include nonvolatile memories, ultralargescale-integration (ULSI) dynamic random-access memories (DRAMs), decoupling capacitors, piezoelectric sensors and actuators, pyroelectric detectors, and neural network components. Moreover in high-performance multichip-module (MCM) technology, there remains a vital need for the replacement of discrete passive devices, which occupy valuable real estate, by embedded ones. These high-density interconnect structures will play a significant role in nondigital electronic modules including mixed-mode circuits, power conversion and conditioning, microwave transmit/receive (T/R), and optoelectronics. Table I specifically illustrates some electronic applications along with their estimated requirements.

Almost all practical engineering applications are multi-physics in nature, and various physical phenomena usually interact and couple with each other. For instance, the resistivity of most conducting metals increases linearly with increases in the surrounding temperature resulting from Joule heating by electrical currents flowing through conductors. Therefore, in order to accurately characterize the performance of high-power integrated circuits (ICs), packages and printed circuit boards (PCBs), it is essential to account for both electrical and thermal effects and the intimate couplings between them. In this paper, we present non-conformal, non-overlapping domain decomposition methods (DDMs) for thermal-aware direct current (DC) IR drop co-analysis of high-power chip-package-PCBs. Here, IR stands for the finite resistivity (R) of metals and current (I) drawn off from the power/ground planes. The proposed DDM starts by partitioning the composite device into inhomogeneous sub-regions with temperature-dependent material properties. Subsequently, each sub-domain is meshed independently according to its own characteristic features. As a consequence, the troublesome mesh-generation task for complex ICs can be greatly subdued. The proposed thermal-aware DC IR drop co-analysis applies the non-conformal DDM for both conduction and steady-state heat-transfer analyses with a two-way coupling between them. Numerical examples, including an IC package and a chip-package-PCB, demonstrate the flexibility and potential of the proposed thermal-aware DC IR-drop co-analysis using non-conformal DDMs.

Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. The technology has a high potential in significant package miniaturization concerning package volume but also in thickness. Main advantages of FOWLP are the substrate-less package, lower thermal resistance, higher performance due to shorter interconnects together with direct IC connection by thin film metallization instead of wire bonds or flip chip bumps and lower parasitic effects. Especially the inductance of the FOWLP is much lower compared to FC-BGA packages. In addition the redistribution layer can also provide embedded passives (R, L, C) as well as antenna structures using a multi-layer structure. It can be used for multi-chip packages for System in Package (SiP) and heterogeneous integration. Manufacturing is currently done on wafer level up to 12″/300 mm and 330 mm respectively. For higher productivity and therewith lower costs larger form factors are forecasted for the near future. Instead of following the wafer level approach to 450 mm, panel level packaging will be the next big step. Sizes for the panel could range up to 18″×24″ or even larger influenced by different technologies coming from e.g. printed circuit board, solar or LCD manufacturing. However, an easy upscaling of technology when moving from wafer to panel level is not possible. Materials, equipment and processes have to be further developed or at least adapted. An overview of state of technology for panel level packaging will be presented and discussed in detailed.

In IC industry, the use of multiple die stack packaging has emerged to meet the increasing demand in miniaturization and improved functionality of mobile devices. During chip operation, transistor power dissipation raises temperature unevenly across a die. The generated thermal hotspots negatively impact reliability and degrade performance. In mechanical aspects, dies become thinner, and bumps and pitch become smaller, which makes heat dissipation more difficult, and lead to increase in mechanical stress. Such stress may cause carrier mobility degradation for transistors and could lead to parametric circuit failure. In the back-end-of-line (BEoL) interconnects, the employed ultra-low k materials prone to damage interconnects when mechanical stress is present, due to its brittle nature and poor adhesion to the barrier materials. These stresses originated at the die packaging step due to thermal mismatch between die and package materials, which is termed as chip package interaction (CPI). We call mechanical CPI (mCPI) when such stress affects reliability of the whole chip, i.e., BEoL, RDL (redistribution layer), bump, or TSVs (through silicon vias). When such stress affects device performance, we call electrical CPI (eCPI). To analyze CPI effects on a feature scale, i.e., in transistor channel or in the individual metal line or ILD (inter layer dielectric) /IMD (inter metal dielectric) gap, an analysis tool must generate accurate feature-scale stress variation across a die. Finite element analysis (FEA) is widely used for analyzing CPI induced problems. However, the traditional FEA cannot effectively handle feature-scale geometries due to huge memory consumption, and instead, treats a die as a uniform material block. Therefore, this approach cannot describe stress distribution caused by local non-uniformity of metal line distribution and fail to provide the needed accuracy for feature-scale analysis. [1] Here, we present an advanced physics-based EDA tool that overcomes the above-mentioned problems by introducing the novel methodology of extracting effective anisotropic thermal-mechanical properties (EMP), as well as employing FEA-based multi-scale simulation procedure. Prior to running FEA, the tool extracts EMP that accurately represent non-uniformities at different scales within a simulation domain. Here, each metal layer in a die is considered a binary system that consists of metal inclusions embedded in an insulator matrix. By dividing the die area into bins, metal density dependent effective properties for each bin are calculated according to theory of anisotropic composite materials. Anisotropy of properties can be obtained by taking routing direction of metal lines into account [2, 3]. EMP can adjust to multi-scale by varying bin size as shown in Fig.1. Here, Young’s modulus is extracted globally with coarse grid, and on sub-modeling region with very fine grid, which shows the corresponding property variation with much finer scale. Since EMP constructs no actual geometrical objects, the methodology can efficiently handle feature-scale objects on a large layout region. When a user selects a circuit block, or a region to be analyzed in detail, the automated tool flow enables two step stress simulation procedure, which is schematically shown in Fig. 2. First, the global-scale stress simulation is performed with coarse both the simulation mesh and EMP bin and extracts the boundary displacements for the circuit block. These boundary displacements are employed in the sub-modeling, with employed fine mesh and EMP bin. Figure 3 demonstrates the importance of EMP for accurate resolution of stress field. The 2D color maps show the x-component of stress distributions in a circuit block as a result of sub-modeling. Here, die BEoL is represented by EMP in (a), while in (b), the entire die including BEoL is represented by silicon, which is employed in traditional FEA. The stress pattern due to interconnect layout details are visible only when EMP is employed. The difference is even more pronounced when 1D stress profile is compared. By back annotating the obtained stress components in a SPICE netlist, the tool enables a user to perform accurate circuit simulation with accounted CPI effects. In eCPI analysis, the tool has been validated by employing measurements of different types of devices [4]. The additional tool capabilities that will be presented are mCPI analysis and thermomechanical stress analysis during chip operating conditions. [1] R. Radojcic, More-than-Moore 2.5D and 3D SiP Integration, Springer, 2017. [2] V. Sukharev et al. J. Electron Test, vol. 28, pp. 63-72, 2012 [3] V. Sukharev et al., Proc. Int. 3D Systems Integration Conference, 2019 [4]. A. Kteyan, et al. Proc. ISPD 2022 Figure 1