Статті в журналах: "Multi-Processor System-on-Chip"

1

Nurmi, Jari. "International Symposium on System-on-Chip 2010." International Journal of Embedded and Real-Time Communication Systems 2, no. 4 (October 2011): 38–45. http://dx.doi.org/10.4018/ijertcs.2011100103.

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International Symposium on System-on-Chip 2010 was the 12th SoC event in Tampere, Finland. The theme of this symposium was Embedded Multi-processor/multi-core Computation Platforms. That was reflecting the increasing interest in multicore and many core implementations on System-on-Chip. This paper discusses briefly the history of the event which is technically co-sponsored by IEEE Circuits and Systems Society. The main focus is in an overview of the year 2010 contents, and in particular in its tutorial and invited talks.

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2

Lee, Seung Eun. "Reusing existing resources for testing a multi-processor system-on-chip." International Journal of Electronics 100, no. 3 (March 2013): 355–70. http://dx.doi.org/10.1080/00207217.2012.713011.

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3

Cui, Yuan, and Bo Nian Li. "A Multimedia System Based on OMAP3530." Applied Mechanics and Materials 40-41 (November 2010): 506–9. http://dx.doi.org/10.4028/www.scientific.net/amm.40-41.506.

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JPEG images decoded and encoded rapidly and effectively based on OMAP3530 chip. USB camera deployed as images’ acquisition equipment, and used the ARM + DSP multi-core OMAP3530 processor as image decode-encode processing chip. The results sent to the user interface ultimately. System’s development was based on DVSDK. The result proved system fast than others.

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4

Liu, Lin, and Yuanyuan Yang. "Energy-aware routing in hybrid optical network-on-chip for future multi-processor system-on-chip." Journal of Parallel and Distributed Computing 73, no. 2 (February 2013): 189–97. http://dx.doi.org/10.1016/j.jpdc.2012.09.018.

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5

Lafi, Walid, Didier Lattard, and Ahmed Jerrya. "An asynchronous hierarchical router for networks-on-chip-based three-dimensional multi-processor system-on-chip." Software: Practice and Experience 42, no. 7 (February 7, 2012): 877–90. http://dx.doi.org/10.1002/spe.1150.

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6

AMAMIYA, MAKOTO, HIDEO TANIGUCHI, and TAKANORI MATSUZAKI. "AN ARCHITECTURE OF FUSING COMMUNICATION AND EXECUTION FOR GLOBAL DISTRIBUTED PROCESSING." Parallel Processing Letters 11, no. 01 (March 2001): 7–24. http://dx.doi.org/10.1142/s0129626401000397.

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We are pursuing the FUCE architecture project at Kyushu University. FUCE means FUsion of Communication and Execution. The main objective of our research is, as the name shows, to develop a new architecture that truly fuses communication and computation. The FUCE project develops a new on-chip-multi-processor and kernel software on it. We name the processor FUCE processor, and the kernel software as CEFOS (Communication and Execution Fusion OS). The FUCE processor is designed as a network node processor to perform mainly switching/transmitting of messages/transaction and handling its contents. FUCE processor architecture is designed as a multiprocessor-on-chip to support the fine-grain multi-threading. The kernel software CEFOS is also developed on the concept of multithreading. User and system processes are constructed as a set of threads, which are executed concurrently according to thread dependences.

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7

Li, Shuo, Gao Chao Xu, Yu Shuang Dong, and Feng Wu. "The Review of Cache Partitioning in Multi-Core Processor." Key Engineering Materials 439-440 (June 2010): 1223–29. http://dx.doi.org/10.4028/www.scientific.net/kem.439-440.1223.

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With the development of microelectronics technology, Chip Multi-Processor (CMP) or multi-core design has become a mainstream choice for major microprocessor vendors. But in a chip-multiprocessor with a shared cache structure , the competing accesses from different applications degrade the system performance , resulting in non-optimal performance and non-predicting executing time. Cache partitioning techniques can exclusively partition the shared cache among multiple competing applications. In this paper, we first introduce the problems caused by Cache pollution in multicore processor structure; then present the different methods of Cache partitioning in multicore processor structure¬ －－categorizing them based on the different metrics. And finally, we discuss some possible directions for future research in the area.

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8

SLIMANI, Hayet, Abderrazak JEMAIU, and Ahmed Chiheb AMMARI. "Multi-Processor System-on-Chip Power Estimation Model At the CABA Level." IFAC Proceedings Volumes 45, no. 7 (2012): 341–46. http://dx.doi.org/10.3182/20120523-3-cz-3015.00065.

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9

Tang, Lin, and Jin Zhao Wu. "The Status and Challenges of Multi-Processor System-on-Chip’s Formal Verification." Applied Mechanics and Materials 602-605 (August 2014): 2926–29. http://dx.doi.org/10.4028/www.scientific.net/amm.602-605.2926.

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With the continuous advancement of processor manufacturing process as well as the exposed limitations of single-core Processors, Multi-Processor System-on-Chip (MPSoC) has become the inevitable outcome of the technological development and practical application needs. It is used to meet the requirements of multitasking, multifunctional and high performance computing. With the improvement of chip complexity, verification module also increases exponentially. Verification of MPSoC is becoming Bottleneck in the process of chip’s design. So this paper first introduces the origin of MPSoC, and analyzes developing tendency of its verification. And then, the theory and main challenges to the formal verification of MPSoC are discussed. This paper will provide support for building the verified theory method and technology that can meet the demand of MPSoC design, and Developing MPSoC high-level architecture design verification technology.

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10

BAGHERZADEH, NADER, and MASARU MATSUURA. "PERFORMANCE IMPACT OF TASK-TO-TASK COMMUNICATION PROTOCOL IN NETWORK-ON-CHIP." Journal of Circuits, Systems and Computers 18, no. 02 (April 2009): 283–94. http://dx.doi.org/10.1142/s021812660900506x.

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Network-on-Chip (NoC) is a strong candidate for scalable interconnect design of Multi-Processor System-on-Chip (MPSoC). Software tasks of MPSoC require a certain protocol to communicate with each other. In NoC such a communication protocol should be handled at Network Interface and/or Processor Element level and it is expected that different protocols show their trade-offs. In consideration of the above, we employed two types of basic protocol and investigated their performance impact. The contribution of this work is to quantitatively evaluate effectiveness of using separate communication protocols depending on the task structure.

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11

Prasad Acharya, G., and M. Asha Rani. "FPGA Prototyping of Micro-Blaze soft-processor based Multi-core System on Chip." International Journal of Engineering & Technology 7, no. 2.16 (April 12, 2018): 57. http://dx.doi.org/10.14419/ijet.v7i2.16.11416.

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The increased demand for processor-level parallelism has many-folded the challenges for SoC designers to design, simulate and verify/validate today’s Multi-core System-On-Chip (SoC) due to the increased system complexity. There is also a need to reduce the design cycle time to produce a complex multi-core SOC system thereby the product can be brought into the market within an affordable time. The Computer-Aided Design (CAD) tools and Field Programmable Gate Arrays (FPGAs) provide a solution for rapidly prototyping and validating the system. This paper presents an implementation of multi-core SoC consisting of 6 Xilinx Micro-Blaze soft-core processors integrated to the Zynq Processing System (PS) using IP Integrator and these cores will be communicated through AXI bus. The functionality of the system is verified using Micro-Blaze system debugger. The hardware framework for the implemented system is implemented and verified on FPGA.

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12

Breaban, Gabriela, Martijn Koedam, Sander Stuijk, and Kees Goossens. "Time synchronization for an emulated CAN device on a Multi-Processor System on Chip." Microprocessors and Microsystems 52 (July 2017): 523–33. http://dx.doi.org/10.1016/j.micpro.2017.04.019.

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13

Milojevic, Dragomir, Luc Montperrus, and Diederik Verkest. "Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications." Journal of Signal Processing Systems 57, no. 2 (July 29, 2008): 139–53. http://dx.doi.org/10.1007/s11265-008-0251-1.

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14

Tang, Qi, Shang-Feng Wu, Jun-Wu Shi, and Ji-Bo Wei. "Optimization of Duplication-Based Schedules on Network-on-Chip Based Multi-Processor System-on-Chips." IEEE Transactions on Parallel and Distributed Systems 28, no. 3 (March 1, 2017): 826–37. http://dx.doi.org/10.1109/tpds.2016.2599166.

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15

Ganeshpure, Kunal, and Sandip Kundu. "Game theoretic approach for run‐time task scheduling on an multi‐processor system on chip." IET Circuits, Devices & Systems 7, no. 5 (September 2013): 243–52. http://dx.doi.org/10.1049/iet-cds.2013.0091.

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16

Lesecq, Suzanne, Diego Puschini, Edith Beigné, Pascal Vivet, and Yeter Akgul. "Low-Cost and Robust Control of a DFLL for Multi-Processor System-on-Chip." IFAC Proceedings Volumes 44, no. 1 (January 2011): 1940–45. http://dx.doi.org/10.3182/20110828-6-it-1002.01706.

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17

Khan, Haroon-Ur-Rashid, Feng Shi, WeiXing Ji, YuJin Gao, YiZhuo Wang, CaiXia Liu, Ning Deng, and JiaXin Li. "Computationally efficient locality-aware interconnection topology for multi-processor system-on-chip (MP-SoC)." Chinese Science Bulletin 55, no. 29 (October 2010): 3363–71. http://dx.doi.org/10.1007/s11434-010-4118-z.

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18

Deng, Yao Hua, Gui Xiong Liu, Wei Han, Zi Wei Fang, Li Ming Wu, and Qing Fu Liao. "Research on Multi-Core Collaborative Computing for FWP Image Processing Algorithm by FPGA." Advanced Materials Research 230-232 (May 2011): 1340–44. http://dx.doi.org/10.4028/www.scientific.net/amr.230-232.1340.

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On the basis of analysis of research on embedded soft hardware collaborative design method, image processing SOPC collaborative design principle is elaborated, relation between complicated algorithm time and soft hardware implementation and the implementation method to accelerate algorithm by multi-processor and multi-core is studied, thus the logical relationship between equipment IP core on the chip with Fast Simplex Link(FSL) bus and bus bridge, connecting conditions and application flow is organized. Finally, design SOPC, for which, multi-core and multi-processor collaborative work with the core of PowerPC 405 processor by taking flexible workpiece path (FWP) image as an example. The test manifests that the computation speed of SOPC designed in this passage is higher 10 times than that of common single-core SOPC in terms of image processing computing, effectively solving the problem of slow speed for computing image preprocessing by software in the embedded system.

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19

Salamy, Hassan. "Energy-Aware Schedules Under Chip Reliability Constraint for Multi-Processor Systems-on-a-Chip." Journal of Circuits, Systems and Computers 29, no. 09 (October 29, 2019): 2050135. http://dx.doi.org/10.1142/s0218126620501352.

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Even though multi-core systems are effective architectures to overcome the limitation of single-core systems, techniques to improve reliability, throughput and power consumption are highly needed. With the increasing complexity of multi-processor systems-on-a-chip (MPSoCs) to handle the ever increasing complexity of embedded computing applications, the reliability of such systems is now a big concern in the industry. Complex MPSoCs typically have multiple execution modes with different throughput and reliability performances. These complex embedded systems are also expected to perform under minimum power and energy consumptions. In this paper, we present efficient techniques for low-energy and thermal-aware schedules that meet the deadlines under chip reliability constraints. The presented techniques under different objective functions are implemented and executed on multiple embedded applications under multiple underlying system architectures to show the performance and efficiency of the techniques.

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20

Salamy, Hassan, and Semih Aslan. "Pipelined-Scheduling of Multiple Embedded Applications on a Multi-Processor-SoC." Journal of Circuits, Systems and Computers 26, no. 03 (November 21, 2016): 1750042. http://dx.doi.org/10.1142/s0218126617500426.

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Due to clock and power constraints, it is hard to extract more power out of single core architectures. Thus, multi-core systems are now the architecture of choice to provide the needed computing power. In embedded system, multi-processor system-on-a-chip (MPSoC) is widely used to provide the needed power to effectively run complex embedded applications. However, to effectively utilize an MPSoC system, tools to generate optimized schedules is highly needed. In this paper, we design an integrated approach to task scheduling and memory partitioning of multiple applications utilizing the MPSoC system simultaneously. This is in contrast to the traditional decoupled approach that looks at task scheduling and memory partitioning as two separate problems. Our framework is also based on pipelined scheduling to increase the throughput of the system. Results on different benchmarks show the effectiveness of our techniques.

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21

Jia, Hao, Shanglin Yang, Ting Zhou, Sizhu Shao, Xin Fu, Lei Zhang, and Lin Yang. "WDM-compatible multimode optical switching system-on-chip." Nanophotonics 8, no. 5 (April 27, 2019): 889–98. http://dx.doi.org/10.1515/nanoph-2019-0005.

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AbstractThe development of optical interconnect techniques greatly expands the communication bandwidth and decreases the power consumption at the same time. It provides a prospective solution for both intra-chip and inter-chip links. Herein reported is an integrated wavelength-division multiplexing (WDM)-compatible multimode optical switching system-on-chip (SoC) for large-capacity optical switching among processors. The interfaces for the input and output of the processor signals are electrical, and the on-chip data transmission and switching process are optical. It includes silicon-based microring optical modulator arrays, mode multiplexers/de-multiplexers, optical switches, microring wavelength de-multiplexers and germanium-silicon high-speed photodetectors. By introducing external multi-wavelength laser sources, the SoC achieved the function of on-chip WDM and mode-division multiplexing (MDM) hybrid-signal data transmission and switching on a standard silicon photonics platform. As a proof of concept, signals with a 25 Gbps data rate are implemented on each microring modulator of the fabricated SoC. We illustrated 25 × 3 × 2 Gbps on-chip data throughput with two-by-two multimode switching functionality through implementing three wavelength-channels and two mode-channel hybrid-multiplexed signals for each multimode transmission waveguide. The architecture of the SoC is flexible to scale, both for the number of supported processors and the data throughput. The demonstration paves the way to a large-capacity multimode optical switching SoC.

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22

Han, Pei Cen, Zhao Hui Ye, Yong Ming Zhou, and Shi Yuan Yang. "SOPC-Based Motion Controller with NURBS Interpolator." Advanced Materials Research 898 (February 2014): 937–43. http://dx.doi.org/10.4028/www.scientific.net/amr.898.937.

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SOPC becomes popular nowadays, which combines software and hardware in a single chip. In this paper, a multi-axis motion controller is implemented based on a SOPC system with a NIOSII processor in a single FPGA chip. The motion controller includes DDA module, spindle module and NURBS calculation module realized in Verilog HDL. DDA algorithm is used to drive the motors while spindle module is to drive the spindle. Because of NURBS recursive nature, NURBS calculation module is used to accelerate the calculation which takes the advantage of parallel structure. The NIOSII processor realizes the feedrate scheduling, in which constant feedrate is adopted. The second-order interpolation algorithm is used to control the feedrate.

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23

Borejko, Tomasz, Krzysztof Marcinek, Krzysztof Siwiec, Paweł Narczyk, Adam Borkowski, Igor Butryn, Arkadiusz Łuczyk, et al. "NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor." Sensors 20, no. 4 (February 16, 2020): 1069. http://dx.doi.org/10.3390/s20041069.

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A dual-frequency all-in-one Global Navigation Satellite System (GNSS) receiver with a multi-core 32-bit RISC (reduced instruction set computing) application processor was integrated and manufactured as a System-on-Chip (SoC) in a 110 nm CMOS (complementary metal-oxide semiconductor) process. The GNSS RF (radio frequency) front-end with baseband navigation engine is able to receive, simultaneously, Galileo (European Global Satellite Navigation System) E1/E5ab, GPS (US Global Positioning System) L1/L1C/L5, BeiDou (Chinese Navigation Satellite System) B1/B2, GLONASS (GLObal NAvigation Satellite System of Russian Government) L1/L3/L5, QZSS (Quasi-Zenith Satellite System development by the Japanese government) L1/L5 and IRNSS (Indian Regional Navigation Satellite System) L5, as well as all SBAS (Satellite Based Augmentation System) signals. The ability of the GNSS to detect such a broad range of signals allows for high-accuracy positioning. The whole SoC (system-on-chip), which is connected to a small passive antenna, provides precise position, velocity and time or raw GNSS data for hybridization with the IMU (inertial measurement unit) without the need for an external application processor. Additionally, user application can be executed directly in the SoC. It works in the −40 to +105 °C temperature range with a 1.5 V supply. The assembled test-chip takes 100 pins in a QFN (quad-flat no-leads) package and needs only a quartz crystal for the on-chip reference clock driver and optional SAW (surface acoustic wave) filters. The radio performance for both wideband (52 MHz) channels centered at L1/E1 and L5/E5 is NF = 2.3 dB, G = 131 dB, with 121 dBc/Hz of phase noise @ 1 MHz offset from the carrier, consumes 35 mW and occupies a 4.5 mm2 silicon area. The SoC reported in the paper is the first ever dual-frequency single-chip GNSS receiver equipped with a multi-core application microcontroller integrated with embedded flash memory for the user application program.

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24

Mhaidat, Khaldoon Moosa, Ahmad Baset, and Osama Al-Khaleel. "OpenSPARC Processor Evaluation Using Virtex-5 FPGA and High Performance Embedded Computing (HPEC) Benchmark Suite." International Journal of Embedded and Real-Time Communication Systems 5, no. 1 (January 2014): 61–74. http://dx.doi.org/10.4018/ijertcs.2014010104.

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OpenSPARC is the only 64-bit Chip Multi-Threaded (CMT) processor that has ever been made open-source and non-proprietary. In this paper, the authors present an FPGA-based embedded system and methodology for prototyping and validating the OpenSPARC processor. They also present synthesis and performance evaluation results for OpenSPARC on a Virtex-5 FPGA platform. Light version of OpenSolaris was successfully booted on the platform, and the High Performance Embedded Computing (HPEC) benchmark suite was used to evaluate the performance. Xilinx ISE suite was used for synthesis, implementation, and chip programming. The down-scaled FPGA implementation of the processor runs at 81.3 MHz. The whole processor would require about 176453 Virtex-5 logic slices. To the best of their knowledge, they are the first researchers to report detailed FPGA synthesis results for OpenSPARC and evaluate its performance on FPGA using the HPEC benchmarks. Other researchers may find these results useful when comparing with other processors or studying the impact of a certain design change or addition on performance and cost.

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25

Zuo, Qi. "Task Assignment for Multiple-Application Workload with Streaming Ones in MPSoC Using Shared Memory." Applied Mechanics and Materials 263-266 (December 2012): 1781–85. http://dx.doi.org/10.4028/www.scientific.net/amm.263-266.1781.

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Large scale Multi-Processor System-on-a-chip (MPSoC) based on Network on Chip (NoC) can support multiple applications running simultaneously. When the multiple-application workload includes streaming applications processing massive data, the communication concentrated on shared memory can't be ignored. In this paper, we propose a task assignment strategy for multiple-application workload which includes one streaming application on a NoC-based MPSoC. The proposed algorithm first assigns the streaming application centering the multi-port shared memory, and then assigns the other applications minimizing external communication congestion. By adopting the proposed algorithm, the memory-contention tasks are assigned to the PEs close to the shared memory and the overall congestion is minimized. This allows the system to provide better overall performance.

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26

Pelissier, Frantz, Hanen Chenini, François Berry, Alexis Landrault, and Jean-Pierre Derutin. "Embedded multi-processor system-on-programmable chip for smart camera pose estimation using nonlinear optimization methods." Journal of Real-Time Image Processing 12, no. 4 (September 30, 2014): 663–79. http://dx.doi.org/10.1007/s11554-014-0454-6.

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27

Abbes, Hanen, Hafedh Abid, Kais Loukil, Mohamed Abid, and Ahmad Toumi. "Fuzzy-based MPPT algorithm implementation on FPGA chip for multi-channel photovoltaic system." International Journal of Reconfigurable and Embedded Systems (IJRES) 11, no. 1 (March 1, 2022): 49. http://dx.doi.org/10.11591/ijres.v11.i1.pp49-58.

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<span lang="EN-US">Microprocessors and microcontrollers are mostly used to control electrical systems. These chips front into problems while monitoring systems that need heavy computing and important processing. Likewise, they fail while handling inputs and outputs speeds, especially with multi-channel photovoltaic (PV) systems. In comparison to a digital signal processor (DSP) and microcontroller implementations, field programmable gate array (FPGA) device is able to integrate a great number of PV channels and to achieve short development time, cost less and more flexible operation. As well, new control algorithms are increasingly complex; using new performing technologies is very motivating. Mainly, FPGA technology is adopted thanks to its ability to control complex applications and intelligent laws. In opposition to traditional controls, fuzzy logic based control presents more efficiency and reliability response for non-linear systems. Therefore, this paper deals with the execution of the fuzzy-based maximum power point tracking (MPPT) technique by the means of the FPGA chip for a multi-channel photovoltaic system. A multi-channel photovoltaic system is designed. Then, the FPGA circuit is investigated to get benefits from this hardware solution. Since software implementation way integrates a limited number of PV panels, hardware implementation is a promising solution that reduces execution time and therefore controls a huge number of photovoltaic channels. Finally, results of simulation of the fuzzy technique implementation on FPGA chip show that the proposed PV system controls more than 4400 channels. Therefore, the system output power is increased and the system profitability is improved.</span>

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28

Liu, Jian Qun, Dong Xu, Ji Rong Wu, Xiao Li, and Jian Huang. "The Design of Carton Samplemaker’s Embedded Numerical Control System Based on Windows CE." Advanced Materials Research 211-212 (February 2011): 330–35. http://dx.doi.org/10.4028/www.scientific.net/amr.211-212.330.

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In this paper, a new embedded numerical control (ENC) system for carton samplemaker based on Windows CE is presented. The hardware design of ENC system based on ARM9 processor S3C2440A and motion control chip MCX314As is discussed principally. Besides, the device driver of MCX314As is developed by using stream interface driver model under Windows CE operating system. Furthermore, the software structure of the ENC system is introduced, and the way how to utilize multi-thread technology to realize the real-time control of the carton samplemaker is also discussed in detail. The system is proved to be good at dealing with multiple tasks processing, real-time and reliability of motion control.

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29

Singh, Akhilesh K., Kevin M. Sullivan, George R. Leal, and Tony Gong. "Assembly challenges with Flip Chip multi-die and interposer-based SiP Modules." International Symposium on Microelectronics 2019, no. 1 (October 1, 2019): 000001–5. http://dx.doi.org/10.4071/2380-4505-2019.1.000001.

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Abstract System in Package (SiP) modules provide integrated functionalities (processor, memory, power, etc.) in a small form factor as compared to PCB based individually laid out packages and passives. SiP modules face assembly related challenges as the complexity of packages increases (multi die, large number of passives, through mold via interposer for external memory, convergence of different technologies). This paper describes assembly challenges associated with a multi-die flip chip (processor, memory and power) module with plastic interposer for external Package-on-Package (PoP) memory. The prototype test package with three flip chip die was processed using different bump structures with bump height variation and differences in coplanarity. The underfill dispense pattern was optimized to eliminate underfill creep to the top of passive components that could lead to interfacial delamination. The interposer solder had no reliability risk due to the added mechanical strength of the underfill. Laser ablation formed through mold vias (TMV) on top of the interposers to connect to a package on package memory device. Partially defined TMV opening profile, adjacent solder bridging, formation of cold joint due to poor coplanarity, and foreign material contamination concerns were mitigated by tightening design and process parameters for flip chip attach (bump shorting and cold joint), underfill (interposer tilt, voids, material creep, dispense pattern, volume), interposer (tilt, warpage, solder voids), TMV laser ablation process (exposed Cu, depth, width), and mounting of passives components (topography, misalignment, cap solder volume).

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30

Wang, Shiyu, Shengbing Zhang, Xiaoping Huang, and Libo Chang. "Single-chip multi-processing architecture for spaceborne SAR imaging and intelligent processing." Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University 39, no. 3 (June 2021): 510–20. http://dx.doi.org/10.1051/jnwpu/20213930510.

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The satellite-borne SAR image intelligent processing system needs to process on-orbit real-time imaging and various tasks of applications, for which reason designing a dedicated high-efficient single-chip multi-processor is of prioritized necessity that can simultaneously satisfy requirements of real-time and low power consumption. Aiming at on-chip data organization and memory access structure, two typical models of SAR(synthetic aperture radar) imaging CSA (chirp scaling) and neural network VGG-11 are analyzed, and then a collaborative computing model for the intelligent processing on remote sensing is extracted. A strip Tile data processing scheme and a dedicated multi-processing architecture is not only proposed, but a data organization and a caching strategy of Tile space synchronization splicing is also presented. In addition, the designed data caching structure among the processing units greatly reduces off-chip access memory bandwidth while supporting parallel pipeline execution of multi-task model. The chip adopts 28 nm CMOS technology featuring with merely 1.83 W of the overall power consumption, whose throughput and energy efficiency reaches 9.89TOPS and 5.4 TOPS/W, respectively. The present architecture can improve real-time performance of the on-orbit remote sensing intelligent processing platform while reducing the complexity of system designing, which is highly adaptive to differentiated expansions according to different models of algorithm.

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31

Shahid, Arsalan, Muhammad Yasir Qadri, Martin Fleury, Hira Waris, Ayaz Ahmad, and Nadia N. Qadri. "AC-DSE: Approximate Computing for the Design Space Exploration of Reconfigurable MPSoCs." Journal of Circuits, Systems and Computers 27, no. 09 (April 26, 2018): 1850145. http://dx.doi.org/10.1142/s0218126618501451.

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This paper concerns the design space exploration (DSE) of Reconfigurable Multi- Processor System-on- Chip (MPSoC) architectures. Reconfiguration allows users to allocate optimum system resources for a specific application in such a way to improve the energy and throughput balance. To achieve the best balance between power consumption and throughput performance for a particular application domain, typical design space parameters for a multi-processor architecture comprise the cache size, the number of processor cores and the operating frequency. The exploration of the design space has always been an offline technique, consuming a large amount of time. Hence, the exploration has been unsuitable for reconfigurable architectures, which require an early runtime decision. This paper presents Approximate Computing DSE (AC-DSE), an online technique for the DSE of MPSoCs by means of approximate computing. In AC-DSE, design space solutions are first obtained from a set of optimization algorithms, which in turn are used to train a neural network (NN). From then on, the NN can be used to rapidly return its own solutions in the form of design space parameters for a desired energy and throughput performance, without any further training.

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32

BAHN, JUN HO, SEUNG EUN LEE, YOON SEOK YANG, JUNGSOOK YANG, and NADER BAGHERZADEH. "ON DESIGN AND APPLICATION MAPPING OF A NETWORK-ON-CHIP(NOC) ARCHITECTURE." Parallel Processing Letters 18, no. 02 (June 2008): 239–55. http://dx.doi.org/10.1142/s0129626408003363.

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As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either traditional or multi-layer bus architectures because of their poor scalability and bandwidth limitation on a single bus. While new interconnection techniques have been explored to overcome such a limitation, the notion of utilizing Network-on-Chip (NoC) technologies for the future generation of high performance and low power chips for myriad of applications, in particular for wireless communication and multimedia processing, has been of great importance. In order for the NoC technologies to succeed, realistic specifications such as throughput, latency, moderate design complexity, programming model, and design tools are necessary requirements. For this purpose, we have covered some of the key and challenging design issues specific to the NoC architecture such as the router design, network interface (NI) issues, and complete system-level modeling. In this paper, we propose a multi-processor system platform adopting NoC techniques, called NePA (Network-based Processor Array). As a component of system platform, the fundamental NoC techniques including the router architecture and generic NI are defined and implemented adopting low power and clock efficient techniques. Using a high-level cycle-accurate simulation, various parameters relevant to its performance and its systematic modeling are extracted and analyzed. By combining various developed systematic models, we construct the tool chain to pursue hardware/software design tradeoffs necessary for better understanding of the NoC techniques. Finally utilizing implementation of parallel FFT algorithms on the homogeneous NePA, the feasibility and advantages of using NoC techniques are shown.

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Wen, Wu, De Hua He, Hua Feng, and Peng Gu. "The Design of a New Network Cabling Experimental Instrument Based on Embedded System." Advanced Materials Research 328-330 (September 2011): 2427–31. http://dx.doi.org/10.4028/www.scientific.net/amr.328-330.2427.

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Structured Cabling is not a demonstrative course, but a course to stimulate students’ learning interest and to improve experiment’s efficiency. Unfortunately there are some disadvantages for experimental instruments on the present market, such as low testing speed, low automation level and less functions, etc. A multi-processor structure is proposed in this paper, which consists of a 32-bit ARM processor S3C2440 and a 8-bit Single Chip Microcomputer STC89LE54. This structure is used to develop a new network cabling experimental instrument, which is based on embedded system. The instrument can achieve precise processing, such as synchronous data acquisition for wire cores of 32 standard network lines according to EIA/TIA568A Standard or EIA/TIA568B Standard, display and data storage, etc. The instrument has characteristics of high efficiency, fast response, automatic identification, and ease of use. It is used to implement consistency between teaching and job training. Therefore it has high practical value.

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Garzia, Fabio, Roberto Airoldi, and Jari Nurmi. "Implementation of FFT on General-Purpose Architectures for FPGA." International Journal of Embedded and Real-Time Communication Systems 1, no. 3 (July 2010): 24–43. http://dx.doi.org/10.4018/jertcs.2010070102.

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This paper describes two general-purpose architectures targeted to Field Programmable Gate Array (FPGA) implementation. The first architecture is based on the coupling of a coarse-grain reconfigurable array with a general-purpose processor core. The second architecture is a homogeneous multi-processor system-on-chip (MP-SoC). Both architectures have been mapped onto two different Altera FPGA devices, a StratixII and a StratixIV. Although mapping onto the StratixIV results in higher operating frequencies, the capabilities of the device are not fully exploited. The implementation of a FFT on the two platforms shows a considerable speed-up in comparison with a single-processor reference architecture. The speed-up is higher in the reconfigurable solution but the MP-SoC provides an easier programming interface that is completely based on C language. The authors’ approach proves that implementing a programmable architecture on FPGA and then programming it using a high-level software language is a viable alternative to designing a dedicated hardware block with a hardware description language (HDL) and mapping it on FPGA.

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35

Zhang, Diandian, Li Lu, Jeronimo Castrillon, Torsten Kempf, Gerd Ascheid, Rainer Leupers, and Bart Vanthournout. "Efficient Implementation of Application-Aware Spinlock Control in MPSoCs." International Journal of Embedded and Real-Time Communication Systems 4, no. 1 (January 2013): 64–84. http://dx.doi.org/10.4018/jertcs.2013010104.

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Spinlocks are a common technique in Multi-Processor Systems-on-Chip (MPSoCs) to protect shared resources and prevent data corruption. Without a priori application knowledge, the control of spinlocks is often highly random which can degrade the system performance significantly. To improve this, a centralized control mechanism for spinlocks is proposed in this paper, which utilizes application-specific information during spinlock control. The complete control flow is presented, which starts from integrating high-level user-defined information down to a low-level realization of the control. An Application-Specific Instruction-set Processor (ASIP) called OSIP, which was originally designed for task scheduling and mapping, is extended to support this mechanism. The case studies demonstrate the high efficiency of the proposed approach and at the same time highlight the efficiency and flexibility advantages of using an ASIP as the system controller in MPSoCs.

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Muscheid, T., A. Boebel, N. Karcher, T. Vanat, L. Ardila-Perez, I. Cheviakov, M. Schleicher, M. Zimmer, M. Balzer, and O. Sander. "DTS-100G — a versatile heterogeneous MPSoC board for cryogenic sensor readout." Journal of Instrumentation 18, no. 02 (February 1, 2023): C02067. http://dx.doi.org/10.1088/1748-0221/18/02/c02067.

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Abstract Heterogeneous devices such as the Multi-Processor System-on-Chip (MPSoC) from Xilinx are extremely valuable in custom instrumentation systems. This contribution presents the joint development of a heterogeneous MPSoC board called DTS-100G by DESY and KIT. The board is built around a Xilinx Zynq Ultrascale+ chip offering all available high-speed transceivers using QSFP28, 28 Gbps FireFly, FMC, and FMC+ interfaces. The board is not designed for a particular application, but can be used as a generic DAQ platform for a variety of physics experiments. The DTS-100G board was successfully developed, built and commissioned. ECHo-100k is the first experiment which will employ the board. This contribution shows the system architecture and explains how the DTS-100G board is a crucial component in the DAQ chain.

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37

Zhang, Diandian, Han Zhang, Jeronimo Castrillon, Torsten Kempf, Bart Vanthournout, Gerd Ascheid, and Rainer Leupers. "Optimized Communication Architecture of MPSoCs with a Hardware Scheduler." International Journal of Embedded and Real-Time Communication Systems 2, no. 3 (July 2011): 1–20. http://dx.doi.org/10.4018/jertcs.2011070101.

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Efficient runtime resource management in multi-processor systems-on-chip (MPSoCs) for achieving high performance and low energy consumption is one of the key challenges for system designers. OSIP, an operating system application-specific instruction-set processor, together with its well-defined programming model, provides a promising solution. It delivers high computational performance to deal with dynamic task scheduling and mapping. Being programmable, it can easily be adapted to different systems. However, the distributed computation among the different processing elements introduces complexity to the communication architecture, which tends to become the bottleneck of such systems. In this work, the authors highlight the vital importance of the communication architecture for OSIP-based systems and optimize the communication architecture. Furthermore, the effects of OSIP and the communication architecture are investigated jointly from the system point of view, based on a broad case study for a real life application (H.264) and a synthetic benchmark application.

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Zhou, Xinbing, Peng Hao, and Dake Liu. "PCCNoC: Packet Connected Circuit as Network on Chip for High Throughput and Low Latency SoCs." Micromachines 14, no. 3 (February 21, 2023): 501. http://dx.doi.org/10.3390/mi14030501.

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Hundreds of processor cores or modules are integrated into a single chip. The traditional bus or crossbar is challenged by bandwidth, scalability, and silicon area, and cannot meet the requirements of high end applications. Network-on-chip (NoC) has become a very promising interconnection structure because of its good scalability, predictable interconnect length and delay, high bandwidth, and reusability. However, the most available packet routing NoC may not be the perfect solution for high-end heterogeneous multi-core real-time systems-on-chip (SoC) because of the excessive latency and cache cost overhead. Moreover, circuit switching is limited by the scale, connectivity flexibility, and excessive overhead of fully connected systems. To solve the above problems and to meet the need for low latency, high throughput, and flexibility, this paper proposes PCCNoC (Packet Connected Circuit NoC), a low-latency and low-overhead NoC based on both packet switching (setting-up circuit) and circuit switching (data transmission on circuit), which offers flexible routing and zero overhead of data transmission latency, making it suitable for high-end heterogeneous multi-core real-time SoC at various system scales. Compared with typically available packet switched NoC, our PCCoC sees 242% improved performance and 97% latency reduction while keeping the silicon cost relatively low.

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Bellemou, A., N. Benblidia, M. Anane, and M. Issad. "MicroBlaze-Based Multiprocessor Embedded Cryptosystem on FPGA for Elliptic Curve Scalar Multiplication Over Fp." Journal of Circuits, Systems and Computers 28, no. 03 (February 24, 2019): 1950037. http://dx.doi.org/10.1142/s0218126619500373.

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In this paper, we present Microblaze-based parallel architectures of Elliptic Curve Scalar Multiplication (ECSM) computation for embedded Elliptic Curve Cryptosystem (ECC) on Xilinx FPGA. The proposed implementations support arbitrary Elliptic Curve (EC) forms defined over large prime field ([Formula: see text]) with different security-level sizes. ECSM is performed using Montgomery Power Ladder (MPL) algorithm in Chudnovsky projective coordinates system. At the low abstraction level, Montgomery Modular Multiplication (MMM) is considered as the critical operation. It is implemented within a hardware Accelerator MMM (AccMMM) core based on the modified high radix, [Formula: see text] MMM algorithm. The efficiency of our parallel implementations is achieved by the combination of the mixed SW/HW approach with Multi Processor System on Programmable Chip (MPSoPC) design. The integration of multi MicroBlaze processor in single architecture allows not only the flexibility of the overall system but also the exploitation of the parallelism in ECSM computation with several degrees. The Virtex-5 parallel implementations of 256-bit and 521-bis ECSM computations run at 100[Formula: see text]MHZ frequency and consume between 2,739 and 6,533 slices, 22 and 72 RAMs and between 16 and 48 DSP48E cores. For the considered security-level sizes, the delays to perform single ECSM are between 115[Formula: see text]ms and 14.72[Formula: see text]ms.

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Ganiee, Sajad Ahmad, Shabeer Ahmad Ganiee, and Jehangir Rashid Dar. "FPGA Design of 8 bit 4×4 Crossbar Switch for Multi Processor System on Chip Using Round Robin Arbitration Algorithm." International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering 04, no. 01 (January 20, 2015): 109–19. http://dx.doi.org/10.15662/ijareeie.2015.0401010.

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41

Mehner, T., L. E. Ardila-Perez, M. N. Balzer, O. Sander, D. Tcherniakhovski, M. Schleicher, M. Fuchs, et al. "ZynqMP-based board-management mezzanines for Serenity ATCA-blades." Journal of Instrumentation 17, no. 03 (March 1, 2022): C03009. http://dx.doi.org/10.1088/1748-0221/17/03/c03009.

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Abstract In the context of the CMS Phase-2 tracker back-end processing system, two mezzanines based on the Zynq Ultrascale+ Multi-Processor System-on-Chip (MPSoC) device have been developed to serve as centralized slow control and board management solution for the Serenity-family Advanced Telecommunications Computing Architecture (ATCA) blades. This paper presents the developments of the MPSoC mezzanines to execute the Intelligent Platform Management Controller (IPMC) software in the real-time capable processors of the MPSoC. In coordination with the Shelf Manager, once full-power is enabled, a CentOS-based Linux distribution is executed in the application processors of the MPSoC, on which EMPButler and the Serenity Management Shell (SMASH) are running.

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42

Bossuet, Lilian, and El Mehdi Benhani. "Performing Cache Timing Attacks from the Reconfigurable Part of a Heterogeneous SoC—An Experimental Study." Applied Sciences 11, no. 14 (July 20, 2021): 6662. http://dx.doi.org/10.3390/app11146662.

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Cache attacks are widespread on microprocessors and multi-processor system-on-chips but have not yet spread to heterogeneous systems-on-chip such as SoC-FPGA that are found in increasing numbers of applications on servers or in the cloud. This type of SoC has two parts: a processing system that includes hard components and ARM processor cores and a programmable logic part that includes logic gates to be used to implement custom designs. The two parts communicate via memory-mapped interfaces. One of these interfaces is the accelerator coherency port that provides optional cache coherency between the two parts. In this paper, we discuss the practicability and potential threat of inside-SoC cache attacks using the cache coherency mechanism of a complex heterogeneous SoC-FPGA. We provide proof of two cache timing attacks Flush+Reload and Evict+Time when SoC-FPGA is targeted, and proof of hidden communication using a cache-based covert channel. The heterogeneous SoC-FPGA Xilinx Zynq-7010 is used as an experimental target.

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Kumar, K. Suresh, S. Anitha, and M. Gayathri. "3D Stacked Cache Data Management for Energy Minimization of 3D Chip Multiprocessor." International Journal of Students' Research in Technology & Management 3, no. 2 (September 27, 2015): 264–68. http://dx.doi.org/10.18510/ijsrtm.2015.325.

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In this model a runtime cache data mapping is discussed for 3-D stacked L2 caches to minimize the overall energy of 3-D chip multiprocessors (CMPs). The suggested method considers both temperature distribution and memory traffic of 3-D CMPs. Experimental result shows energy reduction achieving up to 22.88% compared to an existing solution which considers only the temperature distribution. New tendencies envisage 3D Multi-Processor System-On-Chip (MPSoC) design as a promising solution to keep increasing the performance of the next-generation high performance computing (HPC) systems. However, as the power density of HPC systems increases with the arrival of 3D MPSoCs with energy reduction achieving up to 19.55% by supplying electrical power to the computing equipment and constantly removing the generated heat is rapidly becoming the dominant cost in any HPC facility.

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44

Dey, Somdip, Samuel Isuwa, Suman Saha, Amit Kumar Singh, and Klaus McDonald-Maier. "CPU-GPU-Memory DVFS for Power-Efficient MPSoC in Mobile Cyber Physical Systems." Future Internet 14, no. 3 (March 14, 2022): 91. http://dx.doi.org/10.3390/fi14030091.

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Most modern mobile cyber-physical systems such as smartphones come equipped with multi-processor systems-on-chip (MPSoCs) with variant computing capacity both to cater to performance requirements and reduce power consumption when executing an application. In this paper, we propose a novel approach to dynamic voltage and frequency scaling (DVFS) on CPU, GPU and RAM in a mobile MPSoC, which caters to the performance requirements of the executing application while consuming low power. We evaluate our methodology on a real hardware platform, Odroid XU4, and the experimental results prove the approach to be 26% more power-efficient and 21% more thermal-efficient compared to the state-of-the-art system.

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Leon, Vasileios, George Lentaris, Evangelos Petrongonas, Dimitrios Soudris, Gianluca Furano, Antonis Tavoularis, and David Moloney. "Improving Performance-Power-Programmability in Space Avionics with Edge Devices: VBN on Myriad2 SoC." ACM Transactions on Embedded Computing Systems 20, no. 3 (April 2021): 1–23. http://dx.doi.org/10.1145/3440885.

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The advent of powerful edge devices and AI algorithms has already revolutionized many terrestrial applications; however, for both technical and historical reasons, the space industry is still striving to adopt these key enabling technologies in new mission concepts. In this context, the current work evaluates an heterogeneous multi-core system-on-chip processor for use on-board future spacecraft to support novel, computationally demanding digital signal processors and AI functionalities. Given the importance of low power consumption in satellites, we consider the Intel Movidius Myriad2 system-on-chip and focus on SW development and performance aspects. We design a methodology and framework to accommodate efficient partitioning, mapping, parallelization, code optimization, and tuning of complex algorithms. Furthermore, we propose an avionics architecture combining this commercial off-the-shelf chip with a field programmable gate array device to facilitate, among others, interfacing with traditional space instruments via SpaceWire transcoding. We prototype our architecture in the lab targeting vision-based navigation tasks. We implement a representative computer vision pipeline to track the 6D pose of ENVISAT using megapixel images during hypothetical spacecraft proximity operations. Overall, we achieve 2.6 to 4.9 FPS with only 0.8 to 1.1 W on Myriad2 , i.e., 10-fold acceleration versus modern rad-hard processors. Based on the results, we assess various benefits of utilizing Myriad2 instead of conventional field programmable gate arrays and CPUs.

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46

Vandendriessche, Jurgen, Bruno da Silva, Lancelot Lhoest, An Braeken, and Abdellah Touhafi. "M3-AC: A Multi-Mode Multithread SoC FPGA Based Acoustic Camera." Electronics 10, no. 3 (January 29, 2021): 317. http://dx.doi.org/10.3390/electronics10030317.

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Acoustic cameras allow the visualization of sound sources using microphone arrays and beamforming techniques. The required computational power increases with the number of microphones in the array, the acoustic images resolution, and in particular, when targeting real-time. Such a constraint limits the use of acoustic cameras in many wireless sensor network applications (surveillance, industrial monitoring, etc.). In this paper, we propose a multi-mode System-on-Chip (SoC) Field-Programmable Gate Arrays (FPGA) architecture capable to satisfy the high computational demand while providing wireless communication for remote control and monitoring. This architecture produces real-time acoustic images of 240 × 180 resolution scalable to 640 × 480 by exploiting the multithreading capabilities of the hard-core processor. Furthermore, timing cost for different operational modes and for different resolutions are investigated to maintain a real time system under Wireless Sensor Networks constraints.

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47

EL-MOURSY, ALI A., and FADI N. SIBAI. "V-SET CACHE: AN EFFICIENT ADAPTIVE SHARED CACHE FOR MULTI-CORE PROCESSORS." Journal of Circuits, Systems and Computers 23, no. 07 (June 2, 2014): 1450095. http://dx.doi.org/10.1142/s0218126614500959.

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Development in VLSI design allows multi- to many-cores to be integrated on a single microprocessor chip. This increase in the core count per chip makes it more critical to design an efficient memory sub-system especially the shared last level cache (LLC). The efficient utilization of the LLC is a dominant factor to achieve the best microprocessor throughput. Conventional set-associative cache cannot cope with the new access pattern of the cache blocks in the multi-core processors. In this paper, the authors propose a new design for LLC in multi-core processor. The proposed v-set cache design allows an adaptive and dynamic utilization of the cache blocks. Unlike lately proposed design such as v-way caches, v-set cache design limits the serial access of cache blocks. In our paper, we thoroughly study the proposed design including area and power consumption as well as the performance and throughput. On eight-core microprocessor, the proposed v-set cache design can achieve a maximum speedup of 25% and 12% and an average speedup of 16% and 6% compared to conventional n-way and v-way cache designs, respectively. The area overhead of v-set does not exceed 7% compared to n-way cache.

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48

Ballan, Oscar, Pierre Maillard, Jue Arver, Christina Smith, Roland Petersson, Alexander Griessing, and Federico Venini. "Evaluation of ISO 26262 and IEC 61508 metrics for transient faults of a multi-processor system-on-chip through radiation testing." Microelectronics Reliability 107 (April 2020): 113601. http://dx.doi.org/10.1016/j.microrel.2020.113601.

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49

Ashkenazi, A., and D. Akselrod. "Platform independent overall security architecture in multi-processor system-on-chip integrated circuits for use in mobile phones and handheld devices." Computers & Electrical Engineering 33, no. 5-6 (September 2007): 407–24. http://dx.doi.org/10.1016/j.compeleceng.2007.05.003.

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50

Wang, Shiyu, Shengbing Zhang, Xiaoping Huang, and Hao Lyu. "On-chip data organization and access strategy for spaceborne SAR real-time imaging processor." Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University 39, no. 1 (February 2021): 126–34. http://dx.doi.org/10.1051/jnwpu/20213910126.

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Spaceborne SAR(synthetic aperture radar) imaging requires real-time processing of enormous amount of input data with limited power consumption. Designing advanced heterogeneous array processors is an effective way to meet the requirements of power constraints and real-time processing of application systems. To design an efficient SAR imaging processor, the on-chip data organization structure and access strategy are of critical importance. Taking the typical SAR imaging algorithm-chirp scaling algorithm-as the targeted algorithm, this paper analyzes the characteristics of each calculation stage engaged in the SAR imaging process, and extracts the data flow model of SAR imaging, and proposes a storage strategy of cross-region cross-placement and data sorting synchronization execution to ensure FFT/IFFT calculation pipelining parallel operation. The memory wall problem can be alleviated through on-chip multi-level data buffer structure, ensuring the sufficient data providing of the imaging calculation pipeline. Based on this memory organization and access strategy, the SAR imaging pipeline process that effectively supports FFT/IFFT and phase compensation operations is therefore optimized. The processor based on this storage strategy can realize the throughput of up to 115.2 GOPS, and the energy efficiency of up to 254 GOPS/W can be achieved by implementing 65 nm technology. Compared with conventional CPU+GPU acceleration solutions, the performance to power consumption ratio is increased by 63.4 times. The proposed architecture can not only improve the real-time performance, but also reduces the design complexity of the SAR imaging system, which facilitates excellent performance in tailoring and scalability, satisfying the practical needs of different SAR imaging platforms.

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