Дисертації з теми "Multi-Gate Transistors"
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Chaves, Romero Ferney Alveiro. "Study and Modeling of Multi‐ Gate Transistors in the Context of CMOS Technology Scaling." Doctoral thesis, Universitat Autònoma de Barcelona, 2012. http://hdl.handle.net/10803/96232.
Повний текст джерелаThe scaling of the conventional MOSFETs has led these devices to the nanoscale to increase both the performance and the number of components per chip. In this process, the so-called “Short Channel Effects” have arisen as a limiting factor. To extend the use of the bulk MOSFETs, the most effective ways of suppressing such effects are the reduction of the gate oxide thickness and increasing of the channel doping concentration. When the gate oxide thickness is reduced to a few atomic layers, quantum mechanical tunneling is responsible of a huge increase in the gate leakage current impairing the normal operation of MOSFETs. This has made mandatory the use of high permittivity materials or high-κ as gate dielectrics. Despite the proposed solutions, reduction of the physical dimensions of the conventional MOSFETs cannot be maintained. To keep the technological trend, new MOSFET structures have been suggested such as ultra-thin body Multi-Gate MOSFETs. In particular, the Double-Gate MOSFETs is considered as a promising MG structure for its several qualities and advantages in scaling. This thesis focuses on the modeling of Double-Gate MOSFET and, in particular, on the modeling of the gate leakage current critically affecting the power consumption. First we develop a compact quantum model for both the electrostatic potential and the electric charge in symmetric double-gate MOSFET with undoped thin body. Then, this quantum model is used to propose an analytical compact model for the direct tunnelling current with SiO2 as gate dielectric, firstly, and later assuming a dual layer consisting of a SiO2 interfacial layer and a high-κ material. Finally, an accurate method for the calculation of the gate tunnelling current is developed. It is based on Absorbing Boundary Conditions techniques and, more specifically, on the Perfectly Mached Layer (PML) method. This thesis is motivated by the recommendations given by the “International Technology Roadmap of Semiconductors” (ITRS) about the need for the modeling and simulation of multi-gate semiconductor structures.
Tocci, Gabriele. "Performance estimation and Variability from Random Dopant Fluctuations in Multi-Gate Field Effect Transistors : a Simulation Study." Thesis, KTH, Integrerade komponenter och kretsar, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-93419.
Повний текст джерелаGaben, Loic. "Fabrication et caractérisation de transistors MOS à base de nanofils de silicium empilés et à grille enrobante réalisés par approche Gate-Last pour les noeuds technologiques sub-7 nm." Thesis, Université Grenoble Alpes (ComUE), 2017. http://www.theses.fr/2017GREAT095/document.
Повний текст джерелаThe future of the transistors currently used in Microelectronics is still uncertain: shrinking these devices while increasing their performances always remains a challenge. In this thesis, stacked nanowire transistors are studied, fabricated and optimized. This architecture embeds gate all around which is the ultimate solution for concentrating always more current within a smaller device. Simulations have shown that silicon nanosheets provide an optimal utilization of the space with providing increased performances over the other technologies. Crucial process steps have also been identified. Subsequently, two process flows have been suggested for the fabrication of SNWFETs. The first approach consists in minimizing the number of variations from processes already in mass production. The second alternative has potentially better performances but its development is more challenging. Finally, the fabricated transistors have shown improved performances over state-of-the-art especially due to mechanical stress induced for improving electric transport
Francisco, sousa alves Luciano. "Series-connected SiC-MOSFETs : A Novel Multi-Step Packaging Concept and New Gate Drive Power Supply Configurations." Thesis, Université Grenoble Alpes, 2020. http://www.theses.fr/2020GRALT050.
Повний текст джерелаThis work investigates new gate drive power supply configurations and a novel multi-steppackaging concept in order to improve the performance of series-connected SiC-MOSFETs. The new gate drive configurations are proposed in order to reduce noise currents that circulate in the control part of the electrical system. Furthermore, a new gate drive power supply is proposed to increase the dv/dt of the switching cell. These improvements, i.e., noise current reduction and dv/dt boosting, are achieved by modifying the impedance of the gate drive circuitry. The novel multi-step packaging concept is proposed in order to improve the voltage sharing performance. The proposed package geometry considers optimal dielectric isolation for each device leading to a multi-step geometry. It has a significant impact on the parasitic capacitances introduced by the packaging structure that are responsible for voltageunbalances. The new gate driver configurations and the proposed multi-step packaging concepts are introduced and analysed thanks to equivalent models and time domain simulations. Then, experimental set-ups are performed to confirm that the proposed concepts are better than traditional ones in terms of voltage balancing, switching speed and conducted EMI reduction
Zbierska, Inga Jolanta. "Study of electrical characteristics of tri-gate NMOS transistor in bulk technology." Thesis, Lyon 1, 2014. http://www.theses.fr/2014LYO10282/document.
Повний текст джерелаOne of the recent solutions to overcome the scaling limit issue are multi-gate structures. One cost-effective approach is a three-independent-gate NMOSFET fabricated in a standard bulk CMOS process. Apart from their shape, which takes advantage of the three-dimensional space, multi gate transistors are similar to the conventional one. A multi-gate NMOSFET in bulk CMOS process can be fabricated by integration of polysilicon-filled trenches. This trenches are variety of the applications for instance in DRAM memories, power electronics and in image sensors. The image sensors suffer from the parasitic charges between the pixels, called crosstalk. The polysilicon - filled trenches are one of the solution to reduce this phenomenon. These trenches ensure the electrical insulation on the whole matrix pixels. We have investigated its characteristics using l-V measurements, C-V split method and both two- and three-level charge pumping techniques. Tts tunable-threshold and multi-threshold features were verified. Tts surface- channel low-field electron mobility and the Si/SiO2 interface traps were also evaluated. We observed no significant degradation of these characteristics due to integration of polysilicon-filled trenches in the CMOS process. The structure has been simulated by using 3D TCAD tool. Tts electrical characteristics has been evaluated and compared with results obtained from electrical measurements. The threshold voltage and the effective channel length were extracted. Tts surface-channel low-field electron mobility and the Si/SiO2 interface traps were also evaluated. Owing to the good electrical performances and cost-effective production, we noticed that this device is a good aspirant for analog applications thanks to the multi-threshold voltages
ANTIDORMI, ALEANDRO. "Modelling and Simulation of Silicon Nanowire-Based Electron Devices for Computation and Sensing." Doctoral thesis, Politecnico di Torino, 2016. http://hdl.handle.net/11583/2643159.
Повний текст джерелаBaldauf, Tim. "Integration von Multi-Gate-Transistoren auf Basis einer 22 nm-Technologie." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2014. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-132044.
Повний текст джерелаWithin the past 40 years the continuous scaling of planar MOSFETs was key to shrink the devices and to improve their performance. Techniques like mechanical stressing, rapid thermal annealing and in-situ doped epitaxial growing as well as novel materials, such as high-k-gate-oxide in combination with titanium nitride as metal-gate, has been introduced. However, short-channel-effects and increased scattering of electrical proper-ties significantly complicate the scaling of planar transistors. Thus, the planar MOSFETs gradually reached their limits of functionality with the current 28 nm technology node. For that reason, this work focuses on integration of multi-gate transistors based on a 22 nm technology, which show an improved gate control and allow a continuous scaling. Furthermore, the requirements of a stable and cost-efficient process as decisive condition for mass fabrication were always taken into account. The simulations of the tri-gate transistors present the first step toward a multi-gate technology. The process sequence differs from the planar one solely by a fin formation and offers the possibility of a hybrid 22 nm process. Also, the impact of crystal orientation, mechanical stress and superposition of electrical fields on the efficiency of multi-gate structures were analyzed for the tri-gate transistors. In a second step transistors with fully depleted channel regions were studied. Due to low channel doping they are showing a volume inversion, a higher carrier mobility and a lower sensitivity to random doping fluctuations, which are essential criteria for powerful multi-gate transistors. Reviewed structure variants include planar ultra-thin-body-SOI-MOSFETs, classic FinFETs with a tall, narrow fins and vertical nanowire transistors. Then advantages and disadvantages of the considered transistor structures have been observed for a medium to long term industrial use. For this purpose, an analysis of statistical fluctuations and the scaling-down to 14 nm technology was carried out. A summary of all results and an outlook to the transfer of concepts into mass fabrication complete this work
Weisz, Mario. "Electrothermal device-to-circuit interactions for half THz SiGe∶C HBT technologies." Thesis, Bordeaux 1, 2013. http://www.theses.fr/2013BOR14909/document.
Повний текст джерелаThe power generate by modern silicon germanium (SiGe) heterojunction bipolar transistors (HBTs) can produce large thermal gradients across the silicon substrate. The device opering temperature modifies model parameters and can significantly affect circuit operation. This work characterizes and models self-heating and thermal coupling in SiGe HBTs. The self-heating effect is evaluated with low frequency and pulsed measurements. A novel pulse measurement system is presented that allows isothermal DC and RF measurements with 100ns pulses. Electrothermal intra- and inter-device feedback is extensively studied and the impact on the performance of two analog circuits is evaluated. Novel test structures are designed and fabricated to measure thermal coupling between single transistors (inter-device) as well as between the emitter stripes of a multi-finger transistor (intra-device). Thermal coupling factors are extracted from measurements and from 3D thermal simulations. Thermally coupled simulations of a ring oscillator (RO) with 218 transistors and of a 60GHz power amplifier (PA) are carried out. Current mode logic (CML) ROs are designed and measured. Layout optimizations lead to record gate delay of 1.65ps. The thermal performance of a 60GHz power amplifier is compared when realized with a multi-transistor array (MTA) and with a multi-finger trasistor (MFT). Finally, perspectives of this work within a CAD based circuit design environment are discussed
Baldauf, Tim [Verfasser], Gerald [Akademischer Betreuer] Gerlach, and Roland [Akademischer Betreuer] Stenzel. "Integration von Multi-Gate-Transistoren auf Basis einer 22 nm-Technologie / Tim Baldauf. Gutachter: Gerald Gerlach ; Roland Stenzel. Betreuer: Gerald Gerlach ; Roland Stenzel." Dresden : Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2014. http://d-nb.info/1068444916/34.
Повний текст джерелаWilson, Veas Alan Hjalmar [Verfasser], Steffen [Gutachter] Bernet, Mariusz [Gutachter] Malinowski, and Steffen [Akademischer Betreuer] Bernet. "Investigation of Multi-Level Neutral Point Clamped Voltage Source Converters using Isolated Gate Bipolar Transistor Modules / Alan Hjalmar Wilson Veas ; Gutachter: Steffen Bernet, Mariusz Malinowski ; Betreuer: Steffen Bernet." Dresden : Technische Universität Dresden, 2019. http://d-nb.info/1226899463/34.
Повний текст джерелаRamadout, Benoit. "Capteurs d’images CMOS à haute résolution à Tranchées Profondes Capacitives." Thesis, Lyon 1, 2010. http://www.theses.fr/2010LYO10068.
Повний текст джерелаCMOS image sensors showed in the last few years a dramatic reduction of pixel pitch. However pitch shrinking is increasingly facing crosstalk and reduction of pixel signal, and new architectures are now needed to overcome those limitations. Our pixel with Capacitive Deep Trench Isolation and Vertical Transfer Gate (CDTI+VTG) has been developed in this context. Innovative integration of polysilicon-filled deep trenches allows high-quality pixel isolation, vertically extended photodiode and deep vertical transfer ability. First, specific process steps have been developed. In parallel, a thorough study of pixel MOS transistors has been carried out. We showed that capacitive trenches can be also operated as extra lateral gates, which opens promising applications for a multi-gate transistor compatible with CMOS-bulk technology. Finally, a 3MPixel demonstrator integrating 1.75*1.75 μm² pixels has been realized in a CMOS 120 nm technology. Pixel performances could be measured and exploited. In particular, a low dark current level could be obtained thanks to electrostatic effect of capacitive isolation trenches
"Compact Modeling of Multi-Gate Transistors." Doctoral diss., 2012. http://hdl.handle.net/2286/R.I.15862.
Повний текст джерелаDissertation/Thesis
Ph.D. Electrical Engineering 2012
Kumar, P. Rakesh. "Analytical Modeling Of Quantum Thershold Voltage For Short Channel Multi Gate Silicon Nanowire Transistors." Thesis, 2009. http://hdl.handle.net/2005/969.
Повний текст джерелаRay, Biswajit. "Impact Of Body Center Potential On The Electrostatics Of Undoped Body Multi Gate Transistors : A Modeling Perspective." Thesis, 2008. http://hdl.handle.net/2005/741.
Повний текст джерелаShao, Chi Shen, and 邵繼聖. "Study of Novel Nano-Scale Multi-Gate Junctionless Field Effect Transistors." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/4acdu6.
Повний текст джерела國立交通大學
電子工程學系 電子研究所
103
In this thesis, we presented electrical characteristics of trapezoidal shaped channel for the junctionless (JL) bulk and silicon-on-insulator (SOI) FinFET are numerically explored by using 3D quantum-corrected device simulation. The dependence of device performances, including subthreshold slope, drain-induced barrier lowering, off-current and threshold voltage roll-off, on the various fin angle and fin height are investigated. The JL bulk FinFET exhibits excellent short channel characteristics, gate controllability over trapezoidal shaped channel and less sensitivity of the fin angle to electrical performances by reducing effective channel thickness that is caused by the channel/ substrate junction. Hence, the JL bulk FinFET is highly recommended in sub-10-nm nodes. Additionally, this work demonstrates for the first time the fabrication of a proposed hybrid P/N poly-Si channel junctionless thin-film transistor (JL-TFT) with nanowires and omega-gate structure. The novel hybrid P/N JL-TFTs showed excellent electrical performances in terms of a steep subthreshold swing of 64mV/dec, a high Ion/Ioff current ratio (>107), a low drain-induced barrier lowering value of 3 mV/V, small series resistance and temperature stability were investigated, indicating greater gate electrostatic controllability and less current crowding than in conventional JL-TFTs. Furthermore, simulated results and a quantum model physical model were discussed initially but not detailed enough for future work support experimental data. Hence, the proposed hybrid P/N JL-TFT is highly promising for future further sub-10-nm scaling and 3D stacked ICs applications.
Yang, Yi-Yun, and 楊怡芸. "Study of Vertically Stacked Nanosheet With Multi- Gate Field-Effect-Transistors." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/jfhv3s.
Повний текст джерела國立清華大學
工程與系統科學系
105
In recreant years, the electronic products pursue not only the higher speed and better performance, but also less power consumption and lower cost. The Semiconductor ICs manufacturing companies still follow Moore's law to scaling. In addition to processing technology feasibility limits, it is important to develop a target that suffices high performance and scalability. Information processing technology is driving the semiconductor into a broadening spectrum of new applications according to 2015 ITRS 2.0 report. A significant part of the research to further improve device performance is presently concentrated on III-V materials and Ge. These materials promise higher mobility than Si devices. The combination of 3D device architecture and low power device will usher the Era of Scaling, identified in short as “3D Power Scaling”. In order to increase transistor density for continuing Moore’s law, we implement the stacked nanosheert (NS) vertically inversion-mode field-effect-transistors(VM-FET) in 3D stacked integrated circuit (IC) applications. This research which focus on is showing the following: (1) device process, (2).basic device characteristics analysis, (3) device simulation. There are three kinds device structure. The first one is stacked Fin-FET, The second is stacked Gate all around VM-FET, The third is p-Channel Silicon/Germanium Quantum Well Multi-Gate Field-Effect-Transistor, we adopt the oxidation trimming method to form thin active layer and exhibit quasi-crystal channel due to the reduction of grain boundaries and defects. It is beneficial for excellent electrical performance. In the basic device characteristics analysis. First part will show the comparison of stacked Fin-FET and conventional stacked planar Fin-FET. The stacked Fin-FET exhibits the better performance. After that comparison of stacked Fin-FET and stacked GAA-FET. The stacked GAA-FET achieves lowing subthreshold swing (S.S.) and Off current. Second part will discuss about the change of width dimension for I-V characteristics with stacked structure. However, in the device simulation, we use Sentaurus TCAD to analyze and confirm the measured basic electrical characteristics. In our proposed the stacked NS VM-FET has better electrical characteristics. Moreover, it may provide a probable next-generation CMOS device solution and be utilized in advanced 3D stacked IC applications.
YU, JIA-JYUN, and 余家鈞. "Study of Stacked Nanosheet Channels with Multi-Gate Junctionless Field-Effect-Transistors." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/37e9rr.
Повний текст джерела國立聯合大學
電子工程學系碩士班
106
With the continuous miniaturization of electronic components in the semiconductor companies, in addition to processing technology feasibility limits, it is important to develop a target that suffices high performance and scalability. Conventional inversion-mode Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) face a lot of challenges such as Short channel effects (SCEs), device process technologies, and physical limits in the scaling process. JL-FET is a novel device, which has heavily doping channel with the same type to that of source and drain. Therefore, JL-FET has a slight SCEs and less thermal budget in process of fabrication. In this thesis, we succeed demonstrated the double stacked nanosheet (NS) channels with multi-gate junctionless field effect transistors (MG-JLFET) applied in the future three-dimensional stacked integrated circuit , which includes the component process and the analysis of the electrical characteristics. There are two kinds device structure. The first one is double stacked nanosheet channels with multi-gate junctionless field effect transistors, the second is double stacked nanosheet channels with gate all around junctionless field effect transistors (GAA-JLFET). In the stacked device, we adopt the oxidation trimmed method to form thin active layer and exhibit quasi-crystal channel due to the reduction of grain boundaries and defects. In the basic device characteristics analysis. First part will compare MG JL-FET used different etch methods when definite the contact window, increased on current due to increased metal contact area and reduced Total Resistance, it has better electrical characteristics. The second part compares GAA-JLFET, because the use of GAA process, the transistor has better gate control, and discuss about the change of width dimension for electrical characteristics with stacked structure. In our proposed the stacked JL-FET has better electrical characteristics. Moreover, it may provide a probable next-generation CMOS device solution and be utilized in advanced 3D stacked IC applications.
Jhan, Yi-Ruei, and 詹易叡. "Multi-Gate and Ultra-Thin Active Layer of 12 nm Junctionless Field-Effect Transistors." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/49657120797110062644.
Повний текст джерела國立清華大學
工程與系統科學系
100
As electronic products with each passing day, IC design must be toward the high density development to meet market demand, the size of the components themselves must also be constantly scaling to respond. However, conventional transistors because of structural problems led to encounter considerable difficulties in miniature on the SCE (Short Channel Effect) and random dopant fluctuation. In this study adopted a novel junctionless structure, the characteristics of such a structure, channel and source and drain of the same doping type, doping concentration is also quite, so the channel to the source electrode and the channel to the drain electrode have no junctions. And it has no Charge Sharing Effect in scaling, because there is no junction to avoid short-channel effect. And doped with the same type, a considerable concentration, the doping process will be easy. There have no energy level difference between gate to channel so that can be avoided DIBL (Drain Induce Barrier Lowing) effect. However, the off state characteristic of junctionless transistor depend on the energy level difference between gate to channel, therefore to shut down the junctionless transistor is not an easy thing, so in this study adopted the multi gate to improve the gate control ability. That achieved better subthreshold characteristics in the off state, and more suitable for scaling, to become the next generation of mainstream transistor.
PAN, AN-CHING, and 潘安慶. "Design and Study of the Multi-Split-Gate Metal Oxide Semiconductor Field Effect Transistors." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/a9pckv.
Повний текст джерела華梵大學
電子工程學系碩士班
107
The power loss has always been a problem that humans continue to explore, especially in this high-performance era. In which how to reduce the power loss of electronic products is an important issue. Improving power loss on power devices is a common goal for developers. In recent years, a new structure, called "Split-Gate Metal Oxide Semiconductor Field Effect Transistor (Split-Gate MOSFET)", has been developed, which power loss has been improved, and can be operated in high frequency environments. In this thesis, SILVACO simulation software was used to simulate a 100-volt Split-Gate MOSFET and to study its characteristics. The Split-Gate MOSFETs were optimized by simulation for the purpose of reducing their on-resistance. First the size of the Split-Gate MOSFET was scaled. The purpose is to reduce the specific on-resistance (Ron,sp). Finally, we changed the structure of the device and proposed the Multi-Split-Gate MOSFET including 2 Split-Gate, 4 Split-Gate and 6 Split-Gate. The characteristics of 4 Split-Gate is better than others. Therefore, this structure had been further optimized for the miniature size finally. After a series optimization, compared with 2.5 um cell pitch Split-Gate, Ron,sp had reduced about 55% for new structure with 2.0 um cell pitch and 4 Split-Gate in this paper.
Han, Ming-Hung, and 韓銘鴻. "Physics, device operation, and circuit application of multi-gate junctionless metal-oxide-semiconductor field-effect-transistors." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/19072374204401546242.
Повний текст джерела國立交通大學
電子工程學系 電子研究所
102
In this work, we comprehensively study the physics, device operation, and applications of the multi-gate junctionless (JL) metal-oxide-semiconductor field- effect-transistor (MOSFET). In the first part of this work, we discuss the physics difference between JL transistors and conventional inversion-mode (IM) multi-gate transistors. The bulk conduction of the current in JL transistors has been addressed by the band-diagram and distributions of carrier density. Such conduction mechanism prevents the carrier mobility suffering from high field degradation and surface scattering, but shows a weak dependence on the gate bias. In JL transistor, since the dominating scattering mechanism is the impurity scattering due to heavily doped channel is used, the temperature dependency of the drain current is differ from IM transistor, the zero temperature coefficient point is not observed. Owing to the doping concentration gradient between source/drain and channel is zero, the depletion charge is control by the gate alone, the effective channel length is larger than gate length when JL transistor is turned off, resulting in the better short channel effect control and smaller total gate capacitance due to the reduction of gate to source/drain overlap capacitance. The JL transistor usually operate at flat-band condition when device is turned on, the total gate capacitance is smaller than that in IM transistor, but it also obtain a larger variation with the change of temperature. In the second part of this work, we compare the performance of JL transistor with bulk and silicon-on-insulator (SOI) substrate and study their advantages and limitations. In JL bulk transistor, the carriers concentrate on the top side of the channel due to the channel/substrate junction reduces the effective channel thickness. Such phenomenon improves the control of short channel effect but degrades the on-current simultaneously, and results in a better output conductance but a worse transconductance than those of JL SOI transistor. The JL bulk transistor performs less sensitivity to the device process variation, and provides an additional design parameter, substrate doping concentration, to tune the device performance. For analog and radio frequency characteristics, JL bulk transistor shows worse performance than in JL SOI transistor because of the parasitic substrate capacitance. The JL SOI transistors performs a shorter delay time, a smaller power consumption, and a larger static noise margin than those of the JL bulk transistor in the analysis of inverter and static random access memory (SRAM) circuits, and the JL SOI SRAM can operate at a very low supply voltage, which is benefit to the digital circuit application. In the last part of this work, we successfully fabricate a JL thin-film-transistor (TFT) with 2nm-thick channel; the measurement results demonstrate a 108 on/off current and a 61mV/dec subthrshold swing and are robust to process variation. We also measure the breakdown voltage of such device and compare it to IM TFT and laterally-diffused-metal-oxide-semiconductor (LDMOS). Our JL TFT obtains much higher breakdown voltage because the electric field in the device is uniformly distributed liked a resistor, indicating the potential of high-voltage application.
Rhee, Se Jong. "Electrical and material characteristics of hafnium-based multi-metal high-k gate dielectrics for future scaled CMOS technology: physics, reliability, and process development." Thesis, 2005. http://hdl.handle.net/2152/2287.
Повний текст джерелаKao, I.-Kone, and 郜一匡. "Study on Multi Ion Sensor of Extended Gate Field Effect Transistor." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/6r294x.
Повний текст джерела中原大學
醫學工程研究所
91
Abstract The concentrations of potassium and sodium ion in blood can response the condition of kidney. In addition, acidosis is an important factor in the setting of myocardial ischemia. The inhibition of potassium ion current was decreased during acidosis. Therefore, the concentrations of potassium and sodium ion are the index of health and an significant parameter in clinical diagnosis In this study, the extended-gate field effect transistor (EGFET), with was the SnO2/ITO glass structure, was applied to fabricate the potassium and sodium ion selective electrodes. The valinomycin and Bis[(12-crown-4) methyl]dodecyl- methylmalonate(B12C4) with two kinds of polymer (polyurethane and PVC) based on the EGFET were used for potassium and sodium ion selective electrodes. The polyurethane (Hydro-aliphatic urethane diacrylate,EB2001) membrane can improve the valinomycin and B12C4 to detect the potassium and sodium ions and its selectivity was about 40~50 mV/decade. Then , the potentiometric selectivity coefficient of SnO2 potassium and sodium electrodes will be obtained.
Chen, Zheng-Yao, and 陳政耀. "Study of Multi Gate Field-Effect Transistor with High-k Metal-Gate by Low Temperature Microwave Annealing." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/6fpjed.
Повний текст джерела中華大學
電機工程學系碩士班
101
To improve the performance of complementary metal-oxide-semiconductor (CMOS) devices, it is necessary to use a pair of metals with work functions that are near the conduction-band and valence-band edges of silicon to replace conventional n+/p+ poly-Si gate materials. According to ITRS, metal gate can evade high sheet resistance and poly depletion effect as compared with conventional poly-Si gate. Gate-last process has been adopted to eliminate work function shift, which occurs from the band-edge to the mid-gap, and high-k dielectric degradation after high temperature thermal process for dopant activation in source/drain (S/D) regions. However, these complex processes lead to restrictions on circuit design and process window. If gate-first process efficiently suppresses work function shift of metal gate electrodes and decreases equivalent oxide thickness (EOT) of gate dielectrics after dopant activation process, it will become a ponderable and promising candidate to simplify and reduce cost of nowadays CMOS fabrication process. The first part in this thesis investigated the dopant activation process by means of microwave annealing (MWA) and rapid thermal annealing (RTA) respectively. The results of experiments demonstrated suppressed diffusion profile of dopant which activated by MWA in comparison with conventional RTA process. The second and the third parts in this thesis compared MOSFETs with different gate stacks, which comprised TiN/HfO2/Si and TiN/TaN/HfO2/Si, proceeded post-deposition annealing (PDA) and post-metallization annealing (PMA) by MWA and RTA respectively. The results revealed the devices with post-treatment by MWA were possessed of lower interface trap density (Dit) and thinner EOT. The analysis by transmission electron microscopy (TEM) further explained the variation of EOT. The fourth part in this thesis demonstrated the electrical characteristics of MOSFETs after thermal process proceeded by MWA and RTA respectively. The result turned out that MWA was beneficial for suppressing short channel effect (SCE) in nanoscale MOSFETs. In contrast with MWA process, conventional RTA activated devices performed worse short-channel behavior due to inherent high temperature thermal process.
Baldauf, Tim. "Integration von Multi-Gate-Transistoren auf Basis einer 22 nm-Technologie." Doctoral thesis, 2013. https://tud.qucosa.de/id/qucosa%3A27419.
Повний текст джерелаWithin the past 40 years the continuous scaling of planar MOSFETs was key to shrink the devices and to improve their performance. Techniques like mechanical stressing, rapid thermal annealing and in-situ doped epitaxial growing as well as novel materials, such as high-k-gate-oxide in combination with titanium nitride as metal-gate, has been introduced. However, short-channel-effects and increased scattering of electrical proper-ties significantly complicate the scaling of planar transistors. Thus, the planar MOSFETs gradually reached their limits of functionality with the current 28 nm technology node. For that reason, this work focuses on integration of multi-gate transistors based on a 22 nm technology, which show an improved gate control and allow a continuous scaling. Furthermore, the requirements of a stable and cost-efficient process as decisive condition for mass fabrication were always taken into account. The simulations of the tri-gate transistors present the first step toward a multi-gate technology. The process sequence differs from the planar one solely by a fin formation and offers the possibility of a hybrid 22 nm process. Also, the impact of crystal orientation, mechanical stress and superposition of electrical fields on the efficiency of multi-gate structures were analyzed for the tri-gate transistors. In a second step transistors with fully depleted channel regions were studied. Due to low channel doping they are showing a volume inversion, a higher carrier mobility and a lower sensitivity to random doping fluctuations, which are essential criteria for powerful multi-gate transistors. Reviewed structure variants include planar ultra-thin-body-SOI-MOSFETs, classic FinFETs with a tall, narrow fins and vertical nanowire transistors. Then advantages and disadvantages of the considered transistor structures have been observed for a medium to long term industrial use. For this purpose, an analysis of statistical fluctuations and the scaling-down to 14 nm technology was carried out. A summary of all results and an outlook to the transfer of concepts into mass fabrication complete this work.:Symbol- und Abkürzungsverzeichnis 1 Einleitung 2 Grundlagen und Entwicklung der CMOS-Technologie 2.1 Planare Transistoren 2.1.1 Theoretische Grundlagen von MOSFETs 2.1.2 Skalierung und Kurzkanalverhalten planarer Transistoren 2.1.3 Mechanische Verspannung von Silizium 2.1.4 Techniken zur mechanischen Verspannung 2.2 Multi-Gate-Transistoren 2.2.1 Multi-Gate-Strukturen 2.2.2 Überlagerungseffekte 2.2.3 Quanteneffekte 2.3 Stand der Technik 3 Grundlagen der Simulation 3.1 Prozesssimulation 3.1.1 Abscheiden und Abtragen von Schichten 3.1.2 Implantation 3.1.3 Thermische Ausheilung mit Diffusion 3.2 Bauelementesimulation 3.2.1 Grundgleichungen und Ladungsträgertransport 3.2.2 Bandlückenverengung 3.2.3 Generation und Rekombination 3.2.4 Ladungsträgerbeweglichkeit 3.2.5 Effekte der mechanischen Verspannung 3.2.6 Ladungsträgerquantisierung 3.3 Kalibrierung der Modellparameter 3.3.1 Prozessparameter 3.3.2 Modellparameter 4 Planare Transistoren auf Basis einer 22 nm-Technologie 4.1 Transistoraufbau 4.1.1 Replacement-Gate-Prozess 4.1.2 In-situ-dotierte Source-Drain-Gebiete 4.1.3 Haloimplantation 4.1.4 Elemente der mechanischen Verspannung 4.2 Charakterisierung des elektrischen Verhaltens 4.2.1 Stationäres Verhalten 4.2.2 Gatesteuerung und Kurzkanaleffekte 4.2.3 Dynamisches Verhalten 5 Tri-Gate-Transistoren 5.1 Prozessintegration und Transistoraufbau 5.1.1 Anforderungen an hochintegrierte Schaltkreise 5.1.2 Hybride CMOS-Technologie 5.1.3 Strukturierung der Finne 5.1.4 Geometrieabhängiges Dotierungsprofil 5.2 Charakterisierung des elektrischen Verhaltens 5.2.1 Stationäres Verhalten 5.2.2 Kurzkanaleffekte und Gatesteuerung 5.2.3 Eckeneffekt 5.2.4 Eckenimplantation 5.2.5 Finnengeometrie 5.2.6 Dynamisches Verhalten 5.3 Optimierung der Tri-Gate-Struktur 5.3.1 Gestaltung der epitaktischen Source-Drain-Gebiete 5.3.2 Mechanisch verspanntes Isolationsoxid 5.3.3 Substratorientierung 6 Transistoren mit vollständig verarmtem Kanal 6.1 Ultra-Dünne-SOI-MOSFETs 6.1.1 Prozessintegration 6.1.2 Charakterisierung des elektrischen Verhaltens 6.2 FinFETs 6.2.1 Prozessintegration 6.2.2 Charakterisierung des elektrischen Verhaltens 6.3 Vertikale Nanowire-MOSFETs 6.3.1 Prozessintegration 6.3.2 Strukturierung des Aktivgebiets 6.3.3 Charakterisierung des elektrischen Verhaltens 6.3.4 Asymmetrisches Dotierungsprofil 6.3.5 Mechanische Verspannung 7 Skalierung und statistische Schwankungen der Strukturen 7.1 Skalierung zur 14 nm-Technologie 7.1.1 Leistungsfähigkeit 7.1.2 Kurzkanalverhalten und Steuerfähigkeit 7.2 Statistische Schwankungen 7.2.1 Impedanz-Feld-Methode 7.2.2 Zufällige Dotierungsfluktuation 7.2.3 Fixe Ladungen im Oxid 7.2.4 Metall-Gate-Granularität 7.2.5 Geometrische Variationen 7.2.6 Kombination der Störquellen 8 Zusammenfassung und Ausblick Anhang Literaturverzeichnis Danksagung Acknowledgement
Wang, Yu-Chun, and 王育群. "Two Novel Capacitorless One-Transistor DRAMs with Multi-Gate and Nano-Pillar Structures." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/62848552400920872265.
Повний текст джерела國立中山大學
電機工程學系研究所
103
In this thesis, we propose two novel capacitorless 1T-DRAMs, with the multi-gate and nano-pillar structures : The first type is a double-gate Nanowire TFT, with the fin-gate and pillar-body structure (FGPB). The second type is a vertical current bridge MOSFET, with the gate-all-around and nano-pillar structure (GAANP). We adopt the GIDL mechanism as 1T-DRAM programming method, and use the Sentaurus TCAD 12.0 simulation tool to confirm the memory performance. Compared with the conv. DG-NTFT, the FGPB device has nano-pillar structure, which can increase the pseudo neutral region without additional occupied area. This structure can improve the band-to-band tunneling, and keep the holes away from the P-N junction. The GIDL current is improved about 274.33 %. With fin-gate to control the excess hole efficiently, this structure can also overcome the SRH recombination influence indirectly. In terms of the low-power application, and the power consumption can maintained below 0.8 μW/μm. Compared with the lateral current bridge 1T-DRAMs, the GAANP SOI/Bulk-Silicon device has surrounding gate, which can enhance the excess hole control-ability; the vertical channel not only keeps the device in long-channel, but also maintains at a certain level of memory performance. In terms of the current bridge devices benchmark comparison, the GAANP SOI 1T-DRAM PW is improved at least about 238.54 %. The RT at 358 K is improved about 6.91 %. Two novel devices not only achieve low-power consumption, but also have sufficient operating endurance and disturbance immunity. We provide two excellent candidates for future 1T-DRAM applications.
Lee, Ya-Jui, and 李亞叡. "Investigation of electrical characteristics for multi gate tunneling-carbon nanotube field effect transistor." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/96155269652851592356.
Повний текст джерелаBOUKORTT, NOUR EL ISLAM. "Study and Simulation of a Nanoscale Structure of a Multi-gate MOS Transistor." Doctoral thesis, 2017. http://hdl.handle.net/11570/3103623.
Повний текст джерелаChou, Cheng-Wei, and 周政偉. "Fabrication and Characterization of Metal-induced Lateral Crystallization Polysilicon Thin-film Transistor with Multi-channel and Multi-gate." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/34965260092653740541.
Повний текст джерела國立交通大學
電子工程系所
93
I have studied the effects of NH3 plasma passivation on the electrical characteristics of pattern-dependent metal-induced lateral crystallization (PDMILC) polysilicon thin-film transistors (poly-Si TFTs). These transistors have various numbers of multiple channels. PDMILC TFTs with NH3 plasma passivation outperform those without such passivation. This is because of the effective hydrogen passivation of the grain-boundary dangling bonds, and the pile-up of nitrogen at the SiO2/poly-Si interface. Additionally, the performance of such devices improves as the number of multi-channels increase. In particular, the electrical characteristics of a nano-scale TFT with ten 67 nm-wide split channels (M10) are superior to other TFTs. For example, the M10 TFT has a higher field effect mobility of 84.63 cm2/Vs, a higher ON/OFF current ratio (>106), a steeper subthreshold slope (SS) of 230 mV/decade, an absence of drain-induced barrier lowering (DIBL) and favorable output characteristics. We have found that the active channels of the M10 TFT have exhibit for the best NH3 plasma passivation, due to its split nanowire channels structure. We have also studied for the pattern-dependent nickel (Ni) metal-induced lateral crystallization (Ni-MILC) polysilicon thin-film transistors (poly-Si TFTs) with ten nanowire channels and multi-gate. Experiment results show that employing ten nanowire channels improves the Ni-MILC poly-Si TFT performance, including a higher ON/OFF ratio and a lower threshold voltage (Vth) than single-channel TFT. Furthermore, experimental results reveal that a combination the multi-gate structure and ten nanowire channels can further enhance the entire performance of Ni-MILC TFT, including a low leakage current, a high ON/OFF ratio, a low Vth, a steep subthreshold swing (SS), and a kink-free output characteristics. From our studies, we conclude that the performance of the PDMILC TFTs can be improved by NH3 plasma passivation. The lateral electrical field of a ten multiple nanowire channels TFT can be effectively reduced by additional multi-gate control. The PDMILC TFTs process is compatible with CMOS technology, and involves no extra mask. Such high performance PDMILC TFTs are thus promising for use in future high-performance poly-Si TFT applications, especially in AMLCD and 3D MOSFET stacked circuits.
Hung, Ta-Yu, and 洪大祐. "Study and Fabrication on Multi-Array Extended-Gate Field-Effect Transistor Chloride Ion Sensitive Sensors." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/14804779315882808031.
Повний текст джерела中原大學
電子工程研究所
97
From recent years, people are becoming more and more conscious on health and environment protection issues. An instance in the field of research is real-time monitoring of water quality for safe human consumption having continued impact and significance. This study presents ion sensors that define chlorine concentration (pCl) of aqueous solutions. Chloride ion (Cl-) sensors were prepared using separate extended gate field effect transistor (SEGFET) structure. Two substrates were employed: indium tin oxide on slide glass (ITO/Glass) and aluminum nitride deposited on ITO/Glass (AlN/ITO/Glass). Membrane sensitive to chloride ions was deposited onto windows of these substrates. Such membrane was synthesized from PVC polymer, DOS plasticizer, ETH9033 ionophore, and THF additive. Afterwards, the ITO part in these sensor heads (PVC-DOS-ETH9033-THF/ITO/Glass, PVC-DOS-ETH9033-THF/AlN/ITO/Glass) were connected to commercially available MOSFET transistors (CD4007UB) to complete two kinds of SEGFET chloride ion sensors. The characterization of SEGFET chloride ion sensors utilized a semiconductor device analyzer (Agilent B1500A) and a constant voltage constant current (CVCC) interface circuitry. The sensitivity of sensors was evaluated using sodium chloride (NaCl) solutions with concentration from pCl 1 to pCl 5. Experiments on the sensitivity yielded: 51.8 mV/pCl of 98% linearity for the chloride ion sensor on ITO/Glass; and 54.3 mV/pCl of 97% linearity for the chloride ion sensor on AlN/ITO/Glass. The stability of sensors was also tested. After 8 hours in 1000 ppm NaCl solution, the time drift of sensors was determined: 0.915 V/hr for the chloride ion sensor on ITO/Glass; and 0.018 V/hr for the chloride ion sensor on AlN/ITO/Glass. Furthermore, the hysteresis of sensors was verified using NaCl solution with pCl level altered every 20 minutes in the direction of pCl 3, pCl 2, pCl 1, pCl 2, to pCl 3, pCl 4, pCl 5, pCl 4, and to pCl 3 again. The hysteresis of sensors measured at pCl 3: around 15 mV for the chloride ion sensor on ITO/Glass; and around 16 mV for the chloride ion sensor on AlN/ITO/Glass. Based on experimental results, the SEGFET chloride ion sensors using ITO/Glass and AlN/ITO/Glass both exhibited wide range of pCl detection, good linearity, stable performance and acceptable reproducibility. The CVCC interface of SEGFET chloride ion sensors was fabricated in integrated circuit using TSMC 2P4M 0.35 micron CMOS technology. The design, simulations and tests of this chip are also reported in this study. With the availability of chloride ion sensors suitable for pCl measurements of water, the low cost structure of SEGFET, together with the readout chip implementation, this study successfully showed that a portable chloride ion measurement system for real-time water monitoring application is very possible.
Wilson, Veas Alan Hjalmar. "Investigation of Multi-Level Neutral Point Clamped Voltage Source Converters using Isolated Gate Bipolar Transistor Modules." 2018. https://tud.qucosa.de/id/qucosa%3A33846.
Повний текст джерелаUnter den Multilevel-Spannungsumrichtern für Mittelspannungs- und Hochleistungsanwendungen ist die am häufigsten verwendete Leistungstopologie der NPC-VSC, wegen seinen Merkmalen wie die Gleichstrom-Bus fähigkeit mit mittlerem Punkt, das Fehlen von Schaltern in Reihenschaltung, eine geringe Anzahl von Bauteilen und eine einfache Steuerung. Die Verwendung von Bipolartransistor Modulen mit isolierter Gate-Elektrode als Leistungsschalter bietet weitere Vorteile wie kostengünstige Gatetreiber und Überlebensfähigkeit nach einem Kurzschluss. Die IGBT-Module haben jedoch aufgrund der durch Lastzyklen erzeugten thermischen Belastung eine verkürzte Lebensdauer. Trotz der Vorteile des 3L-NPC-VSC ist der Hauptnachteil die ungleichmäßige Verteilung der Leistungsverluste zwischen den Leistungsgeräten. Um dieses Problem zu beheben und andere Eigenschaften zu verbessern, wurden fortgeschrittenere ML-Konverter entwickelt. Das 3L-ANPC-VSC ermöglicht dank seiner zusätzlichen IGBTs eine verbesserte Verlustleistungsverteilung, wodurch die Anzahl der möglichen Null-Zustände erhöht wird, es ist jedoch ein Verlustausgleichsschema erforderlich, um den richtigen redundanten Null-Zustand, und benötigt auszuwählende komplexere Kommutierungssequenz zwischen Zuständen. Das 3L-NPP-VSC verbessert die Verlustleistungsverteilung durch die Verwendung von in Reihe geschalteten Schaltern zwischen der Ausgangsklemme und den positiven und negativen Zwischenkreisklemmen. Andere fortgeschrittene Leistungstopologien mit einer höheren Anzahl von Stufen umfassen den 5L-ANPC-VSC, der pro Phase einen fliegenden Kondensator zur Erzeugung der zusätzlichen Stufen aufweist; und den 5L-SMC, der pro Phase zwei fliegende Kondensatoren benötigt. Das Ziel dieser Arbeit ist es, die Leistung der oben genannten NPC-VSC, einschließlich der mit fliegenden Kondensatoren, hinsichtlich der Verlustleistungsverteilung und der Sperrschichttemperatur der am stärksten beanspruchten Geräte zu bewerten. Diese definieren zusammen mit der Nennausgangsspannung die maximale Leistung, die der Umrichter liefern kann. Ein zweites Ziel dieser Arbeit ist die Beschreibung der Kommutierungen eines MV 3L-ANPC-VSC- Prototyps mit IGBT-Modulen einschließlich aller Zwischenschaltzustände, um die gewünschten Kommutierungen zu erzeugen.:Figures and Tables V Glossary XIII 1. Introduction 1 2. State of the art of medium voltage source converters and power semiconductors 5 2.1. Overview of medium voltage source converters 5 2.1.1. Multilevel Voltage Source Converter topologies 6 2.1.2. Application oriented basic characteristic of IGCTs and IGBTs 10 2.1.3. Market overview of ML-VSCs 11 2.2. IGBT modules for MV applications 12 2.2.1. Structure and Function 12 2.2.2. Electrical characteristics of the IGBT modules 15 2.2.3. Power losses and junction temperatures estimation 17 2.2.4. Packaging 19 2.2.5. Reliability and Life cycle of IGBT modules 21 2.2.6. Market Overview 23 2.3. Summary of Chapter 2 23 3. Structure, function and characteristics of NPC-based VSCs 25 3.1. The 3L-NPC-VSC 25 3.1.1. Power Topology 25 3.1.2. Switching states, current paths and blocking voltage distribution 26 3.1.3. Modulation of three-level inverters 28 3.1.4. Power loss distribution 32 3.1.5. “Short” and “long” commutation paths 33 3.2. The 3L-NPP-VSC 34 3.2.1. Power Topology 34 3.2.2. Switching states, current paths and blocking voltage distribution 35 3.2.3. Power Loss distribution 36 3.3. The 3L-ANPC-VSC 37 3.3.1. Power Topology 37 3.3.2. Switching states, current paths and blocking voltage distribution 38 3.3.3. Commutations and power loss distribution 39 3.3.4. Loss balancing schemes 57 3.4. The 5L-ANPC-VSC 60 3.4.1. Power Topology 60 3.4.2. Switching states, current paths and blocking voltage distribution 61 3.4.3. Commutation sequences 62 3.4.4. Power Loss distribution 70 3.4.5. Modulation and balancing strategies of capacitor voltages 70 3.5. The 5L-SMC 74 3.5.1. Power Topology 74 3.5.2. Switching states, current paths and blocking voltage distribution 75 3.5.3. Commutations and power loss distribution 78 3.5.4. Modulation and balancing strategies of capacitor voltages 80 3.6. Summary of Chapter 3 81 4. Comparative evaluation and performance of NPC-based converters 83 4.1. Motivation and goal of the comparisons 83 4.2. Basis of the comparison 83 4.2.1. Simulation scheme 85 4.2.2. Losses and thermal models for (4.5 kV, 1.2 kA) IGBT modules 86 4.2.3. Operating points, modulation, controllers and general parameters 88 4.2.4. Life cycle estimation 94 4.3. Simulation results of the 3.3 kV 3L-VSCs 97 4.3.1. Loss distribution and temperature at equal phase current 97 4.3.2. Maximum phase current 109 4.3.3. Life cycle 111 4.4. Simulation results of the 6.6 kV 5L and 3L-VSCs 115 4.4.1. Loss distribution and temperature at equal phase current 115 4.4.2. Maximum phase current 120 4.4.3. Life cycle 128 4.5. Summary of Chapter 4 132 5. Experimental investigation of the 3L-ANPC-VSC with IGBT modules 135 5.1. Goal of the work 135 5.2. Description of the 3L-ANPC-VSC test bench 136 5.2.1. Medium voltage stage 136 5.2.2. Gate drivers and digital signal handling 138 5.2.3. Measurement equipment 139 5.3. Double-pulse test and commutation sequences 140 5.3.1. Description of the double-pulse test for the 3L-ANPC-VSC 140 5.3.2. Commutation sequences for the double-pulse test 142 5.4. Commutation measurements 142 5.4.1. Switching and transition times 144 5.4.2. Type I commutations 145 5.4.3. Type I-U commutations 150 5.4.4. Type II commutations 150 5.4.5. Type III commutations 157 5.4.6. Comparison of the commutation times 157 5.4.7. Stray inductances of the “short” and “long” commutations 163 5.5. Summary of Chapter 5 167 6. Conclusions 169 Appendices 173 A. Thermal model of IGBT modules 175 A.1. General “Y” model 175 A.2. “Foster” thermal circuit 177 A.3. “Cauer” thermal circuit 178 A.4. From “Foster” to “Cauer” 179 A.5. Temperature comparison using “Foster” and “Cauer” networks 181 B. The “Rainflow” cycle counting algorithm 183 C. Description of the wind generator example 187 C.1. Simulation models 188 C.1.1. Wind turbine 188 C.1.2. Synchronous generator, grid and choke filter 189 C.1.3. Converters 189 C.2. Controllers 190 C.2.1. MPPT scheme 190 C.2.2. Pitch angle controller 191 C.2.3. Generator side VSC 192 C.2.4. Grid side VSC 193 D. 3D-surfaces of the maximum load currents in NPC-based converters 195 Bibliography 201 Bibliography 201