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Статті в журналах з теми "Multi-Gate Transistors"
Lin, Jinhan. "Advancement and Challenges of Field Effect Transistors based on Multi-gate Transistor." Journal of Physics: Conference Series 2370, no. 1 (November 1, 2022): 012004. http://dx.doi.org/10.1088/1742-6596/2370/1/012004.
Повний текст джерелаSporea, Radu Alexandru. "(Invited) Multi-Gate Contact-Controlled Transistors." ECS Meeting Abstracts MA2021-01, no. 32 (May 30, 2021): 1058. http://dx.doi.org/10.1149/ma2021-01321058mtgabs.
Повний текст джерелаSeon, Kim, Kim, and Jeon. "Analytical Current-Voltage Model for Gate-All-Around Transistor with Poly-Crystalline Silicon Channel." Electronics 8, no. 9 (September 4, 2019): 988. http://dx.doi.org/10.3390/electronics8090988.
Повний текст джерелаZHANG, WEIQIANG, LI SU, YU ZHANG, LINFENG LI, and JIANPING HU. "LOW-LEAKAGE FLIP-FLOPS BASED ON DUAL-THRESHOLD AND MULTIPLE LEAKAGE REDUCTION TECHNIQUES." Journal of Circuits, Systems and Computers 20, no. 01 (February 2011): 147–62. http://dx.doi.org/10.1142/s0218126611007128.
Повний текст джерелаMo, Zening, Zhidi Jiang, and Jianping Hu. "A Novel Three-Input Field Effect Transistor with Parallel Switching Function Using T-Shaped Channel." Journal of Electrical and Computer Engineering 2022 (April 11, 2022): 1–12. http://dx.doi.org/10.1155/2022/1432545.
Повний текст джерелаYang, Maolong, Yao Lu, Qiancui Zhang, Zhao Han, Yichi Zhang, Maliang Liu, Ningning Zhang, Huiyong Hu, and Liming Wang. "Charge transport behaviors in a multi-gated WSe2/MoS2 heterojunction." Applied Physics Letters 121, no. 4 (July 25, 2022): 043501. http://dx.doi.org/10.1063/5.0097390.
Повний текст джерелаChu, Shunan. "Comparative Analysis of Optimization Schemes of Carry Look-ahead Adder." Journal of Physics: Conference Series 2290, no. 1 (June 1, 2022): 012008. http://dx.doi.org/10.1088/1742-6596/2290/1/012008.
Повний текст джерелаKondo, Jun, Murali Lingalugari, Pik-Yiu Chan, Evan Heller, and Faquir Jain. "Modeling and Fabrication of Quantum Dot Channel Field Effect Transistors Incorporating Quantum Dot Gate." MRS Proceedings 1551 (2013): 149–54. http://dx.doi.org/10.1557/opl.2013.899.
Повний текст джерелаBoampong, Amos Amoako, Jae-Hyeok Cho, Yoonseuk Choi, and Min-Hoi Kim. "Enhancement of the Retention Characteristics in Solution-Processed Ferroelectric Memory Transistor with Dual-Gate Structure." Journal of Nanoscience and Nanotechnology 21, no. 3 (March 1, 2021): 1766–71. http://dx.doi.org/10.1166/jnn.2021.18923.
Повний текст джерелаBhadra, Debabrata. "USING PERCOLATIVE CRYSTALLINE 0.3 CUO/PVDF NANOCOMPOSITE GATE DIELECTRIC FOR FABRICATING HIGH-EFFECT MOBILITY THIN FILM TRANSISTOR OPERATING AT LOW VOLTAGE." International Journal of Advanced Research 9, no. 11 (November 30, 2021): 1095–101. http://dx.doi.org/10.21474/ijar01/13846.
Повний текст джерелаДисертації з теми "Multi-Gate Transistors"
Chaves, Romero Ferney Alveiro. "Study and Modeling of Multi‐ Gate Transistors in the Context of CMOS Technology Scaling." Doctoral thesis, Universitat Autònoma de Barcelona, 2012. http://hdl.handle.net/10803/96232.
Повний текст джерелаThe scaling of the conventional MOSFETs has led these devices to the nanoscale to increase both the performance and the number of components per chip. In this process, the so-called “Short Channel Effects” have arisen as a limiting factor. To extend the use of the bulk MOSFETs, the most effective ways of suppressing such effects are the reduction of the gate oxide thickness and increasing of the channel doping concentration. When the gate oxide thickness is reduced to a few atomic layers, quantum mechanical tunneling is responsible of a huge increase in the gate leakage current impairing the normal operation of MOSFETs. This has made mandatory the use of high permittivity materials or high-κ as gate dielectrics. Despite the proposed solutions, reduction of the physical dimensions of the conventional MOSFETs cannot be maintained. To keep the technological trend, new MOSFET structures have been suggested such as ultra-thin body Multi-Gate MOSFETs. In particular, the Double-Gate MOSFETs is considered as a promising MG structure for its several qualities and advantages in scaling. This thesis focuses on the modeling of Double-Gate MOSFET and, in particular, on the modeling of the gate leakage current critically affecting the power consumption. First we develop a compact quantum model for both the electrostatic potential and the electric charge in symmetric double-gate MOSFET with undoped thin body. Then, this quantum model is used to propose an analytical compact model for the direct tunnelling current with SiO2 as gate dielectric, firstly, and later assuming a dual layer consisting of a SiO2 interfacial layer and a high-κ material. Finally, an accurate method for the calculation of the gate tunnelling current is developed. It is based on Absorbing Boundary Conditions techniques and, more specifically, on the Perfectly Mached Layer (PML) method. This thesis is motivated by the recommendations given by the “International Technology Roadmap of Semiconductors” (ITRS) about the need for the modeling and simulation of multi-gate semiconductor structures.
Tocci, Gabriele. "Performance estimation and Variability from Random Dopant Fluctuations in Multi-Gate Field Effect Transistors : a Simulation Study." Thesis, KTH, Integrerade komponenter och kretsar, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-93419.
Повний текст джерелаGaben, Loic. "Fabrication et caractérisation de transistors MOS à base de nanofils de silicium empilés et à grille enrobante réalisés par approche Gate-Last pour les noeuds technologiques sub-7 nm." Thesis, Université Grenoble Alpes (ComUE), 2017. http://www.theses.fr/2017GREAT095/document.
Повний текст джерелаThe future of the transistors currently used in Microelectronics is still uncertain: shrinking these devices while increasing their performances always remains a challenge. In this thesis, stacked nanowire transistors are studied, fabricated and optimized. This architecture embeds gate all around which is the ultimate solution for concentrating always more current within a smaller device. Simulations have shown that silicon nanosheets provide an optimal utilization of the space with providing increased performances over the other technologies. Crucial process steps have also been identified. Subsequently, two process flows have been suggested for the fabrication of SNWFETs. The first approach consists in minimizing the number of variations from processes already in mass production. The second alternative has potentially better performances but its development is more challenging. Finally, the fabricated transistors have shown improved performances over state-of-the-art especially due to mechanical stress induced for improving electric transport
Francisco, sousa alves Luciano. "Series-connected SiC-MOSFETs : A Novel Multi-Step Packaging Concept and New Gate Drive Power Supply Configurations." Thesis, Université Grenoble Alpes, 2020. http://www.theses.fr/2020GRALT050.
Повний текст джерелаThis work investigates new gate drive power supply configurations and a novel multi-steppackaging concept in order to improve the performance of series-connected SiC-MOSFETs. The new gate drive configurations are proposed in order to reduce noise currents that circulate in the control part of the electrical system. Furthermore, a new gate drive power supply is proposed to increase the dv/dt of the switching cell. These improvements, i.e., noise current reduction and dv/dt boosting, are achieved by modifying the impedance of the gate drive circuitry. The novel multi-step packaging concept is proposed in order to improve the voltage sharing performance. The proposed package geometry considers optimal dielectric isolation for each device leading to a multi-step geometry. It has a significant impact on the parasitic capacitances introduced by the packaging structure that are responsible for voltageunbalances. The new gate driver configurations and the proposed multi-step packaging concepts are introduced and analysed thanks to equivalent models and time domain simulations. Then, experimental set-ups are performed to confirm that the proposed concepts are better than traditional ones in terms of voltage balancing, switching speed and conducted EMI reduction
Zbierska, Inga Jolanta. "Study of electrical characteristics of tri-gate NMOS transistor in bulk technology." Thesis, Lyon 1, 2014. http://www.theses.fr/2014LYO10282/document.
Повний текст джерелаOne of the recent solutions to overcome the scaling limit issue are multi-gate structures. One cost-effective approach is a three-independent-gate NMOSFET fabricated in a standard bulk CMOS process. Apart from their shape, which takes advantage of the three-dimensional space, multi gate transistors are similar to the conventional one. A multi-gate NMOSFET in bulk CMOS process can be fabricated by integration of polysilicon-filled trenches. This trenches are variety of the applications for instance in DRAM memories, power electronics and in image sensors. The image sensors suffer from the parasitic charges between the pixels, called crosstalk. The polysilicon - filled trenches are one of the solution to reduce this phenomenon. These trenches ensure the electrical insulation on the whole matrix pixels. We have investigated its characteristics using l-V measurements, C-V split method and both two- and three-level charge pumping techniques. Tts tunable-threshold and multi-threshold features were verified. Tts surface- channel low-field electron mobility and the Si/SiO2 interface traps were also evaluated. We observed no significant degradation of these characteristics due to integration of polysilicon-filled trenches in the CMOS process. The structure has been simulated by using 3D TCAD tool. Tts electrical characteristics has been evaluated and compared with results obtained from electrical measurements. The threshold voltage and the effective channel length were extracted. Tts surface-channel low-field electron mobility and the Si/SiO2 interface traps were also evaluated. Owing to the good electrical performances and cost-effective production, we noticed that this device is a good aspirant for analog applications thanks to the multi-threshold voltages
ANTIDORMI, ALEANDRO. "Modelling and Simulation of Silicon Nanowire-Based Electron Devices for Computation and Sensing." Doctoral thesis, Politecnico di Torino, 2016. http://hdl.handle.net/11583/2643159.
Повний текст джерелаBaldauf, Tim. "Integration von Multi-Gate-Transistoren auf Basis einer 22 nm-Technologie." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2014. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-132044.
Повний текст джерелаWithin the past 40 years the continuous scaling of planar MOSFETs was key to shrink the devices and to improve their performance. Techniques like mechanical stressing, rapid thermal annealing and in-situ doped epitaxial growing as well as novel materials, such as high-k-gate-oxide in combination with titanium nitride as metal-gate, has been introduced. However, short-channel-effects and increased scattering of electrical proper-ties significantly complicate the scaling of planar transistors. Thus, the planar MOSFETs gradually reached their limits of functionality with the current 28 nm technology node. For that reason, this work focuses on integration of multi-gate transistors based on a 22 nm technology, which show an improved gate control and allow a continuous scaling. Furthermore, the requirements of a stable and cost-efficient process as decisive condition for mass fabrication were always taken into account. The simulations of the tri-gate transistors present the first step toward a multi-gate technology. The process sequence differs from the planar one solely by a fin formation and offers the possibility of a hybrid 22 nm process. Also, the impact of crystal orientation, mechanical stress and superposition of electrical fields on the efficiency of multi-gate structures were analyzed for the tri-gate transistors. In a second step transistors with fully depleted channel regions were studied. Due to low channel doping they are showing a volume inversion, a higher carrier mobility and a lower sensitivity to random doping fluctuations, which are essential criteria for powerful multi-gate transistors. Reviewed structure variants include planar ultra-thin-body-SOI-MOSFETs, classic FinFETs with a tall, narrow fins and vertical nanowire transistors. Then advantages and disadvantages of the considered transistor structures have been observed for a medium to long term industrial use. For this purpose, an analysis of statistical fluctuations and the scaling-down to 14 nm technology was carried out. A summary of all results and an outlook to the transfer of concepts into mass fabrication complete this work
Weisz, Mario. "Electrothermal device-to-circuit interactions for half THz SiGe∶C HBT technologies." Thesis, Bordeaux 1, 2013. http://www.theses.fr/2013BOR14909/document.
Повний текст джерелаThe power generate by modern silicon germanium (SiGe) heterojunction bipolar transistors (HBTs) can produce large thermal gradients across the silicon substrate. The device opering temperature modifies model parameters and can significantly affect circuit operation. This work characterizes and models self-heating and thermal coupling in SiGe HBTs. The self-heating effect is evaluated with low frequency and pulsed measurements. A novel pulse measurement system is presented that allows isothermal DC and RF measurements with 100ns pulses. Electrothermal intra- and inter-device feedback is extensively studied and the impact on the performance of two analog circuits is evaluated. Novel test structures are designed and fabricated to measure thermal coupling between single transistors (inter-device) as well as between the emitter stripes of a multi-finger transistor (intra-device). Thermal coupling factors are extracted from measurements and from 3D thermal simulations. Thermally coupled simulations of a ring oscillator (RO) with 218 transistors and of a 60GHz power amplifier (PA) are carried out. Current mode logic (CML) ROs are designed and measured. Layout optimizations lead to record gate delay of 1.65ps. The thermal performance of a 60GHz power amplifier is compared when realized with a multi-transistor array (MTA) and with a multi-finger trasistor (MFT). Finally, perspectives of this work within a CAD based circuit design environment are discussed
Baldauf, Tim [Verfasser], Gerald [Akademischer Betreuer] Gerlach, and Roland [Akademischer Betreuer] Stenzel. "Integration von Multi-Gate-Transistoren auf Basis einer 22 nm-Technologie / Tim Baldauf. Gutachter: Gerald Gerlach ; Roland Stenzel. Betreuer: Gerald Gerlach ; Roland Stenzel." Dresden : Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2014. http://d-nb.info/1068444916/34.
Повний текст джерелаWilson, Veas Alan Hjalmar [Verfasser], Steffen [Gutachter] Bernet, Mariusz [Gutachter] Malinowski, and Steffen [Akademischer Betreuer] Bernet. "Investigation of Multi-Level Neutral Point Clamped Voltage Source Converters using Isolated Gate Bipolar Transistor Modules / Alan Hjalmar Wilson Veas ; Gutachter: Steffen Bernet, Mariusz Malinowski ; Betreuer: Steffen Bernet." Dresden : Technische Universität Dresden, 2019. http://d-nb.info/1226899463/34.
Повний текст джерелаКниги з теми "Multi-Gate Transistors"
Colinge, Jean-Pierre, ed. FinFETs and Other Multi-Gate Transistors. Boston, MA: Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-71752-4.
Повний текст джерелаColinge, J. P. FinFETs and Other Multi-Gate Transistors. Springer, 2010.
Знайти повний текст джерелаColinge, J. P. FinFETs and Other Multi-Gate Transistors. Springer London, Limited, 2007.
Знайти повний текст джерелаFinFETs and Other Multi-Gate Transistors (Series on Integrated Circuits and Systems). Springer, 2007.
Знайти повний текст джерелаЧастини книг з теми "Multi-Gate Transistors"
Kumar, Subindu, and Tarun Kumar Sharma. "On-Chip Carbon Nanotube Interconnects: Adaptation to Multi-gate Transistors." In Carbon Related Materials, 127–47. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-7610-2_7.
Повний текст джерелаSaini, Gaurav, and Trailokya Nath Sasamal. "Asymmetric Junctionless Transistor." In High-k Materials in Multi-Gate FET Devices, 141–50. Boca Raton: CRC Press, 2021. http://dx.doi.org/10.1201/9781003121589-9.
Повний текст джерелаUsha, C., and P. Vimala. "Influence of High-k Material in Gate Engineering and in Multi-Gate Field Effect Transistor Devices." In High-k Materials in Multi-Gate FET Devices, 33–54. Boca Raton: CRC Press, 2021. http://dx.doi.org/10.1201/9781003121589-3.
Повний текст джерелаKumar, Raj, Shashi Bala, and Arvind Kumar. "Comparative Performance Analysis of Nanowire and Nanotube Field Effect Transistors." In Advances in Computer and Electrical Engineering, 54–70. IGI Global, 2021. http://dx.doi.org/10.4018/978-1-7998-6467-7.ch003.
Повний текст джерела"Multi-Gate Transistor Model." In BSIM4 and MOSFET Modeling For IC Simulation, 387–410. WORLD SCIENTIFIC, 2011. http://dx.doi.org/10.1142/9789812813992_0011.
Повний текст джерелаТези доповідей конференцій з теми "Multi-Gate Transistors"
Weber, Cory, Dipanjan Basu, Roza Kotlyar, and Saurabh Morarka. "Technology CAD challenges of modeling multi-gate transistors." In 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD). IEEE, 2013. http://dx.doi.org/10.1109/sispad.2013.6650588.
Повний текст джерелаSaha, Jhuma, Subindu Kumar, and Shankaranand Jha. "A comparative analysis of some multi-gate junctionless transistors." In 2015 6th International Conference on Computers and Devices for Communication (CODEC). IEEE, 2015. http://dx.doi.org/10.1109/codec.2015.7893201.
Повний текст джерелаSoares, Caroline S., Pranay K. R. Baikadi, Alan C. J. Rossetto, Marcelo A. Pavanello, Dragica Vasileska, and Gilson I. Wirth. "Modeling Quantum Confinement in Multi-Gate Transistors with Effective Potential." In 2022 36th Symposium on Microelectronics Technology (SBMICRO). IEEE, 2022. http://dx.doi.org/10.1109/sbmicro55822.2022.9881047.
Повний текст джерелаThean, A. V.-Y., Z.-H. Shi, L. Mathew, T. Stephens, H. Desjardin, C. Parker, T. White, et al. "Performance and Variability Comparisons between Multi-Gate FETs and Planar SOI Transistors." In 2006 International Electron Devices Meeting. IEEE, 2006. http://dx.doi.org/10.1109/iedm.2006.346923.
Повний текст джерелаChatterjee, A., S. Aur, T. Niuya, P. Yang, and J. A. Seitchik. "Failure in CMOS circuits induced by hot carriers in multi-gate transistors." In 26th International Reliability Physics Symposium. IEEE, 1988. http://dx.doi.org/10.1109/irps.1988.362195.
Повний текст джерелаHan, Shu-Jen, Satoshi Oida, Keith A. Jenkins, and Darsen D. Lu. "High fMAX/fT ratio in multi-finger embedded T-shaped gate graphene transistors." In 2013 71st Annual Device Research Conference (DRC). IEEE, 2013. http://dx.doi.org/10.1109/drc.2013.6633781.
Повний текст джерелаZhang, Xuncai, Dongjun Luo, Guangzhao Cui, Yanfeng Wang, and Buyi Huang. "Construction of Logic Gate Based on Multi-channel Carbon Nanotube Field-Effect Transistors." In 2011 International Conference on Intelligent Human-Machine Systems and Cybernetics (IHMSC). IEEE, 2011. http://dx.doi.org/10.1109/ihmsc.2011.93.
Повний текст джерелаHoque, Asiful, Mohammad Rabib Hossain, and Md Ishfak Tahmid. "A Comparative Study on Design and Characterization of Single Gate and Double Gate Multi-Channel Junctionless Nanowire Transistors." In 2020 IEEE Region 10 Symposium (TENSYMP). IEEE, 2020. http://dx.doi.org/10.1109/tensymp50017.2020.9230591.
Повний текст джерелаJin, Seonghoon, Sung-Min Hong, Woosung Choi, Keun-Ho Lee, and Youngkwan Park. "Coupled drift-diffusion (DD) and multi-subband Boltzmann transport equation (MSBTE) solver for 3D multi-gate transistors." In 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD). IEEE, 2013. http://dx.doi.org/10.1109/sispad.2013.6650646.
Повний текст джерелаChin, Hock-Chun, Moh-Lung Ling, Bin Liu, Xingui Zhang, Jie Li, Yongdong Liu, Jiangtao Hu, and Yee-Chia Yeo. "Metrology solutions for high performance germanium multi-gate field-effect transistors using optical scatterometry." In SPIE Advanced Lithography, edited by Alexander Starikov and Jason P. Cain. SPIE, 2013. http://dx.doi.org/10.1117/12.2013413.
Повний текст джерелаЗвіти організацій з теми "Multi-Gate Transistors"
Nochetto, Horacio C., Nicholas R. Jankowski, Brian Morgan, and Avram Bar-Cohen. A Hybrid Multi-gate Model of a Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) Device Incorporating GaN-substrate Thermal Boundary Resistance. Fort Belvoir, VA: Defense Technical Information Center, October 2012. http://dx.doi.org/10.21236/ada570599.
Повний текст джерела