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Готові списки джерел за темами / Metal oxide semiconductor field-effect transistors / Статті в журналах

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Статті в журналах з теми "Metal oxide semiconductor field-effect transistors"

Автор: Grafiati

Опубліковано: 4 червня 2021

Оновлено: 28 липня 2024

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1

Kumar, Prateek, Maneesha Gupta, Naveen Kumar, Marlon D. Cruz, Hemant Singh, Ishan, and Kartik Anand. "Performance Evaluation of Silicon-Transition Metal Dichalcogenides Heterostructure Based Steep Subthreshold Slope-Field Effect Transistor Using Non-Equilibrium Green’s Function." Sensor Letters 18, no. 6 (June 1, 2020): 468–76. http://dx.doi.org/10.1166/sl.2020.4236.

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With technology invading nanometer regime performance of the Metal-Oxide-semiconductor Field Effect Transistor is largely hampered by short channel effects. Most of the simulation tools available do not include short channel effects and quantum effects in the analysis which raises doubt on their authenticity. Although researchers have tried to provide an alternative in the form of tunnel field-effect transistors, junction-less transistors, etc. but they all suffer from their own set of problems. Therefore, Metal-Oxide-Semiconductor Field-Effect Transistor remains the backbone of the VLSI industry. This work is dedicated to the design and study of the novel tub-type Metal-Oxide-Semiconductor Field-Effect Transistor. For simulation Non-Equilibrium Green’s Function is used as the primary model of simulation. The device is analyzed under different physical variations like work function, permittivity, and interface trap charge. This work uses Silicon-Molybdenum Disulphide heterojunction and Silicon-Tungsten Disulphide heterojunction as channel material. Results for both the heterojunctions are compared. It was analyzed that Silicon-Molybdenum Disulphide heterojunction provides better linearity and Silicon-Tungsten Disulphide heterojunction provides better switching speed than conventional Metal-Oxide-Semiconductor Field-Effect Transistor.

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2

Anderson, Jackson, Yanbo He, Bichoy Bahr, and Dana Weinstein. "Integrated acoustic resonators in commercial fin field-effect transistor technology." Nature Electronics 5, no. 9 (September 23, 2022): 611–19. http://dx.doi.org/10.1038/s41928-022-00827-6.

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AbstractIn radio communication, the growth of beamforming and multiple-input–multiple-output technologies, which increase transceiver complexity, have led to a drive to reduce the size, weight and power of radio components by integrating them into a single system on chip. One approach is to integrate the frequency references of acoustic microelectromechanical systems (MEMS) with complementary metal–oxide–semiconductor processes, typically through a MEMS-first or MEMS-last approach that requires process customization. Here we report unreleased acoustic resonators that are fabricated in 14 nm fin field-effect transistor technology and operate in the X-band frequency range (8–12 GHz). The devices use phononic waveguides for acoustic confinement and exploit metal–oxide–semiconductor capacitors and transistors to electromechanically drive and sense acoustic vibrations. Fifteen device variations are analysed across 30 bias points, quantifying the importance of phononic confinement on resonator performance and demonstrating the velocity-saturated piezoresistive effect in active resonant transistors. Our results illustrate the feasibility of integrating acoustic devices directly into standard complementary metal–oxide–semiconductor processes.

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3

Weng, Wu-Te, Yao-Jen Lee, Horng-Chih Lin, and Tiao-Yuan Huang. "Plasma-Induced Damage on the Reliability of Hf-Based High-k/Dual Metal-Gates Complementary Metal Oxide Semiconductor Technology." International Journal of Plasma Science and Engineering 2009 (December 14, 2009): 1–10. http://dx.doi.org/10.1155/2009/308949.

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This study examines the effects of plasma-induced damage (PID) on Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates that thinning the gate dielectric reduces the impact of damage on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO2/poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for high-k/metal-gate CMOS technology.

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4

John Chelliah, Cyril R. A., and Rajesh Swaminathan. "Current trends in changing the channel in MOSFETs by III–V semiconducting nanostructures." Nanotechnology Reviews 6, no. 6 (November 27, 2017): 613–23. http://dx.doi.org/10.1515/ntrev-2017-0155.

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AbstractThe quest for high device density in advanced technology nodes makes strain engineering increasingly difficult in the last few decades. The mechanical strain and performance gain has also started to diminish due to aggressive transistor pitch scaling. In order to continue Moore’s law of scaling, it is necessary to find an effective way to enhance carrier transport in scaled dimensions. In this regard, the use of alternative nanomaterials that have superior transport properties for metal-oxide-semiconductor field-effect transistor (MOSFET) channel would be advantageous. Because of the extraordinary electron transport properties of certain III–V compound semiconductors, III–Vs are considered a promising candidate as a channel material for future channel metal-oxide-semiconductor transistors and complementary metal-oxide-semiconductor devices. In this review, the importance of the III–V semiconductor nanostructured channel in MOSFET is highlighted with a proposed III–V GaN nanostructured channel (thickness of 10 nm); Al2O3 dielectric gate oxide based MOSFET is reported with a very low threshold voltage of 0.1 V and faster switching of the device.

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5

Duan, Haoyuan. "From MOSFET to FinFET to GAAFET: The evolution, challenges, and future prospects." Applied and Computational Engineering 50, no. 1 (March 25, 2024): 113–20. http://dx.doi.org/10.54254/2755-2721/50/20241285.

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With the swift progression of semiconductor technology, the transition from Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) to Fin Field-Effect Transistors (FinFETs) and further to Gate-All-Around Field-Effect Transistors (GAAFETs) presents significant potential for the future of electronic devices and systems. This article delves into the intricate applications, challenges, and prospective evolutions associated with FinFET and GAAFET technologies. Findings suggest that these technologies are particularly apt for low-power logic systems, high-performance computing, and artificial intelligence domains. However, as dimensions shrink, challenges pertaining to heat dissipation, leakage, and manufacturing consistency become prominent. Despite these hurdles, the horizon for semiconductor technology remains bright, encompassing exploration of alternative materials such as Germanium and 2D compositions and innovative designs like U-shaped Field-Effect Transistors and Complementary Field-Effect Transistors. As the industry continues its relentless pursuit of even more efficient, smaller transistors, the exploration of alternative materials and diversification in architecture may play a pivotal role in future developments. In essence, while the semiconductor sphere confronts challenges, relentless innovation promises a future brimming with even more efficient and compact transistor technologies.

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6

Ouyang, Zhuping, Wanxia Wang, Mingjiang Dai, Baicheng Zhang, Jianhong Gong, Mingchen Li, Lihao Qin, and Hui Sun. "Research Progress of p-Type Oxide Thin-Film Transistors." Materials 15, no. 14 (July 8, 2022): 4781. http://dx.doi.org/10.3390/ma15144781.

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The development of transparent electronics has advanced metal–oxide–semiconductor Thin-Film transistor (TFT) technology. In the field of flat-panel displays, as basic units, TFTs play an important role in achieving high speed, brightness, and screen contrast ratio to display information by controlling liquid crystal pixel dots. Oxide TFTs have gradually replaced silicon-based TFTs owing to their field-effect mobility, stability, and responsiveness. In the market, n-type oxide TFTs have been widely used, and their preparation methods have been gradually refined; however, p-Type oxide TFTs with the same properties are difficult to obtain. Fabricating p-Type oxide TFTs with the same performance as n-type oxide TFTs can ensure more energy-efficient complementary electronics and better transparent display applications. This paper summarizes the basic understanding of the structure and performance of the p-Type oxide TFTs, expounding the research progress and challenges of oxide transistors. The microstructures of the three types of p-Type oxides and significant efforts to improve the performance of oxide TFTs are highlighted. Finally, the latest progress and prospects of oxide TFTs based on p-Type oxide semiconductors and other p-Type semiconductor electronic devices are discussed.

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7

Choi, Woo Young, Jong Duk Lee, and Byung-Gook Park. "Integration Process of Impact-Ionization Metal–Oxide–Semiconductor Devices with Tunneling Field-Effect-Transistors and Metal–Oxide–Semiconductor Field-Effect Transistors." Japanese Journal of Applied Physics 46, no. 1 (January 10, 2007): 122–24. http://dx.doi.org/10.1143/jjap.46.122.

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8

Bendada, E., K. Raïs, P. Mialhe, and J. P. Charles. "Surface Recombination Via Interface Defects in Field Effect Transistors." Active and Passive Electronic Components 21, no. 1 (1998): 61–71. http://dx.doi.org/10.1155/1998/91648.

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Recombination current at the oxide-semiconductor interface of metal-oxide-semiconductor devices has been analyzed and compared with the experimental result. The activity of interface traps is dependent on the energy level and on the operating conditions. A model is shown to be powerful to describe the effect of energy level of bulk recombination centers on the values of reverse recombination current.

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9

Choi, Woo Young. "Comparative Study of Tunneling Field-Effect Transistors and Metal–Oxide–Semiconductor Field-Effect Transistors." Japanese Journal of Applied Physics 49, no. 4 (April 20, 2010): 04DJ12. http://dx.doi.org/10.1143/jjap.49.04dj12.

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10

Diao Wenhao, 刁文豪, 江伟华 Jiang Weihua, and 王新新 Wang Xinxin. "Marx generator using metal-oxide-semiconductor field-effect transistors." High Power Laser and Particle Beams 22, no. 3 (2010): 565–68. http://dx.doi.org/10.3788/hplpb20102203.0565.

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11

Irokawa, Y., Y. Nakano, M. Ishiko, T. Kachi, J. Kim, F. Ren, B. P. Gila, et al. "GaN enhancement mode metal-oxide semiconductor field effect transistors." physica status solidi (c) 2, no. 7 (May 2005): 2668–71. http://dx.doi.org/10.1002/pssc.200461280.

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12

Атамуратова, З. А., А. Юсупов, Б. О. Халикбердиев та А. Э. Атамуратов. "Аномальное поведение боковой C-V-характеристики МНОП-транзистора со встроенным локальным зарядом в нитридном слое". Журнал технической физики 89, № 7 (2019): 1067. http://dx.doi.org/10.21883/jtf.2019.07.47801.319-18.

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C-V dependence of lateral source-base transition of metal-nitride-oxide-semiconductor field effect transistor with localized nitride trapped charge is simulated. Localizing the charge induce anomalous jumping or recession of the capacitance at defined applied voltage. The change of capacitance is connected with redistribution of carriers at semiconductor surface induced by charge trapping. The anomalous behaviour of the capacitance can be used at detecting the localized charge trapped in the dielectric layer of field effect transistors.

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13

GILDENBLAT, G., and D. FOTY. "LOW TEMPERATURE MODELS OF METAL OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTORS." International Journal of High Speed Electronics and Systems 06, no. 02 (June 1995): 317–73. http://dx.doi.org/10.1142/s0129156495000092.

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We review the modeling of silicon MOS devices in the 10–300 K temperature range with an emphasis on the specifics of low-temperature operation. Recently developed one-dimensional models of long-channel transistors are discussed in connection with experimental determination and verification of the effective channel mobility in a wide temperature range. We also present analytical pseudo-two-dimensional models of short-channel devices which have been proposed for potential use in circuit simulators. Several one-, two-, and three-dimensional numerical models are discussed in order to gain insight into the more subtle details of the low-temperature device physics of MOS transistors and capacitors. Particular attention is paid to freezeout effects which, depending on the device design and the ambient temperature range, may or may not be important for actual device operation. The numerical models are applied to study the characteristic time scale of freezeout transients in the space-charge regions of silicon devices, to the analysis and suppression of delayed turn-off in MOS transistors with compensated channel, and to the temperature dependence of three-dimensional effects in short-channel, narrow-channel MOSFETs.

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14

Chang, Wen-Teng, Hsu-Jung Hsu, and Po-Heng Pao. "Vertical Field Emission Air-Channel Diodes and Transistors." Micromachines 10, no. 12 (December 6, 2019): 858. http://dx.doi.org/10.3390/mi10120858.

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Vacuum channel transistors are potential candidates for low-loss and high-speed electronic devices beyond complementary metal-oxide-semiconductors (CMOS). When the nanoscale transport distance is smaller than the mean free path (MFP) in atmospheric pressure, a transistor can work in air owing to the immunity of carrier collision. The nature of a vacuum channel allows devices to function in a high-temperature radiation environment. This research intended to investigate gate location in a vertical vacuum channel transistor. The influence of scattering under different ambient pressure levels was evaluated using a transport distance of about 60 nm, around the range of MFP in air. The finite element model suggests that gate electrodes should be near emitters in vertical vacuum channel transistors because the electrodes exhibit high-drive currents and low-subthreshold swings. The particle trajectory model indicates that collected electron flow (electric current) performs like a typical metal oxide semiconductor field effect-transistor (MOSFET), and that gate voltage plays a role in enhancing emission electrons. The results of the measurement on vertical diodes show that current and voltage under reduced pressure and filled with CO2 are different from those under atmospheric pressure. This result implies that this design can be used for gas and pressure sensing.

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15

Yang, Ji-Woon, Chang Seo Park, Casey E. Smith, Hemant Adhikari, Jeff Huang, Dawei Heh, Prashant Majhi, and Raj Jammy. "Mitigation of Complementary Metal–Oxide–Semiconductor Variability with Metal Gate Metal–Oxide–Semiconductor Field-Effect Transistors." Japanese Journal of Applied Physics 48, no. 4 (April 20, 2009): 04C056. http://dx.doi.org/10.1143/jjap.48.04c056.

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16

Marcoux, J., J. Orchard-Webb, and J. F. Currie. "Complementary metal oxide semiconductor-compatible junction field-effect transistor characterization." Canadian Journal of Physics 65, no. 8 (August 1, 1987): 982–86. http://dx.doi.org/10.1139/p87-156.

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We report on the fabrication and electrical characterization of a vertical junction-gate field-effect transistor (JFET) that is compatible with all complementary metal oxide semiconductor (CMOS) technologies. It can be used as a buried load for an enhancement n-channel metal oxide semiconductor field-effect transistor (n-MOSFET), replacing the p-MOSFET within the standard CMOS inverter configuration and resulting in a 40% net area economy in standard cells. To be entirely CMOS process compatible, this JFET device differs from others in the literature in that dopant concentrations in the n substrates (1014) and in the p wells (1015) are substantially lower. For integrated-circuit applications, one seeks to use the JFET with the smallest area to minimize parasitic capacitances and to maximize switching speeds. However, at these concentration levels, the dc current–voltage characteristics depend critically on the lateral dimension of the JFET's square channel. Above 10 μm, the characteristics are pentode-like and similar to those of a classic MOSFET. Below 10 μm, the channel is naturally pinched-off, and for reverse gate bias, the small JFETs are triode-like. There is also a nonreciprocity between the source and the drain when the source-to-drain voltage polarity is changed, which is due to the distance between the channel and the electrode collecting the carriers. When its gate is forward-biased, the small JFETs behave as bipolar transistors. Depending on source-to-drain voltage polarities, I–V characteristics exhibit saturation effects caused by base-widening phenomena at the JFET's drain contact.

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17

Ahmed Mohammede, Arsen, Zaidoon Khalaf Mahmood, and Hüseyin Demirel. "Study of finfet transistor: critical and literature review in finfet transistor in the active filter." 3C TIC: Cuadernos de desarrollo aplicados a las TIC 12, no. 1 (March 31, 2023): 65–81. http://dx.doi.org/10.17993/3ctic.2023.121.65-81.

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For several decades, the development of metal-oxide-semiconductor field-effect transistors have made available to us better circuit time and efficiency per function with each successive generation of CMOS technology. However, basic product and manufacturing technology limitations will make continuing transistor scaling difficult in the sub-32 nm zone. Field impact transistors with fins were developed. offered as a viable solution to the scalability difficulties. Fin field effect transistors can be made in the same way as regular CMOS transistors, allowing for a quick transition to production. The use of inserted-oxide FinFET technology was presented as a solution to continue transistor scaling. Due to gate fringing electric fields through the added oxide (SiO2) layers, the electromagnetic integrity of an iFinFET is superior to that of a FinFET. We discovered that the proposed mobility model functions admirably and that the Joule effect mostly influences the drain current and the heat source. The major goal of this work is to compare the performance characteristics of combinational logic using CMOS and FinFET technology. The inverting gate is modelled in HSPICE simulation on a 32nm transistor size utilising CMOS and FinFET structures, and respective performances, such as energy consumed, are examined.

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18

Zhao, Jian H. "Silicon Carbide Power Field-Effect Transistors." MRS Bulletin 30, no. 4 (April 2005): 293–98. http://dx.doi.org/10.1557/mrs2005.76.

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AbstractSilicon carbide power field-effect transistors, including power vertical-junction FETs (VJFETs) and metal oxide semiconductor FETs (MOSFETs), are unipolar power switches that have been investigated for high-temperature and high-power-density applications. Recent progress and results will be reviewed for different device designs such as normally-OFF and normally-ON VJFETs, double-implanted MOSFETs, and U-shaped-channel MOSFETs. The advantages and disadvantages of SiC VJFETs and MOSFETs will be discussed. Remaining challenges will be identified.

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19

Dobrovolsky, V. N., and A. N. Krolevets. "Theory of magnetic-field-sensitive metal–oxide–semiconductor field-effect transistors." Journal of Applied Physics 85, no. 3 (February 1999): 1956–60. http://dx.doi.org/10.1063/1.369187.

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20

Sverdlov, Viktor, and Seung-Bok Choi. "Editorial for the Special Issue on Magnetic and Spin Devices, Volume II." Micromachines 14, no. 11 (November 20, 2023): 2131. http://dx.doi.org/10.3390/mi14112131.

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Although the miniaturization of metal–oxide–semiconductor field effect transistors (MOSFETs)—the main driver behind an outstanding increase in the speed, performance, density, and complexity of modern integrated circuits—is continuing, numerous outstanding technological challenges in complimentary metal–oxide–semiconductor (CMOS) device miniaturization are slowly bringing the downscaling to saturation [...]

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21

Yang, Ji-Woon, Chang Seo Park, Casey E. Smith, Hemant Adhikari, Jeff Huang, Dawei Heh, Prashant Majhi, and Raj Jammy. "Erratum: “Mitigation of Complementary Metal–Oxide–Semiconductor Variability with Metal Gate Metal–Oxide–Semiconductor Field-Effect Transistors”." Japanese Journal of Applied Physics 50, no. 11R (November 1, 2011): 119201. http://dx.doi.org/10.7567/jjap.50.119201.

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22

Yang, Ji-Woon, Chang Seo Park, Casey E. Smith, Hemant Adhikari, Jeff Huang, Dawei Heh, Prashant Majhi, and Raj Jammy. "Erratum: “Mitigation of Complementary Metal–Oxide–Semiconductor Variability with Metal Gate Metal–Oxide–Semiconductor Field-Effect Transistors”." Japanese Journal of Applied Physics 50 (October 31, 2011): 119201. http://dx.doi.org/10.1143/jjap.50.119201.

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23

Belford, R. E., B. P. Guo, Q. Xu, S. Sood, A. A. Thrift, A. Teren, A. Acosta, L. A. Bosworth, and J. S. Zell. "Strain enhanced p-type metal oxide semiconductor field effect transistors." Journal of Applied Physics 100, no. 6 (September 15, 2006): 064903. http://dx.doi.org/10.1063/1.2335678.

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24

Lan, H. S., Y. T. Chen, William Hsu, H. C. Chang, J. Y. Lin, W. C. Chang, and C. W. Liu. "Electron scattering in Ge metal-oxide-semiconductor field-effect transistors." Applied Physics Letters 99, no. 11 (September 12, 2011): 112109. http://dx.doi.org/10.1063/1.3640237.

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25

Kleinsasser, A. W., and T. N. Jackson. "Critical currents of superconducting metal-oxide-semiconductor field-effect transistors." Physical Review B 42, no. 13 (November 1, 1990): 8716–19. http://dx.doi.org/10.1103/physrevb.42.8716.

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26

Surya, C., and T. Y. Hsiang. "Surface mobility fluctuations in metal-oxide-semiconductor field-effect transistors." Physical Review B 35, no. 12 (April 15, 1987): 6343–47. http://dx.doi.org/10.1103/physrevb.35.6343.

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27

Huang, Feng-Jung, and K. K. O. "Metal-oxide semiconductor field-effect transistors using Schottky barrier drains." Electronics Letters 33, no. 15 (1997): 1341. http://dx.doi.org/10.1049/el:19970904.

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28

Fiori, G., and G. Iannaccone. "Modeling of ballistic nanoscale metal-oxide-semiconductor field effect transistors." Applied Physics Letters 81, no. 19 (November 4, 2002): 3672–74. http://dx.doi.org/10.1063/1.1519349.

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29

Rumyantsev, S. L., N. Pala, M. S. Shur, R. Gaska, M. E. Levinshtein, M. Asif Khan, G. Simin, X. Hu, and J. Yang. "Low frequency noise in GaN metal semiconductor and metal oxide semiconductor field effect transistors." Journal of Applied Physics 90, no. 1 (July 2001): 310–14. http://dx.doi.org/10.1063/1.1372364.

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30

Agha, Firas, Yasir Naif, and Mohammed Shakib. "Review of Nanosheet Transistors Technology." Tikrit Journal of Engineering Sciences 28, no. 1 (May 20, 2021): 40–48. http://dx.doi.org/10.25130/tjes.28.1.05.

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Nano-sheet transistor can be defined as a stacked horizontally gate surrounding the channel on all direction. This new structure is earning extremely attention from research to cope the restriction of current Fin Field Effect Transistor (FinFET) structure. To further understand the characteristics of nano-sheet transistors, this paper presents a review of this new nano-structure of Metal Oxide Semiconductor Field Effect Transistor (MOSFET), this new device that consists of a metal gate material. Lateral nano-sheet FET is now targeting for 3nm Complementary MOS (CMOS) technology node. In this review, the structure and characteristics of Nano-Sheet FET (NSFET), FinFET and NanoWire FET (NWFET) under 5nm technology node are presented and compared. According to the comparison, the NSFET shows to be more impregnable to mismatch in ON current than NWFET. Furthermore, as comparing with other nanodimensional transistors, the NSFET has the superior control of gate all-around structures, also the NWFET realize lower mismatch in sub threshold slope (SS) and drain induced barrier lowering (DIBL).

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31

Bennett, Brian R., Mario G. Ancona, and J. Brad Boos. "Compound Semiconductors for Low-Power p-Channel Field-Effect Transistors." MRS Bulletin 34, no. 7 (July 2009): 530–36. http://dx.doi.org/10.1557/mrs2009.141.

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AbstractResearch in n-channel field-effect transistors based upon III–V compound semiconductors has been very productive over the last 30 years, with successful applications in a variety of high-speed analog circuits. For digital applications, complementary circuits are desirable to minimize static power consumption. Hence, p-channel transistors are also needed. Unfortunately, hole mobilities are generally much lower than electron mobilities for III–V compounds. This article reviews the recent work to enhance hole mobilities in antimonide-based quantum wells. Epitaxial heterostructures have been grown with the channel material in 1–2% compressive strain. The strain modifies the valence band structure, resulting in hole mobilities as high as 1500 cm2/Vs. The next steps toward an ultra-low-power complementary metal oxide semiconductor technology will include development of a compatible insulator technology and integration of n- and p-channel transistors.

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32

Palma, Fabrizio. "Self-Mixing Model of Terahertz Rectification in a Metal Oxide Semiconductor Capacitance." Electronics 9, no. 3 (March 14, 2020): 479. http://dx.doi.org/10.3390/electronics9030479.

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Metal oxide semiconductor (MOS) capacitance within field effect transistors are of great interest in terahertz (THz) imaging, as they permit high-sensitivity, high-resolution detection of chemical species and images using integrated circuit technology. High-frequency detection based on MOS technology has long been justified using a mechanism described by the plasma wave detection theory. The present study introduces a new interpretation of this effect based on the self-mixing process that occurs in the field effect depletion region, rather than that within the channel of the transistor. The proposed model formulates the THz modulation mechanisms of the charge in the potential barrier below the oxide based on the hydrodynamic semiconductor equations solved for the small-signal approximation. This approach explains the occurrence of the self-mixing process, the detection capability of the structure and, in particular, its frequency dependence. The dependence of the rectified voltage on the bias gate voltage, substrate doping, and frequency is derived, offering a new explanation for several previous experimental results. Harmonic balance simulations are presented and compared with the model results, fully validating the model’s implementation. Thus, the proposed model substantially improves the current understanding of THz rectification in semiconductors and provides new tools for the design of detectors.

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33

Lee, Su Yeon, Hyun Kyu Seo, Se Yeon Jeong, and Min Kyu Yang. "Improved Electrical Characteristics of Field Effect Transistors with GeSeTe-Based Ovonic Threshold Switching Devices." Materials 16, no. 12 (June 11, 2023): 4315. http://dx.doi.org/10.3390/ma16124315.

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Hyper-field effect transistors (hyper-FETs) are crucial in the development of low-power logic devices. With the increasing significance of power consumption and energy efficiency, conventional logic devices can no longer achieve the required performance and low-power operation. Next-generation logic devices are designed based on complementary metal-oxide-semiconductor circuits, and the subthreshold swing of existing metal-oxide semiconductor field effect transistors (MOSFETs) cannot be reduced below 60 mV/dec at room temperature owing to the thermionic carrier injection mechanism in the source region. Therefore, new devices must be developed to overcome these limitations. In this study, we present a novel threshold switch (TS) material, which can be applied to logic devices by employing ovonic threshold switch (OTS) materials, failure control of insulator–metal transition materials, and structural optimization. The proposed TS material is connected to a FET device to evaluate its performance. The results demonstrate that commercial transistors connected in series with GeSeTe-based OTS devices exhibit significantly lower subthreshold swing values, high on/off current ratios, and high durability of up to 108.

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34

Toumazou, Christofer, Tan Sri Lim Kok Thay, and Pantelis Georgiou. "A new era of semiconductor genetics using ion-sensitive field-effect transistors: the gene-sensitive integrated cell." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 372, no. 2012 (March 28, 2014): 20130112. http://dx.doi.org/10.1098/rsta.2013.0112.

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Semiconductor genetics is now disrupting the field of healthcare owing to the rapid parallelization and scaling of DNA sensing using ion-sensitive field-effect transistors (ISFETs) fabricated using commercial complementary metal -oxide semiconductor technology. The enabling concept of DNA reaction monitoring introduced by Toumazou has made this a reality and we are now seeing relentless scaling with Moore's law ultimately achieving the $100 genome. In this paper, we present the next evolution of this technology through the creation of the gene-sensitive integrated cell (GSIC) for label-free real-time analysis based on ISFETs. This device is derived from the traditional metal-oxide semiconductor field-effect transistor (MOSFET) and has electrical performance identical to that of a MOSFET in a standard semiconductor process, yet is capable of incorporating DNA reaction chemistries for applications in single nucleotide polymorphism microarrays and DNA sequencing. Just as application-specific integrated circuits, which are developed in much the same way, have shaped our consumer electronics industry and modern communications and memory technology, so, too, do GSICs based on a single underlying technology principle have the capacity to transform the life science and healthcare industries.

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35

RUMYANTSEV, S. L., N. PALA, M. S. SHUR, M. E. LEVINSHTEIN, P. A. IVANOV, M. ASIF KHAN, G. SIMIN, et al. "LOW-FREQUENCY NOISE IN AlGaN/GaN HETEROSTRUCTURE FIELD EFFECT TRANSISTORS AND METAL OXIDE SEMICONDUCTOR HETEROSTRUCTURE FIELD EFFECT TRANSISTORS." Fluctuation and Noise Letters 01, no. 04 (December 2001): L221—L226. http://dx.doi.org/10.1142/s0219477501000469.

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The dependence of the 1/f noise on 2D electron concentration in the channel n Ch of AlGaN/GaN Heterostructure Field Effect Transistors and Metal Oxide Semiconductor Heterostructure Field Effect Transistors has been studied and compared. The dependencies of Hooge parameter αCh for the noise sources located in the channel of the transistors on sheet electron concentration are found identical for both types of devices. The increase of the Hooge parameter αCh with the decrease of the channel concentration observed in both types of devices confirms that the noise sources are located in the region under the gate in the AlGaN/GaN heterostructure and that electron tunneling from the 2D electron gas into the traps in GaN or AlGaN layers is a probable noise mechanism.

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36

Preisler, E. J., S. Guha, B. R. Perkins, D. Kazazis, and A. Zaslavsky. "Ultrathin epitaxial germanium on crystalline oxide metal-oxide-semiconductor-field-effect transistors." Applied Physics Letters 86, no. 22 (May 30, 2005): 223504. http://dx.doi.org/10.1063/1.1941451.

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37

Yang, Jianan, John P. Denton, and Gerold W. Neudeck. "Edge transistor elimination in oxide trench isolated N-channel metal–oxide–semiconductor field effect transistors." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 19, no. 2 (2001): 327. http://dx.doi.org/10.1116/1.1358854.

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38

Sun, Y., S. E. Thompson, and T. Nishida. "Physics of strain effects in semiconductors and metal-oxide-semiconductor field-effect transistors." Journal of Applied Physics 101, no. 10 (May 15, 2007): 104503. http://dx.doi.org/10.1063/1.2730561.

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39

Natori, Kenji. "Ballistic metal‐oxide‐semiconductor field effect transistor." Journal of Applied Physics 76, no. 8 (October 15, 1994): 4879–90. http://dx.doi.org/10.1063/1.357263.

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40

Maity, Heranmoy. "A New Approach to Design and Implementation of 2-Input XOR Gate Using 4-Transistor." Micro and Nanosystems 12, no. 3 (December 1, 2020): 240–42. http://dx.doi.org/10.2174/1876402912666200309120205.

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Aim: This paper proposed the design and implementation of a 2-input XOR gate using 4- transistor. Method : The XOR gate can be designed using NOT gate and 2:1 multiplexer. The NOT gate is designed using two metal–oxide–semiconductor field-effect transistors MOSFETs and an approximate 2:1 multiplexer. The 2:1 multiplexer is designed using two MOSFETs. So, an XOR gate can be designed using four transistors. Results: The proposed work theoretically and experimentally describes the 2-input XOR gate using 4- transistor. The proposed work was verified using Xilinx (ISE Design Suite).

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41

Kaneko, Kentaro, Yoshito Ito, Takayuki Uchida, and Shizuo Fujita. "Growth and metal–oxide–semiconductor field-effect transistors of corundum-structured alpha indium oxide semiconductors." Applied Physics Express 8, no. 9 (September 1, 2015): 095503. http://dx.doi.org/10.7567/apex.8.095503.

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42

Ferain, Isabelle, Cynthia A. Colinge, and Jean-Pierre Colinge. "Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors." Nature 479, no. 7373 (November 2011): 310–16. http://dx.doi.org/10.1038/nature10676.

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43

Nakatsuka, Nako, Kyung-Ae Yang, John M. Abendroth, Kevin M. Cheung, Xiaobin Xu, Hongyan Yang, Chuanzhen Zhao, et al. "Aptamer–field-effect transistors overcome Debye length limitations for small-molecule sensing." Science 362, no. 6412 (September 6, 2018): 319–24. http://dx.doi.org/10.1126/science.aao6750.

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Detection of analytes by means of field-effect transistors bearing ligand-specific receptors is fundamentally limited by the shielding created by the electrical double layer (the “Debye length” limitation). We detected small molecules under physiological high–ionic strength conditions by modifying printed ultrathin metal-oxide field-effect transistor arrays with deoxyribonucleotide aptamers selected to bind their targets adaptively. Target-induced conformational changes of negatively charged aptamer phosphodiester backbones in close proximity to semiconductor channels gated conductance in physiological buffers, resulting in highly sensitive detection. Sensing of charged and electroneutral targets (serotonin, dopamine, glucose, and sphingosine-1-phosphate) was enabled by specifically isolated aptameric stem-loop receptors.

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44

Palma, Fabrizio. "Physical Insights into THz Rectification in Metal–Oxide–Semiconductor Transistors." Electronics 13, no. 7 (March 25, 2024): 1192. http://dx.doi.org/10.3390/electronics13071192.

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Metal–oxide–semiconductor field-effect transistors (MOSFETs) have proven to be effective devices for rectifying electromagnetic radiation at extremely high frequencies, approximately 1 THz. This paper presents a new interpretation of the THz rectification process in the structure of an MOS transistor. The rectification depends on the nonlinear effect of the carrier dynamics. The paper shows that the so-called self-mixing effect occurs within the interface region between the source and the channel. The basic tool used numerical TCAD simulations, which offer a direct interpretation of different aspects of this interaction. The complex, 2D effect is examined in terms of its basic aspects by comparing the MOS structure with a simplified case study structure. We demonstrate that a contribution to the output-rectified voltage detectable at the drain arises from the charging of the drain well capacitance due to the diffusion of excess electrons from the self-mixing interaction occurring at the source barrier. In addition, the paper provides a quantitative description of the rectification process through the definition of the output equivalent circuit, offering a new perspective for the design of detection systems.

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45

Haugerud, B. M., L. A. Bosworth, and R. E. Belford. "Mechanically induced strain enhancement of metal–oxide–semiconductor field effect transistors." Journal of Applied Physics 94, no. 6 (September 15, 2003): 4102–7. http://dx.doi.org/10.1063/1.1602562.

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46

Chen, Qiang, and James D. Meindl. "Nanoscale metal–oxide–semiconductor field-effect transistors: scaling limits and opportunities." Nanotechnology 15, no. 10 (July 24, 2004): S549—S555. http://dx.doi.org/10.1088/0957-4484/15/10/009.

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47

Gaubert, Philippe, Akinobu Teramoto, Shigetoshi Sugawa, and Tadahiro Ohmi. "Hole Mobility in Accumulation Mode Metal–Oxide–Semiconductor Field-Effect Transistors." Japanese Journal of Applied Physics 51, no. 4S (April 1, 2012): 04DC07. http://dx.doi.org/10.7567/jjap.51.04dc07.

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48

Irokawa, Y., Y. Nakano, M. Ishiko, T. Kachi, J. Kim, F. Ren, B. P. Gila, et al. "MgO/p-GaN enhancement mode metal-oxide semiconductor field-effect transistors." Applied Physics Letters 84, no. 15 (April 12, 2004): 2919–21. http://dx.doi.org/10.1063/1.1704876.

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49

Omura, Yasuhisa. "Hooge parameter in buried-channel metal-oxide-semiconductor field-effect transistors." Journal of Applied Physics 91, no. 3 (February 2002): 1378–84. http://dx.doi.org/10.1063/1.1434543.

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50

Navid, Reza, Christoph Jungemann, Thomas H. Lee, and Robert W. Dutton. "High-frequency noise in nanoscale metal oxide semiconductor field effect transistors." Journal of Applied Physics 101, no. 12 (June 15, 2007): 124501. http://dx.doi.org/10.1063/1.2740345.

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