Готові списки джерел за темами / Memristance

Зміст

Статті в журналах
Дисертації
Книги
Частини книг
Тези доповідей конференцій

Добірка наукової літератури з теми "Memristance"

Автор: Grafiati

Опубліковано: 14 грудня 2024

Оформте джерело за APA, MLA, Chicago, Harvard та іншими стилями

Оберіть тип джерела:

Ознайомтеся зі списками актуальних статей, книг, дисертацій, тез та інших наукових джерел на тему "Memristance".

Біля кожної праці в переліку літератури доступна кнопка «Додати до бібліографії». Скористайтеся нею – і ми автоматично оформимо бібліографічне посилання на обрану працю в потрібному вам стилі цитування: APA, MLA, «Гарвард», «Чикаго», «Ванкувер» тощо.

Також ви можете завантажити повний текст наукової публікації у форматі «.pdf» та прочитати онлайн анотацію до роботи, якщо відповідні параметри наявні в метаданих.

Статті в журналах з теми "Memristance"

Yang, Le, and Zhixia Ding. "A Memristor-Based High-Resolution A/D Converter." Electronics 11, no. 9 (May 3, 2022): 1470. http://dx.doi.org/10.3390/electronics11091470.

Повний текст джерела

Анотація:

Based on the voltage threshold adaptive memristor (VTEAM) model, this paper proposes a circuit design of a memristor-based A/D converter, which can achieve high-resolution conversion by simple configuration. For this A/D converter, there are the input voltage stage and the reference voltage stage in one conversion. According to the memristance change in the two stages, the input analog voltage is converted as the corresponding digital value. In the input voltage stage, the memristance increases from the initial memristance. Meanwhile, the counter rises its value from zero to the maximum. Next, the memristance returns to the initial memristance in the reference voltage stage. At the same time, the counting value starts to increase from zero again. Then, the input analog voltage is mapped to the eventual counting value of the reference voltage stage. The simulations of the memristor-based A/D converter demonstrate that it has good conversion performance. The proposed memristor-based A/D converter not only has more brilliant performance than the CMOS A/D converter, but also has the advantages over existing memristor-based A/D converters of anti-interference ability and high resolution.

Стилі APA, Harvard, Vancouver, ISO та ін.

Ukil, Abhisek. "Memristance View of Piezoelectricity." IEEE Sensors Journal 11, no. 10 (October 2011): 2514–17. http://dx.doi.org/10.1109/jsen.2011.2114878.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Martinsen, Ø. G., S. Grimnes, C. A. Lütken, and G. K. Johnsen. "Memristance in human skin." Journal of Physics: Conference Series 224 (April 1, 2010): 012071. http://dx.doi.org/10.1088/1742-6596/224/1/012071.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Cam, Zehra Gulru, and Herman Sedef. "A New Floating Memristance Simulator Circuit Based on Second Generation Current Conveyor." Journal of Circuits, Systems and Computers 26, no. 02 (November 3, 2016): 1750029. http://dx.doi.org/10.1142/s0218126617500293.

Повний текст джерела

Анотація:

In this paper, a new floating analog memristance simulator circuit based on second generation current conveyors and passive elements is proposed. Theoretical derivations are presented which decribe the circuit characteristics. The hardware of proposed simulator circuit is built using commercially available components. Theoretical derivations are validated with PSPICE simulation and experimental results. Performance of circuit was tested with simple example circuits. All results show that proposed simulator circuit provides frequency dependent pinched hysteresis loop and nonvolatility features. Exciting frequency, minimum and maximum memristance values and memristance range can be adjustable with simple passive element values. Simulator circuit has a frequency range of 1[Formula: see text]Hz to 40[Formula: see text]kHz.

Стилі APA, Harvard, Vancouver, ISO та ін.

Yu, Bo, Yifei Pu, Qiuyan He, and Xiao Yuan. "Principle and Application of Frequency-Domain Characteristic Analysis of Fractional-Order Memristor." Micromachines 13, no. 9 (September 12, 2022): 1512. http://dx.doi.org/10.3390/mi13091512.

Повний текст джерела

Анотація:

Scaling fractional-order memristor circuit is important for realizing a fractional-order memristor. However, the effective operating-frequency range, operation order, and fractional-order memristance of the scaling fractional-order memristor circuit have not been studied thoroughly; that is, the fractional-order memristance in the effective operating-frequency range has not been calculated quantitatively. The fractional-order memristance is a similar and equally important concept as memristance, memcapacitance, and meminductance. In this paper, the frequency-domain characteristic-analysis principle of the fractional-order memristor is proposed based on the order- and F-frequency characteristic functions. The reasons for selecting the order- and F-frequency characteristic functions are explained. Subsequently, the correctness of the frequency-domain characteristic analysis using the order- and F-frequency characteristic functions is verified from multiple perspectives. Finally, the principle of the frequency-domain characteristic analysis is applied to the recently realized chain-scaling fractional-order memristor circuit. The results of this study indicate that the principle of the frequency-domain characteristic analysis of the fractional-order memristor can successfully calculate the fractional-order memristance of the chain-scaling fractional-order memristor circuit. The proposed principle of frequency-domain characteristic analysis can also be applied to mem-elements, such as memristors, memcapacitors, and meminductors. The main contribution of this study is the principle of the frequency-domain characteristic analysis of the fractional-order memristor based on the order- and F-frequency characteristic functions.

Стилі APA, Harvard, Vancouver, ISO та ін.

MUTLU, Reşat, and Ertuğrul KARAKULAK. "A methodology for memristance calculation." TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES 22 (2014): 121–31. http://dx.doi.org/10.3906/elk-1205-16.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Banchuin, Rawid. "On the Memristances, Parameters, and Analysis of the Fractional Order Memristor." Active and Passive Electronic Components 2018 (November 1, 2018): 1–14. http://dx.doi.org/10.1155/2018/3408480.

Повний текст джерела

Анотація:

In this work, the analytical expressions of memristances, related parameters, and time domain behavioral analysis of the fractional order memristor have been proposed. Both DC with arbitrary delay and many AC waveforms including arbitrary phase sinusoidal and cosinusoidal waveform along with arbitrary periodic waveform have been taken into account. Unlike the previous works, the formerly ignored dimensional consistency has been taken into account and the analytical modelling of the boundary effect has been performed. Moreover, both transient and asymptotic behaviors of the fractional order memristor excited by AC waveform have been distinguished and analyzed. The effect of phase of AC waveform has also been studied. The influence of the fractional order to the areas of voltage-current hysteresis loop and memristance-current lissajous curve has also been clearly discussed and the usage of fractional order memristor in the memristor based circuit has also been demonstrated.

Стилі APA, Harvard, Vancouver, ISO та ін.

Le, Minh, Thi Kim Hang Pham, and Son Ngoc Truong. "Noise and Memristance Variation Tolerance of Single Crossbar Architectures for Neuromorphic Image Recognition." Micromachines 12, no. 6 (June 13, 2021): 690. http://dx.doi.org/10.3390/mi12060690.

Повний текст джерела

Анотація:

We performed a comparative study on the Gaussian noise and memristance variation tolerance of three crossbar architectures, namely the complementary crossbar architecture, the twin crossbar architecture, and the single crossbar architecture, for neuromorphic image recognition and conducted an experiment to determine the performance of the single crossbar architecture for simple pattern recognition. Ten grayscale images with the size of 32 × 32 pixels were used for testing and comparing the recognition rates of the three architectures. The recognition rates of the three memristor crossbar architectures were compared to each other when the noise level of images was varied from −10 to 4 dB and the percentage of memristance variation was varied from 0% to 40%. The simulation results showed that the single crossbar architecture had the best Gaussian noise input and memristance variation tolerance in terms of recognition rate. At the signal-to-noise ratio of −10 dB, the single crossbar architecture produced a recognition rate of 91%, which was 2% and 87% higher than those of the twin crossbar architecture and the complementary crossbar architecture, respectively. When the memristance variation percentage reached 40%, the single crossbar architecture had a recognition rate as high as 67.8%, which was 1.8% and 9.8% higher than the recognition rates of the twin crossbar architecture and the complementary crossbar architecture, respectively. Finally, we carried out an experiment to determine the performance of the single crossbar architecture with a fabricated 3 × 3 memristor crossbar based on carbon fiber and aluminum film. The experiment proved successful implementation of pattern recognition with the single crossbar architecture.

Стилі APA, Harvard, Vancouver, ISO та ін.

Liu, Xiaoxin, Lanqing Zou, Chenyang Huang, Na Bai, Kanhao Xue, Huajun Sun, and Xiangshui Miao. "Analog Memristor-Based Dynamic Programmable Analog Filter." Journal of Physics: Conference Series 2356, no. 1 (October 1, 2022): 012008. http://dx.doi.org/10.1088/1742-6596/2356/1/012008.

Повний текст джерела

Анотація:

The memristor study now generally exhibit threshold voltage characteristics. The memristance changes when the voltage across the memristor is greater than the threshold voltage. Otherwise, the memristance is almost constant. Based on this feature, we design a general-purpose memristor programmable circuit that is simple to operate. In the field of communication and signal processing, programmable analog filters are required, and memristors with multi-valued characteristic are suitable as programmable impedance elements for such circuits. Through simulation and physics experiments, we demonstrate a memristor-based programmable low-pass filter using the designed programmable circuit to realize the dynamic adjustment of circuit parameters.

Стилі APA, Harvard, Vancouver, ISO та ін.

Bunnam, Thanasin, Ahmed Soltan, Danil Sokolov, Oleg Maevsky, and Alex Yakovlev. "Toward Designing Thermally-Aware Memristance Decoder." IEEE Transactions on Circuits and Systems I: Regular Papers 66, no. 11 (November 2019): 4337–47. http://dx.doi.org/10.1109/tcsi.2019.2925021.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Більше джерел

Дисертації з теми "Memristance"

Du, Nan. "Beyond "More than Moore": Novel applications of BiFeO3 (BFO)-based nonvolatile resistive switches." Doctoral thesis, Universitätsbibliothek Chemnitz, 2016. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-202508.

Повний текст джерела

Анотація:

The size reduction of transistors has been the main reason for a successful development of semiconductor integrated circuits over the last decades. Because of the physically limited downscaling of transistors, alternative technologies namely the information processing and nonvolatile resistive switches (also termed memristors) have come into focus. Memristors reveal a fast switching speed, long retention time, and stable endurance. Nonvolatile analog bipolar resistive switching with a considerable large On/Off ratio is reported in BiFeO3 (BFO)-based resistive switches. So far resistive switches are mainly applied in memory applications or logic operations. Given the excellent properties of BFO based memristors, the further exploration of functionalities for memristive devices is required. A new approach for hardware based cryptographic system was developed within the framework of this dissertation. By studying the power conversion efficiencies on BFO memristor at various harmonics, it has been shown that two sets of clearly distinguishable power ratios are achievable when the BFO memristor is set into high or into low resistance state. Thus, a BFO-based binary encoding system can be established. As an example the unrecoverable seizure information from encoded medical data suggests the proper functioning of the proposed encryption system. Aside from cryptographic functionality, the single pairing spike timing dependent plasticity (STDP) in BFO-based artificial synapses is demonstrated, which can be considered as the cornerstone for energy-efficient and fast hardware-based neuromorphic networks. In comparison to the biological driven realistic way, only single one pairing of pre- and postsynaptic spikes is applied to the BFO-based artificial synapse instead of 60-80 pairings. Thus, the learning time constant of STDP function can be reduced from 25 ms to 125 us
In den letzten Jahrzehnten war die Größenreduktion von Transistoren einer der Hauptgründe für die Leistungssteigerung von integrierten Halbleiterschaltungen. Aufgrund des physikalisch beschränkten Skalierungspotentials, werden alternative Technologien für Halbleiterschaltungen entwickelt. Dazu zählen neuartige Widerstandsschalter, sogenannte Memristoren, welche wegen ihrer schnellen Schaltgeschwindigkeit, langen Speicherzeit und stabilen Haltbarkeit in den Fokus der Forschung gerückt sind. Das nichtflüchtige analoge bipolare Schalten des Widerstandwertes mit einem On/Off Verhältnis größer als 100 wurde in BiFeO 3 (BFO)-basierten Widerstands-schaltern beobachtet. Bisher wurden Widerstandsschalter hauptsächlich als Speicher oder in rekonfigurierbaren Logikschaltungen verwendet. Aufgrund der ausgezeichneten Eigenschaften von BFO-basierten Memristoren, ist die Untersuchung weiterer neuer Funktionalitäten vielversprechend. Als neuer Ansatz für ein Hardware-basiertes Kryptosystem wird in der vorliegenden Arbeit die Ausnutzung des Leistungsübertragungskoeffizienten in BFO Memristoren vorgeschlagen. Mit Hilfe der unterschiedlichen Oberschwingungen, welche von einem BFO Memristor im ON und OFF Zustand generiert werden, wurde ein Kryptosystem zum Kodieren binärer Daten entwickelt. Ein Test des Hardware-basierten Kryptosystems an Biodaten ergab, dass die kodierten Biodaten keine vorhersagbare Korrelation mehr enthielten. In der vorliegenden Arbeit wurden darüberhinaus BFO-basierte künstliche Synapsen mit einer Aktionspotentials-Intervall abhängigen Plastizität (STDP) für Einzelpulse entwickelt. Diese Einzelpuls-STDP legt den Grundstein für energieffiziente und schnelle neuromorphe Netzwerke mit künstlichen Synapsen. Im Vergleich zu biologischen Synapsen mit einer 60-80-Puls-STDP und einem Lernfenster auf der ms-Zeitskale, konnte das Lernfenster von BFO-basierten künstlichen Synapsen von 25 ms auf 125 μs reduziert werden. Solch ein schnelles Lernen ermöglicht auch die extreme Reduzierung des Leistungsverbrauchs in neuromorphen Netzwerken

Стилі APA, Harvard, Vancouver, ISO та ін.

Wu, Jiaming. "A modular dynamic Neuro-Synaptic platform for Spiking Neural Networks." Electronic Thesis or Diss., université Paris-Saclay, 2024. http://www.theses.fr/2024UPASP145.

Повний текст джерела

Анотація:

Que le réseau de neurones soit biologique ou artificiel, il possède une unité de calcul fondamentale : le neurone. Ces neurones, interconnectés par des synapses, forment ainsi des réseaux complexes qui permettent d’obtenir une pluralité de fonctions. De même, le réseau de neurones neuromorphique, ou plus généralement les ordinateurs neuromorphiques, nécessitent également ces deux éléments fondamentaux que sont les neurones et les synapses. Dans ce travail, nous introduisons une unité matérielle neuro-synaptique à impulsions, inspirée de la biologie et entièrement réalisée avec des composants électroniques conventionnels. Le modèle de cette unité neuro-synaptique repose sur les modèles théoriques classiques du neurone à impulsions et des courants synaptiques et membranaires. Le neurone à impulsions est entièrement analogique et un dispositif memristif, dont les composants électroniques sont facilement disponibles sur le marché, permet d’assurer l’excitabilité du neurone. En ce qui concerne les courants synaptiques et membranaires, leur intensité est ajustable, et ils possèdent une dynamique biomimétique, incluant à la fois des courants excitateurs et inhibiteurs. Tous les paramètres du modèle sont ajustables et permettant ainsi d'adapter le système neuro-synaptique. Cette flexibilité et cette adaptabilité sont des caractéristiques essentielles dans la réalisation d’applications telles que les interfaces cerveau-machine. En nous appuyant sur ces deux unités modulaires, le neurone et la synapse, nous pouvons concevoir des motifs fondamentaux des réseaux de neurones. Ces motifs servent ainsi de base pour implémenter des réseaux aux fonctionnalités plus complexes, telles que des mémoires dynamiques ou des réseaux locomoteurs spinaux (Central Pattern Generator). De plus, il sera possible d’améliorer le modèle existant, que ce soit en y intégrant des memristors à base d’oxydes (actuellement étudiés en science des matériaux), ou en le déployant à grande échelle (VLSI) afin de réaliser des réseaux d’ordres de grandeurs supérieures. L’unité neuro-synaptique peut être considérée comme un bloc fondamental pour implémenter des réseaux neuronaux à impulsions de géométrie arbitraire. Son design compact et modulaire, associé à la large disponibilité des composants électroniques, font de notre plateforme une option attrayante de développement pour construire des interfaces neuronales, que ce soit dans les domaines médical, robotique, ou des systèmes d'intelligence artificielle (par exemple le calcul par réservoir), etc
Biological and artificial neural networks share a fundamental computational unit: the neuron. These neurons are coupled by synapses, forming complex networks that enable various functions. Similarly, neuromorphic hardware, or more generally neuro-computers, also require two hardware elements: neurons and synapses. In this work, we introduce a bio-inspired spiking Neuro-Synaptic hardware unit, fully implemented with conventional electronic components. Our hardware is based on a textbook theoretical model of the spiking neuron, and its synaptic and membrane currents. The spiking neuron is fully analog and the various models that we introduced are defined by their hardware implementation. The neuron excitability is achieved through a memristive device made from off-the-shelf electronic components. Both synaptic and membrane currents feature tunable intensities and bio-mimetic dynamics, including excitatory and inhibitory currents. All model parameters are adjustable, allowing the system to be tuned to bio-compatible timescales, which is crucial in applications such as brain-machine interfaces. Building on these two modular units, we demonstrate various basic neural network motifs (or neuro-computing primitives) and show how to combine these fundamental motifs to implement more complex network functionalities, such as dynamical memories and central pattern generators. Our hardware design also carries potential extensions for integrating oxide-based memristors (which are widely studied in material science),or porting the design to very large-scale integration (VLSI) to implement large-scale networks. The Neuro-Synaptic unit can be considered as a building block for implementing spiking neural networks of arbitrary geometry. Its compact and modular design, as well as the wide availability of ordinary electronic components, makes our approach an attractive platform for building neural interfaces in medical devices, robotics, and artificial intelligence systems such as reservoir computing

Стилі APA, Harvard, Vancouver, ISO та ін.

Maier, Patrick [Verfasser], Lukas [Gutachter] Worschech, Vladimir [Gutachter] Dyakonov, and Ronny [Gutachter] Thomale. "Memristanz und Memkapazität von Quantenpunkt-Speichertransistoren: Realisierung neuromorpher und arithmetischer Operationen / Patrick Maier ; Gutachter: Lukas Worschech, Vladimir Dyakonov, Ronny Thomale." Würzburg : Universität Würzburg, 2018. http://d-nb.info/1163201863/34.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Du, Nan. "Beyond "More than Moore": Novel applications of BiFeO3 (BFO)-based nonvolatile resistive switches." Doctoral thesis, 2015. https://monarch.qucosa.de/id/qucosa%3A20443.

Повний текст джерела

Анотація:

The size reduction of transistors has been the main reason for a successful development of semiconductor integrated circuits over the last decades. Because of the physically limited downscaling of transistors, alternative technologies namely the information processing and nonvolatile resistive switches (also termed memristors) have come into focus. Memristors reveal a fast switching speed, long retention time, and stable endurance. Nonvolatile analog bipolar resistive switching with a considerable large On/Off ratio is reported in BiFeO3 (BFO)-based resistive switches. So far resistive switches are mainly applied in memory applications or logic operations. Given the excellent properties of BFO based memristors, the further exploration of functionalities for memristive devices is required. A new approach for hardware based cryptographic system was developed within the framework of this dissertation. By studying the power conversion efficiencies on BFO memristor at various harmonics, it has been shown that two sets of clearly distinguishable power ratios are achievable when the BFO memristor is set into high or into low resistance state. Thus, a BFO-based binary encoding system can be established. As an example the unrecoverable seizure information from encoded medical data suggests the proper functioning of the proposed encryption system. Aside from cryptographic functionality, the single pairing spike timing dependent plasticity (STDP) in BFO-based artificial synapses is demonstrated, which can be considered as the cornerstone for energy-efficient and fast hardware-based neuromorphic networks. In comparison to the biological driven realistic way, only single one pairing of pre- and postsynaptic spikes is applied to the BFO-based artificial synapse instead of 60-80 pairings. Thus, the learning time constant of STDP function can be reduced from 25 ms to 125 us.
In den letzten Jahrzehnten war die Größenreduktion von Transistoren einer der Hauptgründe für die Leistungssteigerung von integrierten Halbleiterschaltungen. Aufgrund des physikalisch beschränkten Skalierungspotentials, werden alternative Technologien für Halbleiterschaltungen entwickelt. Dazu zählen neuartige Widerstandsschalter, sogenannte Memristoren, welche wegen ihrer schnellen Schaltgeschwindigkeit, langen Speicherzeit und stabilen Haltbarkeit in den Fokus der Forschung gerückt sind. Das nichtflüchtige analoge bipolare Schalten des Widerstandwertes mit einem On/Off Verhältnis größer als 100 wurde in BiFeO 3 (BFO)-basierten Widerstands-schaltern beobachtet. Bisher wurden Widerstandsschalter hauptsächlich als Speicher oder in rekonfigurierbaren Logikschaltungen verwendet. Aufgrund der ausgezeichneten Eigenschaften von BFO-basierten Memristoren, ist die Untersuchung weiterer neuer Funktionalitäten vielversprechend. Als neuer Ansatz für ein Hardware-basiertes Kryptosystem wird in der vorliegenden Arbeit die Ausnutzung des Leistungsübertragungskoeffizienten in BFO Memristoren vorgeschlagen. Mit Hilfe der unterschiedlichen Oberschwingungen, welche von einem BFO Memristor im ON und OFF Zustand generiert werden, wurde ein Kryptosystem zum Kodieren binärer Daten entwickelt. Ein Test des Hardware-basierten Kryptosystems an Biodaten ergab, dass die kodierten Biodaten keine vorhersagbare Korrelation mehr enthielten. In der vorliegenden Arbeit wurden darüberhinaus BFO-basierte künstliche Synapsen mit einer Aktionspotentials-Intervall abhängigen Plastizität (STDP) für Einzelpulse entwickelt. Diese Einzelpuls-STDP legt den Grundstein für energieffiziente und schnelle neuromorphe Netzwerke mit künstlichen Synapsen. Im Vergleich zu biologischen Synapsen mit einer 60-80-Puls-STDP und einem Lernfenster auf der ms-Zeitskale, konnte das Lernfenster von BFO-basierten künstlichen Synapsen von 25 ms auf 125 μs reduziert werden. Solch ein schnelles Lernen ermöglicht auch die extreme Reduzierung des Leistungsverbrauchs in neuromorphen Netzwerken.

Стилі APA, Harvard, Vancouver, ISO та ін.

Maier, Patrick. "Memristanz und Memkapazität von Quantenpunkt-Speichertransistoren: Realisierung neuromorpher und arithmetischer Operationen." Doctoral thesis, 2018. https://nbn-resolving.org/urn:nbn:de:bvb:20-opus-164234.

Повний текст джерела

Анотація:

In dieser Arbeit werden Quantenpunkt-Speichertransistoren basierend auf modulationsdotierten GaAs/AlGaAs Heterostrukturen mit vorpositionierten InAs Quantenpunkten vorgestellt, welche in Abhängigkeit der Ladung auf den Quantenpunkten unterschiedliche Widerstände und Kapazitäten aufweisen. Diese Ladungsabhängigkeiten führen beim Anlegen von periodischen Spannungen zu charakteristischen, durch den Ursprung gehenden Hysteresen in der Strom-Spannungs- und der Ladungs-Spannungs-Kennlinie. Die ladungsabhängigen Widerstände und Kapazitäten ermöglichen die Realisierung von neuromorphen Operationen durch Nachahmung von synaptischen Funktionalitäten und arithmetischen Operationen durch Integration von Spannungs- und Lichtpulsen
In this thesis, state-dependent resistances and capacitances in quantum dot floating gate transistors based on modulation doped GaAs/AlGaAs heterostructures with site-controlled InAs quantum dots are presented. The accumulation of electrons in the quantum dots simultaneously increases the resistance and decreases the capacitance, which leads to characteristic pinched hysteresis loops in the current-voltage- and the charge-voltage-characteristics when applying periodic input signals. The concurrent resistance and capacitance switching enables the realization of neuromorphic operations via mimicking of synaptic functionalities and arithmetic operations via the integration of voltage and light pulses

Стилі APA, Harvard, Vancouver, ISO та ін.

Книги з теми "Memristance"

System Design with Memristor Technologies. Institution of Engineering & Technology, 2018.

Знайти повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Частини книг з теми "Memristance"

Huang, Lixing, Jietao Diao, Shuhua Teng, Zhiwei Li, Wei Wang, Sen Liu, Minghou Li, and Haijun Liu. "A Method for Obtaining Highly Robust Memristor Based Binarized Convolutional Neural Network." In Proceeding of 2021 International Conference on Wireless Communications, Networking and Applications, 813–22. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-2456-9_82.

Повний текст джерела

Анотація:

AbstractRecently, memristor based binarized convolutional neural network has been widely investigated owing to its strong processing capability, low power consumption and high computing efficiency.However, it has not been widely applied in the field of embedded neuromorphic computing for manufacturing technology of the memristor being not mature. With respect to this, we propose a method for obtaining highly robust memristor based binarized convolutional neural network. To demonstrate the performance of the method, a convolutional neural network architecture with two layers is used for simulation, and the simulation results show that binarized convolutional neural network can still achieve more than 96.75% recognition rate on MNIST dataset under the condition of 80% yield of the memristor array, and the recognition rate is 94.53% when the variation of memristance is 26%, and it is 94.66% when the variation of the neuron output is 0.8.

Стилі APA, Harvard, Vancouver, ISO та ін.

Amirsoleimani, Amirali, Tony Liu, Fabien Alibart, Serge Eccofey, Yao-Feng Chang, Dominique Drouin, and Roman Genov. "Mitigating State-Drift in Memristor Crossbar Arrays for Vector Matrix Multiplication." In Memristor - An Emerging Device for Post-Moore’s Computing and Applications. IntechOpen, 2021. http://dx.doi.org/10.5772/intechopen.100246.

Повний текст джерела

Анотація:

In this Chapter, we review the recent progress on resistance drift mitigation techniques for resistive switching memory devices (specifically memristors) and its impact on the accuracy in deep neural network applications. In the first section of the chapter, we investigate the importance of soft errors and their detrimental impact on memristor-based vector–matrix multiplication (VMM) platforms performance specially the memristance state-drift induced by long-term recurring inference operations with sub-threshold stress voltage. Also, we briefly review some currently developed state-drift mitigation methods. In the next section of the chapter, we will discuss an adaptive inference technique with low hardware overhead to mitigate the memristance drift in memristive VMM platform by using optimization techniques to adjust the inference voltage characteristic associated with different network layers. Also, we present simulation results and performance improvements achieved by applying the proposed inference technique by considering non-idealities for various deep network applications on memristor crossbar arrays. This chapter suggests that a simple low overhead inference technique can revive the functionality, enhance the performance of memristor-based VMM arrays and significantly increases their lifetime which can be a very important factor toward making this technology as a main stream player in future in-memory computing platforms.

Стилі APA, Harvard, Vancouver, ISO та ін.

Тези доповідей конференцій з теми "Memristance"

Ntinas, Vasileios, Antonio Rubio, Georgios Ch Sirakoulis, Rosana Rodriguez, and Montserrat Nafria. "Experimental Investigation of Memristance Enhancement." In 2019 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). IEEE, 2019. http://dx.doi.org/10.1109/nanoarch47378.2019.181299.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Bunnam, Thanasin, Ahmed Soltan, Danil Sokolov, Alex Yakovlev, and Oleg Maevsky. "Toward Designing Thermally-Aware Memristance Decoder." In 2020 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2020. http://dx.doi.org/10.1109/iscas45731.2020.9181044.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Gale, Ella. "The Memory-Conservation Theory of Memristance." In 2014 UKSim-AMSS 16th International Conference on Modelling and Simulation (UKSim). IEEE, 2014. http://dx.doi.org/10.1109/uksim.2014.57.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Rose, Garrett S., Robinson Pino, and Qing Wu. "Exploiting memristance for low-energy neuromorphic computing hardware." In 2011 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2011. http://dx.doi.org/10.1109/iscas.2011.5938208.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Budhathoki, Ram Kaji, Maheshwar Pd Sah, Shyam Prasad Adhikari, and Hyongsuk Kim. "Composite memristance of parallel and serial memristor circuits." In 2013 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2013. http://dx.doi.org/10.1109/iscas.2013.6571819.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Karafyllidis, Ioannis, Georgios Ch Sirakoulis, and Panagiotis Dimitrakis. "Representation of Qubit States using 3D Memristance Spaces." In NANOARCH '18: IEEE/ACM International Symposium on Nanoscale Architectures. New York, NY, USA: ACM, 2018. http://dx.doi.org/10.1145/3232195.3232197.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Cam Taskiran, Zehra Gulru, and Murat Taskiran. "A New Fractional Order Memristance Simulator Circuit Design." In 2019 IEEE International Symposium on INnovations in Intelligent SysTems and Applications (INISTA). IEEE, 2019. http://dx.doi.org/10.1109/inista.2019.8778386.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Kim, YoungSu, SangHak Shin, and Kyeong-Sik Min. "Shared memristance restoring circuit for memristor-based Cellular Neural Networks." In 2014 14th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA). IEEE, 2014. http://dx.doi.org/10.1109/cnna.2014.6888625.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Bunnam, Thanasin, Ahmed Soltan, Danil Sokolov, and Alex Yakovlev. "An Excitation Time Model for General-purpose Memristance Tuning Circuit." In 2018 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2018. http://dx.doi.org/10.1109/iscas.2018.8351151.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Ntinas, Vasileios, Antonio Rubio, Georgios Ch Sirakoulis, and Sorin D. Cotofana. "A Pragmatic Gaze on Stochastic Resonance Based Variability Tolerant Memristance Enhancement." In 2019 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2019. http://dx.doi.org/10.1109/iscas.2019.8702792.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Ми пропонуємо знижки на всі преміум-плани для авторів, чиї праці увійшли до тематичних добірок літератури. Зв'яжіться з нами, щоб отримати унікальний промокод!