Статті в журналах: "Memory and power applications"

1

Zhang, Kaiqiang, Dongyang Ou, Congfeng Jiang, Yeliang Qiu, and Longchuan Yan. "Power and Performance Evaluation of Memory-Intensive Applications." Energies 14, no. 14 (July 6, 2021): 4089. http://dx.doi.org/10.3390/en14144089.

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In terms of power and energy consumption, DRAMs play a key role in a modern server system as well as processors. Although power-aware scheduling is based on the proportion of energy between DRAM and other components, when running memory-intensive applications, the energy consumption of the whole server system will be significantly affected by the non-energy proportion of DRAM. Furthermore, modern servers usually use NUMA architecture to replace the original SMP architecture to increase its memory bandwidth. It is of great significance to study the energy efficiency of these two different memory architectures. Therefore, in order to explore the power consumption characteristics of servers under memory-intensive workload, this paper evaluates the power consumption and performance of memory-intensive applications in different generations of real rack servers. Through analysis, we find that: (1) Workload intensity and concurrent execution threads affects server power consumption, but a fully utilized memory system may not necessarily bring good energy efficiency indicators. (2) Even if the memory system is not fully utilized, the memory capacity of each processor core has a significant impact on application performance and server power consumption. (3) When running memory-intensive applications, memory utilization is not always a good indicator of server power consumption. (4) The reasonable use of the NUMA architecture will improve the memory energy efficiency significantly. The experimental results show that reasonable use of NUMA architecture can improve memory efficiency by 16% compared with SMP architecture, while unreasonable use of NUMA architecture reduces memory efficiency by 13%. The findings we present in this paper provide useful insights and guidance for system designers and data center operators to help them in energy-efficiency-aware job scheduling and energy conservation.

2

Kumar, S., M. Santhanalakshmi, and R. Navaneethakrishnan. "Content addressable memory for energy efficient computing applications." Scientific Temper 14, no. 02 (June 6, 2023): 430–36. http://dx.doi.org/10.58414/scientifictemper.2023.14.2.30.

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Content Addressable Memory (CAM) also known as associate memory isa special kind of semiconductor memory device that works differently from conventional Random Access Memory (RAM). A Content Addressable Memory is a memory unit that matches content over a single clock rather than using addresses. Its inherent parallel search mechanism makes it more advantageous than RAM in terms of speed of search operation. Designers aim to reduce two design characteristics: increasing silicon size and power consumption. As the need for CAM increases, the problem of power consumption also increases. Recent research on CAM is concentrated around diminishing power utilization without forfeiting speed or area. The main reason for the high-power consumption in conventional CAM architecture is devoid of control over the voltage on the Match Line recharge and Search Line precharge. A novel CAM architecture is proposed by removing the necessity of the search line recharge and also by introducing a transistor with gate connected to ML_Eval input that act as a control over the search operation. An Extra transistor with gate connected to Mask_Bar decides whether the circuit can be operated as Ternary Content Addressable Memory (TCAM) or Binary Content Addressable Memory (Bi-CAM). This CAM Architecture is found to be power efficient up to 50% due to the control over recharged voltage on ML. It is also inferred that the delay associated with the search operation can be reduced to a certain extent. The proposed CAM architecture is simulated using Cadence Virtuoso IC 6.1.6 in General Process Design Kit (GPDK) with90nm technology.

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Tyler, Neil. "Tempo Targets Low-Power Chips for AI Applications." New Electronics 52, no. 13 (July 9, 2019): 7. http://dx.doi.org/10.12968/s0047-9624(22)61557-8.

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Kumar Lamba, Anil, and Anuradha Konidena. "IoT Applications: Analysis of MTCMOS Cache Memory Architecture in a Processor." Journal of Futuristic Sciences and Applications 2, no. 1 (2019): 24–33. http://dx.doi.org/10.51976/jfsa.211905.

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The main goals of the suggested inquiry are to measure how much power an amplifier uses, determine how much leaks through SRAM, and use the data. The main issue with the cache memory's design was leakage power. The charge transfer sense amplifier had the lowest value compared to other sense amplifiers' power consumption figures, even though we used MTCMOS and Footer Stack to reduce leaky power. The design included MTCMOS-CTSA and MTCMOS-SRAM memory to reduce power consumption. Fusing CTSA and SRAM with MTCMOS technology can produce low-power cache memory. This cache memory uses a lot less power than CTSA and SRAM devices

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Zuo, Ze Yu, Wei Hu, Rui Xin Hu, Heng Xiong, Wen Bin Du, and Xiu Cai. "Efficient Scratchpad Memory Management for Mobile Multimedia Application." Advanced Materials Research 748 (August 2013): 932–35. http://dx.doi.org/10.4028/www.scientific.net/amr.748.932.

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Mobile devices have been popular in recent years and the proliferation of mobile devices inspires the interest in mobile multimedia applications. However, memory is always the bottleneck in the traditional memory hierarchy. Scratchpad memory (SPM) is a promising on-chip SRAM to solve such problem. It has faster access time and less power-consumption compared to cache and off-chip memory. In this paper, we propose the efficient scratchpad memory management approach for mobile multimedia applications. SPM is partitioned for the assignment of the slices of the applications based on the profiling and the recorded history. Through the use of SPM, the memory footprint of mobile multimedia applications will be reduced for better performance and less power-consumption. The experimental results show that our approach is able to significantly reduce the power consumption and improve the performance of mobile multimedia applications.

6

Birla, Shilpi. "Variability aware FinFET SRAM cell with improved stability and power for low power applications." Circuit World 45, no. 4 (November 4, 2019): 196–207. http://dx.doi.org/10.1108/cw-12-2018-0098.

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Purpose Major area of a die is consumed in memory components. Almost 60-70% of chip area is being consumed by “Memory Circuits”. The dominant memory in this market is SRAM, even though the SRAM size is larger than embedded DRAM, as SRAM does not have yield issues and the cost is not high as compared to DRAM. At the same time, the other attractive feature for the SRAM is speed, and it can be used for low power applications. CMOS SRAM is the crucial component in microprocessor chips and applications, and as the said major portion of the area is dedicated to SRAM arrays, CMOS SRAM is considered to be the stack holders in the memory market. Because of the scaling feature of CMOS, SRAM had its hold in the market over the past few decades. In recent years, the limitations of the CMOS scaling have raised so many issues like short channel effects, threshold voltage variations. The increased thrust for alternative devices leads to FinFET. FinFET is emerging as one of the suitable alternatives for CMOS and in the region of memory circuits. Design/methodology/approach In this paper, a new 11 T SRAM cell using FinFET technology has been proposed, the basic component of the cell is the 6 T SRAM cell with 4 NMOS access transistors to improve the stability and also makes it a dual port memory cell. The proposed cell uses a header scheme in which one extra PMOS transistor is used which is biased at different voltages to improve the read and write stability thus, helps in reducing the leakage power and active power. Findings The cell shows improvement in RSNM (read static noise margin) with LP8T by 2.39× at sub-threshold voltage 2.68× with D6T SRAM cell, 5.5× with TG8T. The WSNM (write static noise margin) and HM (hold margin) of the SRAM cell at 0.9 V is 306 mV and 384 mV. It shows improvement at sub-threshold operation also. The leakage power is reduced by 0.125× with LP8T, 0.022× with D6T SRAM cell, TG8T and SE8T. The impact of process variation on cell stability is also discussed. Research limitations/implications The FinFet has been used in place of CMOS even though the FinFet has been not been a matured technology; therefore, pdk files have been used. Practical implications SRAM cell has been designed which has good stability and reduced leakage by which we can make an array and which can be used as SRAM array. Social implications The cell can be used for SRAM memory for low power consumptions. Originality/value The work has been done by implementing various leakage techniques to design a stable and improved SRAM cell. The advantage of this work is that the cell has been working for low voltage without degrading the stability factor.

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Marchal, P., J. I. Gomez, D. Atienza, S. Mamagkakis, and F. Catthoor. "Power aware data and memory management for dynamic applications." IEE Proceedings - Computers and Digital Techniques 152, no. 2 (2005): 224. http://dx.doi.org/10.1049/ip-cdt:20045077.

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8

K, Bharathi, and Vijayakumar S. "QCA Design of Encoder for Low Power Memory Applications." International Journal of Electronics and Communication Engineering 3, no. 11 (November 25, 2016): 13–15. http://dx.doi.org/10.14445/23488549/ijece-v3i11p114.

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9

Fang, Juan, Jiajia Lu, Mengxuan Wang, and Hui Zhao. "A Performance Conserving Approach for Reducing Memory Power Consumption in Multi-Core Systems." Journal of Circuits, Systems and Computers 28, no. 07 (June 27, 2019): 1950113. http://dx.doi.org/10.1142/s0218126619501135.

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With more cores integrated into a single chip and the fast growth of main memory capacity, the DRAM memory design faces ever increasing challenges. Previous studies have shown that DRAM can consume up to 40% of the system power, which makes DRAM a major factor constraining the whole system’s growth in performance. Moreover, memory accesses from different applications are usually interleaved and interfere with each other, which further exacerbates the situation in memory system management. Therefore, reducing memory power consumption has become an urgent problem to be solved in both academia and industry. In this paper, we first proposed a novel strategy called Dynamic Bank Partitioning (DBP), which allocates banks to different applications based on their memory access characteristics. DBP not only effectively eliminates the interference among applications, but also fully takes advantage of bank level parallelism. Secondly, to further reduce power consumption, we propose an adaptive method to dynamically select an optimal page policy for each bank according to the characteristics of memory accesses that each bank receives. Our experimental results show that our strategy not only improves the system performance but also reduces the memory power consumption at the same time. Our proposed scheme can reduce memory power consumption up to 21.2% (10% on average across all workloads) and improve the performance to some extent. In the case that workloads are built with mixed applications, our scheme reduces the power consumption by 14% on average and improves the performance up to 12.5% (3% on average).

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Yadav, Pradeep Singh, and Harsha Jain. "Review of 6T SRAM for Embedded Memory Applications." Indian Journal of VLSI Design 3, no. 1 (March 30, 2023): 24–30. http://dx.doi.org/10.54105/ijvlsid.a1217.033123.

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Due to the substantial impact embedded Static Random Access Memory (SRAM)s have on the overall system and their relatively limited design, it is essential to manage embedded SRAM trade-offs strategically. SRAMs have power, performance and density trade-offs in general. In all applications, all three dimensions are necessary to some extent; accordingly, embedded SRAM design must incorporate the most crucial system-specific requirements when developing embedded SRAM. This paper discusses many SRAM factors, including Static Noise Margin (SNM), Read Access Time (RAT),Write Access Time (WAT), Read Stability and Write Ability, Power, Data Retention Voltage (DRV), and Process Control. All these factors are crucial when designing SRAM for embedded memory applications. There has also been a discussion of the parameter comparisons and the literature review of the current papers.

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Kumar, Anurag, and Sheo Kumar. "Memory Architecture: Low-Power Single-Bit Cache." Journal of Futuristic Sciences and Applications 3, no. 2 (2020): 64–72. http://dx.doi.org/10.51976/jfsa.322007.

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Researchers investigated the functionality and efficiency of the single-bit cache memory architecture in terms of numbers. There are three different memory locations in a single-bit cache. A write driver, an SRAM cell, and a sensing amplifier are a few of these parts. SRAM blocks and sensing amplifiers are extensively used in constructing single-bit cache memory to reduce power usage. Both process corner simulation and circuit Monte Carlo simulation have researched their potential applications. It was subsequently determined that a forced stack design was more energy-efficient than a single-bit cache architecture.

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Pal, Srijani, Divya S. Salimath, Banusha Chandran, A. Anita Angeline, and V. S. Kanchana Bhaaskaran. "Low Power Memory System Design Using Power Gated SRAM Cell." IOP Conference Series: Materials Science and Engineering 1187, no. 1 (September 1, 2021): 012008. http://dx.doi.org/10.1088/1757-899x/1187/1/012008.

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Abstract Static Random-Access Memory (SRAM) is widely used in cache memory, microprocessors, general computing applications and electronic circuits involving ASIC, FPGA and CPLD. The most commonly used SRAM is the 6T SRAM. However, it incurs higher power consumption and degraded signal to noise margin (SNM) during write and read operations. To overcome these shortcomings, a single ended power gated 11T SRAM for low power operation is proposed. The power consumption reduction is achieved using power gating through virtual VSS (VVSS) signal and transmission gates. Due to the introduction of transmission gates, memory cells realize enhanced write margin characteristics as compared to existing technologies. The proposed cell realizes 33.33% lower power consumption and 50% improvement in read SNM as compared to existing SRAM technologies. To study the impact of technology scaling on our proposed design, the work is carried out in Cadence Virtuoso® tool using both 180nm CMOS technology and BPTM 32nm FinFET technology.

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Santoro, Giulia, Giovanna Turvani, and Mariagrazia Graziano. "New Logic-In-Memory Paradigms: An Architectural and Technological Perspective." Micromachines 10, no. 6 (May 31, 2019): 368. http://dx.doi.org/10.3390/mi10060368.

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Processing systems are in continuous evolution thanks to the constant technological advancement and architectural progress. Over the years, computing systems have become more and more powerful, providing support for applications, such as Machine Learning, that require high computational power. However, the growing complexity of modern computing units and applications has had a strong impact on power consumption. In addition, the memory plays a key role on the overall power consumption of the system, especially when considering data-intensive applications. These applications, in fact, require a lot of data movement between the memory and the computing unit. The consequence is twofold: Memory accesses are expensive in terms of energy and a lot of time is wasted in accessing the memory, rather than processing, because of the performance gap that exists between memories and processing units. This gap is known as the memory wall or the von Neumann bottleneck and is due to the different rate of progress between complementary metal–oxide semiconductor (CMOS) technology and memories. However, CMOS scaling is also reaching a limit where it would not be possible to make further progress. This work addresses all these problems from an architectural and technological point of view by: (1) Proposing a novel Configurable Logic-in-Memory Architecture that exploits the in-memory computing paradigm to reduce the memory wall problem while also providing high performance thanks to its flexibility and parallelism; (2) exploring a non-CMOS technology as possible candidate technology for the Logic-in-Memory paradigm.

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Akdemir, Bayram, and Hasan Üzülmez. "Providing Security of Vital Data for Conventional Microcontroller Applications." Applied Mechanics and Materials 789-790 (September 2015): 1059–66. http://dx.doi.org/10.4028/www.scientific.net/amm.789-790.1059.

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Microcontrollers are widely used in industrial world, and almost all kind of devices were based on microcontroller to achieve high flexibility and abilities. All microcontrollers have nonvolatile and volatile memories to execute the software. During the running, microcontroller calculates many variables and records them to any non-volatile memory to use later. After re-energizing, microcontroller takes the data calculated before the power off and executes the program. In case of any electrical writing error or any power loss during the writing procedure, un-written memory blocks or any un-written data leads to malfunctions. Proposed method uses a gray code based signed two memory blocks to secure the memory reserved for data. Microcontroller uses these memory blocks in alternately. Even if microcontroller has no any real-time ability, gray code provides a guarantee which block is written in last. For every re-starting microcontroller dos not lose the data. In case of any reading problem during the starting, microcontroller has two chances to decide the action. One is to start with default values and the other is to start with the previous data. This study is tested at elevator applications not to lose position and vital values.

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Tabbassum, Kavita, Shahnawaz Talpur, and Noor-u.-Zaman Laghari. "Managing Scratchpad Memory Architecture for Lower Power Consumption Using Programming Techniques." Asian Journal of Applied Science and Engineering 9, no. 1 (May 18, 2020): 79–86. http://dx.doi.org/10.18034/ajase.v9i1.31.

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In embedded systems Scratch memory is generally used as an addition to caches or as a substitute of cache, but due to their comprehensive ease of programmability cache containing architectures are still to be chosen in numerous applications. Power consumption of ported applications can be significantly lowered as well as the portability of scratchpad architectures will be advanced with our suggested language-agnostic software management method. To enhance the memory configuration on relevant architectures, a variety of present methods is reviewed for finding the chances of optimizations and usage of new methods as well as their applicability to numerous memory schemes are discussed in this paper.

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L, Saranya, Abinaya Inbamani, Nivedita A, and Arulanantham D. "Power Reduction in 4T DRAM Cell Using Low Power Topologies." ECS Transactions 107, no. 1 (April 24, 2022): 5569–75. http://dx.doi.org/10.1149/10701.5569ecst.

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In today’s world there is a high demand in the development of VLSI circuits. The designers are paying attention to designing a good performance with zero hunger circuits in terms of power. At present, to design a high speed and a low cost device is becoming a major challenge for designers. In order to enlarge the demand of VLSI, CMOS technology plays a fundamental role. Dynamic Random Access Memory is the volatile memory, which is used in wide ranges of electronic based gadget applications. In this paper, the low power techniques like sleep transistor logic and Self Voltage Controllable Logic (SCVL) are implemented. A 4T DRAM cell using these low power logics has been designed and implemented. The power has been analyzed at 90nm technology. The simulation is done using the Tanner 13.1.EDA tool.

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Datti, VenkataRamana, and Dr P. V. Sridevi. "A Novel Ternary Content Addressable Memory Cell." International Journal of Engineering & Technology 7, no. 4.24 (November 27, 2018): 67. http://dx.doi.org/10.14419/ijet.v7i4.24.21857.

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Ternary content addressable memories (TCAM) are used for parallel searching. The parallel searching, results high speed but consumes more power. For higher search speed applications, NOR type matchline TCAMs are useful. The NOR type matchline TCAM needs high power; therefore, the power reduction is the major objective of many reported designs. Here, a novel TCAM cell is proposed. The proposed Ternary CAM cell power consumption is 32% lesser than the NOR type matchline TCAM cell. Simulations are performed using cadence 45-nm technology.

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Xue, Xingsi, Aruru Sai Kumar, Osamah Ibrahim Khalaf, Rajendra Prasad Somineni, Ghaida Muttashar Abdulsahib, Anumala Sujith, Thanniru Dhanuja, and Muddasani Venkata Sai Vinay. "Design and Performance Analysis of 32 × 32 Memory Array SRAM for Low-Power Applications." Electronics 12, no. 4 (February 7, 2023): 834. http://dx.doi.org/10.3390/electronics12040834.

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Computer memory comprises temporarily or permanently stored data and instructions, which are utilized in electronic digital computers. The opposite of serial access memory is Random Access Memory (RAM), where the memory is accessed immediately for both reading and writing operations. There has been a vast technological improvement, which has led to tremendous information on the amount of complexity that can be designed on a single chip. Small feature sizes, low power requirements, low costs, and great performance have emerged as the essential attributes of any electronic component. Designers have been forced into the sub-micron realm for all these reasons, which places the leakage characteristics front and centre. Many electrical parts, especially digital ones, are made to store data, emphasising the need for memory. The largest factor in the power consumption of SRAM is the leakage current. In this article, a 1 KB memory array was created using CMOS technology and a supply voltage of 0.6 volts employing a 1-bit 6T SRAM cell. We developed this SRAM with a 1-bit, 32- × 1-bit, and 32 × 32 configuration. The array structure was implemented using a 6T SRAM cell with a minimum leakage current of 18.65 pA and an average delay of 19 ns. The array structure was implemented using a 6T SRAM cell with a power consumption of 48.22 μW and 385 μW for read and write operations. The proposed 32 × 32 memory array SRAM performed better than the existing 8T SRAM and 7T SRAM in terms of power consumption for read and write operations. Using the Cadence Virtuoso tool (Version IC6.1.8-64b.500.14) and 22 nm technology, the functionality of a 1 KB SRAM array was verified.

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Konig, R., U. Maurer, and R. Renner. "On the Power of Quantum Memory." IEEE Transactions on Information Theory 51, no. 7 (July 2005): 2391–401. http://dx.doi.org/10.1109/tit.2005.850087.

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20

Farrahi, Amir H., Gustavo E. Téllez, and Majid Sarrafzadeh. "Exploiting Sleep Mode for Memory Partitioning and Other Applications." VLSI Design 7, no. 3 (January 1, 1998): 271–87. http://dx.doi.org/10.1155/1998/50491.

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Sleep mode operation and exploiting it to minimize the average power consumption are of great importance in modern VLSI circuits. In general, sleep mode refers to the mode in which part(s) of the system are idle. In this paper, we study the problem of partitioning a circuit according to the activity patterns of its elements such that circuit elements with similar activity patterns are packed into the same partition. Then a partition can be placed in sleep mode during the time intervals all elements contained in that partition are idle. We formulate the partitioning problem to exploit sleep mode operation and show that the problem is NP-complete. We present polynomial time algorithms for practical classes of the problem. Applications of the problem to memory and module partitioning and clock gating are discussed. The experimental data confirm that a careful partitioning allows upto 40% more sleep time which could be exploited to minimize the average power consumption.

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Zhan, Ming, Zhibo Pang, Kan Yu, and Hong Wen. "Reverse Calculation-Based Low Memory Turbo Decoder for Power Constrained Applications." IEEE Transactions on Circuits and Systems I: Regular Papers 68, no. 6 (June 2021): 2688–701. http://dx.doi.org/10.1109/tcsi.2021.3068623.

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Singh, Pooran, B. S. Reniwal, V. Vijayvargiya, V. Sharma, and S. K. Vishvakarma. "Dynamic Feedback Controlled Static Random Access Memory for Low Power Applications." Journal of Low Power Electronics 13, no. 1 (March 1, 2017): 47–59. http://dx.doi.org/10.1166/jolpe.2017.1470.

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23

Guchang, Han, Huang Jiancheng, Sim Cheow Hin, Michael Tran, and Lim Sze Ter. "Switching methods in magnetic random access memory for low power applications." Journal of Physics D: Applied Physics 48, no. 22 (May 6, 2015): 225001. http://dx.doi.org/10.1088/0022-3727/48/22/225001.

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Salamy, Hassan, and Semih Aslan. "Pipelined-Scheduling of Multiple Embedded Applications on a Multi-Processor-SoC." Journal of Circuits, Systems and Computers 26, no. 03 (November 21, 2016): 1750042. http://dx.doi.org/10.1142/s0218126617500426.

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Due to clock and power constraints, it is hard to extract more power out of single core architectures. Thus, multi-core systems are now the architecture of choice to provide the needed computing power. In embedded system, multi-processor system-on-a-chip (MPSoC) is widely used to provide the needed power to effectively run complex embedded applications. However, to effectively utilize an MPSoC system, tools to generate optimized schedules is highly needed. In this paper, we design an integrated approach to task scheduling and memory partitioning of multiple applications utilizing the MPSoC system simultaneously. This is in contrast to the traditional decoupled approach that looks at task scheduling and memory partitioning as two separate problems. Our framework is also based on pipelined scheduling to increase the throughput of the system. Results on different benchmarks show the effectiveness of our techniques.

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Lai, Chun Sing, Zhekang Dong, and Donglian Qi. "Memristive Devices and Systems: Modeling, Properties and Applications." Electronics 12, no. 3 (February 2, 2023): 765. http://dx.doi.org/10.3390/electronics12030765.

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The memristor is considered to be a promising candidate for next-generation computing systems due to its nonvolatility, high density, low power, nanoscale geometry, nonlinearity, binary/multiple memory capacity, and negative differential resistance. [...]

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Gnawali, Krishna Prasad, Seyed Nima Mozaffari, and Spyros Tragoudas. "Low Power Spintronic Ternary Content Addressable Memory." IEEE Transactions on Nanotechnology 17, no. 6 (November 2018): 1206–16. http://dx.doi.org/10.1109/tnano.2018.2869734.

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KOUGIA, STAMATIKI, ALEXANDER CHATZIGEORGIOU, and SPIRIDON NIKOLAIDIS. "EVALUATING POWER EFFICIENT DATA-REUSE DECISIONS FOR EMBEDDED MULTIMEDIA APPLICATIONS: AN ANALYTICAL APPROACH." Journal of Circuits, Systems and Computers 13, no. 01 (February 2004): 151–80. http://dx.doi.org/10.1142/s0218126604001313.

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Power consumption of multimedia applications executing on embedded cores is heavily dependent on data transfers between system memory and processing units. The purpose of this paper is to extend an existing power optimizing methodology based on data-reuse decisions, in order to determine the optimal solution in a rapid and reliable way. An analytical approach is proposed by extracting expressions for the number of accesses to each memory layer. Moreover, the design space is further reduced since these analytical expressions are calculated only for a subset of all transformations. The results concerning the power efficiency of data-reuse transformations are in agreement to those in previous studies. However, the exploration time of the design space is significantly reduced. The proposed methodology is also applied to the case of multiple parallel processing cores, proving that the relative effect of each transformation is independent on the number of processors and the applied memory architecture.

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Krishna, R., and Punithavathi Duraiswamy. "Low leakage decoder using dual-threshold technique for static random-access memory applications." Indonesian Journal of Electrical Engineering and Computer Science 30, no. 3 (June 1, 2023): 1420. http://dx.doi.org/10.11591/ijeecs.v30.i3.pp1420-1427.

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Decoders are one of the significant peripheral components of static random-access memory (SRAM). As the CMOS technology moves towards nano scale regime, the leakage power starts dominating dynamic power. In this paper, we propose decoders using NAND logic in 32 nm CMOS technology. Leakage power is reduced by employing dual-threshold technique. Dual thresholding is a technique that uses transistors of two different threshold voltages. The technique is implemented in simulation by two methods; first method uses transistors with different threshold voltage and the second method uses substrate biasing to vary the threshold voltage. Row and column decoders are designed and simulated in H-Spice. The leakage power is calculated and compared for both the methods. The NAND gate implemented by Method-1 and Method-2 provides a maximum leakage power savings of 87.67% and 90.81% respectively. The maximum leakage power savings of 96.76% and 98.74% is reported for the row decoder implemented by Method-1 and Method-2 respectively. Similarly, Method-1 gives maximum leakage power savings of 97.09% and Method-2 gives a savings of 99.11% for column decoder. The difference in leakage power savings of Method-1 and Method-at same threshold voltage is 3.14%, 1.98%, and 2.02% for NAND gate, row decoder and column decoder respectively.

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Yook, Chan-Gi, Jung Nam Kim, Yoon Kim, and Wonbo Shim. "Design Strategies of 40 nm Split-Gate NOR Flash Memory Device for Low-Power Compute-in-Memory Applications." Micromachines 14, no. 9 (September 7, 2023): 1753. http://dx.doi.org/10.3390/mi14091753.

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The existing von Neumann architecture for artificial intelligence (AI) computations suffers from excessive power consumption and memory bottlenecks. As an alternative, compute-in-memory (CIM) technology has been emerging. Among various CIM device candidates, split-gate NOR flash offers advantages such as a high density and low on-state current, enabling low-power operation, and benefiting from a high level of technological maturity. To achieve high energy efficiency and high accuracy in CIM inference chips, it is necessary to optimize device design by targeting low power consumption at the device level and surpassing baseline accuracy at the system level. In split-gate NOR flash, significant factors that can cause CIM inference accuracy drop are the device conductance variation, caused by floating gate charge variation, and a low on-off current ratio. Conductance variation generally has a trade-off relationship with the on-current, which greatly affects CIM dynamic power consumption. In this paper, we propose strategies for designing optimal devices by adjusting oxide thickness and other structural parameters. As a result of setting Tox,FG to 13.4 nm, TIPO to 4.6 nm and setting other parameters to optimal points, the design achieves erase on-current below 2 μA, program on-current below 10 pA, and off-current below 1 pA, while maintaining an inference accuracy of over 92%.

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Birla, Shilpi. "FinFET SRAM cell with improved stability and power for low power applications." Journal of Integrated Circuits and Systems 14, no. 2 (August 25, 2019): 1–8. http://dx.doi.org/10.29292/jics.v14i2.57.

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In this paper, a new 11T SRAM cell using Double gate FET (FinFET technology) has been proposed, cell basic component is the 6T SRAM cell with 4 NMOS access transistors to improve the stability over CMOSFET circuits and also makes it a dual port memory cell. The proposed cell also used a header scheme in which one extra PMOS transistor is used which is biased at different voltages to improve the read and write stability which helps in reducing the leakage current, active power. The cell shows improvement in RSNM (Read Static Noise Margin) with LP8T by 2.39x at threshold and subthreshold voltage 2.68x with D6T SRAM cell, 5.5x with TG8T. The WSNM (Write Static Noise Margin) and HM (Hold Margin) of the SRAM cell at 0.9V is 306mV and 384mV.At subthreshold operation also, it shows improvement. The Leakage power reduced by 0.125x with LP8T, 0.022x with D6T SRAM cell, TG8T and SE8T. Impact of process variation on cell stability also been analyzed.

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Rhee, Chae Eun, Seung-Won Park, Jungwoo Choi, Hyunmin Jung, and Hyuk-Jae Lee. "Power-Time Exploration Tools for NMP-Enabled Systems." Electronics 8, no. 10 (September 28, 2019): 1096. http://dx.doi.org/10.3390/electronics8101096.

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Recently, dramatic improvements in memory performance have been highly required for data demanding application services such as deep learning, big data, and immersive videos. To this end, the throughput-oriented memory such as high bandwidth memory (HBM) and hybrid memory cube (HMC) has been introduced to provide a high bandwidth. For its effective use, various research efforts have been conducted. Among them, the near-memory-processing (NMP) is a concept that utilizes bandwidth and power consumption by placing computation logic near the memory. In the NMP-enabled system, a processor hierarchy consisting of hosts and NMPs is formed based on the distance from the main memory. In this paper, an evaluation tool is proposed to obtain the optimal design decision considering the power-time trade-off in the processor hierarchy. Every time the operating condition and constraints change, the decision of task-level offloading is dynamically made. For the realistic NMP-enabled system environment, the relationship among HBM, host, and NMP should be carefully considered. Hosts and NMPs are almost hidden from each other and the communications between them are extremely limited. In the simulation results, popular benchmarks and a machine learning application are used to demonstrate power-time trade-offs depending on applications and system conditions.

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Banerjee, Writam. "Challenges and Applications of Emerging Nonvolatile Memory Devices." Electronics 9, no. 6 (June 22, 2020): 1029. http://dx.doi.org/10.3390/electronics9061029.

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Emerging nonvolatile memory (eNVM) devices are pushing the limits of emerging applications beyond the scope of silicon-based complementary metal oxide semiconductors (CMOS). Among several alternatives, phase change memory, spin-transfer torque random access memory, and resistive random-access memory (RRAM) are major emerging technologies. This review explains all varieties of prototype and eNVM devices, their challenges, and their applications. A performance comparison shows that it is difficult to achieve a “universal memory” which can fulfill all requirements. Compared to other emerging alternative devices, RRAM technology is showing promise with its highly scalable, cost-effective, simple two-terminal structure, low-voltage and ultra-low-power operation capabilities, high-speed switching with high-endurance, long retention, and the possibility of three-dimensional integration for high-density applications. More precisely, this review explains the journey and device engineering of RRAM with various architectures. The challenges in different prototype and eNVM devices is disused with the conventional and novel application areas. Compare to other technologies, RRAM is the most promising approach which can be applicable as high-density memory, storage class memory, neuromorphic computing, and also in hardware security. In the post-CMOS era, a more efficient, intelligent, and secure computing system is possible to design with the help of eNVM devices.

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Tripathi, Tripti, D. S. Chauhan, and S. K. Singh. "Low leakage SRAM cell for ULP applications." International Journal of Engineering & Technology 7, no. 4 (September 24, 2018): 2521. http://dx.doi.org/10.14419/ijet.v7i4.14028.

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Leakage power is becoming a major concern in battery operated and hand held devices. With the ever reducing size of electronic devices and the use of memory in most of them, the need for low power devices is vastly increasing. These devices are either in active or standby mode of operation. Leakage power in standby mode of operation is of major concern and various methods to minimize it have been proposed at various stages of design cycle. This paper proposes fingering technique that can be used in 6T SRAM cell to reduce leakage power. Leakage power is calculated for 6T SRAM cell designed using two fingers in access transistors and on comparison with conventional 6T SRAM cell, significant reduction in leakage current is obtained. The layout has been designed in UMC 55nm technology using Cadence Virtuoso tool and it has been shown that the leakage power and delay can be reduced.

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ZHAO, WEISHENG, RAPHAEL MARTINS BRUM, LIONEL TORRES, JACQUES-OLIVIER KLEIN, GILLES SASSATELLI, DAFINÉ RAVELOSONA, and CLAUDE CHAPPERT. "SPINTRONIC MEMORY-BASED RECONFIGURABLE COMPUTING." SPIN 03, no. 04 (December 2013): 1340010. http://dx.doi.org/10.1142/s2010324713400109.

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Reconfigurable computing provides a number of advantages such as low Research and Development (R&D) cost and design flexibility when compared to application specific logic circuits (ASLC). However its low power efficiency greatly limits its applications. One of the major reasons of this shortcoming is that Static Random Access Memory (SRAM)-based configuration memory occupies a large die area and consumes high static power. The later is more severe due to the rapidly increasing leakage currents, which are intrinsic and become worse following the fabrication node shrinking. Spintronic memories (e.g., STT-MRAM and racetrack memory (RM)) are emerging nonvolatile memory technologies under intense investigation by both academics and industries. They promise ultra-high storage density, nonvolatility and low power. In this paper, we review the current status of spintronic memories for reconfigurable computing, the related device-circuit-system design requirements and present its perspectives. Mixed simulations based on spintronic device compact models show its high density and low power performance when compared to conventional SRAM-based reconfigurable computing.

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Fanariotis, Anastasios, Theofanis Orphanoudakis, and Vassilis Fotopoulos. "Reducing the Power Consumption of Edge Devices Supporting Ambient Intelligence Applications." Information 15, no. 3 (March 12, 2024): 161. http://dx.doi.org/10.3390/info15030161.

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Having as a main objective the exploration of power efficiency of microcontrollers running machine learning models, this manuscript contrasts the performance of two types of state-of-the-art microcontrollers, namely ESP32 with an LX6 core and ESP32-S3 with an LX7 core, focusing on the impact of process acceleration technologies like cache memory and vectoring. The research employs experimental methods, where identical machine learning models are run on both microcontrollers under varying conditions, with particular attention to cache optimization and vector instruction utilization. Results indicate a notable difference in power efficiency between the two microcontrollers, directly linked to their respective process acceleration capabilities. The study concludes that while both microcontrollers show efficacy in running machine learning models, ESP32-S3 with an LX7 core demonstrates superior power efficiency, attributable to its advanced vector instruction set and optimized cache memory usage. These findings provide valuable insights for the design of power-efficient embedded systems supporting machine learning for a variety of applications, including IoT and wearable devices, ambient intelligence, and edge computing and pave the way for future research in optimizing machine learning models for low-power, embedded environments.

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Chang, Meng-Fan, Mary Jane Irwin, and Robert Michael Owens. "Power-Area Trade-Offs in Divided Word Line Memory Arrays." Journal of Circuits, Systems and Computers 07, no. 01 (February 1997): 49–67. http://dx.doi.org/10.1142/s021812669700005x.

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Since on-chip caches account for a significant portion of the power budget of modern microprocessors, low power caches are needed in microprocessors destined for portable electronic applications. A significant portion of the power consumption of caches comes from accessing the cache memory array and most of the power consumption of the memory array comes from driving the bit line pairs (i.e., the column current). Various memory array architectures have been proposed to improve the word line delay and the column current. For example, in a divided word line memory array memory cells in each row are organized into blocks. Only the memory cells which are in the activated block have their bit line pairs driven, thus both improving the speed (by decreasing the word line delay) and lowering the power consumption (by decreasing the column current). In this paper we analyze the power-area tradeoffs of divided word line memories with different size blocks. We compare the area and power consumption of 16 Kbit and 64 Kbit memory arrays with 2, 4, 8, and 16 memory cells per block. Our experiments show that a divided word line memory array can lower the power consumption by 50% to 90% over a nondivided word line memory array. However, they consume more area; the area of a divided word line memory array can be 15% to 27% larger than the area of a comparable nondivided word line array. Our experiments also showed that divided word line memory arrays with two or four memory cells in a block have better power-area product than those with more than four cells per block.

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Dawwd, Shefa, and Suha Nori. "Reduced Area and Low Power Implementation of FFT/IFFT Processor." Iraqi Journal for Electrical and Electronic Engineering 14, no. 2 (December 1, 2018): 108–19. http://dx.doi.org/10.37917/ijeee.14.2.3.

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The Fast Fourier Transform (FFT) and Inverse FFT(IFFT) are used in most of the digital signal processing applications. Real time implementation of FFT/IFFT is required in many of these applications. In this paper, an FPGA reconfigurable fixed point implementation of FFT/IFFT is presented. A manually VHDL codes are written to model the proposed FFT/IFFT processor. Two CORDIC-based FFT/IFFT processors based on radix-2and radix-4 architecture are designed. They have one butterfly processing unit. An efficient In-place memory assignment and addressing for the shared memory of FFT/IFFT processors are proposed to reduce the complexity of memory scheme. With "in-place" strategy, the outputs of butterfly operation are stored back to the same memory location of the inputs. Because of using DIF FFT, the output was to be in reverse order. To solve this issue, we have re-use the block RAM that used for storing the input sample as reordering unit to reduce hardware cost of the proposed processor. The Spartan-3E FPGA of 500,000 gates is employed to synthesize and implement the proposed architecture. The CORDIC based processors can save 40% of power consumption as compared with Xilinx logic core architectures of system generator.

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Maciel, Nilson, Elaine Marques, Lírida Naviner, Yongliang Zhou, and Hao Cai. "Magnetic Tunnel Junction Applications." Sensors 20, no. 1 (December 24, 2019): 121. http://dx.doi.org/10.3390/s20010121.

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Spin-based devices can reduce energy leakage and thus increase energy efficiency. They have been seen as an approach to overcoming the constraints of CMOS downscaling, specifically, the Magnetic Tunnel Junction (MTJ) which has been the focus of much research in recent years. Its nonvolatility, scalability and low power consumption are highly attractive when applied in several components. This paper aims at providing a survey of a selection of MTJ applications such as memory and analog to digital converter, among others.

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Kotb, Youssef, Islam Elgamal, and Mohamed Serry. "Shape Memory Alloy Capsule Micropump for Drug Delivery Applications." Micromachines 12, no. 5 (May 6, 2021): 520. http://dx.doi.org/10.3390/mi12050520.

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We introduce a shape memory alloy (SMA) actuated micropump optimized for drug delivery applications. The proposed novel design integrates a built-in replaceable drug reservoir within the pump package forming a self-contained preloaded capsule pump with an overall pump volume of 424.7 μL. The new design results in a compact, simple, and inexpensive micropump and reduces the probability of contamination with attained almost zero dead volume values. The pump consists of NiTi-alloy SMA wires coiled on a flexible polymeric enclosure and actuated by joule heating. Unlike diaphragm and peristaltic SMA micropump designs that actuate transversely, our design is actuated longitudinally along the direction of the highest mechanical compliance resulting in large strokes in the order of 5.6 mm at 27% deflection ratio, actuation speed up to 11 mm/s, and static head pressures up to 14 kPa (105 mmHg) at 7.1 W input power; thus, high throughputs exceeding 2524 μL/min under free convention conditions could be achieved. A model was developed to optimize the pump’s geometrical parameters and the enclosure material. The model concluded that low stiffness enclosure material combined with thinner SMA wire diameter would result in the maximum deflection at the lowest power rating. To prove its viability for drug delivery applications, the pump was operated at a constant discharge volume at a relatively constant static head pressure. Furthermore, a design of bicuspid-inspired polymeric check-valves is presented and integrated onto the pump to regulate the flow. Since the built-in reservoir is replaceable, the pump capsule can be reused multiple times and for multiple drug types.

40

Chen, Ying-Chen, Szu-Tung Hu, Chih-Yang Lin, Burt Fowler, Hui-Chun Huang, Chao-Cheng Lin, Sungjun Kim, Yao-Feng Chang, and Jack C. Lee. "Graphite-based selectorless RRAM: improvable intrinsic nonlinearity for array applications." Nanoscale 10, no. 33 (2018): 15608–14. http://dx.doi.org/10.1039/c8nr04766a.

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Selectorless graphite-based resistive random-access memory (RRAM) has been demonstrated by utilizing the intrinsic nonlinear resistive switching (RS) characteristics, without an additional selector or transistor for low-power RRAM array application.

41

Hayashikoshi, Masanori, Hideyuki Noda, Hiroyuki Kawai, Yasumitsu Murai, Sugako Otani, Koji Nii, Yoshio Matsuda, and Hiroyuki Kondo. "Low-Power Multi-Sensor System with Power Management and Nonvolatile Memory Access Control for IoT Applications." IEEE Transactions on Multi-Scale Computing Systems 4, no. 4 (October 1, 2018): 784–92. http://dx.doi.org/10.1109/tmscs.2018.2827388.

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42

Takagi, Shinichi, Kasidit Toprasertpong, Kent Tahara, Eishin Nako, Ryosho Nakane, Zeyu Wang, Xuan Luo, Tsung-En Lee, and Mitsuru Takenaka. "(Invited) HfZrO-Based Ferroelectric Devices for Lower Power AI and Memory Applications." ECS Transactions 104, no. 4 (October 1, 2021): 17–26. http://dx.doi.org/10.1149/10404.0017ecst.

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43

Takagi, Shinichi, Kasidit Toprasertpong, Kent Tahara, Eishin Nako, Ryosho Nakane, Zeyu Wang, Xuan Luo, Tsung-En Lee, and Mitsuru Takenaka. "(Invited) HfZrO-Based Ferroelectric Devices for Lower Power AI and Memory Applications." ECS Meeting Abstracts MA2021-02, no. 30 (October 19, 2021): 909. http://dx.doi.org/10.1149/ma2021-0230909mtgabs.

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44

Banerjee, Writam, Sheikh Ziaur Rahaman, Amit Prakash та Siddheswar Maikap. "High-κ Al2O3/WOxBilayer Dielectrics for Low-Power Resistive Switching Memory Applications". Japanese Journal of Applied Physics 50, № 10S (1 жовтня 2011): 10PH01. http://dx.doi.org/10.7567/jjap.50.10ph01.

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45

Balestra, Francis. "Multi-gate Devices for High Performance, Ultra Low Power and Memory Applications." ECS Transactions 25, no. 7 (December 17, 2019): 77–90. http://dx.doi.org/10.1149/1.3203945.

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46

Barradas, Filipe M., Pedro M. Tome, Telmo R. Cunha, and Jose C. Pedro. "Compensation of Power Amplifier Long-Term Memory Behavior for Pulsed Radar Applications." IEEE Transactions on Microwave Theory and Techniques 67, no. 12 (December 2019): 5249–56. http://dx.doi.org/10.1109/tmtt.2019.2940185.

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47

Hansoo Kim and In-Cheol Park. "High-performance and low-power memory-interface architecture for video processing applications." IEEE Transactions on Circuits and Systems for Video Technology 11, no. 11 (2001): 1160–70. http://dx.doi.org/10.1109/76.964782.

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48

Wang, Chen, Xiuli Zhao, Hao Liu, Xin Chao, Hao Zhu, and Qingqing Sun. "A High-Density Memory Design Based on Self-Aligned Tunneling Window for Large-Capacity Memory Application." Electronics 10, no. 16 (August 13, 2021): 1954. http://dx.doi.org/10.3390/electronics10161954.

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Despite the continuous downscaling of complementary metal–oxide–semiconductor (CMOS) devices, various scenarios of technology have also been proposed toward the shrinking of semiconductor memory. In this paper, a high-density memory (HDM) has been proposed on the basis of band-to-band tunneling (BTBT) for low-power, high density, and high-speed memory applications. The geometric structure and electrical properties have been demonstrated by using TCAD tools. Typical memory operations including read, program, and erase have been designed and performed. High operation speed, lower power consumption, as well as good reliability characteristics have been achieved by simulation, which indicates that the HDM may have potential application value as a novel semiconductor memory device.

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Rao, M. V. Nageswara, Mamidipaka Hema, Ramakrishna Raghutu, Ramakrishna S. S. Nuvvula, Polamarasetty P. Kumar, Ilhami Colak, and Baseem Khan. "Design and Development of Efficient SRAM Cell Based on FinFET for Low Power Memory Applications." Journal of Electrical and Computer Engineering 2023 (June 7, 2023): 1–13. http://dx.doi.org/10.1155/2023/7069746.

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Stationary random-access memory (SRAM) undergoes an expansion stage, to repel advanced process variation and support ultra-low power operation. Memories occupy more than 80% of the surface in today’s microdevices, and this trend is expected to continue. Metal oxide semiconductor field effect transistor (MOSFET) face a set of difficulties, that results in higher leakage current (Ileakage) at lower strategy collisions. Fin field effect transistor (FinFET) is a highly effective substitute to complementary metal oxide semiconductor (CMOS) under the 45 nm variant due to advanced stability. Memory cells are significant in the large-scale computation system. SRAM is the most commonly used memory type; SRAMs are thought to utilize more than 60% of the chip area. The proposed SRAM cell is developed with FinFETs at 16 nm knot. Power, delay, power delay product (PDP), Ileakage, and stationary noise margin (SNM) are compared with traditional 6T SRAM cells. The designed cell decreases leakage power, current, and read access time. While comparing 6T SRAM and earlier low power SRAM cells, FinFET-based 10T SRAM provides significant SNM with reduced access time. The proposed 10T SRAM based on FinFET provides an 80.80% PDP reduction in write mode and a 50.65% PDP reduction in read mode compared to MOSEFET models. There is an improvement of 22.20% in terms of SNM and 25.53% in terms of Ileakage.

50

Struharik, Rastislav, and Vuk Vranjković. "Striping input feature map cache for reducing off-chip memory traffic in CNN accelerators." Telfor Journal 12, no. 2 (2020): 116–21. http://dx.doi.org/10.5937/telfor2002116s.

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Data movement between the Convolutional Neural Network (CNN) accelerators and off-chip memory is critical concerning the overall power consumption. Minimizing power consumption is particularly important for low power embedded applications. Specific CNN computes patterns offer a possibility of significant data reuse, leading to the idea of using specialized on-chip cache memories which enable a significant improvement in power consumption. However, due to the unique caching pattern present within CNNs, standard cache memories would not be efficient. In this paper, a novel on-chip cache memory architecture, based on the idea of input feature map striping, is proposed, which requires significantly less on-chip memory resources compared to previously proposed solutions. Experiment results show that the proposed cache architecture can reduce on-chip memory size by a factor of 16 or more, while increasing power consumption no more than 15%, compared to some of the previously proposed solutions.

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