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Статті в журналах з теми "MAC UNIT"

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Автор: Grafiati

Опубліковано: 11 вересня 2023

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1

Santhosh, K. V., and S. Nithin. "Optimized Mac Unit." International Journal of Students' Research in Technology & Management 3, no. 7 (October 27, 2015): 413. http://dx.doi.org/10.18510/ijsrtm.2015.371(1).

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In this paper, a new multiplier design is proposed which reduces the number of partial products by 25%. This multiplier has been used with different adders available in literature to implement multiplier accumulator (MAC) unit and parameters such as propagation delay, power consumed and area occupied have been compared in each case.From the results, Kogg tone adder has been chosen as it provided optimum values of delay and power dissipation. Later, the results obtained have been compared with that of other multipliers and it has been observed that the proposed multiplier has the lowest propagation delay when compared with Array and Booth multipliers.

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2

Lee, Jinyoung, Seiyoung Lee, Dukki Hong, and Woo-Chan Park. "The Design of Low-area and High-efficiency MAC Unit." Journal of the Institute of Electronics and Information Engineers 54, no. 11 (November 30, 2017): 78–85. http://dx.doi.org/10.5573/ieie.2017.54.11.78.

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3

Mohammaden, Amr, Mohammed Fouda, Ihsen Alouani, Lobna A. Said, and Ahmed Radwan. "CNTFET-Based Ternary Multiply-and-Accumulate Unit." Electronics 11, no. 9 (April 30, 2022): 1455. http://dx.doi.org/10.3390/electronics11091455.

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Multiply-Accumulate (MAC) is one of the most commonly used operations in modern computing systems due to its use in matrix multiplication, signal processing, and in new applications such as machine learning and deep neural networks. Ternary number system offers higher information processing within the same number of digits when compared to binary systems. In this paper, a MAC is proposed using a CNTFET-based ternary logic number. Specifically, we build a 5-trit multiplier and 10-trit adder as building blocks of two ternary MAC unit designs. The first is a basic MAC which has two methods to implement, serial and pipeline. The second is an improved MAC design that optimizes the number of transistors, offers higher performance and lower power consumption. The designed MAC unit can operate up to 300MHz. Finally, a comparative study in terms of power, delay, and area variations is conducted under different supply voltages and temperature levels.

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4

Mehta, Sonali, Balwinder singh, and Dilip Kumar. "Performance Analysis of Floating Point MAC Unit." International Journal of Computer Applications 78, no. 1 (September 18, 2013): 38–41. http://dx.doi.org/10.5120/13456-1139.

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5

Bhuvaneswary, N., S. Prabu, K. Tamilselvan, and K. G. Parthiban. "Efficient Implementation of Multiply Accumulate Operation Unit Using an Interlaced Partition Multiplier." Journal of Computational and Theoretical Nanoscience 18, no. 4 (April 1, 2021): 1321–26. http://dx.doi.org/10.1166/jctn.2021.9398.

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A new strategy for quick multiplication of two numbers is introduced. Inputs are separated into segments, and one segment is replaced by two with zeros interlocking in each alternative segments. With zero carries between segments the product are computed, within the time needed to multiply the short partitions and add the partial sums. The multiplication of two numbers generated and adds that product to an accumulator by multiply accumulate operation (MAC unit). This operation is performed within the MAC unit. MAC is an advanced co-processor that plays a vital role in FFT, DFT, etc. The MAC unit is utilized for additional execution and its input is given to the proposed multiplier that provides a trivial speed increment over the array multiplier designs. This paper is utilized to design speed enhanced multiply Accumulate Unit by an Interlaced Partition Multiplier. This new multiplier design simulation is optimized with existing method.

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6

Simon, DI, NK Rao, H. Xu, Y. Wei, O. Majdic, E. Ronne, L. Kobzik, and HA Chapman. "Mac-1 (CD11b/CD18) and the urokinase receptor (CD87) form a functional unit on monocytic cells." Blood 88, no. 8 (October 15, 1996): 3185–94. http://dx.doi.org/10.1182/blood.v88.8.3185.bloodjournal8883185.

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The leukocyte integrin Mac-1 (CD11b/CD18) and the urokinase receptor (uPAR, CD87) mediate complementary functions in myelomonocytic cells. Both receptors promote degradation of fibrin(ogen) and also confer adhesive properties on cells because Mac-1 and uPAR bind fibrin and vitronectin, respectively. Staining of lung biopsy specimens from patients with acute lung injury indicated that fibrin and vitronectin colocalize at exudative sites in which macrophages bearing these receptors accumulate. Because of the parallel roles and physical proximity of Mac-1 and uPAR, the capacity of these receptors to functionally interact was explored. Induction of Mac-1 and uPAR expression on monocytic cell lines by transforming growth factor-beta 1 and 1.25-(OH)2 vitamin D3 conferred urokinase and uPAR-dependent adhesion to vitronectin, which was further promoted by engagement of Mac-1. Vitronectin attachment promoted subsequent Mac-1-mediated fibrinogen degradation threefold to fourfold. In contrast, enhancement of uPAR occupancy by exogenous urokinase or receptor binding fragments thereof inhibited Mac-1 function. Addition of urokinase progressively inhibited Mac-1-mediated fibrinogen binding and degradation (maximal inhibition, 91% +/- 14% and 72% +/- 15%, respectively). Saturation of uPAR with urokinase also inhibited binding of the procoagulant Mac-1 ligand, Factor X. These inhibitory effects of uPAR were reproduced in fresh monocytes, cultured monocytic cells, and in Chinese hamster ovary (CHO) cells transfected with both human Mac-1 and human uPAR. These data show that the procoagulant and fibrinolytic potential of monocytic cells is co-ordinately regulated by ligand binding to both Mac-1 and uPAR and identify uPAR as a regulator of integrin function. Vitronectin-enhanced fibrin(ogen) turnover by Mac-1 may operate as a salvage pathway in the setting of urokinase and plasmin inhibitors to promote clearance of the provisional matrix and subsequent healing.

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7

HG, Rangaraju, Arpitha H S, and Muralidhara K N. "Design of Efficient Reversible Multiply Accumulate (MAC) Unit." International Journal of Computer Applications 85, no. 16 (January 16, 2014): 1–12. http://dx.doi.org/10.5120/14922-3338.

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8

Kavitha, V., and S. Mohanraj. "Power Efficient MAC Unit Based Digital PID Controllers." JOURNAL OF ADVANCES IN CHEMISTRY 12, no. 9 (November 3, 2016): 4324–29. http://dx.doi.org/10.24297/jac.v12i9.4090.

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Proper closed loop has been an ever hot issue in the automotive industry. The industrial equipments governed by PID controllers have very simple control architecture and efficiency but still they find a trouble dueto large power consumption and slow mathematical computation. Many researchers have worked out and are trying to design a low power, less delay PID. This paper reviews three MAC architectures with array, booth and wallace tree multipliers incorporated in PID architecture. The simulations are done and the area, power, delay results are synthesized using Xilinx ISE. Comparisons are made between these three architectures in terms of power delay product and area delay product.

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9

Madasamy, Rajmohan, and Himanshu Shekhar. "SERIAL ADDER BASED MULTIPLICATION AND ACCUMULATION UNIT (MAC)." International Journal of Advances in Signal and Image Sciences 3, no. 1 (June 30, 2017): 25. http://dx.doi.org/10.29284/ijasis.3.1.2017.25-30.

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10

Bakshi, Sana Zeba, and Prof Mohammad Nasiruddin. "Optimization of MAC unit using full pipelined accumulator." International Journal of Research in Advent Technology 7, no. 5 (June 10, 2019): 352–55. http://dx.doi.org/10.32622/ijrat.742019187.

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11

YAO, JUN, JIE CHEN, and ZHAOJUN LIN. "HIGH PERFORMANCE MAC UNIT USING MODIFIED SIGN EXTENSION ALGORITHM AND A NEW HIGH-SPEED ALU IN DSP-CORE." International Journal of Software Engineering and Knowledge Engineering 15, no. 02 (April 2005): 427–32. http://dx.doi.org/10.1142/s0218194005002002.

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This paper describes a high performance multiply-accumulator (MAC) unit in DSP-core. Since the most critical timing path of the DSP lies in the MAC, great endeavors have been paid to speed it up. The MAC unit can perform fixed-point operation with rounding optional, on operands with a throughput of 1 cycle. In this design, the modified sign extension algorithm is presented to eliminate the sign bits array of partial products to reduce computation time and area. Further increase in speed is achieved by using a new three 40 bit inputs (also known as operands) high-speed arithmetic logical unit (ALU) to shorten the delay of the critical path.

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12

IMPERIALE, B. R., R. D. MOYANO, A. B. DI GIULIO, M. A. ROMERO, M. F. ALVARADO PINEDO, M. P. SANTANGELO, G. E. TRAVERÍA, N. S. MORCILLO, and M. I. ROMANO. "Genetic diversity ofMycobacterium aviumcomplex strains isolated in Argentina by MIRU-VNTR." Epidemiology and Infection 145, no. 7 (February 7, 2017): 1382–91. http://dx.doi.org/10.1017/s0950268817000139.

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SUMMARYMycobacterium aviumsp.avium(MAA),M. aviumsp.hominissuis(MAH), andM. aviumsp.paratuberculosis(MAP) are the main members of theM. aviumcomplex (MAC) causing diseases in several hosts. The aim of this study was to describe the genetic diversity of MAC isolated from different hosts. Twenty-six MAH and 61 MAP isolates were recovered from humans and cattle, respectively. GenoType CM®and IS1311-PCR were used to identifyMycobacteriumspecies. The IS901-PCR was used to differentiate between MAH and MAA, while IS900-PCR was used to identify MAP. Genotyping was performed using a mycobacterial interspersed repetitive-unit-variable-number tandem-repeat (MIRU-VNTR) scheme (loci: 292, X3, 25, 47, 3, 7, 10, 32) and patterns (INMV) were assigned according to the MAC-INMV database (http://mac-inmv.tours.inra.fr/). Twenty-two (22/26, 84·6%) MAH isolates were genotyped and 16 were grouped into the following, INMV 92, INMV 121, INMV 97, INMV 103, INMV 50, and INMV 40. The loci X3 and 25 showed the largest diversity (D: 0·5844), and the global discriminatory index (Hunter and Gaston discriminatory index, HGDI) was 0·9300. MAP (100%) isolates were grouped into INMV 1, INMV 2, INMV 11, INMV 8, and INMV 5. The HGDI was 0·6984 and loci 292 and 7 had the largestD(0·6980 and 0·5050). MAH presented a higherDwhen compared with MAP. The MIRU-VNTR was a useful tool to describe the genetic diversity of both MAH and MAP as well as to identify six new MAH patterns that were conveniently reported to the MAC-INMV database. It was also demonstrated that, in the geographical region studied, human MAC cases were produced by MAH as there was no MAA found among the human clinical samples.

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13

Aalia, P. Samreen, and K. Yogitha Bali. "Optimization of Delay IIN Pipeline Mac Unit Using Wallace Tree Multiplier." International Journal for Research in Applied Science and Engineering Technology 10, no. 11 (November 30, 2022): 1328–34. http://dx.doi.org/10.22214/ijraset.2022.47584.

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Abstract: A prompt pipelined MAC unit is implemented in this paper. Due to carrying propagations in additions, including additions of multiplications and additions of accumulations, we will experience a significant path delay as well as a significant increase in power consumption when using the conventional methodology. To resolve these issues, we are including a portion of improvements to the partial product reduction procedure. The pipelined MAC implementation does not complete the addition and accumulation of the most weighted bits until the partial product reduction step of the subsequent multiplication. In order to manage the overspill bits during the partial product reduction procedure, we are designing the small size adder which computes the total number of carries. By comparing with the conventional methodologies, we will get the diminished area as well as power consumption for the proposed pipelined MAC implementation.

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14

V. Kumaravel, M. Pooja, S. Gayathri Priya, J. Jagan Babu,. "Low Power and Area Efficient Borrow Save Adder for MAC Unit in VLSI Application." INFORMATION TECHNOLOGY IN INDUSTRY 9, no. 2 (March 31, 2021): 828–34. http://dx.doi.org/10.17762/itii.v9i2.420.

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In hypercompetitive embedded system environment, to develop the unique characteristic of machine learning computation for more efficient MAC design for reduced both the area and power. In this paper, Multiply–accumulate (MAC) computations account for a large part of machine learning accelerator operations use in pipelined structure is usually adopted to improve the performance by reducing the number of adder circuits. The proposed a pipelining method that eliminates some of the flip-flops in carry look adder in selectively. Here, introduce the applying the Feed forward-Cutset-Free (FCF) pipelining method in borrow save adder (BSA) to the accumulator by reducing the design, optimized the power dissipation and undesired data transition in (MFCF-PA). From the FPGA Xilinx simulation output result shows that, the MAC unit reached between 15% and 25% energy saving and area reduction of 15% over the existing carry look ahead adder (CLA) conformist pipelined MAC units.

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15

Kalaiselvi, K., and H. Mangalam. "Area Efficient High Speed and Low Power MAC Unit." International Journal of Computer Applications 67, no. 23 (April 18, 2013): 40–44. http://dx.doi.org/10.5120/11539-7414.

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16

Sathya, M. "Design of Digital FIR Filter using Modified MAC Unit." International Journal for Research in Applied Science and Engineering Technology 6, no. 1 (January 31, 2018): 1441–55. http://dx.doi.org/10.22214/ijraset.2018.1219.

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17

Raghav, Sachin, and Rinkesh Mittal. "Implementation of Fast and Efficient Mac Unit on FPGA." International Journal of Mathematical Sciences and Computing 2, no. 4 (November 8, 2016): 24–33. http://dx.doi.org/10.5815/ijmsc.2016.04.03.

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18

Kulkarni, Karthik S. "MAC Unit Optimization for Area, Power and Timing Constraints." International Journal for Research in Applied Science and Engineering Technology 9, no. 5 (May 31, 2021): 2023–35. http://dx.doi.org/10.22214/ijraset.2021.34753.

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19

M, Deepika Kumari. "Design and Implementation of RoBA Multiplier on MAC Unit." International Journal for Research in Applied Science and Engineering Technology 7, no. 7 (July 31, 2019): 864–68. http://dx.doi.org/10.22214/ijraset.2019.7139.

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20

Maitra, Subhashis, and Amitabha Sinha. "High performance MAC unit for DSP and cryptographic applications." ACM SIGARCH Computer Architecture News 41, no. 2 (May 29, 2013): 47–55. http://dx.doi.org/10.1145/2490302.2490311.

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21

Mclenachan, John, Nicki Alexander, Kate Theodosiou, Cheng Zhang, and Alistair McNarry. "McGrath MAC Videolaryngoscope use in a tertiary obstetric unit." Trends in Anaesthesia and Critical Care 30 (February 2020): e106. http://dx.doi.org/10.1016/j.tacc.2019.12.262.

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22

Lakshmi, Santhana. "Error Reduction of Modified Booth Multipliers in Mac Unit." IOSR Journal of Electronics and Communication Engineering 7, no. 6 (2013): 20–26. http://dx.doi.org/10.9790/2834-0762026.

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23

Rahul Reddy, P., Pandya Vyomal N, and Abhishek Choubey. "An Efficient MAC Architecture using Multiplier for DSP and DIP Operations." International Journal of Engineering & Technology 7, no. 2.16 (April 12, 2018): 110. http://dx.doi.org/10.14419/ijet.v7i2.16.11505.

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DSP operations are very important part of engineering as well as medical discipline. For the designing of DSP operations Multiplication is play important role to perform signal processing operations. Multiplier is one of the critical components in the area of digital signal processing and hearing aids. So the objective is to design an efficient MAC hardware architecture using multiplier with assistance of compressors by conserving less area, power and delay. In this paper, efficient hardware architecture of MAC using a modified Wallace tree multiplier is proposed. The proposed MAC uses multiplier with novel compressor designs and adders as primitive building blocks for efficient application. Further, the Verilog-HDL coding of 8 bit MAC architecture and their FPGA implementation by Xilinx ISE 14.4 Synthesis Tool on Virtex7 kit have been done. The proposed compressor and adder based architecture used to be applied to MAC unit and in comparison to the previous design MAC unit and verified that the proposed architecture have reduce in terms of area, delay and power. The high performance is obtained by using a new hierarchical structure, these adders are called compressors. These compressors make the multipliers faster as compared to the conventional design used in Engineering, Science & Technology as well as medical discipline.

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24

T U, Anusree, and Bonifus P L. "Design and Analysis of Modified Fast Compressors for MAC Unit." International Journal of Computer Trends and Technology 36, no. 4 (June 25, 2016): 213–18. http://dx.doi.org/10.14445/22312803/ijctt-v36p137.

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25

Gierenz, Volker, Christian Panis, and Jari Nurmi. "Parameterized MAC unit generation for a scalable embedded DSP core." Microprocessors and Microsystems 34, no. 5 (August 2010): 138–50. http://dx.doi.org/10.1016/j.micpro.2010.02.001.

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26

Karthikeyan, K. V., R. Babu, N. Mathan, and B. Karthick. "Performance analysis of an efficient MAC unit using CNTFET technology." Materials Today: Proceedings 3, no. 6 (2016): 2525–31. http://dx.doi.org/10.1016/j.matpr.2016.04.171.

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27

Masadeh, Mahmoud, Osman Hasan, and Sofiene Tahar. "Input-Conscious Approximate Multiply-Accumulate (MAC) Unit for Energy-Efficiency." IEEE Access 7 (2019): 147129–42. http://dx.doi.org/10.1109/access.2019.2946513.

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28

Abinaya, A., and M. Maheswari. "Efficient Fused MAC Unit Using Multi-Operand Parallel Prefix Adder." Radioelectronics and Communications Systems 65, no. 4 (April 2022): 213–20. http://dx.doi.org/10.3103/s0735272722040057.

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29

Dinah, Shalo Thanga, and V. Jeyalakshm. "High Performance Multiply Accumulate (MAC) Unit Based FIR Filter Design." International Journal of Applied Engineering Research 17, no. 6 (December 30, 2022): 565–72. http://dx.doi.org/10.37622/ijaer/17.6.2022.565-572.

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30

BARANDIARAN, S., A. M. PÉREZ, A. K. GIOFFRÉ, M. MARTÍNEZ VIVOT, A. A. CATALDI, and M. J. ZUMÁRRAGA. "Tuberculosis in swine co-infected withMycobacterium aviumsubsp.hominissuisandMycobacterium bovisin a cluster from Argentina." Epidemiology and Infection 143, no. 5 (December 12, 2014): 966–74. http://dx.doi.org/10.1017/s095026881400332x.

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SUMMARYIn Argentina little is known about the epidemiology of tuberculosis (TB) infection in swine. We characterized the epidemiological dynamics ofMycobacterium aviumcomplex (MAC) infection in a swine population of Argentina using molecular tools and spatial analysis techniques. Isolates (n = 196) obtained from TB-like lesions (n = 200) were characterized by polymerase chain reaction. The isolates were positive to eitherM. bovis(IS6110) (n = 160) orM. avium(IS1245) (n= 16) while the remaining 20 (10·2%) isolates were positive to bothM. bovisandM. avium. The detection of both bacteria together suggests co-infection at the animal level. In addition, MAC-positive isolates (n = 36) were classified asM. aviumsubsp.avium(MAA) (n = 30) andM. aviumsubsp.hominissuis(MAH) (n = 6), which resulted in five genotypes when they were typed using mycobacterial interspersed repetitive unit, variable number of tandem repeats (MIRU-VNTR). One significant (P = 0·017) spatial clustering of genotypes was detected, in which the proportion of MAH isolates was larger than expected under the null hypothesis of even distribution of genotypes. These results show that in Argentina the proportion of TB cases in pigs caused byM. aviumis larger than that reported in earlier studies. The proportion ofM. bovis–MAC co-infections was also higher than in previous reports. These results provide valuable information on the epidemiology of MAC infection in swine in Argentina.

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31

Shin, Jeong-Ih, Sung Jae Shin, and Min-Kyoung Shin. "Differential Genotyping of Mycobacterium avium Complex and Its Implications in Clinical and Environmental Epidemiology." Microorganisms 8, no. 1 (January 10, 2020): 98. http://dx.doi.org/10.3390/microorganisms8010098.

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In recent decades, the incidence and prevalence of nontuberculous mycobacteria (NTM) have greatly increased, becoming a major worldwide public health problem. Among numerous NTM species, the Mycobacterium avium complex (MAC) is the most predominant species, causing disease in humans. MAC is recognized as a ubiquitous microorganism, with contaminated water and soil being established sources of infection. However, the reason for the recent increase in MAC-associated disease has not yet been fully elucidated. Furthermore, human MAC infections are associated with a variety of infection sources. To improve the determination of infection sources and epidemiology of MAC, feasible and reliable genotyping methods are required to allow for the characterization of the epidemiology and biology of MAC. In this review, we discuss genotyping methods, such as pulsed-field gel electrophoresis, a variable number of tandem repeats, mycobacterial interspersed repetitive-unit-variable number of tandem repeats, and repetitive element sequence-based PCR that have been applied to elucidate the association between the MAC genotypes and epidemiological dominance, clinical phenotypes, evolutionary process, and control measures of infection. Characterizing the association between infection sources and the epidemiology of MAC will allow for the development of novel preventive strategies for the effective control of MAC infection.

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32

Sennerich, Maximilian, Peter G. Weidler, Stefan Heißler, and Bettina Kraushaar-Czarnetzki. "Effect of Cesium and Phosphate Addition to Mo/V/W Mixed Oxide Catalysts for the Gas Phase Oxidation of Methacrolein to Methacrylic Acid." Catalysts 11, no. 2 (February 9, 2021): 231. http://dx.doi.org/10.3390/catal11020231.

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The present study investigates modified Mo/V/W mixed oxides as a possible alternative for state of the art heteropoly acid catalysts (HPA) in the partial oxidation of methacrolein (MAC) to methacrylic acid (MAA). Even though HPAs show an excellent activity and MAA selectivity, their long-term stability is unsatisfying, rendering the catalyst inoperable after runtimes of roughly 6 months. Mo/V/W mixed oxides consisting of M1 and a hexagonal (Mo,V,W)Ox-phase (h-phase) in varying proportions were modified by impregnation with aqueous solutions containing cesium and phosphate ions. All samples were characterized with respect to specific surface area, crystallinity, elemental and phase composition. The catalytic performance in the oxidation of MAC to MAA was investigated using a continuously operated reaction unit with tubular fixed bed reactor. Impregnation with cesium and phosphate ions and subsequent heating triggers the transformation of the mixed oxide into a Keggin-type HPA, whereby the h-phase is more reactive than M1. The transformation into HPA is accompanied by a change in the catalytic properties, i.e., the selectivity to MAA is considerably improved. Compared to HPA synthesized directly, however, the HPA samples obtained by transformation of mixed oxides exhibit no advantages, be it with respect to activity, MAA selectivity or stability.

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33

Reddy Hemantha, G., S. Varadarajan, and M. N. Giriprasad. "DA Based Systematic Approach Using Speculative Addition for High Speed DSP Applications." International Journal of Engineering & Technology 7, no. 2.24 (April 25, 2018): 197. http://dx.doi.org/10.14419/ijet.v7i2.24.12030.

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In recent years Parallel-prefix topologies has been emerged to offer a high-speed solution for many DSP applications. Here in this paper carrier approximation is introduced to incorporate speculation in Han Carlson prefix method. And overall latency is considerably reduced using single Brent-Kung addition as a pre and post processing unit. In order to improve the reliability error detection network is combined with the approximated adder and it is assert the error correction unit whenever speculation fails during carries propagation from LSB segment to MSB unit. The proposed speculative adder based on Han-Carlson parallel-prefix topology attains better latency reduction than variable latency Kogge-Stone topology. Finally, multiplier-accumulation unit (MAC) is designed using serial shift-based accumulation where the proposed speculative adder is used for partial product addition iteratively. The performance merits and latency reduction of proposed adder unit is proved through FPGA hardware synthesis. Obtained results show that proposed MAC unit outperforms both previously proposed speculative architectures and all other high-speed multiplication methods.

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34

Lee, Ha Cheol. "A MAC Throughput in the IEEE 802.11ac over Error-Prone Channel." Applied Mechanics and Materials 631-632 (September 2014): 801–5. http://dx.doi.org/10.4028/www.scientific.net/amm.631-632.801.

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This paper analyzes a MAC (Medium Access Control) layer throughput over error-prone channel in the IEEE 802.11ac-based wireless LAN with DCF (Distributed Coordination Function) protocol and A-MPDU (MAC Protocol Data Unit Aggregation) scheme, using theoretical analysis method. The MAC saturation throughput is evaluated by using a PER (Packet Error Rate) on the condition that the number of station, transmission probability, the number of parallel beams and the number of frames in each A-MPDU are variables. When the PER is 10-2 and the number of aggregated MPDUs in each A-MPDU is 20, it is identified that the MAC layer throughput of IEEE 802.11ac can be maximally attained up to a 92.8% of physical transmission rate.

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35

Gugan, K., and S. V. Saravanan. "Optimization of Arithmetical Operators for the Enhanced Wallace Stage." Indonesian Journal of Electrical Engineering and Computer Science 9, no. 3 (March 1, 2018): 591. http://dx.doi.org/10.11591/ijeecs.v9.i3.pp591-594.

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<p>In the field of Digital signal processing (DSP), the reduction of some logical elements counts is one of the main considerations. To minimize the area, computational delay, and power, the digital form FIR filter is to be implemented. The optimization of the ATP (Area, Time and Power) is achieved by using the efficient multiplication and accumulation unit (MAC). In this work, the direct form FIR filter with the efficient MAC unit is presented. At the initial stage, the half adders and full adders are to be modified by the reduction of the logical gates. The modified half and full adder are implemented in the Wallace tree multiplier for performing the efficient multiplication process. Carry save adder is divided into the two stages to reduce the computational delay of arithmetical operators. The proposed MAC design is implemented in the direct form FIR filter by using the HDL language.</p>

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36

Nivedha, M., and V. Priyadharshini. "Design and Implementation of High Speed and Area Efficient MAC Unit." International Journal of MC Square Scientific Research 9, no. 1 (April 16, 2017): 117–29. http://dx.doi.org/10.20894/ijmsr.117.009.001.014.

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37

Munasypova, Alina M., Aigul M. Rakhmangulova, Airat I. Akhunov, Olga Yu Belousova, and Rustem Sh Yapaev. "RESEARCH OF CATALYTIC CRACKING CATALYST ACTIVITY AT LINTEL MAC-10 UNIT." Oil and Gas Business, no. 1 (February 2020): 195. http://dx.doi.org/10.17122/ogbus-2020-1-195-212.

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38

Maitra, Subhashis, and Amitabha Sinha. "Design and simulation of MAC unit using combinational circuit and adder." ACM SIGARCH Computer Architecture News 41, no. 5 (December 18, 2013): 25–33. http://dx.doi.org/10.1145/2641361.2641365.

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39

Xiaoping Huang, Wen-Jung Liu, and B. W. Y. Wei. "A high-performance CMOS redundant binary multiplication-and-accumulation (MAC) unit." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 41, no. 1 (1994): 33–39. http://dx.doi.org/10.1109/81.260217.

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40

Vanama, Chinababu. "Implementation of High Speed Modified Booth Multiplier and Accumulator (Mac) Unit." IOSR Journal of Electronics and Communication Engineering 8, no. 5 (2013): 17–25. http://dx.doi.org/10.9790/2834-0851725.

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41

Mohsin, Syed, Rahul J. Gowda, Asha CN, and Sumalatha S. "Physical Design of 64-bit Multiplier and Accumulator (MAC) Unit Using Vedic Multiplier and CLA Adder." Journal of Electrical Engineering and Electronics Design 1, no. 1 (2023): 5–9. http://dx.doi.org/10.48001/joeeed.2023.115-9.

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In digital signal processing, communication systems and many other applications, multiplier and accumulator units play a crucial role. This work presents an overview of 64-bit MAC Unit, where Vedic multiplier is used as multiplier unit and compared Carry select adders (CSA) and Carry look-ahead adder (CLA) which must be used for adder unit, accumulator unit consist of Parallel in parallel out (PIPO) shift registers. As a result, CLA adder to be more effective in terms of lower delay by comparing with other adders. The MAC Unit was modelled using Verilog-HDL, where its functional verification and synthesized was done using Intel Quartus Prime 21.1, which was simulated on Questa Intel FPGA 21.1. Further GDSII file was created using the cadence tool with the help of Incisive for functional simulation, Genus for synthesis and pre-layout timing analysis, and innovus for physical design. Entire study was carried out in 180nm technology from RTL-GDSII. The delay, power, area was monitored, the memory usage, Pre-Clock Tree Synthesis, Post-Clock Tree Synthesis (CTS) were noted before and after optimization of design.

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42

Rao, Dr B. Rama. "Design and Implementation of 6-Tap FIR Filter Using MAC for Low Power Applications." International Journal for Research in Applied Science and Engineering Technology 10, no. 6 (June 30, 2022): 1506–11. http://dx.doi.org/10.22214/ijraset.2022.44081.

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Abstract: A Significant number of mathematical operations, such as multiplication and accumulation, are often required by a digital signal processing (DSP) algorithm. Many DSP applications have latency limitations, which mean that the DSP operation must be performed within a certain amount of time for the system to function, and because DSP gives high accuracy, filters constructed in DSP have tighter control over the output accuracy. As a result, DSP applications must be fast, have a high throughput, and use little power. Filters with a finite impulse response (FIR) are commonly employed in digital signal processing (DSP) applications. A FIR filter that is efficient in terms of electricity is being built. The multiplier and accumulator (MAC) unit used a new implementation approach to develop this system. FIR filter is a type of filter. Multipliers, adders, and a variety of other components are commonly used in FIR filters. Multipliers, adders, and a series of delays are used to form the filter's output in FIR filters. The goal of this project is to design and implement a 6-tap finite impulse response (FIR) filter by replacing multipliers with an 8-bit Multiplier and Accumulator (MAC) unit within the FIR filter, where a low-power MAC unit is always a key to achieving high performance in a DSP system, and D flip-flops are used in place of delays and constructed using a latch-based design. The Wallace tree Multiplier was utilised in the construction of the MAC unit because it reduces the amount of partial products, and the adders used for accumulation are half adders and full adders. In the FIR filter, for the purpose of summing This work evaluates performance of FIR filter in terms of speed and power and synthesis are executed in Xilinx Vivado 2018.1 software environment and the implementation is done using VHDL codes. The result analysis shows that the proposed FIR filter consumes low power than conventional (standard) FIR filter. As the dynamic power results up to 11.932W and after implementation it results up to 12.029W. Keywords: MAC, Low power, latch-based design.

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43

Legkii, Alexander, Natalya Karapuzova, Alexei Kudashev, Vladimir Zlobin, and Oksana Vlasova. "Environmental efficiency investigation of a gas turbine unit." E3S Web of Conferences 281 (2021): 09017. http://dx.doi.org/10.1051/e3sconf/202128109017.

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A method for purifying the gas-air mixture of a gas turbine unit and a waste-heat boiler is considered [1-3]. This work describes the principle of a gas-turbine plant and a waste-heat boiler operation using a catalytic afterburner, with the help of which a more complete process of carbon dioxide and nitrogenous compounds release occurs. Also, as a result of the exhaust gas-air mixture deeper cleaning process, there is a decrease in emissions within the maximum admissible concentrations (MAC), namely, by the amount of nitrogen and carbon oxides [4–7]. That allows to reduce the number of harmful substances, oxides of nitrogenous and carbon compounds, emitted into the environment. A scheme for cleaning a catalytic afterburner using rotary mesh devices, followed by disposal of carbon deposits and soot substances from the cleaning chamber is shown. This makes it possible to perform a stable ion exchange process, reducing the exhaust gases combustion products amount. It is proposed in this article to use mesh devices in the afterburner, treated with active substances by the method of ion implantation, as one of the most promising methods for modifying mesh surfaces. These processes occurring when the gas-air mixture passes through the afterburner, can reduce MAC emissions for various options for utilizing the discharge fuel mixture of a gas turbine unit (GTU) and heat supply to the waste heat boiler.

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44

Lyakhov, Pavel, Maria Valueva, Georgii Valuev, and Nikolai Nagornov. "A Method of Increasing Digital Filter Performance Based on Truncated Multiply-Accumulate Units." Applied Sciences 10, no. 24 (December 18, 2020): 9052. http://dx.doi.org/10.3390/app10249052.

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This paper proposes new digital filter architecture based on a modified multiply-accumulate (MAC) unit architecture called truncated MAC (TMAC), with the aim of increasing the performance of digital filtering. This paper provides a theoretical analysis of the proposed TMAC units and their hardware simulation. Theoretical analysis demonstrated that replacing conventional MAC units with modified TMAC units, as the basis for the implementation of digital filters, can theoretically reduce the filtering time by 29.86%. Hardware simulation showed that TMAC units increased the performance of digital filters by up to 10.89% compared to digital filters using conventional MAC units, but were associated with increased hardware costs. The results of this research can be used in the theory of digital signal processing to solve practical problems such as noise reduction, amplification and suppression of the frequency spectrum, interpolation, decimation, equalization and many others.

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45

Neumann, Frank, Oliver Lobitz, Roland Fenk, Mustafa Kondakci, Thorsten Graef, Ingmar Bruns, Malte Kelm, Ali-Nuri Huenerlituerkoglu, Rainer Haas, and Guido Kobbe. "Poor Prognosis for Patients after Myelo- and Non-Myeloablative Conditioning Therapy Followed by Allogeneic Peripheral Blood Stem Cell Transplantation Admitted to Intensive Care Unit." Blood 108, no. 11 (November 16, 2006): 3678. http://dx.doi.org/10.1182/blood.v108.11.3678.3678.

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Abstract Background and Aims: The role of intensive care unit (ICU) support for patients following allogeneic peripheral blood stem cell transplantation (PBSCT) is controversial. In an era of constrained resources, we assessed prognostic factors predictive for survival in patients after myeloablative (MAC) and non-myeloablative allogeneic (non-MAC) PBSCT over a period of seven years. Patients: Between January 1999 and February 2006 three-hundred and one patients with various hematological malignancies underwent allogeneic stem cell tranplantation in our institution (MAC 196, non-MAC 105). Of these, sixty-four patients (21,3%) with a median age of 47 years (range 18–64 years; female 24, male 40; MAC 49, non-MAC 15) were admitted to the ICU during the first two years following PBSCT (median 55 days, range 1–631 days). We looked for variables defining the SOFA (Sequential Organ Failure Assessment) and the SAPS (Simplified Acute Physiology Score) score on the day of ICU admission and five days later to discriminate patients with poor and good prognosis with regard to survival. We also looked for variables such as age of patients, diagnosis, disease status, donor type, time between transplantation and ICU admission, reason for ICU admission and occurrence of veno-occlusive disease and GVHD. Results: Mechanical ventilation was required by all patients admitted to the ICU. Median survival following referral to ICU was 22 days (range 0 – 959 days). The main reason for death was sepsis (56%). Among 49 patients who had received MAC 19 (39%) survived the ICU stay with a median survival time of 11 months (range 0–29 months). In the group of patients who had received non-MAC 3 out of 15 patients (20%) could be discharged from the ICU with a median survival time of 5 months (range 4–12 months). Looking at the twenty-two ICU survivors there were seven patients who survived the following year resulting in an overall survival of 11% one year after ICU admission. Only the SOFA score (p = 0.002) on the day of ICU admission was of prognostic relevance for survival. Conclusion: ICU admission and respiratory failure are associated with poor prognosis after allogeneic stem cell transplantation The probability of survival is independent from the type of conditioning therapy. The SOFA score is a predictor for short term survival but fails to identify long term survivors.

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46

Devic, Guillaume, Gilles Sassatelli, and Abdoulaye Gamatié. "A Bottom-Up Methodology for the Fast Assessment of CNN Mappings on Energy-Efficient Accelerators." Journal of Low Power Electronics and Applications 13, no. 1 (January 5, 2023): 5. http://dx.doi.org/10.3390/jlpea13010005.

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The execution of machine learning (ML) algorithms on resource-constrained embedded systems is very challenging in edge computing. To address this issue, ML accelerators are among the most efficient solutions. They are the result of aggressive architecture customization. Finding energy-efficient mappings of ML workloads on accelerators, however, is a very challenging task. In this paper, we propose a design methodology by combining different abstraction levels to quickly address the mapping of convolutional neural networks on ML accelerators. Starting from an open-source core adopting the RISC-V instruction set architecture, we define in RTL a more flexible and powerful multiply-and-accumulate (MAC) unit, compared to the native MAC unit. Our proposal contributes to improving the energy efficiency of the RISC-V cores of PULPino. To effectively evaluate its benefits at system level, while considering CNN execution, we build a corresponding analytical model in the Timeloop/Accelergy simulation and evaluation environment. This enables us to quickly explore CNN mappings on a typical RISC-V system-on-chip model, manufactured under the name of GAP8. The modeling flexibility offered by Timeloop makes it possible to easily evaluate our novel MAC unit in further CNN accelerator architectures such as Eyeriss and DianNao. Overall, the resulting bottom-up methodology assists designers in the efficient implementation of CNNs on ML accelerators by leveraging the accuracy and speed of the combined abstraction levels.

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47

Hoang, Tung Thanh, Magnus Sjalander, and Per Larsson-Edefors. "A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit." IEEE Transactions on Circuits and Systems I: Regular Papers 57, no. 12 (December 2010): 3073–81. http://dx.doi.org/10.1109/tcsi.2010.2091191.

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48

Lee, Joyoung, Zijia Zhong, Bo Du, Slobodan Gutesa, and Kitae Kim. "Low-Cost and Energy-Saving Wireless Sensor Network for Real-Time Urban Mobility Monitoring System." Journal of Sensors 2015 (2015): 1–8. http://dx.doi.org/10.1155/2015/685786.

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This paper presents a low-cost and energy-saving urban mobility monitoring system based on wireless sensor networks (WSNs). The primary components of the proposed sensor unit are a Bluetooth sensor and a Zigbee transceiver. Within the WSN, the Bluetooth sensor captures the MAC addresses of Bluetooth units equipped in mobile devices and car navigation systems. The Zigbee transceiver transmits the collected MAC addresses to a data center without any major communications infrastructures (e.g., fiber optics and 3G/4G network). A total of seven prototype sensor units have been deployed on roadway segments in Newark, New Jersey, for a proof of concept (POC) test. The results of the POC test show that the performance of the proposed sensor unit appears promising, resulting in 2% of data drop rates and an improved Bluetooth capturing rate.

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49

Nagaraju, N., and S. M. Ramesh. "Implementation of high speed and area efficient MAC unit for industrial applications." Cluster Computing 22, S2 (March 2, 2018): 4511–17. http://dx.doi.org/10.1007/s10586-018-2060-z.

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50

Jadhav, Shubham, Ved Gund, Benyamin Davaji, Debdeep Jena, Huili (Grace) Xing, and Amit Lal. "HZO-based FerroNEMS MAC for in-memory computing." Applied Physics Letters 121, no. 19 (November 7, 2022): 193503. http://dx.doi.org/10.1063/5.0120629.

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This paper demonstrates a hafnium zirconium oxide (HZO)-based ferroelectric NEMS unimorph as the fundamental building block for very low-energy capacitive readout in-memory computing. The reported device consists of a [Formula: see text]2 unimorph cantilever with 20-nm-thick ferroelectric HZO on 1 μm SiO2. Partial ferroelectric switching in HZO achieves analog programmable control of the piezoelectric coefficient (d31), which serves as the computational weight for multiply accumulate (MAC) operations. The displacement of the piezoelectric unimorph was recorded by actuating the device with different input voltages Vin. The resulting displacement was measured as a function of the ferroelectric programming/poling voltage [Formula: see text]. The slopes of central beam displacement (δmax) vs Vin were measured to be between 182.9 nm/V (for −8 Vp) and −90.5 nm/V (for 8 Vp), which corresponds to displacement proportionality constant β of 68 nm/V2 for +ve Vp and 47 nm/V2 for −ve Vp, demonstrating linear behavior of the multiplier unit. The resultant δmax from AC actuation is in the range of −18 to 36 nm and is a scaled product of Vin and programmed d31 (governed by the Vp). The multiplication function serves as the fundamental unit for MAC operations with the ferroelectric NEMS unimorph. The displacement from many such beams can be added by summing the capacitance changes, providing a pathway to implement a multi-input and multi-weight neuron. A scaling and fabrication analysis suggests that this device can be CMOS compatible, achieving high in-memory computational throughput.

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