Увійти

Готові списки джерел за темами / Lowe Power Accelerators

Зміст

Дисертації

Добірка наукової літератури з теми "Lowe Power Accelerators"

Автор: Grafiati

Опубліковано: 14 березня 2023

Оформте джерело за APA, MLA, Chicago, Harvard та іншими стилями

Оберіть тип джерела:

Ознайомтеся зі списками актуальних статей, книг, дисертацій, тез та інших наукових джерел на тему "Lowe Power Accelerators".

Біля кожної праці в переліку літератури доступна кнопка «Додати до бібліографії». Скористайтеся нею – і ми автоматично оформимо бібліографічне посилання на обрану працю в потрібному вам стилі цитування: APA, MLA, «Гарвард», «Чикаго», «Ванкувер» тощо.

Також ви можете завантажити повний текст наукової публікації у форматі «.pdf» та прочитати онлайн анотацію до роботи, якщо відповідні параметри наявні в метаданих.

Дисертації з теми "Lowe Power Accelerators"

1

ROOZMEH, MEHDI. "High Performance Computing via High Level Synthesis." Doctoral thesis, Politecnico di Torino, 2018. http://hdl.handle.net/11583/2710706.

Повний текст джерела

Анотація:

As more and more powerful integrated circuits are appearing on the market, more and more applications, with very different requirements and workloads, are making use of the available computing power. This thesis is in particular devoted to High Performance Computing applications, where those trends are carried to the extreme. In this domain, the primary aspects to be taken into consideration are (1) performance (by definition) and (2) energy consumption (since operational costs dominate over procurement costs). These requirements can be satisfied more easily by deploying heterogeneous platfor

Стилі APA, Harvard, Vancouver, ISO та ін.

2

Riera, Villanueva Marc. "Low-power accelerators for cognitive computing." Doctoral thesis, Universitat Politècnica de Catalunya, 2020. http://hdl.handle.net/10803/669828.

Повний текст джерела

Анотація:

Deep Neural Networks (DNNs) have achieved tremendous success for cognitive applications, and are especially efficient in classification and decision making problems such as speech recognition or machine translation. Mobile and embedded devices increasingly rely on DNNs to understand the world. Smartphones, smartwatches and cars perform discriminative tasks, such as face or object recognition, on a daily basis. Despite the increasing popularity of DNNs, running them on mobile and embedded systems comes with several main challenges: delivering high accuracy and performance with a small memory an

Стилі APA, Harvard, Vancouver, ISO та ін.

3

Yang, Yunfeng. "Low Power UDP/IP Accelerator for IM3910 Processor." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-92241.

Повний текст джерела

Анотація:

Due to their attractive flexibility and high productivity, general purpose processors (GPPs) are found to be spreading over large domain of applications. The growing complexity of modern applications results in high performance demands and as a response, several solutions have came to fulfill these demands. One of these solutions is to couple the GPP with a hardware accelerator to off-load critical functionalities. In this thesis, A UDP/IP hardware accelerator is build to and coupled with an existing GPP with DMA interface, namely IM3910 form Imsys Technology AB in Stockholm, Sweden. The main

Стилі APA, Harvard, Vancouver, ISO та ін.

4

Yazdani, Aminabadi Reza. "Ultra low-power, high-performance accelerator for speech recognition." Doctoral thesis, Universitat Politècnica de Catalunya, 2019. http://hdl.handle.net/10803/667429.

Повний текст джерела

Анотація:

Automatic Speech Recognition (ASR) is undoubtedly one of the most important and interesting applications in the cutting-edge era of Deep-learning deployment, especially in the mobile segment. Fast and accurate ASR comes at a high energy cost, requiring huge memory storage and computational power, which is not affordable for the tiny power budget of mobile devices. Hardware acceleration can reduce power consumption of ASR systems as well as reducing its memory pressure, while delivering high-performance. In this thesis, we present a customized accelerator for large-vocabulary, speaker-indepen

Стилі APA, Harvard, Vancouver, ISO та ін.

5

Prasad, Rohit <1991&gt. "Integrated Programmable-Array accelerator to design heterogeneous ultra-low power manycore architectures." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2022. http://amsdottorato.unibo.it/9983/1/PhD_thesis__20_January_2022_.pdf.

Повний текст джерела

Анотація:

There is an ever-increasing demand for energy efficiency (EE) in rapidly evolving Internet-of-Things end nodes. This pushes researchers and engineers to develop solutions that provide both Application-Specific Integrated Circuit-like EE and Field-Programmable Gate Array-like flexibility. One such solution is Coarse Grain Reconfigurable Array (CGRA). Over the past decades, CGRAs have evolved and are competing to become mainstream hardware accelerators, especially for accelerating Digital Signal Processing (DSP) applications. Due to the over-specialization of computing architectures, the focus i

Стилі APA, Harvard, Vancouver, ISO та ін.

6

Tabani, Hamid. "Low-power architectures for automatic speech recognition." Doctoral thesis, Universitat Politècnica de Catalunya, 2018. http://hdl.handle.net/10803/462249.

Повний текст джерела

Анотація:

Automatic Speech Recognition (ASR) is one of the most important applications in the area of cognitive computing. Fast and accurate ASR is emerging as a key application for mobile and wearable devices. These devices, such as smartphones, have incorporated speech recognition as one of the main interfaces for user interaction. This trend towards voice-based user interfaces is likely to continue in the next years which is changing the way of human-machine interaction. Effective speech recognition systems require real-time recognition, which is challenging for mobile devices due to the compute-in

Стилі APA, Harvard, Vancouver, ISO та ін.

7

Gandolfi, Riccardo. "Design of a memory-to-memory tensor reshuffle unit for ultra-low-power deep learning accelerators." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2021. http://amslaurea.unibo.it/23706/.

Повний текст джерела

Анотація:

In the context of IoT edge-processing, deep learning applications and near-sensor analytics, the constraints on having low area occupation and low power consumption in MCUs (Microcontroller Units) performing computationally intensive tasks are more stringent than ever. A promising direction is to develop HWPEs (Hardware Processing Engines) that support and help the end-node in the execution of these tasks. The following work concerns the design and testing of the Datamover, a small and easily configurable HWPE for tensor shuffling and data marshaling operation. The accelerator is to be integra

Стилі APA, Harvard, Vancouver, ISO та ін.

8

Bleakley, Steven Shea, and steven bleakley@qr com au. "Time Frequency Analysis of Railway Wagon Body Accelerations for a Low-Power Autonomous Device." Central Queensland University, 2006. http://library-resources.cqu.edu.au./thesis/adt-QCQU/public/adt-QCQU20070622.121515.

Повний текст джерела

Анотація:

This thesis examines the application of the techniques of Fourier spectrogram and wavelet analysis to a low power embedded microprocessor application in a novel railway and rollingstock monitoring system. The safe and cost effective operation of freight railways is limited by the dynamic performance of wagons running on track. A monitoring system has been proposed comprising of low cost wireless sensing devices, dubbed Health Cards, to be installed on every wagon in the fleet. When marshalled into a train, the devices would sense accelerations and communicate via radio network to a master

Стилі APA, Harvard, Vancouver, ISO та ін.

9

Xu, Hongjie. "Energy-Efficient On-Chip Cache Architectures and Deep Neural Network Accelerators Considering the Cost of Data Movement." Doctoral thesis, Kyoto University, 2021. http://hdl.handle.net/2433/263786.

Повний текст джерела

Анотація:

付記する学位プログラム名: 京都大学卓越大学院プログラム「先端光・電子デバイス創成学」<br>京都大学<br>新制・課程博士<br>博士(情報学)<br>甲第23325号<br>情博第761号<br>京都大学大学院情報学研究科通信情報システム専攻<br>(主査)教授小野寺秀俊, 教授大木英司, 教授佐藤高史<br>学位規則第4条第1項該当<br>Doctor of Informatics<br>Kyoto University<br>DFAM

Стилі APA, Harvard, Vancouver, ISO та ін.

10

Das, Satyajit. "Architecture and Programming Model Support for Reconfigurable Accelerators in Multi-Core Embedded Systems." Thesis, Lorient, 2018. http://www.theses.fr/2018LORIS490/document.

Повний текст джерела

Анотація:

La complexité des systèmes embarqués et des applications impose des besoins croissants en puissance de calcul et de consommation énergétique. Couplé au rendement en baisse de la technologie, le monde académique et industriel est toujours en quête d'accélérateurs matériels efficaces en énergie. L'inconvénient d'un accélérateur matériel est qu'il est non programmable, le rendant ainsi dédié à une fonction particulière. La multiplication des accélérateurs dédiés dans les systèmes sur puce conduit à une faible efficacité en surface et pose des problèmes de passage à l'échelle et d'interconnexion.

Стилі APA, Harvard, Vancouver, ISO та ін.

Більше джерел

Ми пропонуємо знижки на всі преміум-плани для авторів, чиї праці увійшли до тематичних добірок літератури. Зв'яжіться з нами, щоб отримати унікальний промокод!