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Статті в журналах з теми "LOW-POWER PULSE-TRIGGERED"
Karimi, Ahmad, Abdalhossein Rezai, and Mohammad Mahdi Hajhashemkhani. "Ultra-Low Power Pulse-Triggered CNTFET-Based Flip-Flop." IEEE Transactions on Nanotechnology 18 (2019): 756–61. http://dx.doi.org/10.1109/tnano.2019.2929233.
Повний текст джерелаHU, YINGBO, and RUNDE ZHOU. "LOW CLOCK-SWING TSPC FLIP-FLOPS FOR LOW-POWER APPLICATIONS." Journal of Circuits, Systems and Computers 18, no. 01 (February 2009): 121–31. http://dx.doi.org/10.1142/s0218126609004971.
Повний текст джерелаHwang, Yin-Tsung, Jin-Fa Lin, and Ming-Hwa Sheu. "Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20, no. 2 (February 2012): 361–66. http://dx.doi.org/10.1109/tvlsi.2010.2096483.
Повний текст джерелаS, Vinothini Jane, Senthilkumar J. P, and Ravi G. "Improved low power implicit pulse triggered flip-flop with reduced power dissipation." International Journal of Computational Complexity and Intelligent Algorithms 1, no. 1 (2018): 1. http://dx.doi.org/10.1504/ijccia.2018.10021267.
Повний текст джерелаRavi, G., J. P. SenthilKumar, and S. Vinothini Jane. "Improved low power implicit pulse triggered flip-flop with reduced power dissipation." International Journal of Computational Complexity and Intelligent Algorithms 1, no. 2 (2019): 145. http://dx.doi.org/10.1504/ijccia.2019.103746.
Повний текст джерелаVerma, Shreya, Tunikipati Usharani, S. Iswariya, and Bhavana Godavarthi. "Implementation of MHLFF based low power pulse triggered flip flop." International Journal of Engineering & Technology 7, no. 1.1 (December 21, 2017): 483. http://dx.doi.org/10.14419/ijet.v7i1.1.10150.
Повний текст джерелаLokhande, Vinay R., and Sagar P. Soitkar. "Low Power Positive Edge Triggered Pulse Generater Using Ring Oscillator." Journal of Computational Intelligence and Electronic Systems 5, no. 1 (March 1, 2016): 54–57. http://dx.doi.org/10.1166/jcies.2016.1130.
Повний текст джерелаMr. Kankan Sarkar. "Design and analysis of Low Power High Speed Pulse Triggered Flip Flop." International Journal of New Practices in Management and Engineering 5, no. 03 (September 30, 2016): 01–06. http://dx.doi.org/10.17762/ijnpme.v5i03.45.
Повний текст джерелаJyothula, Sudhakar. "Low power aware pulse triggered flip flops using modified clock gating approaches." World Journal of Engineering 15, no. 6 (December 3, 2018): 792–803. http://dx.doi.org/10.1108/wje-09-2017-0309.
Повний текст джерелаkaala, D. S. R. Krishna. "Design of Low Power Negative Pulse-Triggered Flip-Flop with Enhanced Latch." IOSR Journal of VLSI and Signal Processing 3, no. 3 (2013): 06–12. http://dx.doi.org/10.9790/4200-0330612.
Повний текст джерелаДисертації з теми "LOW-POWER PULSE-TRIGGERED"
Renukaiah, Vishwas. "Low-power pulse-triggered flip-flop design based on a signal feed-through scheme." Thesis, California State University, Long Beach, 2015. http://pqdtopen.proquest.com/#viewpdf?dispub=1601314.
Повний текст джерелаIn this project, a novel pulse-triggered flip-flop design is proposed, which employs a modified True Single Phase Clock (TSPC) latch structure with a mixed style design consisting of pass transistor and pseudo nMOS logic. The proposed flip-flop design adopts a signal feed-through technique to improve the delay recovery, and achieves better performance in terms of speed and power consumption. The proposed flip-flop design has a weak pull-up pMOS transistor with gate connected to the ground in the first stage of TSPC latch. This structure is a pseudo nMOS logic style design. Post layout simulation results using CMOS 120nm technology affirms that in the proposed design delay is reduced when compared to existing system.
KUMAR, VICKY. "STUDY OF LOW-POWER PULSE-TRIGGERED FLIP-FLOPS." Thesis, 2017. http://dspace.dtu.ac.in:8080/jspui/handle/repository/16014.
Повний текст джерелаCho, Yu-Ru, and 卓育儒. "Design and application of low power pulse-triggered flip-flops." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/42558328998390817052.
Повний текст джерела國立雲林科技大學
電子與資訊工程研究所
97
Low power design of VLSI circuits has been identified as a critical technological need. The power consumption of the clock system, which consists of the clock distribution networks and storage elements, is estimated as about 20% to 45% of the total system power. As a result, reducing the power consumed by flip flops has a huge impact on the total power consumption. In particular, digital designs nowadays often adopt intensive pipelining techniques and employ many FF rich modules such as register file, shift register and FIFO. FFs thus contribute a significant portion of gate count and power consumption to the overall system design. In this thesis, a novel low power pulse-triggered based flip-flop is presented. By using a 2-transistor AND gate to control the pulse generation, the critical path of the design is effectively shortened. A conditional pulse enhancement technique is further incorporated to achieve a faster discharging along the critical path. Both design measures facilitate smaller transistor sizes in delay inverter and pulse generation circuit, which lead to better power performance against rival designs. Various post-layout simulation results based on UMC CMOS 90nm process technology reveal that, the proposed design can achieve over 17% saving in term of power and power-delay-product when compared with previous pulse-triggered based flip-flop designs. The reduction in leakage power consumption is as high as a factor of 2.4 due to the shrunken transistor size.
Wang, Peng-Siang, and 王鵬翔. "Low Power Pulse-Triggered Flip-Flops Designs with Hybrid Logic Style." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/04631727021339755036.
Повний текст джерела國立雲林科技大學
電子與資訊工程研究所
99
In recent years, power consumption is important issue on System on Chip and Very Large Scale Integration design. Besides the portable electronic products are indispensable on our life so that low-power IC design technique becomes a major trend. The clock system consists clock distribution network and storage elements (Flip-Flops、Latches), in which, storage elements power consumption account total power about 20~45% power of clock system. Therefore if we would reduce the flip-flops power consumption, the overall system could gain huge efficient on power consumption. Proposed circuits use a Hybrid-Logic technique that merge the PTL Logic to flip-flop successfully reduce the transistor counts and speed up the data propagation time and we employ TSMC 90nm and UMC 90nm to verify the proposed design performance, in dynamic latch part proposed design improved the PDP 25.9% and 27.94% respectively, further, in static latch part improved the PDP 12.6% and 11.68% respectively.
Li, Miao-Shan, and 李妙善. "Low power pipelined array multiplier design using delay line controlled dynamic adders and embedded pulse triggered FFs." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/82705044381793041937.
Повний текст джерелаPontikakis, Bill. "A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications." Thesis, 2003. http://spectrum.library.concordia.ca/2311/1/MQ83874.pdf.
Повний текст джерелаЧастини книг з теми "LOW-POWER PULSE-TRIGGERED"
Ma, Junjun, Fei Qiao, Huazhong Yang, and Hui Wang. "A PVT-Aware and Low Power Pulse-Triggered Flip-Flop." In Lecture Notes in Electrical Engineering, 11–20. Dordrecht: Springer Netherlands, 2012. http://dx.doi.org/10.1007/978-94-007-5076-0_2.
Повний текст джерелаSakthivel, Erulappan, and Rengaraj Madavan. "MAS: Maximum Energy-Aware Sense Amplifier Link for Asynchronous Network on Chip." In Network-on-Chip [Working Title]. IntechOpen, 2021. http://dx.doi.org/10.5772/intechopen.95075.
Повний текст джерелаТези доповідей конференцій з теми "LOW-POWER PULSE-TRIGGERED"
Samal, Lopamudra, Sauvagya Ranjan Sahoo, and Chiranjibi Samal. "A novel modified low power pulse triggered flip-flop." In 2017 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT). IEEE, 2017. http://dx.doi.org/10.1109/iceeccot.2017.8284552.
Повний текст джерелаIndira, P., and M. Kamaraju. "Low Power PVT robust area efficient pulse triggered Flip-Flop Design." In 2018 International Conference on Recent Innovations in Electrical, Electronics & Communication Engineering (ICRIEECE). IEEE, 2018. http://dx.doi.org/10.1109/icrieece44171.2018.9009201.
Повний текст джерелаZhao Xianghong, Guo Jiankang, and Song Guanghui. "An improved low-power clock-gating pulse-triggered JK flip-flop." In 2010 International Conference on Information, Networking and Automation (ICINA 2010). IEEE, 2010. http://dx.doi.org/10.1109/icina.2010.5636463.
Повний текст джерелаAnjaneyulu, O., A. Veena, C. H. Shravan, and C. V. Krishna Reddy. "Self driven pass-transistor based low-power pulse triggered flip-flop design." In 2015 International Conference on Signal Processing And Communication Engineering Systems (SPACES). IEEE, 2015. http://dx.doi.org/10.1109/spaces.2015.7058266.
Повний текст джерелаGuang-Ping Xiang, Ji-Zhong Shen, Xue-Xiang Wu, and Liang Geng. "Design of a low-power pulse-triggered flip-flop with conditional clock technique." In 2013 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2013. http://dx.doi.org/10.1109/iscas.2013.6571797.
Повний текст джерелаLin, Jin-Fa, Ming-Hwa Sheu, and Peng-Siang Wang. "A low power dual-mode pulse triggered flip-flop using pass transistor logic." In 2010 International Symposium on Next-Generation Electronics (ISNE). IEEE, 2010. http://dx.doi.org/10.1109/isne.2010.5669163.
Повний текст джерелаParakundil, Liaqat Moideen, and N. Saraswathi. "Low power pulse triggered D-flip flops using MTCMOS and Self-controllable voltage level circuit." In 2014 International Conference on Advanced Communication, Control and Computing Technologies (ICACCCT). IEEE, 2014. http://dx.doi.org/10.1109/icaccct.2014.7019139.
Повний текст джерелаKavali, Krishna, S. Rajendar, and P. Vamshi Bhargava. "A novel low power double edge triggered flip-flop based on clock gated pulse suppression technique." In 2015 International Conference on Electrical, Electronics, Signals, Communication and Optimization (EESCO). IEEE, 2015. http://dx.doi.org/10.1109/eesco.2015.7253849.
Повний текст джерелаAguirre-Hernandez, M., and M. Linares-Aranda. "A Clock-Gated Pulse-Triggered D Flip-Flop for Low-Power High-Performance VLSI Synchronous Systems." In 2006 International Caribbean Conference on Devices, Circuits and Systems. IEEE, 2006. http://dx.doi.org/10.1109/iccdcs.2006.250876.
Повний текст джерелаWeiner, A. M., Y. Silberberg, H. Fouckhardt, D. E. Leaird, M. A. Saifi, M. J. Andrejco, and P. W. Smith. "Avoidance of Pulse Break-up in All-Optical Switching by Using Femtosecond Square Pulses." In Nonlinear Guided-Wave Phenomena. Washington, D.C.: Optica Publishing Group, 1989. http://dx.doi.org/10.1364/nlgwp.1989.pd5.
Повний текст джерела