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Готові списки джерел за темами / Kintex-7

Добірка наукової літератури з теми "Kintex-7"

Автор: Grafiati

Опубліковано: 30 травня 2022

Оновлено: 31 травня 2022

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Статті в журналах з теми "Kintex-7"

1

Ye, Y., H. Li, J. Li, and G. Gong. "Sub-nanosecond synchronization implementation in pure Xilinx Kintex-7 FPGA." Journal of Instrumentation 16, no. 11 (November 1, 2021): P11036. http://dx.doi.org/10.1088/1748-0221/16/11/p11036.

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Abstract White Rabbit (WR) provides high-performance synchronization with sub-nanosecond accuracy and picoseconds precision, and it has been included in the new High Accuracy Default PTP Profile in the IEEE 1588-2019. As an open-source project, WR Precision Time Protocol (WR-PTP) core has been implemented in different FPGA platforms with dedicated clock circuits. This paper presents a novel approach to achieve the WR function in Xilinx Kintex-7 FPGA depending on the on-chip resource. This approach could achieve sub-nanosecond accuracy and tens of picoseconds precision, simplifying WR devices' hardware design and making it possible to port the WR PTP core to many mature hardware platforms.

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2

Pandey, Bishwajeet, Geetam S. Tomar, Rajina R. Mohamed, D. M. Akbar Hussain, and Amit Kant Pandit. "Energy Efficient Design on 16 nm Ultrascale Plus Architecture Using Static Probability and Toggle Rate." Journal of Computational and Theoretical Nanoscience 17, no. 11 (November 1, 2020): 5122–24. http://dx.doi.org/10.1166/jctn.2020.9351.

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Scientists in 2010 were using a 40 nanometer Process based FPGA called Virtex-6 and 45 nm Process Technology based FPGA called Spartan-6. After 2010, researchers shifted their focus towards 28 nm technology based 7 series FPGA (Artix-7, Kintex-7, and Virtex-7) due to their intrinsic capability of low power consumption than both 40 nm and 45 nm technology based FPGA. In December, 2013, Xilinx introduced the 20 nm process technology based UltraScale series: Virtex UltraScale and Kintex UltraScale families. But now in 2020, researchers are using 16 nm technology based UltraScale+ FPGA. In our work, we are also using 16 nm technology based UltraScale+ FPGA for implementing our memory using VIVADO 2018.3 hardware programming tool and Verilog Hardware Description Language. There is 49.42%, 25.28% saving in design power on UltraScale+ FPGA when we minimize static probabilities to 0.1 and 0.2 respectively.

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3

Rashid, Muhammad, Sajjad Shaukat Jamal, Sikandar Zulqarnain Khan, Adel R. Alharbi, Amer Aljaedi, and Malik Imran. "Elliptic-Curve Crypto Processor for RFID Applications." Applied Sciences 11, no. 15 (July 31, 2021): 7079. http://dx.doi.org/10.3390/app11157079.

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This work presents an Elliptic-curve Point Multiplication (ECP) architecture with a focus on low latency and low area for radio-frequency-identification (RFID) applications over GF(2163). To achieve low latency, we have reduced the clock cycles by using: (i) three-shift buffers in the datapath to load Elliptic-curve parameters as well as an initial point, (ii) the identical size of input/output interfaces in all building blocks of the architecture. The low area is preserved by using the same hardware resources of squaring and multiplication for inversion computation. Finally, an efficient controller is used to control the inferred logic. The proposed ECP architecture is modeled in Verilog and the synthesis results are given on three different 7-series FPGA (Field Programmable Gate Array) devices, i.e., Kintex-7, Artix-7, and Virtex-7. The performance of the architecture is provided with the integration of a schoolbook multiplier (implemented with two different logic styles, i.e., combinational and sequential). On Kintex-7, the combinational implementation style of a schoolbook multiplier results in power-optimized, i.e., 161 μW, values with an expense of (i) hardware resources, i.e., 3561 look-up-tables and 1527 flip-flops, (ii) clock frequency, i.e., 227 MHz, and (iii) latency, i.e., 11.57 μs. On the same Kintex-7 device, the sequential implementation style of a schoolbook multiplier provides, (i) 2.88 μs latency, (ii) 1786 look-up-tables and 1855 flip-flops, (iii) 647 μW power, and (iv) 909 MHz clock frequency. Therefore, the reported area, latency and power results make the proposed ECP architecture well-suited for RFID applications.

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4

Abu Al-Haija, Qasem, and Sharifah M. S. Ahmad. "Fast Radix-2 Sequential Multiplier Using Kintex-7 FPGA Chip Family." Open Cybernetics & Systemics Journal 12, no. 1 (March 9, 2018): 30–41. http://dx.doi.org/10.2174/1874110x01812010030.

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5

Wang, Zibo, Wei Chen, Zhibin Yao, Fengqi Zhang, Yinhong Luo, Xiaobin Tang, Xiaoqiang Guo, Lili Ding, and Cong Peng. "Proton-induced single-event effects on 28 nm Kintex-7 FPGA." Microelectronics Reliability 107 (April 2020): 113594. http://dx.doi.org/10.1016/j.microrel.2020.113594.

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6

Sano, Y., Y. Horii, M. Ikeno, O. Sasaki, M. Tomoto, and T. Uchida. "Subnanosecond time-to-digital converter implemented in a Kintex-7 FPGA." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 874 (December 2017): 50–56. http://dx.doi.org/10.1016/j.nima.2017.08.038.

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7

Rahman, Atiqur. "Thermal Aware Power Efficient Frame Buffer Design on Kintex-7 FPGA." Gyancity Journal of Engineering and Technology 1, no. 1 (January 1, 2015): 29–39. http://dx.doi.org/10.21058/gjet.2015.1104.

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8

Rashid, Muhammad, Harish Kumar, Sikandar Zulqarnain Khan, Ismail Bahkali, Ahmed Alhomoud, and Zahid Mehmood. "Throughput/Area Optimized Architecture for Elliptic-Curve Diffie-Hellman Protocol." Applied Sciences 12, no. 8 (April 18, 2022): 4091. http://dx.doi.org/10.3390/app12084091.

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Анотація:

This paper presents a high-speed and low-area accelerator architecture for shared key generation using an elliptic-curve Diffie-Hellman protocol over GF(2233). Concerning the high speed, the proposed architecture employs a two-stage pipelining and a Karatsuba finite field multiplier. The use of pipelining shortens the critical path which ultimately improves the clock frequency. Similarly, the employment of a Karatsuba multiplier decreases the required number of clock cycles. Moreover, an efficient rescheduling of point addition and doubling operations avoids data hazards that appear due to pipelining. Regarding the low area, the proposed architecture computes finite field squaring and inversion operations using the hardware resources of the Karatsuba multiplier. Furthermore, two dedicated controllers are used for efficient control functionalities. The implementation results after place-and-route are provided on Virtex-7, Spartan-7, Artix-7 and Kintex-7 FPGA (field-programmable gate arrays) devices. The utilized FPGA slices are 5102 (on Virtex-7), 5634 (on Spartan-7), 5957 (on Artix-7) and 6102 (on Kintex-7). In addition to this, the time required for one shared-key generation is 31.08 (on Virtex-7), 31.68 (on Spartan-7), 31.28 (on Artix-7) and 32.51 (on Kintex-7). For performance comparison, a figure-of-merit in terms of throughputarea is utilized which shows that the proposed architecture is 963.3 and 2.76 times faster as compared to the related architectures. In terms of latency, the proposed architecture is 302.7 and 132.88 times faster when compared to the most relevant state-of-the-art approaches. The achieved results and performance comparison prove the significance of presented architecture in all those shared key generation applications which require high speed with a low area.

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9

Rashid, Muhammad, Mohammad Mazyad Hazzazi, Sikandar Zulqarnain Khan, Adel R. Alharbi, Asher Sajid, and Amer Aljaedi. "A Novel Low-Area Point Multiplication Architecture for Elliptic-Curve Cryptography." Electronics 10, no. 21 (November 4, 2021): 2698. http://dx.doi.org/10.3390/electronics10212698.

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This paper presents a Point Multiplication (PM) architecture of Elliptic-Curve Cryptography (ECC) over GF(2163) with a focus on the optimization of hardware resources and latency at the same time. The hardware resources are reduced with the use of a bit-serial (traditional schoolbook) multiplication method. Similarly, the latency is optimized with the reduction in a critical path using pipeline registers. To cope with the pipelining, we propose to reschedule point addition and double instructions, required for the computation of a PM operation in ECC. Subsequently, the proposed architecture over GF(2163) is modeled in Verilog Hardware Description Language (HDL) using Vivado Design Suite. To provide a fair performance evaluation, we synthesize our design on various FPGA (field-programmable gate array) devices. These FPGA devices are Virtex-4, Virtex-5, Virtex-6, Virtex-7, Spartan-7, Artix-7, and Kintex-7. The lowest area (433 FPGA slices) is achieved on Spartan-7. The highest speed is realized on Virtex-7, where our design achieves 391 MHz clock frequency and requires 416 μs for one PM computation (latency). For power, the lowest values are achieved on the Artix-7 (56 μW) and Kintex-7 (61 μW) devices. A ratio of throughput over area value of 4.89 is reached for Virtex-7. Our design outperforms most recent state-of-the-art solutions (in terms of area) with an overhead of latency.

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10

Du, Boyang, Luca Sterpone, Sarah Azimi, David Merodio Codinachs, Veronique Ferlet-Cavrois, Cesar Boatella Polo, Ruben Garcia Alia, Maria Kastriotou, and Pablo Fernandez-Martinez. "Ultrahigh Energy Heavy Ion Test Beam on Xilinx Kintex-7 SRAM-Based FPGA." IEEE Transactions on Nuclear Science 66, no. 7 (July 2019): 1813–19. http://dx.doi.org/10.1109/tns.2019.2915207.

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Більше джерел

Дисертації з теми "Kintex-7"

1

Жданова, Ю. В., та І. В. Свид. "Огляд сьомої серії FPGA компанії Xilinx". Thesis, Кременчуцький льотний коледж, 2019. http://openarchive.nure.ua/handle/document/9371.

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2

Свид, І. В., О. С. Мальцев, Л. Ф. Сайківська, and О. В. Зубков. "Review of Seventh Series FPGA Xilinx." Thesis, NURE, MC&FPGA, 2019. https://doi.org/10.35598/mcfpga.2019.008.

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3

Свид, І. В., О. С. Мальцев, Л. Ф. Сайківська, and О. В. Зубков. "Review of Seventh Series FPGA Xilinx." Thesis, NURE, MC&FPGA, 2019. https://mcfpga.nure.ua/conf/2019-mcfpga/10-35598-mcfpga-2019-008.

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Частини книг з теми "Kintex-7"

1

Arul Murugan C. and Banuselvasaraswathy B. "Challenges in FPGA Technology Paradigm for the Implementation of IoT Applications." In Advances in Systems Analysis, Software Engineering, and High Performance Computing, 1–21. IGI Global, 2020. http://dx.doi.org/10.4018/978-1-5225-9806-0.ch001.

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Internet of things (IoT) is a recent technology, and it will become the next generation of internet that connects several physical objects to interact amongst themselves without the assistance of human beings. It plays a significant role in our day-to-day lives and is used in several applications. IoT is a boon to this modern world, but it lacks in security. It cannot protect the user data from assailants, hackers, and vulnerabilities. Field programmable gate arrays (FPGA) helps to achieve all these objectives by incorporating secured end-to-end layer into its architecture. In this chapter, ultralow power and reduced area AES architecture with energy efficient DSE-S box techniques and clock gating for IoT applications are introduced. The proposed AES architecture is implemented over different FPGA families such as Cyclone I, Cyclone II, Virtex 5, and Kintex 7, respectively. From the experimental results, it is observed that the Kintex 7 FPGA kit consumes less power than other FPGA families.

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2

M, Babu, Sathish Kumar G.A, Gurumurthy J., and Josephine Shermila P. "Perspective Chapter: The Importance of Pipeline in Modern Cryptosystem." In Cryptography - Modern Theory and Practices [Working Title]. IntechOpen, 2022. http://dx.doi.org/10.5772/intechopen.102983.

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In this digital world, all the digital information transmitted through the wireless channel has a threat to its security. Along with security, encryption speed is also a significant factor in transmitting the data as fast as possible. The pipeline is the technique used to improve the throughput of the encryption process so that the amount of data encrypted per unit time will be increased. In this chapter, the design of the modern SMS4-BSK cryptosystem is briefed, various pipeline designs of SMS4 algorithms are surveyed and the pipeline implementation on SMS4-BSK cryptosystem is analyzed. The SMS4-BSK cryptosystem is robust, fast and has a throughput of 7.4 Gbps. This modern cryptosystem can resist all kinds of cryptanalysis attacks. The pipelining technique is implemented in this cryptosystem to improve the throughput further. The pipelining method is applied in the encryption architecture of the cryptosystem. The pipelined design is implemented in Kintex-7 FPGA. The design achieved a throughput of 9.9 Gbps. The pipeline implementation can be extended to the key scheduling architecture also as both the encryption and the key scheduling use the same architecture. As per the SMS4-BSK algorithm, the keys are generated in the host system to improve the throughput.

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Тези доповідей конференцій з теми "Kintex-7"

1

Kumar, Keshav, Amanpreet Kaur, and K. R. Ramkumar. "Effective Data Transmission with UART on Kintex-7 FPGA." In 2020 12th International Conference on Computational Intelligence and Communication Networks (CICN). IEEE, 2020. http://dx.doi.org/10.1109/cicn49253.2020.9242604.

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2

Pechenkin, Alexander A., Alexander A. Novikov, Marina M. Novikova, Dmitriy V. Bobrovsky, and George S. Sorokoumov. "SEL and SEFI discrimination in Kintex-7 using focused laser irradiation." In 2018 18th European Conference on Radiation and Its Effects on Components and Systems (RADECS). IEEE, 2018. http://dx.doi.org/10.1109/radecs45761.2018.9328667.

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3

Cojocariu, L. N., V. M. Placinta, and L. Dumitru. "Monitoring system for testing the radiation hardness of a KINTEX-7 FPGA." In 9TH INTERNATIONAL PHYSICS CONFERENCE OF THE BALKAN PHYSICAL UNION (BPU-9). AIP Publishing LLC, 2016. http://dx.doi.org/10.1063/1.4944199.

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4

Akash, D., M. Kishore, Mohana, and K. Hassen Basha. "Interfacing of flash memory and DDR3 RAM memory with Kintex 7 FPGA board." In 2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT). IEEE, 2017. http://dx.doi.org/10.1109/rteict.2017.8256950.

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5

Devakumar, Harshit, M. S. Panse, Ajay Khandare, and Miheer Mayekar. "Design of lightning acquisition and smart triggering using Kintex-7 FPGA and NI cRIO." In 2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT). IEEE, 2016. http://dx.doi.org/10.1109/rteict.2016.7808068.

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6

Hiemstra, David M., and Valeri Kirischian. "Single Event Upset Characterization of the Kintex-7 Field Programmable Gate Array Using Proton Irradiation." In 2014 IEEE Radiation Effects Data Workshop (REDW) (in conjunction with NSREC 2014). IEEE, 2014. http://dx.doi.org/10.1109/redw.2014.7004593.

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7

van-Harten, Louis, Roel Jordans, and Hamid Pourshaghaghi. "Necessity of Fault Tolerance Techniques in Xilinx Kintex 7 FPGA Devices for Space Missions: A Case Study." In 2017 Euromicro Conference on Digital System Design (DSD). IEEE, 2017. http://dx.doi.org/10.1109/dsd.2017.45.

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8

Wang, Yonggang, Peng Kuang, and Chong Liu. "A 256-channel multi-phase clock sampling-based time-to-digital converter implemented in a Kintex-7 FPGA." In 2016 IEEE International Instrumentation and Measurement Technology Conference (I2MTC). IEEE, 2016. http://dx.doi.org/10.1109/i2mtc.2016.7520401.

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9

Lee, David S., Michael Wirthlin, Gary Swift, and Anthony C. Le. "Single-Event Characterization of the 28 nm Xilinx Kintex-7 Field-Programmable Gate Array under Heavy Ion Irradiation." In 2014 IEEE Radiation Effects Data Workshop (REDW) (in conjunction with NSREC 2014). IEEE, 2014. http://dx.doi.org/10.1109/redw.2014.7004595.

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10

Sielewicz, Krzysztof M., Gianluca Aglieri Rinella, Matthias Bonora, Piero Giubilato, Matteo Lupi, Marcus J. Rossewij, Joachim Schambach, and Tomas Vanat. "Experimental Methods and Results for the Evaluation of Triple Modular Redundancy SEU Mitigation Techniques with the Xilinx Kintex-7 FPGA." In 2017 IEEE Nuclear & Space Radiation Effects Conference (NSREC): Radiation Effects Data Workshop (REDW). IEEE, 2017. http://dx.doi.org/10.1109/nsrec.2017.8115451.

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Звіти організацій з теми "Kintex-7"

1

Quinn, Heather, and Jeff Barton. LANSCE test results of the Kintex-7: early analysis results. Office of Scientific and Technical Information (OSTI), March 2012. http://dx.doi.org/10.2172/1164739.

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