Дисертації з теми "Interconnect architectures"
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Venkatesan, Raguraman. "Multilevel interconnect architectures for gigascale integration (GSI)." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/13370.
Повний текст джерелаMeng, Wang. "Verifying Deadlock-Freedom for Advanced Interconnect Architectures." Thesis, Linköpings universitet, Institutionen för datavetenskap, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-171922.
Повний текст джерелаCook, Jason Todd. "Interconnect Thermal Management of High Power Packaged Electronic Architectures." Thesis, Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/5013.
Повний текст джерелаChen, Hongyu. "On-chip interconnect architectures perspectives of layout, circuits, and systems /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2006. http://wwwlib.umi.com/cr/ucsd/fullcit?p3237549.
Повний текст джерелаTitle from first page of PDF file (viewed December 12, 2006). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 131-137).
Bhide, Kanchan P. "DESIGN ENHANCEMENT AND INTEGRATION OF A PROCESSOR-MEMORY INTERCONNECT NETWORK INTO A SINGLE-CHIP MULTIPROCESSOR ARCHITECTURE." UKnowledge, 2004. http://uknowledge.uky.edu/gradschool_theses/253.
Повний текст джерелаBhaduri, Debayan. "Tools and Techniques for Evaluating Reliability Trade-offs for Nano-Architectures." Thesis, Virginia Tech, 2002. http://hdl.handle.net/10919/9918.
Повний текст джерелаMaster of Science
Solkowski, Tomasz. "Multimedia workstation architecture with ATM interconnect." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp01/MQ28851.pdf.
Повний текст джерелаNousias, Ioannis. "Reconfigurable instruction cell architecture : reconfiguration and interconnects." Thesis, University of Edinburgh, 2009. http://hdl.handle.net/1842/11222.
Повний текст джерелаDines, Julian A. B. "Optoelectronic computing : interconnects, architectures and a systems demonstrator." Thesis, Heriot-Watt University, 1997. http://hdl.handle.net/10399/647.
Повний текст джерелаDennison, Larry R. (Larry Robert). "The reliable router : an architecture for fault tolerant interconnect." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/11001.
Повний текст джерелаIncludes bibliographical references (p. 152-154).
by Larry R. Dennison.
Ph.D.
Hassan, Abu S. M. (Abu Saleem Mahmudul). "Testing of board interconnects using boundary scan architecture." Thesis, McGill University, 1989. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=74304.
Повний текст джерелаIn the recent past, several researchers have proposed different schemes for PCB interconnect testing based on the boundary scan architecture.
In this dissertation, a new approach, based on the concept of built-in self-test (BIST), is developed using the boundary scan architecture for PCB interconnect testing. BIST, at the component level, generally consists of incorporating additional circuitry on the chip to generate test patterns and to compact the response of the circuit under test into a reference signature. For the PCB level BIST, the board is considered as the unit under test. A family of BIST schemes are developed for board interconnect testing utilizing the properties of the boundary scan architecture. The BIST approach has removed the dependence on automatic test equipment (ATE) for generation of test vector sets and analysis of output data sets. Techniques are developed for the generation of test vector sets which require very simple test generation hardware. Test vector sets are shown to be independent of the order of the input/output (I/O) scan cells in the boundary scan chain and of the structural complexity of the interconnects under test. Response compaction techniques proposed in the schemes are such that fault detection and diagnosis can be done independent of the topological information about the interconnects. These response compaction techniques can be implemented within each boundary scan cell or outside the boundary scan chain, providing a trade-off in terms of test time and hardware complexity. The various uses of the boundary scan architecture make the proposed schemes more attractive and advantageous than the existing approaches for board interconnect testing.
Moreover, a family of interconnect testing schemes is proposed for a partial boundary scan environment. Partial boundary scan environment refers to a board with a mix of boundary scan and non-boundary scan components. Such an environment is more complex compared to a complete boundary scan environment. The proposed schemes are BIST-able despite the inherently complex test environment. However, fault coverage is limited because of the reduced accessibility of the partial boundary scan environment.
Debnath, Kapil. "Photonic crystal cavity based architecture for optical interconnects." Thesis, University of St Andrews, 2013. http://hdl.handle.net/10023/3870.
Повний текст джерелаBalakrishnan, Anant. "Analysis and optimization of global interconnects for many-core architectures." Thesis, Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/39632.
Повний текст джерелаKarkar, Ammar Jallawi Mahmood. "Interconnects architectures for many-core era using surface-wave communication." Thesis, University of Newcastle upon Tyne, 2016. http://hdl.handle.net/10443/3380.
Повний текст джерелаAzadeh, Mohammad. "Current mode processing and architecture for optoelectronically interconnected arrays /." Thesis, Connect to this title online; UW restricted, 2000. http://hdl.handle.net/1773/6104.
Повний текст джерелаNeel, Brian. "High Performance Shared Memory Networking in Future Many-core Architectures UsingOptical Interconnects." Ohio University / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1397488118.
Повний текст джерелаChung, Kee Shik. "ILP-SIMD : an instruction parallel SIMD architecture with short-wire interconnects." Diss., Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/15455.
Повний текст джерелаHUANG, RENQIU. "PHYSICAL AWARE HIGH LEVEL SYNTHESIS AND INTERCONNECT FOR FPGAs." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147616884.
Повний текст джерелаSato, Ken-ichi, Hiroshi Hasegawa, and Yuto Iwai. "A large-scale photonic node architecture that utilizes interconnected OXC subsystems." Optical Society of America, 2013. http://hdl.handle.net/2237/21044.
Повний текст джерелаApsel, Alyssa Beth. "Optoelectronic receivers in silicon on sapphire CMOS architecture and design for efficient parallel interconnects /." Available to US Hopkins community, 2002. http://wwwlib.umi.com/dissertations/dlnow/3068111.
Повний текст джерелаKaplan, Adam Blake. "Architectural integration of RF-Interconnect to enhance on-chip communication for many-core chip multiprocessors." Diss., Restricted to subscribing institutions, 2008. http://proquest.umi.com/pqdweb?did=1780840191&sid=1&Fmt=2&clientId=1564&RQT=309&VName=PQD.
Повний текст джерелаLi, Hui. "Design methods for energy-efficient silicon photonic interconnects on chip." Thesis, Lyon, 2016. http://www.theses.fr/2016LYSEC059/document.
Повний текст джерелаSilicon photonics is an emerging technology considered as one of the key solutions for future generation on-chip interconnects, providing several prospective advantages such as low transmission latency and high bandwidth. However, it still encounters challenges in energy efficiency. Different topologies, physical layouts, and architectures provide various interconnect options for on-chip communication. This leads to a large variation in optical losses, which is one of the predominant factors in power consumption. In addition, silicon photonic devices are highly sensitive to temperature variation. Under a given chip activity, this leads to a lower laser efficiency and a drift of wavelengths of optical devices (on-chip lasers and microring resonators (MRs)), which in turn results in a higher Bit Error Ratio (BER) and consequently reduces the energy efficiency of optical interconnects. In this thesis, we work on design methodologies for energy-efficient silicon photonic interconnects on chip related to topology/layout, thermal variation, and architecture
Zhu, Lingbo. "Controlled Fabrication of Aligned Carbon Nanotube Architectures for Microelectronics Packaging Applications." Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/19739.
Повний текст джерелаWit, Mark Stuart de. "The MINT architecture : a design for providing quality of service support in desktop-level interconnects." Thesis, University of Glasgow, 2006. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.434028.
Повний текст джерелаCloonan, Thomas J. "A high bit-rate packet switch architecture with advanced electronic packaging and free-space optical interconnects." Thesis, Heriot-Watt University, 1993. http://hdl.handle.net/10399/1461.
Повний текст джерелаMcKenny, Martin. "An investigation into the performance of the RapidIO interconnect architecture in the context of a generic routing device." Thesis, University of Glasgow, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.412933.
Повний текст джерелаWeinberg, Gil 1967. "Interconnected musical networks : bringing expression and thoughtfulness to collaborative group playing." Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/28287.
Повний текст джерелаIncludes bibliographical references (p. 211-219).
(cont.) In order to addressee the latter challenge I have decided to employ the digital network--a promising candidate for bringing a unique added value to the musical experience of collaborative group playing. I have chosen to address both challenges by embedding cognitive and educational concepts in newly designed interconnect instruments and applications, which led to the development of a number of such Interconnected Musical Networks (IMNs)--live performance systems that allow players to influence, share, and shape each other's music in real-time. In my thesis I discuss the concepts, motivations, and aesthetics of IMNs and review a number of historical and current technological landmarks that led the way to the development of the field. I then suggest a comprehensive theoretical framework for artistic interdependency, based on which I developed a set of instruments and activities in an effort to turn IMNs into an expressive and intuitive art form that provides meaningful learning experiences, engaging collaborative interactions, and worthy music.
Music today is more ubiquitous, accessible, and democratized than ever. Thanks to technologies such as high-end home studios, audio compression, and digital distribution, music now surrounds us in everyday life, almost every piece of music is a few minutes of download away, and almost any western musician, novice or expert, can compose, perform and distribute their music directly to their listeners from their home studios. But at the same time these technologies lead to some concerning social effects on the culture of consuming and creating music. Although music is available for more people, in more locations, and for longer periods of time, most listeners experience it in an incidental, unengaged, or utilitarian manner. On the creation side, home studios promote private and isolated practice of music making where hardly any musical instruments or even musicians are needed, and where the value of live group interaction is marginal. My thesis work attempts to use technology to address these same concerning effects that it had created by developing tools and applications that would address two main challenges: 1. Facilitating engaged and thoughtful as well as intuitive and expressive musical experiences for novices and children 2. Enhancing the inherent social attributes of music making by connecting to and intensifying the roots of music as a collaborative socialritual. My approach for addressing the first challenge is to study and model music cognition and education theories and to design algorithms that would bridge between the thoughtful and the expressive, allowing novices and children an access to meaningful and engaging musical experiences.
by Gil Weinberg.
Ph.D.
Gruenwald, Benjamin Charles. "Toward Verifiable Adaptive Control Systems: High-Performance and Robust Architectures." Scholar Commons, 2018. https://scholarcommons.usf.edu/etd/7676.
Повний текст джерелаPuche, Lara José. "Novel Cache Hierarchies with Photonic Interconnects for Chip Multiprocessors." Doctoral thesis, Universitat Politècnica de València, 2021. http://hdl.handle.net/10251/165254.
Повний текст джерела[CA] Els processadors multinucli actuals compten amb recursos compartits entre els diferents nuclis. Dos d'aquests recursos compartits, la memòria d’últim nivell i l'ample de banda de memòria principal, poden convertir-se en colls d'ampolla per al rendiment. A mes, amb el creixement del nombre de nuclis que implementen els dissenys mes recents, la xarxa dins del xip també es converteix en un coll d'ampolla que pot afectar negativament el rendiment, ja que les xarxes tradicionals poden trobar limitacions a la seva escalabilitat en el futur proper. Pràcticament la totalitat dels dissenys actuals implementen jerarquies de memòria que es comuniquen mitjançant rapides xarxes d’interconnexió. Aquesta organització es eficaç ates que permet reduir el nombre d'accessos que es realitzen a memòria principal i la latència mitjana d’accés a memòria. Les caches, la xarxa d’interconnexió i la memòria principal, conjuntament amb altres tècniques conegudes com la prebúsqueda, permeten reduir les enormes latències d’accés a memòria principal, limitant així l'impacte negatiu ocasionat per la diferencia de rendiment existent entre els nuclis de còmput i la memòria. No obstant això, compartir els recursos esmentats és font de diversos problemes i reptes, sent un dels principals la gestió de la interferència entre aplicacions. Fer un us eficient de la jerarquia de memòria i les caches, així com comptar amb una xarxa d’interconnexió apropiada, es necessari per sostenir el creixement del rendiment en els dissenys tant actuals com futurs. Aquesta tesi analitza i estudia els principals problemes i inconvenients observats en aquests dos recursos: la memòria cache d’últim nivell i la xarxa dins del xip. En primer lloc, s'estudia l'escalabilitat de les xarxes tradicionals dins del xip amb topologia de malla, així com aquesta es pot veure compromesa en propers dissenys que compten amb major nombre de nuclis. Els resultats d'aquest estudi mostren que, a major nombre de nuclis, l'impacte negatiu de la distància entre nuclis en la latència pot afectar seriosament al rendiment del processador. Com a solució' a aquest problema, en aquesta tesi proposem una xarxa d’interconnexió' òptica modelada en un entorn de simulació detallat, que suposa una solució viable als problemes d'escalabilitat observats en els dissenys tradicionals. A continuació, aquesta tesi dedica un esforç important a identificar i proposar solucions als principals problemes de disseny de les jerarquies de memòria actuals com son, per exemple, el sobredimensionat de l'espai de memòria cache privat, l’existència de repliques de dades i la rigidesa i incapacitat d’adaptació' de les estructures de memòria cache. Encara que ben coneguts, aquests problemes i els seus efectes adversos en el rendiment poden ser evitats en processadors d'alt rendiment gracies a l'enorme capacitat de la memòria cache d’últim nivell que aquest tipus de processadors típicament implementen. No obstant això, en processadors de baix consum, no hi ha la possibilitat de comptar amb aquestes capacitats, i fer un us eficient de l'espai disponible es torna crític per mantenir el rendiment. Com a solució a aquests problemes en processadors de baix consum, proposem una nova organització de jerarquia de dos nivells de memòria cache que utilitza una xarxa d’interconnexió òptica. Els resultats obtinguts mostren que, comparat amb dissenys convencionals, el consum d'energia estàtica en l'arquitectura proposada és un 60% menor, malgrat que els resultats de rendiment presenten valors similars. Per últim, hem estes l'arquitectura proposada per donar suport tant a aplicacions paral·leles com seqüencials. Els resultats obtinguts amb aquesta nova arquitectura mostren un estalvi de fins al 78 % d'energia estàtica en l’execució d'aplicacions paral·leles.
[EN] Current multicores face the challenge of sharing resources among the different processor cores. Two main shared resources act as major performance bottlenecks in current designs: the off-chip main memory bandwidth and the last level cache. Additionally, as the core count grows, the network on-chip is also becoming a potential performance bottleneck, since traditional designs may find scalability issues in the near future. Memory hierarchies communicated through fast interconnects are implemented in almost every current design as they reduce the number of off-chip accesses and the overall latency, respectively. Main memory, caches, and interconnection resources, together with other widely-used techniques like prefetching, help alleviate the huge memory access latencies and limit the impact of the core-memory speed gap. However, sharing these resources brings several concerns, being one of the most challenging the management of the inter-application interference. Since almost every running application needs to access to main memory, all of them are exposed to interference from other co-runners in their way to the memory controller. For this reason, making an efficient use of the available cache space, together with achieving fast and scalable interconnects, is critical to sustain the performance in current and future designs. This dissertation analyzes and addresses the most important shortcomings of two major shared resources: the Last Level Cache (LLC) and the Network on Chip (NoC). First, we study the scalability of both electrical and optical NoCs for future multicoresand many-cores. To perform this study, we model optical interconnects in a cycle-accurate multicore simulation framework. A proper model is required; otherwise, important performance deviations may be observed otherwise in the evaluation results. The study reveals that, as the core count grows, the effect of distance on the end-to-end latency can negatively impact on the processor performance. In contrast, the study also shows that silicon nanophotonics are a viable solution to solve the mentioned latency problems. This dissertation is also motivated by important design concerns related to current memory hierarchies, like the oversizing of private cache space, data replication overheads, and lack of flexibility regarding sharing of cache structures. These issues, which can be overcome in high performance processors by virtue of huge LLCs, can compromise performance in low power processors. To address these issues we propose a more efficient cache hierarchy organization that leverages optical interconnects. The proposed architecture is conceived as an optically interconnected two-level cache hierarchy composed of multiple cache modules that can be dynamically turned on and off independently. Experimental results show that, compared to conventional designs, static energy consumption is improved by up to 60% while achieving similar performance results. Finally, we extend the proposal to support both sequential and parallel applications. This extension is required since the proposal adapts to the dynamic cache space needs of the running applications, and multithreaded applications's behaviors widely differ from those of single threaded programs. In addition, coherence management is also addressed, which is challenging since each cache module can be assigned to any core at a given time in the proposed approach. For parallel applications, the evaluation shows that the proposal achieves up to 78% static energy savings. In summary, this thesis tackles major challenges originated by the sharing of on-chip caches and communication resources in current multicores, and proposes new cache hierarchy organizations leveraging optical interconnects to address them. The proposed organizations reduce both static and dynamic energy consumption compared to conventional approaches while achieving similar performance; which results in better energy efficiency.
Puche Lara, J. (2021). Novel Cache Hierarchies with Photonic Interconnects for Chip Multiprocessors [Tesis doctoral]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/165254
TESIS
Rajamanikkam, Chidhambaranathan. "Understanding Security Threats of Emerging Computing Architectures and Mitigating Performance Bottlenecks of On-Chip Interconnects in Manycore NTC System." DigitalCommons@USU, 2019. https://digitalcommons.usu.edu/etd/7453.
Повний текст джерелаSiboni, Didier. "La gestion de service sur les réseaux hétérogènes interconnectes : utilisation des techniques d'intelligence artificielle et architectures hybrides." Versailles-St Quentin en Yvelines, 1997. http://www.theses.fr/1997VERS0005.
Повний текст джерелаYoung, Jeffrey. "Dynamic partitioned global address spaces for high-efficiency computing." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26467.
Повний текст джерелаCommittee Chair: Yalamanchili, Sudhakar; Committee Member: Riley, George; Committee Member: Schimmel, David. Part of the SMARTech Electronic Thesis and Dissertation Collection.
Arsenault, Patrick. "Cross-talk analysis of a 12 channel 2.5 GBs VCSEL array based parallel optical interconnect for a multi-stage scalable router architecture." Thesis, McGill University, 2002. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=29571.
Повний текст джерелаTo study the crosstalk properties of the optical interconnect, a special test set-up and detailed test procedures were created to analyse the bit error rate and jitter performance of the parallel optical interconnect in multi-channel operation. The results obtained from the pre-defined experiments confirmed the degradation of the interconnect performance due to inter-channel crosstalk. This performance penalty also limits system scalability, especially when it is combined with the inherent crosstalk properties of the optical redirection boxes. The sources of inter-channel crosstalk were also determined. Finally the system optical link budgets were adjusted and rough system scalability limits were obtained.
Polster, Robert. "Architecture of Silicon Photonic Links." Thesis, Paris 11, 2015. http://www.theses.fr/2015PA112177/document.
Повний текст джерелаFuture high performance computer (HPC) systems will face two major challenges: interconnection bandwidth density and power consumption. Silicon photonic technology has been proposed recently as a cost-effective solution to tackle these issues. Currently, copper interconnections are replaced by optical links at rack and board level in HPCs and data centers. The next step is the interconnection of multi-core processors, which are placed in the same package on silicon interposers, and define the basic building blocks of these computers. Several works have demonstrated the possibility of integrating all elements needed for the realization of short optical links on a silicon substrate.The first contribution of this thesis is the optimization of a silicon photonic link for highest energy efficiency in terms of energy per bit. The optimization provides energy consumption models for the laser, a de- and serialization stage, a ring resonator as modulator and supporting circuitry, a receiver front-end and a decision stage. The optimization shows that the main consumers in optical links is the power consumed by the laser and the modulator's supporting circuitry. Using consumption parameters either gathered by design and simulation or found in recent publications, the optimal bit rate is found in the range between 8 Gbps and 22 Gbps, depending on the used CMOS technology. Nevertheless, if the static power consumption of modulators is reduced it could decrease even below 8 Gbps.To apply the results from the optimization an optical link receiver was designed and fabricated. It is designed to run at a bit rate of 8 Gbps. The receiver uses time interleaving to reduce the needed clock speed and aleviate the need of a dedicated deserialization stage. The front-end was adapted for a wide dynamic input range. In order to take advantage of it, a fast mechanism is proposed to find the optimal threshold voltage to distinguish ones from zeros.Furthermore, optical clock channels are explored. Using silicon photonics a clock can be distributed to several processors with very low skew. This opens the possibility to clock all chips synchronously, relaxing the requirements for buffers that are needed within the communication channels. The thesis contributes to this research direction by presenting two novel optical clock receivers. Clock distribution inside chips is a major power consumer, with small adaptation the clock receivers could also be used inside on-chip clocking trees
Potluri, Sreeram. "Enabling Efficient Use of MPI and PGAS Programming Models on Heterogeneous Clusters with High Performance Interconnects." The Ohio State University, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=osu1397797221.
Повний текст джерелаReehal, Gursharan Kaur. "Designing Low Power and High Performance Network-on-Chip Communication Architectures for Nanometer SoCs." The Ohio State University, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=osu1340022240.
Повний текст джерелаWu, Jiesheng. "Communication and memory management in networked storage systems." The Ohio State University, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=osu1095696917.
Повний текст джерелаAnterola, Jeremy K. "Intelligent adaptive environments : proposal for inclusive, interactive design enabling the creation of an interconnected public open space on the Iron Horse trestle interurban-railroad-subway [St. Louis, Missouri]." Manhattan, Kan. : Kansas State University, 2009. http://hdl.handle.net/2097/1493.
Повний текст джерелаTonchev, Anton. "Door, Passage, Courtyard: Shifting Perspective in Gamla Stan." Thesis, KTH, Arkitektur, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-281363.
Повний текст джерелаBui, Thanh Thi Thanh. "Interconnect architectures for dynamically partially reconfigurable systems." Thesis, 2017. http://hdl.handle.net/2440/113589.
Повний текст джерелаThesis (Ph.D.) -- University of Adelaide, School of Electrical and Electronic Engineering, 2018
Chen, Yi-Chiao, and 陳意喬. "High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Architectures." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/98720923319134048396.
Повний текст джерела國立清華大學
資訊工程學系
102
In a modern System on Chip (SoC) design, hundreds of cores and Intellectual Properties (IPs) can be integrated into a single chip. To be suitable for high-performance interconnects, designers increasingly adopt advanced interconnect protocols which support novel mechanisms of parallel accessing including outstanding transactions and out-of-order completion of transactions. To implement those novel mechanisms, a master tags an ID to each transaction to decide in-order or out-of-order properties. However, these advanced protocols may lead to a deadlock problem that does not occur in traditional protocols. To prevent the deadlock problem, current solutions stall suspicious transactions and in certain cases, many such stalls can cause serious performance penalty. In this paper, we propose a novel ID assignment mechanism which guarantees the issued transactions to be deadlock-free and results in significant reduction in the number of stalls. Our experimental results show encouraging performance improvement compared to previous works with little hardware overhead.
Masud, Muhammad Imran. "FPGA routing structures : a novel switch block and depopulated interconnect matrix architectures." Thesis, 2000. http://hdl.handle.net/2429/10309.
Повний текст джерелаLi, Katherine Shu-Min, and 李淑敏. "Interconnect-Centric Oscillation Ring Architectures and Algorithms for SoC Testability and Yield Enhancement." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/a6p467.
Повний текст джерела國立交通大學
電子工程系所
94
Interconnects play a dominant role in deep-submicron and nanotechnologies. As a result, testability and yield problems of interconnects attract increasing attention. The paradigm shift of the interconnect-related problems is indispensable to cope with two major challenges as technology advances into nanometer territory: �� The ever increasing design complexity of gigascale integration renders testability (detection and diagnosability) and yield enhancement inevitable. �� The complicated physical effects inherent from the scaling effects in nanoscale technology make crosstalk noise (crosstalk-induced glitch faults and crosstalk-induced delay) inevitable, and thus signal integrity and delay faults can no long be ignored. The motivation of this research is targeted at testability and yield enhancement with test time reduction at design stages by our proposed Oscillation Ring (OR) test mechanism. These advantages of the oscillation ring test mechanism have made interconnects detectable and diagnosable through a systematic graph modeling approach. As a relatively novel methodology, OR mechanism for system-level interconnects should be compliant to IEEE Std. 1500. Thus, it is desirable to consider test architectures and algorithms for interconnect testing for System on Chip (SoC) under IEEE Std. 1500, and develop interconnect-centric computer-aided-design tools including design, detection, and diagnosis. To handle the first challenge, the ever increasing design complexity of gigascale integration, we integrate our proposed oscillation ring test techniques into a signal-integrity-aware router. We propose an integrated multilevel full-chip routing algorithm that improves testability and diagnosability, manufacturability, and signal integrity for yield enhancement. Two major issues are addressed. (1) An oscillation ring test and diagnosis scheme for interconnects, based on IEEE Std. 1500, is integrated into the multilevel routing framework to achieve testability enhancement. We augment the traditional multilevel framework by introducing a preprocessing stage of Interconnect Oscillation Ring Detection (IORT) that analyzes the oscillation ring structure for better resource estimation before the coarsening stage, and a postprocessing (final) stage of Interconnect Oscillation Ring Diagnosis (IORD) after uncoarsening that improves testability to achieve 100% interconnect fault coverage and maximal diagnosability. (2) We present a heuristic to balance routing congestion, and the goals of this router include minimizing multiple-fault probability, reducing crosstalk effects, and improving yield for both chemical-mechanical-polishing (CMP) and optical-proximity-correction (OPC) induced manufacturability problems. Experimental results on the MCNC benchmark circuits demonstrate that the proposed OR method achieves 100% fault coverage and the optimal diagnosis resolution for interconnects, and the multilevel congestion-driven routing algorithm effectively balances the routing density to achieve 100% routing completion. Experimental results show that our method significantly improves routing quality for testability and yield enhancement. To deal with the second challenge for signal integrity problem, the crosstalk-induced faults have caused significant impact on interconnect performance as technology advances into nanometer era. The crosstalk is a phenomenon of parasitic capacitance caused by continuous scaling effects. It directly influences reliability, manufacturability and yield of VLSI circuits. (1) We present buffer planning techniques for designing and analyzing crosstalk noise together with performance during floorplanning, and show theoretically and experimentally that our interconnect-aware floorplanner outperforms currently available ones with simultaneously considering crosstalk and timing as our preliminary work which paves the base for IORT and IORD. (2) There are two types of crosstalk: crosstalk-induced glitch and crosstalk-induced delay. We analyze and design the detection of crosstalk faults for interconnect bus, and show experimentally that the unified detection scheme for crosstalk-induced glitch and crosstalk-induced delay is feasible and effectively. This scheme is based on a built-in pulse detector with an adjustable threshold voltage, and we show that this design works well under process variations. Furthermore, the pulse detector in the crosstalk unified detection scheme is embedded into IEEE Std. 1500 wrapper compliant cells so that oscillation ring test for the interconnect test can handle the delay fault, which poses challenges to system performance. (3) We study interconnect detection and diagnosis problems for interconnects. We show a class of oscillation ring approximation algorithms for an interconnect detection and diagnosis problem and prove that oscillation ring mechanism with IEEE Std. 1500 compliant test architecture guarantees 100% fault detection (by IORT) and the optimal diagnosis resolution (by IORD) not only under the fault models of traditional stuck-at and open faults, but also delay and crosstalk glitch faults. Solutions to the interconnect problems by applying oscillation ring methodology pave the way for developing a novel integrated multilevel routing framework with a congestion metric for routing as mentioned above. (4) Finally, the oscillation ring test method has been successfully modified and applied to synchronous sequential circuits to facilitate at-speed test for delay fault detectable in addition to traditional stuck-at and open fault models. In summary, both testability and signal integrity issues have significant impact on interconnect design and test. In my PhD dissertation, an interconnect-centric oscillation ring architectures and algorithms targeted for SoC testability and yield enhancement is proposed to deal with system-level interconnect test and diagnosis, full-chip integrated multilevel router framework, and RTL (register transfer level) synchronous sequential circuits for at-speed testability.
Palaniappan, Arun. "Modeling, Optimization and Power Efficiency Comparison of High-speed Inter-chip Electrical and Optical Interconnect Architectures in Nanometer CMOS Technologies." Thesis, 2010. http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8618.
Повний текст джерелаNagpal, Rahul. "Compiler-Assisted Energy Optimization For Clustered VLIW Processors." Thesis, 2008. http://hdl.handle.net/2005/684.
Повний текст джерелаKhun, Jush Farshad. "Architectural enhancement for message passing interconnects." Thesis, 2008. http://hdl.handle.net/1828/1225.
Повний текст джерелаGrecu, Cristian. "SoC interconnect architecture design and evaluation under timing constraints." Thesis, 2003. http://hdl.handle.net/2429/15310.
Повний текст джерелаKao, Chih-Heng, and 高智恆. "Re-configurable Hybrid Interconnect Architecture for a Multicore System." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/32935897780557569240.
Повний текст джерела國立交通大學
電子工程學系 電子研究所
102
To achieve superior performance of parallel applications on a Multi-Processor System on Chip (MPSoC), an effective and efficient interconnect design has been a critical research topic in architecture design for System on Chip. The conventional design of interconnection targets on specific applications with fixed configurations. However, a fixed interconnect architecture cannot be efficiently applied on applications with different characteristics. To address this issue, this thesis proposes a novel architecture and implementation of Reconfigurable Hybrid Interconnect (RHI) for MPSoC. By cooperating with known traffic characteristics, the proposed RHI has demonstrated an average of 25% to 40% of latency reduction by applying proper configurations.
(8815964), Minsuk Koo. "Energy Efficient Neuromorphic Computing: Circuits, Interconnects and Architecture." Thesis, 2020.
Знайти повний текст джерелаLin, Shiuann-Shiuh, and 林炫旭. "Exact Solution for Net Assignment Problem in Partial Crossbar Interconnect Architecture." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/13614866725628807242.
Повний текст джерела國立清華大學
資訊工程學系
88
In this thesis, we will study the net assignment problem in partial crossbar interconnection architecture [1,4]. Net assignment of two-terminal nets in this interconnection structure is guaranteed to be completed in polynomial time. However, net assignment of multi-terminal nets becomes NP-complete. Previous paper [1] has proposed a simple heuristic to perform net assignment for multi-terminal nets. Its results showed that it failed to complete routing all nets for many cases. It is inadequate to have net assignment algorithm which does not guarantee an exact solution, for the failure of interconnecting FPGAs will result in the failure of whole mapping to the computing engine or redoing the previous steps, e.g., partitioning of circuits. Therefore, we will propose an exact algorithm to solve the net assignment problem. The exact algorithm will find a solution if there exists one. However, the exact algorithm may take exponential time. Accordingly, a two-phase approach will be taken in this research. A time-efficient heuristic method [14,15] will be called first. The exact solver will be called only if the heuristic fails to deliver a solution.