Добірка наукової літератури з теми "Interconnect architectures"
Оформте джерело за APA, MLA, Chicago, Harvard та іншими стилями
Ознайомтеся зі списками актуальних статей, книг, дисертацій, тез та інших наукових джерел на тему "Interconnect architectures".
Біля кожної праці в переліку літератури доступна кнопка «Додати до бібліографії». Скористайтеся нею – і ми автоматично оформимо бібліографічне посилання на обрану працю в потрібному вам стилі цитування: APA, MLA, «Гарвард», «Чикаго», «Ванкувер» тощо.
Також ви можете завантажити повний текст наукової публікації у форматі «.pdf» та прочитати онлайн анотацію до роботи, якщо відповідні параметри наявні в метаданих.
Статті в журналах з теми "Interconnect architectures"
Marrakchi, Zied, Hayder Mrabet, Umer Farooq, and Habib Mehrez. "FPGA Interconnect Topologies Exploration." International Journal of Reconfigurable Computing 2009 (2009): 1–13. http://dx.doi.org/10.1155/2009/259837.
Повний текст джерелаFarahani, Esmat Kishani, and Reza Sarvari. "Design of n-Tier Multilevel Interconnect Architectures by Using Carbon Nanotube Interconnects." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23, no. 10 (October 2015): 2128–34. http://dx.doi.org/10.1109/tvlsi.2014.2360713.
Повний текст джерелаHollman, Richard. "High Speed Electroplating of 200um High Cu Bumps for Die Stacking Architectures." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, DPC (January 1, 2016): 000611–30. http://dx.doi.org/10.4071/2016dpc-tp13.
Повний текст джерелаSuboh, Suboh, Vikram Narayana, Mohamed Bakhouya, Jaafar Gaber, and Tarek El‐Ghazawi. "Methodology for adapting on‐chip interconnect architectures." IET Computers & Digital Techniques 8, no. 3 (May 2014): 109–17. http://dx.doi.org/10.1049/iet-cdt.2013.0021.
Повний текст джерелаEzhumalai, P., A. Chilambuchelvan, and C. Arun. "Novel NoC Topology Construction for High-Performance Communications." Journal of Computer Networks and Communications 2011 (2011): 1–6. http://dx.doi.org/10.1155/2011/405697.
Повний текст джерелаNeumann, B., T. von Sydow, H. Blume, and T. G. Noll. "Design and quantitative analysis of parametrisable eFPGA-architectures for arithmetic." Advances in Radio Science 4 (September 6, 2006): 251–57. http://dx.doi.org/10.5194/ars-4-251-2006.
Повний текст джерелаYanushkevich, S. N., V. P. Shmerko, and B. Steinbach. "Spatial Interconnect Analysis for Predictable Nanotechnologies." Journal of Computational and Theoretical Nanoscience 5, no. 1 (January 1, 2008): 56–69. http://dx.doi.org/10.1166/jctn.2008.007.
Повний текст джерелаKrishnan, Gokul, Sumit K. Mandal, Chaitali Chakrabarti, Jae-Sun Seo, Umit Y. Ogras, and Yu Cao. "Impact of On-chip Interconnect on In-memory Acceleration of Deep Neural Networks." ACM Journal on Emerging Technologies in Computing Systems 18, no. 2 (April 30, 2022): 1–22. http://dx.doi.org/10.1145/3460233.
Повний текст джерелаGAO, Shanghua, Hiroaki YOSHIDA, Kenshu SETO, Satoshi KOMATSU, and Masahiro FUJITA. "Interconnect-Aware Pipeline Synthesis for Array-Based Architectures." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E92-A, no. 6 (2009): 1464–75. http://dx.doi.org/10.1587/transfun.e92.a.1464.
Повний текст джерелаPalaniappan, Arun, and Samuel Palermo. "Power Efficiency Comparisons of Interchip Optical Interconnect Architectures." IEEE Transactions on Circuits and Systems II: Express Briefs 57, no. 5 (May 2010): 343–47. http://dx.doi.org/10.1109/tcsii.2010.2047319.
Повний текст джерелаДисертації з теми "Interconnect architectures"
Venkatesan, Raguraman. "Multilevel interconnect architectures for gigascale integration (GSI)." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/13370.
Повний текст джерелаMeng, Wang. "Verifying Deadlock-Freedom for Advanced Interconnect Architectures." Thesis, Linköpings universitet, Institutionen för datavetenskap, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-171922.
Повний текст джерелаCook, Jason Todd. "Interconnect Thermal Management of High Power Packaged Electronic Architectures." Thesis, Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/5013.
Повний текст джерелаChen, Hongyu. "On-chip interconnect architectures perspectives of layout, circuits, and systems /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2006. http://wwwlib.umi.com/cr/ucsd/fullcit?p3237549.
Повний текст джерелаTitle from first page of PDF file (viewed December 12, 2006). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 131-137).
Bhide, Kanchan P. "DESIGN ENHANCEMENT AND INTEGRATION OF A PROCESSOR-MEMORY INTERCONNECT NETWORK INTO A SINGLE-CHIP MULTIPROCESSOR ARCHITECTURE." UKnowledge, 2004. http://uknowledge.uky.edu/gradschool_theses/253.
Повний текст джерелаBhaduri, Debayan. "Tools and Techniques for Evaluating Reliability Trade-offs for Nano-Architectures." Thesis, Virginia Tech, 2002. http://hdl.handle.net/10919/9918.
Повний текст джерелаMaster of Science
Solkowski, Tomasz. "Multimedia workstation architecture with ATM interconnect." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp01/MQ28851.pdf.
Повний текст джерелаNousias, Ioannis. "Reconfigurable instruction cell architecture : reconfiguration and interconnects." Thesis, University of Edinburgh, 2009. http://hdl.handle.net/1842/11222.
Повний текст джерелаDines, Julian A. B. "Optoelectronic computing : interconnects, architectures and a systems demonstrator." Thesis, Heriot-Watt University, 1997. http://hdl.handle.net/10399/647.
Повний текст джерелаDennison, Larry R. (Larry Robert). "The reliable router : an architecture for fault tolerant interconnect." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/11001.
Повний текст джерелаIncludes bibliographical references (p. 152-154).
by Larry R. Dennison.
Ph.D.
Книги з теми "Interconnect architectures"
Dubois, Michel. Cache and Interconnect Architectures in Multiprocessors. Boston, MA: Springer US, 1990.
Знайти повний текст джерелаBamberg, Lennart, Jan Moritz Joseph, Alberto García-Ortiz, and Thilo Pionteck. 3D Interconnect Architectures for Heterogeneous Technologies. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-98229-4.
Повний текст джерелаDubois, Michel, and Shreekant S. Thakkar, eds. Cache and Interconnect Architectures in Multiprocessors. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4613-1537-7.
Повний текст джерела1953-, Dubois Michel, and Thakkar S. S, eds. Cache and interconnect architectures in multiprocessors. Boston: Kluwer Academic Publishers, 1990.
Знайти повний текст джерелаO'Connor, Ian, and Gabriela Nicolescu, eds. Integrated Optical Interconnect Architectures for Embedded Systems. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4419-6193-8.
Повний текст джерелаPasricha, Sudeep. On-chip communication architectures: System on chip interconnect. Boston: Elsevier/Morgan Kaufmann, 2008.
Знайти повний текст джерелаPasricha, Sudeep. On-chip communication architectures: System on chip interconnect. Amsterdam: Elsevier / Morgan Kaufmann Publishers, 2008.
Знайти повний текст джерелаPasricha, Sudeep. On-Chip Communication Architectures: System on Chip Interconnect. Burlington: Elsevier, 2008.
Знайти повний текст джерелаSolkowski, Tomasz. Multimedia workstation architecture with ATM interconnect]. Ottawa: National Library of Canada = Bibliothèque nationale du Canada, 1999.
Знайти повний текст джерелаRoopchansingh, Ajay. Nearest neighbour interconnect architecture in deep-submicron FPGAs. Ottawa: National Library of Canada, 2002.
Знайти повний текст джерелаЧастини книг з теми "Interconnect architectures"
Chai, S. M., and D. Scott Wills. "Interconnect-Centric Computer Architectures." In Interconnect Technology and Design for Gigascale Integration, 263–92. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-0461-0_7.
Повний текст джерелаBamberg, Lennart, Jan Moritz Joseph, Alberto García-Ortiz, and Thilo Pionteck. "Interconnect Architectures for 3D Technologies." In 3D Interconnect Architectures for Heterogeneous Technologies, 27–47. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-98229-4_2.
Повний текст джерелаSrini, Vason P. "Crossbar-Multi-Processor Architecture." In Cache and Interconnect Architectures in Multiprocessors, 223–43. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4613-1537-7_12.
Повний текст джерелаTeller, Patricia J. "The Cost of TLB Consistency." In Cache and Interconnect Architectures in Multiprocessors, 1–14. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4613-1537-7_1.
Повний текст джерелаJames, David V. "SCI (Scalable Coherent Interface) Cache Coherence." In Cache and Interconnect Architectures in Multiprocessors, 189–208. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4613-1537-7_10.
Повний текст джерелаHopper, Andy, Alan Jones, and Dimitris Lioupis. "Performance Evaluation of Wide Shared Bus Multiprocessors." In Cache and Interconnect Architectures in Multiprocessors, 209–22. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4613-1537-7_11.
Повний текст джерелаLioupis, Dimitris, and Nikos Kanellopoulos. "“CHESS” Multiprocessor A Processor-Memory Grid for Parallel Programming." In Cache and Interconnect Architectures in Multiprocessors, 245–57. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4613-1537-7_13.
Повний текст джерелаCheong, Hoichi, and Alexander V. Veidenbaum. "Software-directed Cache Management in Multiprocessors." In Cache and Interconnect Architectures in Multiprocessors, 259–76. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4613-1537-7_14.
Повний текст джерелаCekleov, Michel, Michel Dubois, Jin-Chin Wang, and Fayé A. Briggs. "Virtual-Address Caches in Multiprocessors." In Cache and Interconnect Architectures in Multiprocessors, 15–35. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4613-1537-7_2.
Повний текст джерелаBitar, Philip. "A Critique of Trace-Driven Simulation for Shared-Memory Multiprocessors." In Cache and Interconnect Architectures in Multiprocessors, 37–52. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4613-1537-7_3.
Повний текст джерелаТези доповідей конференцій з теми "Interconnect architectures"
Lu, Mei-Chien. "Enabling Packaging Architectures and Interconnect Technologies for Image Sensors." In ASME 2020 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems. American Society of Mechanical Engineers, 2020. http://dx.doi.org/10.1115/ipack2020-2526.
Повний текст джерелаWiatr, Pawel, Di Yuan, Lena Wosinska, and Jiajia Chen. "Optical Interconnect Architectures for Datacenters." In 2018 IEEE Photonics Conference (IPC). IEEE, 2018. http://dx.doi.org/10.1109/ipcon.2018.8527245.
Повний текст джерелаMarkov, I. "Session details: Advanced interconnect architectures." In SLIP07: International Workshop on System Level Interconnect Prediction. New York, NY, USA: ACM, 2007. http://dx.doi.org/10.1145/3246484.
Повний текст джерелаRabaey, Jan M. "Brain-inspired interconnect architectures and technologies." In 2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC). IEEE, 2016. http://dx.doi.org/10.1109/iitc-amc.2016.7507737.
Повний текст джерелаDu Nguyen, H. A., Lei Xie, Jintao Yu, Mottaqiallah Taouil, and Said Hamdioui. "Interconnect networks for resistive computing architectures." In 2017 12th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS). IEEE, 2017. http://dx.doi.org/10.1109/dtis.2017.7929872.
Повний текст джерелаZiakas, Dimitrios, Allen Baum, Robert A. Maddox, and Robert J. Safranek. "Intel® QuickPath Interconnect Architectural Features Supporting Scalable System Architectures." In 2010 IEEE 18th Annual Symposium on High-Performance Interconnects (HOTI). IEEE, 2010. http://dx.doi.org/10.1109/hoti.2010.24.
Повний текст джерелаXie, Lei, Hoang Anh Du Nguyen, Mottaqiallah Taouil, Said Hamdioui, and Koen Bertels. "Interconnect networks for memristor crossbar." In 2015 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH'15). IEEE, 2015. http://dx.doi.org/10.1109/nanoarch.2015.7180598.
Повний текст джерелаHarris, Ian G., and Russell Tessier. "Interconnect testing in cluster-based FPGA architectures." In the 37th conference. New York, New York, USA: ACM Press, 2000. http://dx.doi.org/10.1145/337292.337310.
Повний текст джерелаPeter, Eldhose, Janibul Bashir, and Smruti R. Sarangi. "POSTER: BigBus: A Scalable Optical Interconnect." In 2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT). IEEE, 2017. http://dx.doi.org/10.1109/pact.2017.18.
Повний текст джерелаLiu, Jiangjiang, Jianyong Zhang, and Nihar Mahapatra. "Interconnect system compression analysis for multi-core architectures." In 2010 IEEE International SOC Conference (SOCC). IEEE, 2010. http://dx.doi.org/10.1109/socc.2010.5784654.
Повний текст джерелаЗвіти організацій з теми "Interconnect architectures"
Akers, Lex A., Mark R. Walker, and Siamack Haghighi. Design and Training of Limited-Interconnect Architectures. Fort Belvoir, VA: Defense Technical Information Center, July 1991. http://dx.doi.org/10.21236/ada251598.
Повний текст джерелаAkers, Lex. Adaptable Locally-Interconnected Architectures. Fort Belvoir, VA: Defense Technical Information Center, August 1996. http://dx.doi.org/10.21236/ada311781.
Повний текст джерелаMalas, D., and J. Livingood, eds. Session PEERing for Multimedia INTerconnect (SPEERMINT) Architecture. RFC Editor, November 2011. http://dx.doi.org/10.17487/rfc6406.
Повний текст джерелаMurdocca, Miles, Apostolos Gerasoulis, and Saul Levy. Novel Optical Computer Architecture Utilizing Reconfigurable Interconnects. Fort Belvoir, VA: Defense Technical Information Center, October 1991. http://dx.doi.org/10.21236/ada244057.
Повний текст джерелаDrake, J., N. Bitar, G. Swallow, D. Ceccarelli, and X. Zhang. Problem Statement and Architecture for Information Exchange between Interconnected Traffic-Engineered Networks. Edited by A. Farrel. RFC Editor, July 2016. http://dx.doi.org/10.17487/rfc7926.
Повний текст джерела