Дисертації з теми "Integrated Computer Modeling"
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Wu, SunMan Patrick. "Modeling of micro-electro-mechanical integrated test structures." Thesis, Massachusetts Institute of Technology, 1995. http://hdl.handle.net/1721.1/36044.
Повний текст джерелаIncludes bibliographical references (leaf 38).
by SunMan Patrick Wu.
M.Eng.
Michael, Christopher I. "Statistical modeling for computer-aided design of analog MOS integrated circuits /." The Ohio State University, 1991. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487688973683252.
Повний текст джерелаFan, Wei Ph D. Massachusetts Institute of Technology. "Advanced modeling of planarization processes for integrated circuit fabrication." Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/78446.
Повний текст джерелаCataloged from PDF version of thesis.
Includes bibliographical references (p. 215-225).
Planarization processes are a key enabling technology for continued performance and density improvements in integrated circuits (ICs). Dielectric material planarization is widely used in front-end-of-line (FEOL) processing for device isolation and in back-end-of-line (BEOL) processing for interconnection. This thesis studies the physical mechanisms and variations in the planarization using chemical mechanical polishing (CMP). The major achievement and contribution of this work is a systematic methodology to physically model and characterize the non-uniformities in the CMP process. To characterize polishing mechanisms at different length scales, physical CMP models are developed in three levels: wafer-level, die-level and particle-level. The wafer-level model investigates the CMP tool effects on wafer-level pressure non-uniformity. The die-level model is developed to study chip-scale non-uniformity induced by layout pattern density dependence and CMP pad properties. The particle-level model focuses on the contact mechanism between pad asperities and the wafer. Two model integration approaches are proposed to connect wafer-level and particle-level models to the die-level model, so that CMP system impacts on die-level uniformity and feature size dependence are considered. The models are applied to characterize and simulate CMP processes by fitting polishing experiment data and extracting physical model parameters. A series of physical measurement approaches are developed to characterize CMP pad properties and verify physical model assumptions. Pad asperity modulus and characteristic asperity height are measured by nanoindentation and microprofilometry, respectively. Pad aging effect is investigated by comparing physical measurement results at different pad usage stages. Results show that in-situ conditioning keeps pad surface properties consistent to perform polishing up to 16 hours, even in the face of substantial pad wear during extended polishing. The CMP mechanisms identified from modeling and physical characterization are applied to explore an alternative polishing process, referred to as pad-in-a-bottle (PIB). A critical challenge related to applied pressure using pad-in-a-bottle polishing is predicted.
by Wei Fan.
Ph.D.
Pang, Huey, and 彭栩怡. "Computer modeling of building-integrated photovoltaic systems using genetic algorithms for optimization." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2002. http://hub.hku.hk/bib/B31227764.
Повний текст джерелаLin, Yi-Tzer. "Modeling and analysis for message reachability in distributed manufacturing systems." Diss., Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/24292.
Повний текст джерелаMa, Min. "Model order reduction for efficient modeling and simulation of interconnect networks." Thesis, McGill University, 2007. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=103269.
Повний текст джерелаIn this thesis, a number of new reduction techniques were developed in order to address the key shortcomings of current model order reduction methods. Specifically a new approach for handling macromodels with a very large number of ports was developed, a multi-level reduction and sprasification method was proposed for regular as well as parametric macromodels, and finally a new time domain reduction method was presented for the macromodeling of nonlinear parametric systems. Using these approaches, CPU speedups of 1 to 2 orders of magnitude were obtained.
Short, Kristin Ilene 1971. "Towards integrated Intranet services : modeling the costs of corporate IP technology." Thesis, Massachusetts Institute of Technology, 1997. http://hdl.handle.net/1721.1/43530.
Повний текст джерелаAbrokwah, Kwaku O. "Characterization and modeling of plasma etch pattern dependencies in integrated circuits." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/37054.
Повний текст джерелаLeaf 108 blank.
Includes bibliographical references (leaves 106-107).
A quantitative model capturing pattern dependent effects in plasma etching of integrated circuits (ICs) is presented. Plasma etching is a key process for pattern formation in IC manufacturing. Unfortunately, pattern dependent non-uniformities arise in plasma etching due to microloading and RIE lag. This thesis contributes a semi-empirical methodology for capturing and modeling microloading, RIE lag, and related pattern dependent effects. We apply this methodology to the study of interconnect trench etching, and show that an integrated model is able to predict both pattern density and feature size dependent non-uniformities in trench depth. Previous studies of variation in plasma etching have characterized microloading (due to pattern density), and RIE lag (aspect ratio dependent etching or ARDE) as distinct causes of etch non-uniformity for individual features. In contrast to these previous works, we present here a characterization and computational methodology for predicting IC etch variation on a chip scale that integrates both layout pattern density and feature scale or ARDE dependencies. The proposed integrated model performs well in predicting etch variation as compared to a pattern density only or feature scale only model.
by Kwaku O. Abrokwah.
M.Eng.
Hickey, Ann Marie. "Integrated scenario and process modeling support for collaborative requirements elicitation." Diss., The University of Arizona, 1999. http://hdl.handle.net/10150/284823.
Повний текст джерелаPark, Tae Hong 1973. "Characterization and modeling of pattern dependencies in copper interconnects for integrated circuits." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/8082.
Повний текст джерелаIncludes bibliographical references (p. 173-176).
Copper metallization has emerged as the leading interconnect technology for deep sub-micron features, where electroplating and chemical mechanical polish (CMP) processes have a vital role in the fabrication of integrated circuits. The processes both suffer from a similar problem: the copper electroplated profiles and the polished surface exhibit pattern dependent topography. In this thesis, a methodology for the characterization and modeling of pattern dependent problems in copper interconnect topography is developed. For the electroplating process, the methodology consists of test structure and mask design to examine feature scale copper step height and the height of copper array regions as a function of underlying layout parameters. Semi-empirical response surface models are then generated with model parameters extracted from conventional and superfill plating processes. Once the models are calibrated, layout parameters including pattern density, line width distributions, and line length are extracted for each cell in a 40 gm by 40 tm discretization of any random chip layout. Then, a chip-scale prediction is achieved by simulating generalized average heights for each grid cell across the entire chip. The prediction result shows root mean square errors of less than 1000 A for array height and around 500 A for step height. This methodology provides the first known chip-scale prediction of electroplated topography. For pattern dependencies in copper CMP, this thesis focuses on the development of test structures and masks (including multi-level structures) to identify key pattern effects in both single-level and multi-level polishing.
(cont.) Especially for the multi-level studies, electrical test structures and measurements in addition to surface profile scans are seen to be important in accurately determining thickness variations. The developed test vehicle and characterization of copper dishing and oxide erosion serve as a basis for further pattern dependent model development. Finally, integration of electroplating and CMP chip-scale models is illustrated; the simulated step and array heights as well as topography pattern density are used as an input for the initial starting topography for CMP simulation of subsequent polishing profile evolution.
by Tae Hong Park.
Ph.D.
Hoffman, Joseph A. "VHDL modeling of ASIC power dissipation." Master's thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-10222009-124831/.
Повний текст джерелаWan, Bo. "MCAST : automatic device modeling in model compiler for efficient and accurate circuit simulation /." Thesis, Connect to this title online; UW restricted, 2004. http://hdl.handle.net/1773/5959.
Повний текст джерелаYu, Jie Petropulu Athina P. "Modeling of high-speed wireline and wireless network traffic /." Philadelphia, Pa. : Drexel University, 2005. http://dspace.library.drexel.edu/handle/1860/469.
Повний текст джерелаRobinson, William Hugh. "Modeling and implementation of an integrated pixel processing tile for focal plane systems." Diss., Available online, Georgia Institute of Technology, 2004:, 2003. http://etd.gatech.edu/theses/available/etd-04072004-180157/unrestricted/robinson%5Fwilliam%5Fh%5F200312%5Fphd.pdf.
Повний текст джерелаMUKHERJEE, ANINDO. "AN INTEGRATED ARCHITECTURE FOR MULTI-HOP INFRASTRUCTURE WIRELESS NETWORKS." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1155834305.
Повний текст джерелаPatel, Girish N. "A neuromorphic architecture for modeling intersegmental coordination." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/13528.
Повний текст джерелаDoustmohammadi, Ali. "Modeling and analysis of production systems." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/15776.
Повний текст джерелаKoh, Sau W. "Fatigue modeling of nano-structured chip-to-package interconnections." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/28263.
Повний текст джерелаCommittee Chair: Rao R. Tummala; Committee Co-Chair: Ashok Saxena; Committee Member: Karl Jacob; Committee Member: Suresh Sitaraman; Committee Member: Thomas H. Sanders, Jr.
Cho, Choongeol. "RF circuit nonlinearity characterization and modeling for embedded test." [Gainesville, Fla.] : University of Florida, 2005. http://purl.fcla.edu/fcla/etd/UFE0013086.
Повний текст джерелаGruener, Charles J. "Design and implementation of a computational cluster for high performance design and modeling of integrated circuits /." Online version of thesis, 2009. http://hdl.handle.net/1850/11204.
Повний текст джерелаLiang, Bowen. "Integrated Multi-Scale Modeling Framework for Simulating Failure Response of Materials with Complex Microstructures." The Ohio State University, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=osu1542233231302831.
Повний текст джерелаSriwiriyarat, Tongchai. "Computer Program Development for the Design of IFAS Wastewater Treatment Processes." Thesis, Virginia Tech, 1999. http://hdl.handle.net/10919/32065.
Повний текст джерелаMaster of Science
Johnson, Joy Marie. "Modeling of advanced integrated circuit planarization processes : electrochemical-mechanical planarization (eCMP), STI CMP using non-conventional slurries." Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/52807.
Повний текст джерелаThis electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student submitted PDF version of thesis.
Includes bibliographical references (p. 95-99).
Progression of technology nodes in integrated circuit design is only possible if there are sustainable, cost-efficient processes by which these designs can be implemented. As future technologies are increasing device density, shrinking device dimensions, and employing novel structures, semiconductor processing must also advance to effectively and eciently process these devices. Arguably one of the most critical, inefficient, poorly understood and costly processes is planarization. Thus, this thesis focuses on two types of planarization processes. Models of efficient and environmentally benign electrochemical-mechanical copper planarization (eCMP) are developed, with a focus on electrochemical mechanisms and wafer-scale uniformity. Specifically, previous models for eCMP are enhanced to consider the full electrochemical system driving planarization in eCMP. We explore the notion of electrochemical reactions at both the cathode and anode, in addition to lateral current flow in a time-averaged calculation. More ecient and accurate models for planarization of shallow-trench isolation (STI) structures are proposed, with a focus on die-scale and feature-scale uniformity. This thesis captures the fundamental weakness of CMP, pattern dependencies, and uses deposition prole effects as well as the pattern-density to more accurately model and physically represent STI structures during CMP. We model, for the first time, the evolution of pattern density as a function of time and step-height, and use layout biasing to account for deposition prole evolution for the accurate prediction of die and feature-scale CMP.
by Joy Marie Johnson.
S.M.
Crutchfield, David Allen. "VERIFICATION AND DEBUG TECHNIQUES FOR INTEGRATED CIRCUIT DESIGNS." UKnowledge, 2009. http://uknowledge.uky.edu/gradschool_theses/631.
Повний текст джерелаKimoto, Daiki. "Characterization and Modeling of SiC Integrated Circuits for Harsh Environment." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-223422.
Повний текст джерелаHarsh environment electronics, which can be operated at high-temperature, high-radiation, and corrosive gas environment, has been strongly desired in space exploration and monitoring of nuclear reactors. Silicon Carbide (SiC) is one of the candidates of materials for harsh environment electronics because of its high-temperature and high-radiation tolerance. The objective of this thesis is to characterize 4H-SiC MOSFETs at high- temperature and to construct SPICE models of the 4H-SiC MOSFETs. The MOSFET devices were characterized up to 500ºC. Using the characteristic of a 4H-SiC NMOSFET with L/W = 10 µm/50 µm, a SPICE LEVEL 2 circuit model was constructed. This model describes the DC characteristic of the 4H-SiC MOSFETs in the range of 25 – 450ºC. Based on the SPICE circuit model, the characteristics of operational amplifiers and digital inverters were simulated. Furthermore, the operation of pseudo-CMOS at high-temperature was analyzed and the operation principle of pseudo-CMOS was suggested. The device area and yield of pseudo-CMOS integrated circuits were estimated and it is shown that SiC pseudo-CMOS integrated circuits can use less area than SiC CMOS integrated circuits.
Narayanan, Sundaram. "Design and development of an object-oriented architecture for modeling and simulation of discrete-part manufacturing systems." Diss., Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/24374.
Повний текст джерелаKhakimbayev, Jasur S. "Development of integrated 3D terrain maps for Unmanned Aerial Vehicle (UAV) Flight and Mission Control Support System (FMCSS)." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2006. http://library.nps.navy.mil/uhtbin/hyperion/06Mar%5FKhakimbayev.pdf.
Повний текст джерелаThesis Advisor(s): Wolfgang Baer, Curtis L. Blais. "March 2006." Includes bibliographical references (p.99-101). Also available online.
Rendell, Gerard Vincent Alfred. "An integrated modeling framework for concept formation : developing number-sense, a partial resolution of the learning paradox." Thesis, Kingston University, 2012. http://eprints.kingston.ac.uk/27841/.
Повний текст джерелаJoshi, Anand Mukund. "Behavioral delay fault modeling and test generation." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-07292009-090436/.
Повний текст джерелаNaber, John F. "The optimization of SPICE modeling parameters utilizing the Taguchi methodology." Diss., Virginia Tech, 1992. http://hdl.handle.net/10919/38542.
Повний текст джерелаPh. D.
Bounhieng, Vilaysane. "INTEGRATED IMPACT ASSESSMENT OF CLIMATE CHANGE ON HYDROLOGY OF THE XEDONE RIVER BASIN, LAO PDR." 京都大学 (Kyoto University), 2016. http://hdl.handle.net/2433/204586.
Повний текст джерелаMenezes, Gary. "Modeling, design, fabrication and characterization of glass package-to-PCB interconnections." Thesis, Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/51781.
Повний текст джерелаPop, Adrian. "Integrated Model-Driven Development Environments for Equation-Based Object-Oriented Languages." Doctoral thesis, Linköping : Department of Computer and Information Science, Linköpings universitet, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-11416.
Повний текст джерелаPark, Hoon. "Formal Modeling and Verification of Delay-Insensitive Circuits." PDXScholar, 2015. https://pdxscholar.library.pdx.edu/open_access_etds/2639.
Повний текст джерелаLiu, Xiang. "Reliability study of InGaP/GaAs heterojunction bipolar transistor MMIC technology by characterization, modeling and simulation." Doctoral diss., University of Central Florida, 2011. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4967.
Повний текст джерелаID: 030423028; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (Ph.D.)--University of Central Florida, 2011.; Includes bibliographical references (p. 82-88).
Ph.D.
Doctorate
Electrical Engineering and Computer Science
Engineering and Computer Science
Nugent, Steven Paul. "A Second Generation Generic Systems Simulator (GENESYS) for a Gigascale System-on-a-Chip (SoC)." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/6885.
Повний текст джерелаPanchal, Jitesh H. "A framework for simulation-based integrated design of multiscale products and design processes." Diss., Available online, Georgia Institute of Technology, 2005, 2005. http://etd.gatech.edu/theses/available/etd-11232005-112626/.
Повний текст джерелаEastman, Chuck, Committee Member ; Paredis, Chris, Committee Co-Chair ; Allen, Janet, Committee Member ; Rosen, David, Committee Member ; Tsui, Kwok, Committee Member ; McDowell, David, Committee Member ; Mistree, Farrokh, Committee Chair. Includes bibliographical references.
Kumar, Sharad Kumar. "Analysis of Machine Learning Modeling Attacks on Ring Oscillator based Hardware Security." University of Toledo / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1541759752027838.
Повний текст джерелаShiang, Jyue-Jon 1956. "APTMC: AN INTERFACE PROGRAM FOR USE WITH ANSYS FOR THERMAL AND THERMALLY INDUCED STRESS MODELING/SIMULATION OF LEVEL 1 AND LEVEL 2 VLSI PACKAGING." Thesis, The University of Arizona, 1987. http://hdl.handle.net/10150/291399.
Повний текст джерелаLiu, Yidong. "CMOS RF cituits sic] variability and reliability resilient design, modeling, and simulation." Doctoral diss., University of Central Florida, 2011. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4969.
Повний текст джерелаID: 029809399; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (Ph.D.)--University of Central Florida, 2011.; Includes bibliographical references (p. 90-105).
Ph.D.
Doctorate
Electrical Engineering and Computer Science
Engineering and Computer Science
Wen, Yangyang. "MODELING AND DIGITAL CONTROL OF HIGH FREQUENCY DC-DC POWER CONVERTERS." Doctoral diss., University of Central Florida, 2007. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3671.
Повний текст джерелаPh.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering PhD
Elahi, Behin. "Integrated Optimization Models and Strategies for Green Supply Chain Planning." University of Toledo / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1467266039.
Повний текст джерелаZhu, Wenhua. "3D modeling of city building and lifecycle simulation." Thesis, Compiègne, 2017. http://www.theses.fr/2017COMP2344/document.
Повний текст джерелаWith the construction and development of the smart city, how to construct the realistic 3D model of the large-scale city buildings quickly and efficiently which becomes the research hotspot. In this thesis, a novel 3D modeling approach is proposed to quickly and efficiently build 3D model of large-scale city buildings based on shape grammar and facade rule modeling. Building Information Model (BIM) is an important technical means to enhance the construction industry, for the city building design and construction, how to better research and application of BIM technology which is the key, in this thesis City Building Integrated Information Model (CBIIM) is specified to manage the information of building lifecycle effectively and realize the information sharing and exchanging. This thesis has studied the acquisition and processing of the modeling data. Google Earth and ArcGIS software are mainly used to acquire and process image-maps data and elevation-maps data of the target area, these two kinds of data match and overlay, which can generate 3D city terrain data with geographic location information. Then OpenStreetMap is used to acquire road data of the target area, and it can be optimal processed to the necessary road network by JOSM software. 3D laser scanning technology is used to collect building surface texture images and create the point clouds model of the target architecture modeling so as to get the modeling dimensions by measurement. On this basis, this thesis mainly has studied the principle and the process of CGA rule to create building models, and studied the method that can separate architectural elements using image segmentation to generate CGA rule automatically and to create building model furtherly. Thus 3D building models have been established in the CityEngine software using CGA rules and facade modeling technology. This thesis has specified the City Building Integrated Information Model (CBIIM) based on BIM. The city building information are classified and integrated, and the building and component was described with the IFC standard, in order to manage the informations of building lifecycle effectively. This thesis studies the integrated information association model technology, that it can realize standardized component design with associated features and intelligent building design with associated parameters in knowledge rules combined with IFC. The construction simulation technology is studied. The knowledge rules in the integrated information model provide a reliable reference for the construction simulation, and the simulation scene is created through the invoking the integrated information model, thus the construction simulation process is completed by the program. Taking Baoshan Campus of Shanghai University as an example, the modeling process of the whole scene is illustrated, and the modeling steps of all kinds of 3D objects are described in detail to solve the specific problems in the actual modeling process. Thus the feasibility and validity of the procedural intelligent modeling approach are verified. Taking the dormitory of Shanghai University as an example, a simulation scene and the simulation model were created by the integrated informations, combined with the relevant construction information the construction simulation was completed by the program. Thus the feasibility and validity of the CBIIM are verified
Seo, Chung-Seok. "Physical Design of Optoelectronic System-on-a-Chip/Package Using Electrical and Optical Interconnects: CAD Tools and Algorithms." Diss., Available online, Georgia Institute of Technology, 2005, 2004. http://etd.gatech.edu/theses/available/etd-11102004-150844/.
Повний текст джерелаDavid E. Schimmel, Committee Member ; C.P. Wong, Committee Member ; John A. Buck, Committee Member ; Abhijit Chatterjee, Committee Chair ; Madhavan Swaminathan, Committee Member. Vita. Includes bibliographical references.
Varsamidis, Thomas. "Object-oriented information modelling for computer-aided control engineering." Thesis, Bangor University, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.245177.
Повний текст джерелаLong, Jianghua. "Computer-integrated information modelling for design of building structures /." View abstract or full-text, 2004. http://library.ust.hk/cgi/db/thesis.pl?CIVL%202004%20LONG.
Повний текст джерелаIncludes bibliographical references (leaves 223-232). Also available in electronic version. Access restricted to campus users.
Zhong, Shida. "Fault modelling and accelerated simulation of integrated circuits manufacturing defects under process variation." Thesis, University of Southampton, 2013. https://eprints.soton.ac.uk/349929/.
Повний текст джерелаDupont, Lionel. "Algorithmes et ordonnancements." Phd thesis, Grenoble 2 : ANRT, 1986. http://catalogue.bnf.fr/ark:/12148/cb37597342h.
Повний текст джерелаRichards, Andrew John. "An integrated approach to three-dimensional computer modelling of sedimentary basins." Thesis, Keele University, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.311738.
Повний текст джерелаYu, Bing. "Hybrid modelling methodology for system design." Thesis, Loughborough University, 1995. https://dspace.lboro.ac.uk/2134/6999.
Повний текст джерела