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Статті в журналах з теми "Integrated circuits"

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Автор: Grafiati

Опубліковано: 4 червня 2021

Оновлено: 11 вересня 2023

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1

Wu, Jian, Yi-an Liu, and Tingting Luo. "Research on Talents Training Mode for integrated circuit major under the Background of the Science-education and Industry-education Integration." SHS Web of Conferences 171 (2023): 03028. http://dx.doi.org/10.1051/shsconf/202317103028.

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With the rapid development of information technology, the requirements for integrated circuits, which are the key elements of information technology, are becoming higher and higher. However, the gap of integrated circuit talents is still large. The national and social development has an extremely urgent demand for integrated circuit talents. To meet the national needs, UESTC integrates ideological and political elements, reconstructs the curriculum teaching matrix, creates a challenge system step by step, and adheres to multiple synergies to build a “cross-integration, system integration, and whole-process” talents training mode of Science-education and Industry-education integration in integrated circuits.

2

Shepherd, Paul, Dillon Kaiser, Michael Glover, Sonia Perez, A. Matt Francis, and H. Alan Mantooth. "Integrated Protection Circuits for an NMOS Silicon Carbide Gate Driver Integrated Circuit." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, HITEC (January 1, 2014): 000218–23. http://dx.doi.org/10.4071/hitec-wp14.

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Recent work has been done to build a Silicon Carbide (SiC) gate driver IC for use with a 1,200V SiC power MOSFET. Protection circuits form an important part of the complete gate driver/power device system. Under-voltage lockout (UVLO) protection disables the gate driver when power supplies are insufficient to turn the power device fully on. Desaturation detection provides protection to the power device by recognizing over-current conditions and disabling the gate driver for a set duration. The protection circuits described in this paper are integrated with a novel SiC gate-driver architecture utilizing discrete 20 V and 40 V power supplies. Two separate UVLO circuits monitor these power supplies while being powered by the 20 V supply. The desaturation detection circuit ensures that the power device is in its safe operating area. The desaturation detection circuit is designed to work with a 20A SiC MOSFET in less than 500ns, while avoiding false triggering on leading-edge spikes. Bench test results of the two UVLOs and desaturation detection circuits were captured and are compared to simulated results.

3

Jackson, Keit, and JeffreyA Niehaus. "4752729 Test circuit for VSLI integrated circuits." Microelectronics Reliability 29, no. 2 (January 1989): 291. http://dx.doi.org/10.1016/0026-2714(89)90600-8.

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4

Li, Zihan. "Application of Integrated Circuits in Cardiac Pacemakers." Highlights in Science, Engineering and Technology 62 (July 27, 2023): 84–89. http://dx.doi.org/10.54097/hset.v62i.10428.

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This article briefly describes the application of integrated circuits in the medical field, such as wearable and implantable medical devices. The article introduces the development process of integrated circuits used in cardiac pacemakers, explaining how it evolved from bipolar junction transistors integrated circuits in the past to today's complementary metal oxide semiconductor integrated circuits. The basic components of the pacemaker are described from a system level, including the signal amplifier, pulse generator, battery management system, and analog-to-digital converter. This allows for a clear presentation of the working process of the pacemaker. Furthermore, the article explains how analog integrated circuits and digital integrated circuits can be used together to achieve the goal of low power consumption of cardiac pacemakers at a circuit level, with reference to some cutting-edge scientific and technological achievements. The necessity and advantages of integrated circuits in medical applications are demonstrated, and the future development of integrated circuits in related aspects is forecasted based on the current development situation.

5

HARUNA, Masamitsu, and Hiroshi NISHIHARA. "Optical integrated circuits." Journal of the Japan Society for Precision Engineering 56, no. 3 (1990): 469–72. http://dx.doi.org/10.2493/jjspe.56.469.

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6

Yakushenkov, P. O. "Photonic Integrated Circuits." Photonics Russia 68, no. 8 (2017): 58–67. http://dx.doi.org/10.22184/1993-7296.2017.68.8.58.67.

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7

Mavor, J. "Monolithic Integrated Circuits." Electronics and Power 32, no. 3 (1986): 234. http://dx.doi.org/10.1049/ep.1986.0153.

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8

Simmons, John G. "Analogue Integrated Circuits." Electronics and Power 32, no. 3 (1986): 234. http://dx.doi.org/10.1049/ep.1986.0154.

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9

Chisholm, G. H., S. T. Eckmann, C. M. Lain, and R. L. Veroff. "Understanding integrated circuits." IEEE Design & Test of Computers 16, no. 2 (1999): 26–37. http://dx.doi.org/10.1109/54.765201.

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10

Silva, M. M. "Linear integrated circuits." Proceedings of the IEEE 73, no. 8 (1985): 1340. http://dx.doi.org/10.1109/proc.1985.13290.

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11

Forrest, S. R. "Optoelectronic integrated circuits." Proceedings of the IEEE 75, no. 11 (1987): 1488–97. http://dx.doi.org/10.1109/proc.1987.13910.

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12

Hurst, Stanley L. "Analog integrated circuits." Microelectronics Journal 29, no. 6 (June 1998): 353–54. http://dx.doi.org/10.1016/s0026-2692(97)00042-6.

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13

Free, C. E. "Microwave integrated circuits." Microelectronics Journal 24, no. 1-2 (January 1993): 158–59. http://dx.doi.org/10.1016/0026-2692(93)90112-r.

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14

Vardaxoglou, J. C. "Microwave integrated circuits." Microprocessors and Microsystems 20, no. 3 (May 1996): 197. http://dx.doi.org/10.1016/0141-9331(95)01064-5.

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15

Grierson, J. R., and S. Hollock. "Semicustom integrated circuits." IEE Proceedings E Computers and Digital Techniques 132, no. 2 (1985): 49. http://dx.doi.org/10.1049/ip-e.1985.0006.

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16

Evtikhiev, N. N., and V. N. Morozov. "Integrated optoelectronic circuits." Soviet Journal of Quantum Electronics 17, no. 11 (November 30, 1987): 1366–74. http://dx.doi.org/10.1070/qe1987v017n11abeh010834.

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17

Chakrabarti, N. B. "GaAs Integrated Circuits." IETE Journal of Research 38, no. 2-3 (March 1992): 163–78. http://dx.doi.org/10.1080/03772063.1992.11437044.

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18

Ferrell, Ph.D., Thomas L., Charles L. Britton, Ph.D., William L. Bryan, Ph.D., Lloyd G. Clonts, Ph.D., Michael S. Emery, Ph.D., M. Nance Ericson, Ph.D., Fabrice Merraudeau, Ph.D., et al. "Telesensor Integrated Circuits." World Journal of Surgery 25, no. 11 (November 1, 2001): 1412–18. http://dx.doi.org/10.1007/s00268-001-0126-0.

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19

Knight, WilliamL, Mark Paraskeva, and DavidF Burrows. "4764926 Integrated circuits." Microelectronics Reliability 29, no. 4 (January 1989): 666. http://dx.doi.org/10.1016/0026-2714(89)90535-0.

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20

Koch, Thomas L., and Uziel Koren. "Photonic Integrated Circuits." AT&T Technical Journal 71, no. 1 (January 2, 1992): 63–74. http://dx.doi.org/10.1002/j.1538-7305.1992.tb00148.x.

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21

Moldovan, Emilia, Nazih Khaddaj Mallat, and Serioja Ovidiu Tatu. "MHMIC Six-port Interferometer for W-band Transceivers: Design and Characterization." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 4 (August 1, 2019): 2703. http://dx.doi.org/10.11591/ijece.v9i4.pp2703-2714.

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The study has presented an extensive analysis of an integrated millimeter wave six-port interferometer, operating over a 10 GHz band, from 80 to 90 GHz. It has covered both semi-unlicensed point-to-point links (81-86 GHz), and imaging sensor system frequencies (above 85 GHz). An in-house process is used to fabricate miniaturized hybrid millimeter wave integrated circuits on a very thin ceramic substrate. Two-port S-parameter measurements are performed on a minimum number of circuits integrated on the same die, exploiting the circuit’s physical symmetry and chosen to collect enough data for full-port characterization. Based on these measurements on an integrated prototype, a six-port circuit computer model implemented and advanced system simulations performed for circuit analysis. Interferometer performances evaluated using several methods: analysis of harmonic balance, qi points’, homodyne quadrature demodulation, and error vector modulation (EVM). The analysis showed that this circuit can directly perform, without any calibration, the demodulation of various PSK and QAM signals over the 10 GHz band, with very good results.

22

Guang, Yang, Bin Yu, and Huang Hai. "Design of a High Performance CMOS Bandgap Voltage Reference." Advanced Materials Research 981 (July 2014): 90–93. http://dx.doi.org/10.4028/www.scientific.net/amr.981.90.

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Bandgap voltage reference, to provide a temperature and power supply insensitive output voltage, is a very important module in the analog integrated circuits and mixed-signal integrated circuits. In this paper, a high performance CMOS bandgap with low-power consumption has been designed. It can get the PTAT (Proportional to absolute temperature) current, and then get the reference voltage. Based on 0.35μm CMOS process, using HSPICE 2008 software for circuit simulation, the results showed that , when the temperature changes from -40 to 80 °C, the proposed circuit’s reference voltage achieve to 1.2V, temperature coefficient is 3.09ppm/°C. Adopt a series of measures, like ESD protection circuit, in layout design. The ultimately design through the DRC and LVS verification, and the final layout size is 700μm * 560μm.

23

Lim, Taek-Kyu, Kunal Sandip Garud, Jae-Hyeong Seo, Moo-Yeon Lee, and Dong-Yeon Lee. "Experimental Study on Heating Performances of Integrated Battery and HVAC System with Serial and Parallel Circuits for Electric Vehicle." Symmetry 13, no. 1 (January 7, 2021): 93. http://dx.doi.org/10.3390/sym13010093.

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The objective of the present study is to conduct experiments for investigating heating performances of integrated system with serial and parallel circuits for battery and heating ventilation and air conditioning system (HVAC) of electric vehicles under various operating conditions. In addition, the artificial neural network (ANN) model is proposed to accurately predict the heating performances of integrated system with serial and parallel circuits for battery and HVAC. A test bench of integrated system with serial and parallel circuits has been developed for establishing the trade-off between battery heating and HVAC heating. The heating performances namely, battery out temperature, battery temperature rise rate, battery heating capacity, HVAC heating capacity and total heating capacity are evaluated experimentally for the integrated system with serial and parallel circuits. The behavior of various heating performances is evaluated under influence of flow rate and heater power. Battery out temperature reaches 40 °C within 10 min with rise rate of 2.17 °C/min for the integrated system with serial circuit and that within 20 min with rise rate of 1.22 °C/min for the integrated system with parallel circuit. Integrated system with serial circuit shows higher HVAC heating capacity than integrated system with parallel circuit which are 5726.33 W and 3869.15 W, respectively. ANN model with back-propagation algorithm, Levenberg-Marquardt training variant, Tan-sigmoidal transfer function and 20 hidden neurons presents the accurate prediction of heating performances of the integrated system with serial and parallel circuits for battery and HVAC.

24

Lim, Taek-Kyu, Kunal Sandip Garud, Jae-Hyeong Seo, Moo-Yeon Lee, and Dong-Yeon Lee. "Experimental Study on Heating Performances of Integrated Battery and HVAC System with Serial and Parallel Circuits for Electric Vehicle." Symmetry 13, no. 1 (January 7, 2021): 93. http://dx.doi.org/10.3390/sym13010093.

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The objective of the present study is to conduct experiments for investigating heating performances of integrated system with serial and parallel circuits for battery and heating ventilation and air conditioning system (HVAC) of electric vehicles under various operating conditions. In addition, the artificial neural network (ANN) model is proposed to accurately predict the heating performances of integrated system with serial and parallel circuits for battery and HVAC. A test bench of integrated system with serial and parallel circuits has been developed for establishing the trade-off between battery heating and HVAC heating. The heating performances namely, battery out temperature, battery temperature rise rate, battery heating capacity, HVAC heating capacity and total heating capacity are evaluated experimentally for the integrated system with serial and parallel circuits. The behavior of various heating performances is evaluated under influence of flow rate and heater power. Battery out temperature reaches 40 °C within 10 min with rise rate of 2.17 °C/min for the integrated system with serial circuit and that within 20 min with rise rate of 1.22 °C/min for the integrated system with parallel circuit. Integrated system with serial circuit shows higher HVAC heating capacity than integrated system with parallel circuit which are 5726.33 W and 3869.15 W, respectively. ANN model with back-propagation algorithm, Levenberg-Marquardt training variant, Tan-sigmoidal transfer function and 20 hidden neurons presents the accurate prediction of heating performances of the integrated system with serial and parallel circuits for battery and HVAC.

25

Koo, Jae-Mo, Sungjun Im, Linan Jiang, and Kenneth E. Goodson. "Integrated Microchannel Cooling for Three-Dimensional Electronic Circuit Architectures." Journal of Heat Transfer 127, no. 1 (January 1, 2005): 49–58. http://dx.doi.org/10.1115/1.1839582.

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The semiconductor community is developing three-dimensional circuits that integrate logic, memory, optoelectronic and radio-frequency devices, and microelectromechanical systems. These three-dimensional (3D) circuits pose important challenges for thermal management due to the increasing heat load per unit surface area. This paper theoretically studies 3D circuit cooling by means of an integrated microchannel network. Predictions are based on thermal models solving one-dimensional conservation equations for boiling convection along microchannels, and are consistent with past data obtained from straight channels. The model is combined within a thermal resistance network to predict temperature distributions in logic and memory. The calculations indicate that a layer of integrated microchannel cooling can remove heat densities up to 135W/cm2 within a 3D architecture with a maximum circuit temperature of 85°C. The cooling strategy described in this paper will enable 3D circuits to include greater numbers of active levels while exposing external surface area for functional signal transmission.

26

He, Yucheng. "Application of Artificial Intelligence in Integrated Circuits." Journal of Physics: Conference Series 2029, no. 1 (September 1, 2021): 012090. http://dx.doi.org/10.1088/1742-6596/2029/1/012090.

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Abstract Integrated circuit and artificial intelligence technology are inseparable. Artificial intelligence technology depends on the learning ability and computing ability of computers and other machines. In this process, integrated circuits provide hardware support for the operation of artificial intelligence algorithms. For a long time, the application research of artificial intelligence technology in the field of integrated circuit mainly focuses on circuit fault analysis and artificial intelligence chips. Especially in recent years, due to the rapid development of technology, the combination of the two has become more closely, and more scientists and researchers have invested in the interdisciplinary research of the two disciplines. In this paper, the application of artificial intelligence technology in the field of integrated circuits is explored, that is, its applications in the three aspects of chip, integrated circuit fault diagnosis and circuit design optimization is discussed, and the relationship between artificial intelligence technology and integrated circuit is reflected. Finally, it is concluded that the cross research and application of integrated circuit and artificial intelligence technology will have an important impact on the level of science and technology and the level of human social life.

27

Yordanov, Hristomir, and Peter Russer. "Integrated on-chip antennas for communication on and between monolithic integrated circuits." International Journal of Microwave and Wireless Technologies 1, no. 4 (June 29, 2009): 309–14. http://dx.doi.org/10.1017/s1759078709990407.

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The rate of signal transmission on or between monolithic integrated circuits is limited by the cross-talk and the dispersion due to the wired interconnects. The bandwidth limitations can be overcome by wireless chip-to-chip and on-chip interconnects via integrated antennas. In this work the utilization of the electronic circuit ground planes as radiating elements for the integrated antennas has been proposed. This allows for optimal usage of chip area, as the antennas share the same metallization structure as the circuits. By exciting the interconnects between the patch areas in transmission line modes as well as in antenna modes, the interference between signals from circuit to circuit and antenna excitation signals is minimized. This has been achieved by inserting a transformer in the antenna feeding network. Examples of possible antenna and feeding structures have been investigated numerically. Scaled prototypes of the integrated antennas have been manufactured and measured.

28

BARNABY, H. J. "TOTAL DOSE EFFECTS IN LINEAR BIPOLAR INTEGRATED CIRCUITS." International Journal of High Speed Electronics and Systems 14, no. 02 (June 2004): 519–41. http://dx.doi.org/10.1142/s0129156404002491.

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Electronics systems that operate in space or strategic environments can be severely damaged by exposure to ionizing radiation. Space-based systems that utilize linear bipolar integrated circuits are particularly susceptible to radiation-induced damage because of the enhanced sensitivity of these circuits to the low rate of radiation exposure. The phenomenon of enhanced low-dose-rate sensitivity (ELDRS) demonstrates the need for a comprehensive understanding of the mechanisms of total dose effects in linear bipolar circuits. The majority of detailed bipolar total dose studies to date have focused on radiation effects mechanisms at either the process or transistor level. The goal of this text is to provide an overview of total dose mechanisms from the circuit perspective; in particular, the effects of transistor gain degradation on specific linear bipolar circuit parameters and the effects of circuit parameter degradation on select linear bipolar circuit applications.

29

Gao, Sirui. "Analog integrated circuit design with machine learning." Theoretical and Natural Science 5, no. 1 (May 25, 2023): 788–95. http://dx.doi.org/10.54254/2753-8818/5/20230495.

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Due to the widespread application of semiconductor technology in integrated circuits, more and more design studies on analog integrated circuits are gradually being implemented. However, due to the nature of analog integrated circuits, it is time-consuming and inefficient. Therefore, there are lots of experts studying how to reduce the design cycle of analog ICs. The use of machine learning in analog circuits stands out, as machine learning-based design methods have significantly reduced the analog cycle time. This review report will first introduce the algorithms related to machine learning, and the second half will outline the existing applications of machine learning in an analog integrated circuit and compare them.

30

Hu, Jian-Guo, Wen-Zhuo Mei, Jin Wu, Jia-Wei Li, and De-Ming Wang. "A Fully Integrated RFID Reader SoC." Micromachines 14, no. 9 (August 29, 2023): 1691. http://dx.doi.org/10.3390/mi14091691.

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The traditional RFID reader module relies on a discrete original design. This design integrates a microcontroller, high-frequency RFID reader IC and other multiple chips onto a PCB board, leading to bottlenecks in cost, power consumption, stability and reliability. To align with the trend towards high integration, miniaturization and low power consumption in RFID reader, this paper introduces a fully integrated RFID Reader SoC. The SoC employs the open-source Cortex-M0 core to integrate the RF transceiver, analog circuits, baseband protocol processing, memory and interface circuits into one chip. It’s compatible with ISO/IEC 14443 A-type and B-type and ISO/IEC 15693 transmission protocols and rates. Manufactured using a 0.18 μm process, the chip is compatible with multiple standards. The optimized design of the digital baseband control circuit results in a chip area of only 11.95 mm2 offering clear advantages in both area and integration compared to similar work.

31

Bhat, Rajeshwari, Mohammad Rashid Ansari, and Ruqaiya Khanam. "Effect of integrated power and clock networks on combinational circuits." International Journal of Reconfigurable and Embedded Systems (IJRES) 9, no. 3 (November 1, 2020): 242. http://dx.doi.org/10.11591/ijres.v9.i3.pp242-248.

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<p class="western" align="JUSTIFY"><span style="font-size: small;"><span style="color: #000000;"><span style="font-family: 'Times New Roman', serif;"><span><span>Reduction of power consumption is necessary in a system on chip. To achieve this, power and clock networks can be integrated. This leads to a significant reduction in power consumption in a circuit. This paper explores the effect of such a network on various combinational circuits and compares the power consumption of these circuits with conventional combinational circuits. The combinational circuits which are powered by the proposed circuit consume lesser power as compared to conventional combinational circuits.</span></span></span></span></span></p>

32

Jantos, P., D. Grzechca, and J. Rutkowski. "Evolutionary algorithms for global parametric fault diagnosis in analogue integrated circuits." Bulletin of the Polish Academy of Sciences: Technical Sciences 60, no. 1 (March 1, 2012): 133–42. http://dx.doi.org/10.2478/v10175-012-0019-4.

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Evolutionary algorithms for global parametric fault diagnosis in analogue integrated circuitsAn evolutionary method for analogue integrated circuits diagnosis is presented in this paper. The method allows for global parametric faults localization at the prototype stage of life of an analogue integrated circuit. The presented method is based on the circuit under test response base and the advanced features classification. A classifier is built with the use of evolutionary algorithms, such as differential evolution and gene expression programming. As the proposed diagnosis method might be applied at the production phase there is a method for shortening the diagnosis time suggested. An evolutionary approach has been verified with the use of several exemplary circuits - an oscillator, a band-pass filter and two operational amplifiers. A comparison of the presented algorithm and two classical methods - the linear classifier and the nearest neighborhood method - proves that the heuristic approach allows for acquiring significantly better results.

33

Takeda, Yasunori, Tomohito Sekine, Rei Shiwaku, Tomohide Murase, Hiroyuki Matsui, Daisuke Kumaki, and Shizuo Tokito. "Printed Organic Complementary Inverter with Single SAM Process Using a p-type D-A Polymer Semiconductor." Applied Sciences 8, no. 8 (August 9, 2018): 1331. http://dx.doi.org/10.3390/app8081331.

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The demonstration of the complementary integrated circuit using printing processes is indispensable for realizing electronic devices using organic thin film transistors. Although complementary integrated circuits have advantages such as low power consumption and a wide output voltage range, complementary integrated circuits fabricated by the printing method have problems regarding driving voltage and performance. Studies on fabrication processes of electronic circuits for printing technology, including optimization and simplification, are also important research topics. In this study, the fabrication process of the printed complementary integrated circuit was simplified by applying a p-type donor-acceptor (D-A) polymer semiconductor, which is not strongly affected by the electrode work function. An inverter circuit and the ring oscillator circuit were demonstrated using this process. The fabricated ring oscillator array showed excellent performance, with low voltage operation and low performance variation.

34

Stavrinidou, Eleni, Roger Gabrielsson, Eliot Gomez, Xavier Crispin, Ove Nilsson, Daniel T. Simon, and Magnus Berggren. "Electronic plants." Science Advances 1, no. 10 (November 2015): e1501136. http://dx.doi.org/10.1126/sciadv.1501136.

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The roots, stems, leaves, and vascular circuitry of higher plants are responsible for conveying the chemical signals that regulate growth and functions. From a certain perspective, these features are analogous to the contacts, interconnections, devices, and wires of discrete and integrated electronic circuits. Although many attempts have been made to augment plant function with electroactive materials, plants’ “circuitry” has never been directly merged with electronics. We report analog and digital organic electronic circuits and devices manufactured in living plants. The four key components of a circuit have been achieved using the xylem, leaves, veins, and signals of the plant as the template and integral part of the circuit elements and functions. With integrated and distributed electronics in plants, one can envisage a range of applications including precision recording and regulation of physiology, energy harvesting from photosynthesis, and alternatives to genetic modification for plant optimization.

35

Yagodkin, A., V. Zolnikov, Tatyana Skvortsova, A. Achkasov, Sergey Kuznecov, and F. Makarenko. "Development of algorithms and programs for the analysis of electrical characteristics BIS." Modeling of systems and processes 15, no. 4 (December 13, 2022): 136–48. http://dx.doi.org/10.12737/2219-0767-2022-15-4-136-148.

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Modern mathematical models for automatic analysis of electrical characteristics of integrated circuits are considered. The requirements for the analysis programs are formulated. A comparative analysis of machine methods for calculating integrated circuits is carried out in terms of their accuracy, RAM volumes and calculation time. The features of the development of modern automation tools for designing integrated circuits are considered. One of the main tasks of designing an integrated circuit is a schematic analysis, which must be carried out both at the preliminary stage and after the development of the integrated circuit topology. However, it is possible to identify the main re-quirements that a modern analysis program must meet: reliability - stable calculation of a wide class of electronic circuits, obtaining solutions even for poorly conditioned tasks; high performance - this requirement is especially important when calculating BIS, in tasks of multivariate analysis, such as statistical analysis, and optimization; low costs of machine memory and expansion of the maximum permissible complexity of the analyzed circuits; flexibility, the possibility of making changes to the program, in particular, the replacement of mathematical models of circuit components, the introduction of new models, the improvement of the computational algorithm, the inclusion of the pro-gram in more complex programs, etc.; the availability of convenient input and output of initial information.

36

Deeb, Ali, Abdalrahman Ibrahim, Mohamed Salem, Joachim Pichler, Sergii Tkachov, Anjeza Karaj, Fadi Al Machot, and Kyamakya Kyandoghere. "A Robust Automated Analog Circuits Classification Involving a Graph Neural Network and a Novel Data Augmentation Strategy." Sensors 23, no. 6 (March 9, 2023): 2989. http://dx.doi.org/10.3390/s23062989.

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Analog mixed-signal (AMS) verification is one of the essential tasks in the development process of modern systems-on-chip (SoC). Most parts of the AMS verification flow are already automated, except for stimuli generation, which has been performed manually. It is thus challenging and time-consuming. Hence, automation is a necessity. To generate stimuli, subcircuits or subblocks of a given analog circuit module should be identified/classified. However, there currently needs to be a reliable industrial tool that can automatically identify/classify analog sub-circuits (eventually in the frame of a circuit design process) or automatically classify a given analog circuit at hand. Besides verification, several other processes would profit enormously from the availability of a robust and reliable automated classification model for analog circuit modules (which may belong to different levels). This paper presents how to use a Graph Convolutional Network (GCN) model and proposes a novel data augmentation strategy to automatically classify analog circuits of a given level. Eventually, it can be upscaled or integrated within a more complex functional module (for a structure recognition of complex analog circuits), targeting the identification of subcircuits within a more complex analog circuit module. An integrated novel data augmentation technique is particularly crucial due to the harsh reality of the availability of generally only a relatively limited dataset of analog circuits’ schematics (i.e., sample architectures) in practical settings. Through a comprehensive ontology, we first introduce a graph representation framework of the circuits’ schematics, which consists of converting the circuit’s related netlists into graphs. Then, we use a robust classifier consisting of a GCN processor to determine the label corresponding to the given input analog circuit’s schematics. Furthermore, the classification performance is improved and robust by involving a novel data augmentation technique. The classification accuracy was enhanced from 48.2% to 76.6% using feature matrix augmentation, and from 72% to 92% using Dataset Augmentation by Flipping. A 100% accuracy was achieved after applying either multi-Stage augmentation or Hyperphysical Augmentation. Overall, extensive tests of the concept were developed to demonstrate high accuracy for the analog circuit’s classification endeavor. This is solid support for a future up-scaling towards an automated analog circuits’ structure detection, which is one of the prerequisites not only for the stimuli generation in the frame of analog mixed-signal verification but also for other critical endeavors related to the engineering of AMS circuits.

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Goswami, Neelaksha, and Satendra Singh. "Learning on Proposal and Optimization of Stumpy Influence CMOS Transconductance Operational Amplifier." RESEARCH REVIEW International Journal of Multidisciplinary 6, no. 12 (December 15, 2021): 184–90. http://dx.doi.org/10.31305/rrijm.2021.v06.i12.028.

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Portable systems, such as wireless communication systems, laptops, smart phones, consumer electronics, and implanted medical devices, are in high demand in the rapidly expanding consumer market. When it comes to extending the running duration of these portable devices, low-power and low-voltage integrated circuits are used almost universally to achieve this. The design of an analogue integrated circuit with somewhat excellent processing characteristics, when compared to its digital equivalent, is a difficult undertaking, especially when it comes to applications requiring low voltage and low power. The use of a digitally driven CMOS technology for the design of an analogue circuit equivalent has increased the difficulty of the difficulties in today's environment. Because of this, the design of ultra-low power analogue circuits has become the bottleneck in the contemporary Complementary Metal Oxide Semiconductor (CMOS) technology. This thesis analyses some of the frequently utilised low power design strategies, which are specifically suited for analogue circuits and are being widely adopted. In today's electronic age, it is necessary to build competitive analogue integrated circuits in order to stay up with the high performance digital integrated circuits that are now available. Since its invention, the amplifier has played a critical role in the design of the vast majority of analogue integrated circuits. Despite this, the performance of the amplifier is what distinguishes the majority of analogue circuits such as converters, filters, and tracking circuits.

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Shibata, Tadashi, and Tadahiro Ohmi. "Implementing Intelligence in Silicon Integrated Circuits Using Neuron-Like High-Functionality Transistors." Journal of Robotics and Mechatronics 8, no. 6 (December 20, 1996): 508–15. http://dx.doi.org/10.20965/jrm.1996.p0508.

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The primary objective of this article is not to present integrated circuit implementation of neural networks in the sense that neurophysiological models are constructed in electronic circuits, but to describe new-architecture intelligent electronic circuits built using a neuron-like high-functionality transistor as a basic circuit element. This has greatly reduced the VLSI hardware/software burden in carrying out intelligent data processing and would find promising applications in robotics. The transistor is a multiple-input-gate thresholding device called a neuron MOSFET (neuMOS or νMOS) due to its functional similarity to a simple neuron model. vMOS circuits are characterized by a high degree of parallelism in hardware computation, large flexibility in the hardware configuration, and a dramatic reduction in circuit complexity compared to conventional integrated circuits. As a result, a number of new-concept circuits has been developed. Examples include a real-time reconfigurable logic circuit called flexware and associative memory conducting a fully parallel search for the most similar targets. A simple hardware model for self-learning systems is also presented. The enhancement in functionality at a very elemental transistor level is critical to building human-like intelligent systems on silicon.

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DJAHANSHAHI, HORMOZ, MAJID AHMADI, GRAHAM A. JULLIEN, and WILLIAM C. MILLER. "NEURAL NETWORK INTEGRATED CIRCUITS WITH SINGLE-BLOCK MIXED SIGNAL ARRAYS." Journal of Circuits, Systems and Computers 08, no. 05n06 (October 1998): 589–604. http://dx.doi.org/10.1142/s0218126698000377.

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This paper discusses the design and implementation of a family of mixed-signal neural network integrated circuits for general and application-specific purposes. Regular Arrays of a nonlinearly-loaded multiplier block form the core of multi-layer neural networks. Input-output circuitry and network size, however, vary depending on design applications. Salient features of the present architecture, such as modularity and reduced interconnection problems and areas are highlighted and circuit design and improvements are presented for its universal building block. Other design issues such as supply voltage and power reduction and pin limitations are discussed together with experimental results.

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Hu, Xiao Ming. "A Study on Wafer and Feature Size." Advanced Materials Research 1049-1050 (October 2014): 762–66. http://dx.doi.org/10.4028/www.scientific.net/amr.1049-1050.762.

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the paper introduced the bare silicon crystal how to become a wafer .then, it told the processing of wafers to produce integrated circuits .Today, most integrated circuits (ICs) are made of silicon. every integrated circuit is tested and functional and formed a dies. At last , the article explain feature size and the number of gross die per wafer (DPW).

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Xu, Zulin. "An intelligent fault detection approach for digital integrated circuits through graph neural networks." Mathematical Biosciences and Engineering 20, no. 6 (2023): 9992–10006. http://dx.doi.org/10.3934/mbe.2023438.

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<abstract><p>To quickly and accurately realize the fault diagnosis of analog circuits, this paper introduces the graph neural network method and proposes a fault diagnosis method for digital integrated circuits. The method filters the signals present in the digital integrated circuit to remove noise signals and redundant signals and analyzes the digital integrated circuit characteristics after the filtering process to obtain the digital integrated circuit leakage current variation. To the problem of the lack of a parametric model for Through-Silicon Via (TSV) defect modeling, the method of TSV defect modeling based on finite element analysis is proposed. The common TSV defects such as voids, open circuits, leakage, and unaligned micro-pads are modeled and analyzed by using industrial-grade FEA tools Q3D and HFSS, and the equivalent circuit model of resistance inductance conductance capacitance (RLGC) for each defect is obtained. Finally, the superior performance of this paper in fault diagnosis accuracy and fault diagnosis efficiency is verified by comparing and analyzing with the traditional graph neural network method and random graph neural network method for active filter circuits.</p></abstract>

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Punati, Mounika, and R. Yuvaraj. "Substrate integrated circuits for high frequency of opto electronics." International Journal of Reconfigurable and Embedded Systems (IJRES) 9, no. 3 (November 1, 2020): 224. http://dx.doi.org/10.11591/ijres.v9.i3.pp224-228.

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Another age of high-recurrence coordinated circuits is displayed, which is called substrate incorporated circuits (SICS). Current cutting edge of circuit plan and implementation stages dependent on this new idea are assessed and dis-cussed in delail. Various potential outcomes and various favorable circumstances of the SICS are appeared for microwave, millimeter-wave and opto hardware applications. Down to earth models are delineated with hypothetical and trial results for substrate coordinated waveguide (SIW), substrate incorporated chunk waveguide (SISW) and substrate incorporated non-transmitting dielectric (SI") direct circuits. Future innovative work patterns are likewise dis-cussed regarding ease imaginative plan of millimeter-wave and optoelectronic coordinated circuits.

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Qiu, Tian. "Application and possibility of machine learning in integrated circuit design." Applied and Computational Engineering 6, no. 1 (June 14, 2023): 60–66. http://dx.doi.org/10.54254/2755-2721/6/20230457.

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Artificial Intelligence has had an impact on the field of integrated circuits. Artificial Intelligence technology is gradually replacing the traditional methodology of implementing Integrated Circuit tasks, which consumes a lot of time, funding, and labor. Traditionally, electronic products, like chips, which consist of a large number of circuits, were very slow and costly to process, because it was done by humans. The engineers have to design the layout, carry out operations, verify, and test the circuits, and this is actually extremely inefficient and expensive. However, with the help of Artificial Intelligence technology, efficiency can be greatly improved. The algorithms of Artificial Intelligence to a large extent, accelerated the process of designing, detecting, and maintaining the Integrated Circuit. Nowadays, many companies are applying Artificial Intelligence to upgrade their own products. Machine Learning is one of the main branches of Artificial Intelligence, and its powerfulness has provided a lot of help in the Integrated Circuit tasks. This paper discussed and analyzed the application and possibility of machine learning specifically in Integrated Circuit design activities through literature review and data research.

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Butt, Muhammad A. "Integrated Optics: Platforms and Fabrication Methods." Encyclopedia 3, no. 3 (June 28, 2023): 824–38. http://dx.doi.org/10.3390/encyclopedia3030059.

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Integrated optics is a field of study and technology that focuses on the design, fabrication, and application of optical devices and systems using integrated circuit technology. It involves the integration of various optical components, such as waveguides, couplers, modulators, detectors, and lasers, into a single substrate. One of the key advantages of integrated optics is its compatibility with electronic integrated circuits. This compatibility enables seamless integration of optical and electronic functionalities onto the same chip, allowing efficient data transfer between optical and electronic domains. This synergy is crucial for applications such as optical interconnects in high-speed communication systems, optical sensing interfaces, and optoelectronic integrated circuits. This entry presents a brief study on some of the widely used and commercially available optical platforms and fabrication methods that can be used to create photonic integrated circuits.

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Mohan, Navya, and J. P. Anita. "Early Detection of Clustered Trojan Attacks on Integrated Circuits Using Transition Delay Fault Model." Cryptography 7, no. 1 (January 28, 2023): 4. http://dx.doi.org/10.3390/cryptography7010004.

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The chances of detecting a malicious reliability attack induced by an offshore foundry are grim. The hardware Trojans affecting a circuit’s reliability do not tend to alter the circuit layout. These Trojans often manifest as an increased delay in certain parts of the circuit. These delay faults easily escape during the integrated circuits (IC) testing phase, hence are difficult to detect. If additional patterns to detect delay faults are generated during the test pattern generation stage, then reliability attacks can be detected early without any hardware overhead. This paper proposes a novel method to generate patterns that trigger Trojans without altering the circuit model. The generated patterns’ ability to diagnose clustered Trojans are also analyzed. The proposed method uses only single fault simulation to detect clustered Trojans, thereby reducing the computational complexity. Experimental results show that the proposed algorithm has a detection ratio of 99.99% when applied on ISCAS’89, ITC’99 and IWLS’05 benchmark circuits. Experiments on clustered Trojans indicate a 46% and 34% improvement in accuracy and resolution compared to a standard Automatic Test Pattern Generator (ATPG)Tool.

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Kazior, Thomas E. "Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 372, no. 2012 (March 28, 2014): 20130105. http://dx.doi.org/10.1098/rsta.2013.0105.

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Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications.

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Greenstein, Shane. "Shortages of Integrated Circuits." IEEE Micro 41, no. 4 (July 1, 2021): 86–88. http://dx.doi.org/10.1109/mm.2021.3086540.

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Sorger, Volker J., Rupert F. Oulton, Ren-Min Ma, and Xiang Zhang. "Toward integrated plasmonic circuits." MRS Bulletin 37, no. 8 (August 2012): 728–38. http://dx.doi.org/10.1557/mrs.2012.170.

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Koch, T. L., and U. Koren. "Semiconductor photonic integrated circuits." IEEE Journal of Quantum Electronics 27, no. 3 (March 1991): 641–53. http://dx.doi.org/10.1109/3.81373.

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Chien, Charles, and Zhiwei Xu. "Integrated Circuits for Communications." IEEE Communications Magazine 55, no. 10 (October 2017): 134. http://dx.doi.org/10.1109/mcom.2017.8067700.

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