Добірка наукової літератури з теми "Integer-N phase-locked loop"
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Статті в журналах з теми "Integer-N phase-locked loop"
Kuan, Ting-Kuei, and Shen-Iuan Liu. "A Loop Gain Optimization Technique for Integer-$N$ TDC-Based Phase-Locked Loops." IEEE Transactions on Circuits and Systems I: Regular Papers 62, no. 7 (July 2015): 1873–82. http://dx.doi.org/10.1109/tcsi.2015.2423793.
Повний текст джерелаWu, Jian-Ming, Stephen Chou, Simon Cimin Li, and Cheng-Yu Ho. "Comparing phase noise of integer-N phase-locked loop of voltage-controlled and digitally controlled oscillators." Microwave and Optical Technology Letters 56, no. 10 (July 22, 2014): 2226–28. http://dx.doi.org/10.1002/mop.28559.
Повний текст джерелаSumi, Yasuaki, Shigeki Obote, Yutaka Fukui, Kazutoshi Tsuda, and Kouichi Syoubu. "A New Fractional-N PLL Frequency Synthesizer." Journal of Circuits, Systems and Computers 07, no. 05 (October 1997): 395–405. http://dx.doi.org/10.1142/s0218126697000292.
Повний текст джерелаKazeminia, Sarang, Khayrollah Hadidi, and Abdollah Khoei. "A Wide-Range Low-Jitter PLL Based on Fast-Response VCO and Simplified Straightforward Methodology of Loop Stabilization in Integer-N PLLs." Journal of Circuits, Systems and Computers 24, no. 07 (June 17, 2015): 1550104. http://dx.doi.org/10.1142/s0218126615501042.
Повний текст джерелаKoithyar, Aravinda, and Telugu Kuppushetty Ramesh. "Integer‐ N charge pump phase locked loop for 2.4 GHz application with a novel design of phase frequency detector." IET Circuits, Devices & Systems 14, no. 1 (January 2020): 60–65. http://dx.doi.org/10.1049/iet-cds.2019.0189.
Повний текст джерелаPandit, Vabya Kumar, Chitra Ramamurthy, Sourabh Basu, and Deepak V. Ingale. "Design and development of Ka-band carrier generator for IRS applications." International Journal of Microwave and Wireless Technologies 7, no. 6 (August 13, 2014): 637–44. http://dx.doi.org/10.1017/s175907871400107x.
Повний текст джерелаJin, Junting, Yuhua Jin та Yebing Gan. "A 500 kHz to 150 MHz Multi-Output Clock Generator Using Analog PLL and Open-Loop Fractional Divider with 0.13 μm CMOS". Electronics 11, № 15 (27 липня 2022): 2347. http://dx.doi.org/10.3390/electronics11152347.
Повний текст джерелаJo, Jongwan, David Kim, Arash Hejazi, YoungGun Pu, Yeonjae Jung, Hyungki Huh, Seokkee Kim, Joon-Mo Yoo, and Kang-Yoon Lee. "Low Phase-Noise, 2.4 and 5.8 GHz Dual-Band Frequency Synthesizer with Class-C VCO and Bias-Controlled Charge Pump for RF Wireless Charging System in 180 nm CMOS Process." Electronics 11, no. 7 (April 1, 2022): 1118. http://dx.doi.org/10.3390/electronics11071118.
Повний текст джерелаTrinh, Van-Son, Hyohyun Nam, Jeong-Moon Song, and Jung-Dong Park. "A 78.8–84 GHz Phase Locked Loop Synthesizer for a W-Band Frequency-Hopping FMCW Radar Transceiver in 65 nm CMOS." Sensors 22, no. 10 (May 10, 2022): 3626. http://dx.doi.org/10.3390/s22103626.
Повний текст джерелаSánchez-Azqueta, Carlos, Erick Guerrero, Cecilia Gimeno, and Santiago Celma. "A Reconfigurable Radio-Frequency Converter IC in 0.18 µm CMOS." Electronics 8, no. 10 (October 10, 2019): 1146. http://dx.doi.org/10.3390/electronics8101146.
Повний текст джерелаДисертації з теми "Integer-N phase-locked loop"
Tiagaraj, Sathya Narasimman. "Design of an Ultra-Low Phase Noise and Wide-Band Digital Phase Locked Loop for AWS and PCS Band Applications and CppSim Evaluation." The Ohio State University, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=osu1461262041.
Повний текст джерелаSharkia, Ahmad. "On the design of type-i integer-n phase-locked loops." Thesis, University of British Columbia, 2015. http://hdl.handle.net/2429/54504.
Повний текст джерелаApplied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
Wang, Jian-Xing, and 汪建興. "Design a Phase-Locked Loop Based Integer-N Frequency Synthesizer for 802.11b WLAN." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/85256795312159484228.
Повний текст джерела逢甲大學
電子工程所
92
ABSTRACT Design a 2.4 GHz CMOS Integer-N frequency synthesizer for 802.11b wireless communication system is described in this these. This frequency synthesizer consists of a off-chip VCO, a phase-frequency detector, a charge pump, a second-order loop filter, and dual-modulus frequency divider. This is realized by 0.35um 2P4M TSMC CMOS process. The operation frequency of divider can operate more than 2.4GHz. It was verified by h-spice software and total function was proved by Matlab Simulink software.
Kamal, Noorfazila. "Reference spurs in an integer-N phase-locked loop : analysis, modelling and design." Thesis, 2013. http://hdl.handle.net/2440/80592.
Повний текст джерелаThesis (Ph.D. )-- University of Adelaide, School of Electrical and Electronic Engineering, 2013
Liao, Yu-Yu, and 廖佑予. "Design and Implementation of a CMOS Low Power Integer-N Cascaded Phase-Locked Loop for Implantable Medical SOCs." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/49048124277386257094.
Повний текст джерела國立交通大學
電子工程學系 電子研究所
101
In recent year, the implanted biomedical devices are got more and more attention in medical treatment. The Federal Communications Commission (FCC) announced the MICS (Medical Implant Communication Service) band for the implanted communication devices in 1999. In 2009, the band was broadened and renamed as MedRadio (Medical Device Radiocommunications Service) for diagnostic and therapeutic purposes. In this thesis, a low power integer-N cascaded phase locked loop (PLL) is presented to provide the carrier signal and clock signals for a SOC with MedRadio-band transceiver, ADC, DSP, and 13.56-MHz wireless power supply. In the proposed cascaded PLL, the first PLL provides the sampling clocks while the second PLL provides the carrier clock. Furthermore, the 13.56-MHz signal from the receiving coil of the wireless power transmission system is utilized as the input reference signal. Ring-based voltage controlled oscillator (VCO) is designed to minimize both power consumption and chip area. The chip is designed and implemented in TSMC 0.18-μm CMOS technology. According to the experimental results, the output of this PLL oscillates at 402.9MHz and exhibits phase noise of -79 dBc/Hz at 100 kHz offset. The result shows that the cascade structure work well, while only consume 0.28mW in the first PLL and 0.46mW in the second PLL with a 1.8V supply voltage. The die area is 0.525 mm2. The proposed cascaded PLL has low power dissipation, small chip area, and no off-chip components or crystal oscillator. It is suitable for the integration with implantable medical system-on-chips (SOCs). Finally, a discussion about poor jitter performance when turning on two PLL in the same time is made and the improvement is proposed.
Chuang, Chih-Cheng, and 莊志成. "Implementations on X-Band CMOS Quadrature Voltage Controlled Oscillator, Integer-N Phase Locked Loop and GaN High Power and High Efficiency Voltage Controlled Oscillator." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/qkzg4v.
Повний текст джерела國立中央大學
電機工程學系
107
This thesis developed four local oscillator (LO) circuits for the signal source of X band and Ka band transceivers. The X-band LO was realized in tsmcTM 0.18 μm technology. The Ka-band LO was ikplemented in tsmcTM 90 nm technology. The X-band high power and high efficiency was realized in WINTM 0.25 μm GaN process. The developed LO circuits are listed as follow, A.Implementation on X-Band Quadrature Voltage Controlled Oscillator Using Cascode Coupling Technique The circuit improves the phase noise in traditional parallel coupling technique by using cascaded-coupling topology. After measurements, the operation frequency is from 9.27 to 10.12 GHz (i.e., 8.7% tuning range). The best phase noise is -115.2 dBc/Hz at 1-MHz offset. The output power including transmission loss is -4.78 dBm. Under 1.45-V supply voltage, the power consumption is 7.72 mW which is correspondent to an FoM of -185. The chip size includes all pads is 1.096 × 0.593 mm2. B.Implementation on X-Band Integer-N Phase Locked Loop (PLL) The functional circuit blocks of the designed PLL include a voltage controlled oscillator, a current mode logic divider, a differential to single buffer, a TSPC divider, a phase and frequency detector, a charge pump, and a loop filter. This thesis analyzes the behavior model of PLL. Meanwhile, we also analyze the issue of the differential-to-single buffer amplifier. The thesis adopts the phase and frequency detector with zero dead zone topology. The PLL is locked from 9.6 to 10.05 GHz when reference signal is 37.5 to 39.2578125 MHz. The division ratio is 256 and the total power consumption is 39.2 mW. The reference spur is as low as -45.7 dBc and phase noise is -93.7 dBc/Hz at 1-MHz offset. The chip size includes all pads is 1.035 × 0.809 mm2. C.Implementation on X-Band Tunable Feedback Type Voltage Controlled Oscillator The implementation on the VCO is realized in WINTM 0.25 μm GaN process under the constraint of the via-hole at source node that makes common source topology can be only adopted. Meanwhile, no varactor model is available. After measurements, the tuning frequency is from 9.348 to 9.46 GHz, and the output power including the transmission line loss and a 30-dB attenuator is 27.89 dBm. The best phase noise is -121.62 dBc/Hz at 1-MHz offset frequency. Under the 19-V supply voltage, the total power consumption is 2204 mW. The DC-to-RF conversion efficiency is 27.89%. The FoMp and FoMposc are -195.49 and -223.38, respectively. The chip size includes all pads is 2 × 1 mm2. D.Implementation on Ka-Band Integer-N Phase Locked Loop (PLL) The functional blocks of PLL include a VCO, an injection locked frequency divider, a current mode logic divider, a differential-to-single buffer, a TSPC divider, a phase and frequency detector, a charge pump, and a loop filter. The PLL is locked from 26.52 to 27.88 GHz when reference signal is 103.6 to 108.9 MHz. The division ratio is 256 and the total power consumption is 43.9 mW. The reference spur is -48.9 dBc and phase noise is -95.8 dBc/Hz at 1-MHz offset when PLL is locked. The chip size includes all pads is 1.015 × 0.972 mm2.
Chan, Kai-Chun, and 詹凱鈞. "Implementations on C-band CMOS Low Phase Noise Class-C Voltage Controlled Oscillator, Transformer-coupled Quadrature Voltage Controlled Oscillator, C-band Integer-N Phase Locked Loop with Class-F Voltage Controlled Oscillator and X-band III-V Power Oscillators." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/5554um.
Повний текст джерела國立中央大學
電機工程學系
106
This thesis developed six local oscillator (LO) circuits for the signal sources of C band and X band transceivers. Three C band LOs were realized in tsmcTM CMOS processes. The X band high power LOs were realized in WINTM 0.25 m GaN and InGaAs pHEMT technologies. The developed LO circuits are listed as follow, A Implementations on C-band CMOS Local Oscillator Circuits I.Low Phase Noise Class-C Voltage Control Oscillator The Class-C oscillator has the features of low power consumption, high current efficiency and low phase noise. This thesis analyzed the phase noise performance of the traditional Colpitts oscillator and Class-C oscillator, repectively. Then, the author proposed a dynamic bias circuit to solve hard start-up problem of the Class-C oscillator. The designed oscillator consumed the dc power of 3.9 mW. The measured tuning range is 5.28 - 5.53 GHz (4.62 %). The lowest phase noise at 1-MHz offset frequency is -120.1 dBc/Hz which is correspondent to the FoM of -188.7. The chip size includes all pads is 0.671 × 0.909 mm2. II.Transformer Coupled Quadrature Voltage Control Oscillator The thesis introduced the requirements of the quadrature signal and how to generate the IQ signals by using transformer coupling technique. Meanwhile, the bi-model problem in IQ signal generation can be solved by this technique accordingly. The use of tail filter also improved the phase noise of quadrature oscillator. These IQ signals totally consumed the dc power of 21.6 mW. The tuning range of the circuit is from 5.23 to 5.73 GHz (9.1 %). The lowest phase noise at 1-MHz offset frequency is -119.75 dBc/Hz which is correspondent to a lowest FoM of -180.8. The chip size include all pads is 1.132 × 0.738 mm2. III.Integer-N Phase Locked Loop (PLL) with Class-F Voltage Controlled Oscillator The PLL adopted a Class-F VCO to improve the phase noise perforamnce. This thesis analyzed the mathematical model of the PLL and developed all functional block cicruits of the PLL. The PLL consumed the dc power of 32.5 mW. The phase noise at 10-kHz offset frequency as the PLL was locked is -95.4 dBc/Hz, and achieves a low frequency FoM of -192.3. The chip size include all pads is 0.887 × 1.077 mm2. B.Implementations on X-band III-V High Power Local Oscillator Circuits I.Clapp Power Oscillator The Clapp power oscillator circuit was realized in WINTM 0.25 m GaN high power process. Total power consumption of the circuit is 416 mW. The lowest phase noise at 1 MHz offset frequency is -118.02 dBc/Hz. The output power is 19.6 dBm. The DC-RF conversion efficiency is 21.9 %. The FoMPOSC, which adds output power and efficiency performance in the conventional FoM of oscillator, is -210.9. The chip size includes all pads is 1.5 × 1 mm2. II.Clapp Power Voltage Control Oscillator The Clapp power voltage control oscillator circuit was realized by 0.15 m InGaAs pHEMT technology. The GaAs equvilent diode was used as a varactor for the frequrncy tuning. The total power consumption is 20 mW. The tuning range is from 9.41 to 10.04 GHz (6.4 %). The lowest phase noise at 1 MHz offset frequency is -100.55 dBc/Hz. The highest output power is 7.7 dBm. The DC-R Fconversion efficiency is 35.6 %. The FoMPOSC is -202.4. The chip size included all pads is 1.5 × 1 mm2. III.Power Oscillator use Class-E Network The Class-E power oscillator was realized in 0.25 m GaN high power process. The phase noise was estimated according to the phase noise measured before. Since the circuit is still in the process, the design process and full EM simulation result is shown in this thesis. The expected total power consumption is 2.9 W. The lowest phase noise at 1 MHz offset frequency is estimated as -126.5 dBc/Hz. The highest output power is 30.5 dBm. The DC-RF efficiency 39.1 % was calculated. The FoMPOSC is -232.9. The chip size is 1.5 × 1 mm2.
"A 1.5 V, 2.4 GHz monolithic CMOS sub-integer-N frequency synthesizer for WLAN application." Thesis, 2011. http://library.cuhk.edu.hk/record=b6075113.
Повний текст джерелаTo demonstrate the feasibility of the two proposed coupling methodologies, two subinteger-N PLLs with different fractional frequency dividers have been fabricated in a 0.35 11m standard CMOS process. In design 1, the dual divide-by-4 ILFD in the fractional frequency divider is implemented with the cross-coupling scheme while the coherent-coupling scheme is used in design 2. The measured spurious tones of both designs are under -64 dBc and their measured phase noise at 1 MHz frequency offset is less than -115 dBc/Hz. The two proposed frequency synthesizers settle at approximately 32 us and their phase mismatches of the quadrature outputs are better than 38 dB (characterized by image rejection ratio). Moreover, both designs individually occupy a chip area as small as 0.70 mm2. At a supply of 1.5 V, the total power consumption for each design is below 24.1 mW.
Wireless local area networks (WLANs) are being extensively deployed since their introduction in the late 1990s. Low cost, high performance frequency synthesizers are indispensable in WLAN telecommunication systems. Meanwhile, integer-N phase-locked loop (PLL) architecture is commonly chosen due to its low circuit complexity and clean output spectrum with few spurs. However, designers have to face the tradeoffs between frequency resolution, phase noise performance and switching time. To solve the above dilemma, fractional-N PLL architecture is proposed, but fractional spurs emerge in the output spectrum, degrading the spectrum purity. Sub-integer-N PLL is thus a compromise between the integer-N and fractional-N PLL. Its structure is same as that of the integer-N while fractional division is achieved by a fractional frequency divider that is not relied on time-varying modulus control as in the fractional-N PLL.
Chang, Ka Fai.
Adviser: Kwok-Keung Cheng.
Source: Dissertation Abstracts International, Volume: 73-04, Section: B, page: .
Thesis (Ph.D.)--Chinese University of Hong Kong, 2011.
Includes bibliographical references (leaves 176-188).
Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Abstract also in Chinese.
Частини книг з теми "Integer-N phase-locked loop"
Choudhary, Vikas, and Krzysztof (Kris) Iniewski. "Phase-Locked Loop—Based Integer-N RF Synthesizer." In Wireless Technologies, 383–426. CRC Press, 2017. http://dx.doi.org/10.1201/9780849379970-16.
Повний текст джерелаChoudhary, Vikas, and Krzysztof (Kris) Iniewski. "Phase-Locked Loop–Based Integer-N RF Synthesizer." In Wireless Technologies, 383–426. CRC Press, 2007. http://dx.doi.org/10.1201/9780849379970.ch14.
Повний текст джерелаТези доповідей конференцій з теми "Integer-N phase-locked loop"
Liao, Te-Wen, Jun-Ren Su, and Chung-Chih Hung. "Low-spur technique for Integer-N phase-locked loop." In 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2012. http://dx.doi.org/10.1109/mwscas.2012.6292078.
Повний текст джерелаKoithyar, Aravinda, and T. K. Ramesh. "Integer-N charge pump phase locked loop with reduced current mismatch." In 2017 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET). IEEE, 2017. http://dx.doi.org/10.1109/wispnet.2017.8299840.
Повний текст джерелаRong, Chao, Susnata Mondal, L. Richard Carley, and Jeyanandh Paramesh. "A 60-GHz Digital Sub-Sampling Integer-N Phase-Locked Loop." In 2020 IEEE Texas Symposium on Wireless and Microwave Circuits and Systems (WMCS). IEEE, 2020. http://dx.doi.org/10.1109/wmcs49442.2020.9172416.
Повний текст джерелаTeixeira, Rui Moutinho, and Jose Machado da Silva. "Design for Calibratability of a N-Integer Low-Frequency Phase-Locked Loop." In 2018 Conference on Design of Circuits and Integrated Systems (DCIS). IEEE, 2018. http://dx.doi.org/10.1109/dcis.2018.8681479.
Повний текст джерелаKamal, Noorfazila, Said Al-Sarawi, and Derek Abbott. "An accurate analytical spur model for an integer-N phase-locked loop." In 2012 4th International Conference on Intelligent & Advanced Systems (ICIAS). IEEE, 2012. http://dx.doi.org/10.1109/icias.2012.6306096.
Повний текст джерелаButryn, Igor, Krzysztof Siwiec, Jakub Kopanski, and Witold A. Pleskacz. "Integer-N phase locked loop for bluetooth receiver in CMOS 130 nm technology." In 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE, 2016. http://dx.doi.org/10.1109/ddecs.2016.7482469.
Повний текст джерелаLiao, Yu-Yu, Wei-Ming Chen, and Chung-Yu Wu. "A CMOS MedRadio-band low-power integer-N cascaded phase-locked loop for implantable medical SOCs." In 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS). IEEE, 2013. http://dx.doi.org/10.1109/biocas.2013.6679695.
Повний текст джерелаYi-Xiao Wang, Wei-Ming Chen, and Chung-Yu Wu. "A 65nm CMOS low-power MedRadio-band integer-N cascaded phase-locked loop for implantable medical systems." In 2014 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC). IEEE, 2014. http://dx.doi.org/10.1109/embc.2014.6943673.
Повний текст джерелаLei, Feiran, and Marvin H. White. "A low noise, inductor-less, integer-N RF synthesizer using phase-locked loop with reference injection (PLL-RI)." In 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2017. http://dx.doi.org/10.1109/mwscas.2017.8052934.
Повний текст джерелаBiggio, Matteo, Federico Bizzarri, Angelo Brambilla, Giorgio Carlini, and Marco Storace. "Reliable and efficient phase noise simulation of mixed-mode integer-N Phase-Locked Loops." In 2013 European Conference on Circuit Theory and Design (ECCTD). IEEE, 2013. http://dx.doi.org/10.1109/ecctd.2013.6662284.
Повний текст джерела