Дисертації з теми "Input differential"
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Zhang, Peichang. "Coherent versus differential multiple-input multiple-output systems." Thesis, University of Southampton, 2015. https://eprints.soton.ac.uk/376511/.
Повний текст джерелаShahiri, Hazrul Izuan. "Labor Input Elasticity, Employment Outcomes, and Occupation Segregation." Diss., The University of Arizona, 2012. http://hdl.handle.net/10150/232492.
Повний текст джерелаFoley, Dawn Christine. "Applications of State space realization of nonlinear input/output difference equations." Thesis, Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/16818.
Повний текст джерелаFujimoto, Kenji, Jacquelien M. A. Scherpen, and 健治 藤本. "Nonlinear input-normal realizations based on the differential eigenstructure of Hankel operators." IEEE, 2005. http://hdl.handle.net/2237/6745.
Повний текст джерелаWalker, Kenneth N. (Kenneth Neal). "Differential Effects of Biofeedback Input on Lowering Frontalis Electromyographic Levels in Right and Left Handers." Thesis, University of North Texas, 1990. https://digital.library.unt.edu/ark:/67531/metadc331405/.
Повний текст джерелаDanielson, Jon David. "Mobile boom cranes and advanced input shaping control." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24651.
Повний текст джерелаDang, Xiaoyu. "An Optimum Detector for Space-Time Trellis Coded Differential MSK." International Foundation for Telemetering, 2007. http://hdl.handle.net/10150/604515.
Повний текст джерелаThe accuracy of channel estimation plays a crucial role in the demodulation of data symbols sent across an unknown wireless medium. In this work a new analytical expression for the channel estimation error of a multiple input multiple output (MIMO) system is obtained when the wireless medium is continuously changing in the temporal domain. Numerical examples are provided to illustrate our findings. Space-time (ST) coding using Continuous Phase Modulation (CPM) has spectral advantages relative to linear modulations. In spite of the spectral benefits, Space-Time Trellis Codes (STTC) using the CPM implementation of Minimum Shift Keying (MSK) scheme has inherent inphase and quadrature interference, when the received complex baseband signal is the input into the matchfilter to remove the shaped sinusoid pulses. In this paper a novel optimum transmitting and detecting structure for STTC-MSK is proposed. Treating the Alamouti scheme as an outer code, each STTC MSK waveform frame is immediately followed by the orthogonal conjugate waveform frame at the transmit side. At the receiver first orthogonal wave forming is applied, then a new time-variant yet simple trellis structure of the STTC-MSK signals is developed. This STTC-MSK detector is absolutely guaranteed to be I/Q interference-free and still keeps a smaller computation load compared with STTC-QPSK. Simulations are made over quasi-static AWGN fading channel. It is shown that our detector for ST-MSK has solved the I/Q interference problem and has around 2.8 dB gain compared with the Alamouti Scheme and 3.8 dB gain for bit error rate at 5 X 10^(-3) in a 2 by 1 Multiple Input Single Output system.
Noller, Yannic. "Hybrid Differential Software Testing." Doctoral thesis, Humboldt-Universität zu Berlin, 2020. http://dx.doi.org/10.18452/21968.
Повний текст джерелаDifferential software testing is important for software quality assurance as it aims to automatically generate test inputs that reveal behavioral differences in software. The concrete analysis procedure depends on the targeted result: differential testing can reveal divergences between two execution paths (1) of different program versions or (2) within the same program. The first analysis type would execute different program versions with the same input, while the second type would execute the same program with different inputs. Therefore, detecting regression bugs in software evolution, analyzing side-channels in programs, maximizing the execution cost of a program over multiple executions, and evaluating the robustness of neural networks are instances of differential software analysis with the goal to generate diverging executions of program paths. The key challenge of differential software testing is to simultaneously reason about multiple program paths, often across program variants, in an efficient way. Existing work in differential testing is often not (specifically) directed to reveal a different behavior or is limited to a subset of the search space. This PhD thesis proposes the concept of Hybrid Differential Software Testing (HyDiff) as a hybrid analysis technique to generate difference revealing inputs. HyDiff consists of two components that operate in a parallel setup: (1) a search-based technique that inexpensively generates inputs and (2) a systematic exploration technique to also exercise deeper program behaviors. HyDiff’s search-based component uses differential fuzzing directed by differential heuristics. HyDiff’s systematic exploration component is based on differential dynamic symbolic execution that allows to incorporate concrete inputs in its analysis. HyDiff is evaluated experimentally with applications specific for differential testing. The results show that HyDiff is effective in all considered categories and outperforms its components in isolation.
Bondarenko, A. I., M. O. Mittsel, and A. P. Kogushko. "Laboratory stand for research of the workflow in hydrostatic mechanical transmissions." Thesis, Vela Verlag, Germany, 2014. http://repository.kpi.kharkov.ua/handle/KhPI-Press/42212.
Повний текст джерелаIamratanakul, Dhanakorn. "Pre-actuation and post-actuation in control applications /." Thesis, Connect to this title online; UW restricted, 2007. http://hdl.handle.net/1773/9968.
Повний текст джерелаChembil, Palat Ramesh. "VT-STAR design and implementation of a test bed for differential space-time block coding and MIMO channel measurements." Thesis, Virginia Tech, 2002. http://hdl.handle.net/10919/35712.
Повний текст джерелаMaster of Science
Islam, Mohammad Tauhidul. "Palladium coated high-flux tubular membranes for hydrogen separation at high temperatures and differential pressures, and, Mathematical modeling of a fluidized bed reformer with oxygen input." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/mq24719.pdf.
Повний текст джерелаSouza, Iderval Silva de. "Geometria do desacoplamento e integração numérica de equações diferenciais não lineares implícitas." Universidade de São Paulo, 2006. http://www.teses.usp.br/teses/disponiveis/3/3139/tde-19042007-161721/.
Повний текст джерелаClassical methods for numerical integration of diferential algebraic equations (DAEs) can be formal in the literature. In this work, using a diferential geometric approach, a numerical method of integration of DAEs is established. This method is inspired in the decoupling theory of nonlinear explicit systems, when one considers that the outputs are algebraic constraints. The main result is the construction of an explicit system, whose solutions converge to the solutions of the DAE.
Pisár, Peter. "Metody návrhu aktivních kmitočtových filtrů na základě pasivního RLC prototypu." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-218107.
Повний текст джерелаMartin, André, Tom Petzold, Matthias Hackert-Oschätzchen, Gunnar Meichsner, and Andreas Schubert. "Experimental Derivation of Process Input Parameters for Electrochemical Machining with Differentially Switched Currents." IIF Institut für Industriekommunikation und Fachmedien GmbH, 2018. https://monarch.qucosa.de/id/qucosa%3A36081.
Повний текст джерелаGiri, Jeeten Krishna. "REGIONAL WAGE DIFFERENTIALS, INTRA-NATIONAL TRADE, AND INDUSTRY-LEVEL INTERNATIONAL TRADE, IN INDIA." OpenSIUC, 2018. https://opensiuc.lib.siu.edu/dissertations/1590.
Повний текст джерелаShah, Syed Suhail Mumtaz. "Differential responses of a Scottish landrace of barley (Bere) to a range of agricultural inputs in Orkney." Thesis, University of Aberdeen, 2011. http://digitool.abdn.ac.uk:80/webclient/DeliveryManager?pid=182246.
Повний текст джерелаHurley, Noel P. "Resource allocation and student achievement: A microlevel impact study of differential resource inputs on student achievement outcomes." Thesis, University of Ottawa (Canada), 1995. http://hdl.handle.net/10393/9724.
Повний текст джерелаGrifo, Anabela Dias Ramalho Vale Leitão. "Inputs and yield optimization on irrigated maize." Doctoral thesis, Universidade de Évora, 2016. http://hdl.handle.net/10174/18319.
Повний текст джерелаHrycík, Tomáš. "Porovnání použití přístrojových transformátorů a senzorů v aplikacích s ochranou REF 542plus." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2010. http://www.nusl.cz/ntk/nusl-218429.
Повний текст джерелаWang, Huei-Chi, and 王惠琪. "Design of Current Mode Operational Amplifier with Differential Input and Differential Output." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/90020224361357870789.
Повний текст джерела淡江大學
電機工程學系
85
In the last few decades, the analogue designers more thought about processing signal by current mode signal. As the current mode circuit compares with the voltage mode circuit, the former proves to be two conceptual advantages: higher frequency capabilities and larger dynamic range. And the architecture of current mode circuit form, it is more convenient and direct to copy or operate the signal than the voltage mode. Such as the switch current filter in the recently developing. In this thesis, a new CMOS current operational amplifier (COA) with fully differential input and differential output is proposed and analyzed. The amplifier is implemented from a differential current mirror input transimpedance stage followed by a differential output transconductance gain stage. A differential mode design technique is proposed and used in the feedback circuit. The simulation results of the new COA are based upon the 0.5um CMOS process and ±1.5V supply voltage. The new COA exhibits an open-loop differential gain of 51.71dB with the gain-bandwidth product 314MHz and a settling time of 14ns. To design VLSI circuit in the recent, the mix mode circuit design is the future trend in order to cooperate with the digital process. So the low voltage, and low power analogue circuit design is indispensable. Specially in the mobile personal communication system. So in this paper, we first analysis the basis current cell circuits, e.g. low voltage current mirror. And we will discuss the property of the circuit, as follows describe: (a) bandwidth improvement (b) parasitic capacitor effect improvement (c) unit step function time response (d) temperature stability discussion (e) bias circuit and dynamic range discussion In the last, the applications of the COA in processing current signals are proven to be the counterpart of the traditional voltage mode operational amplifier (VOA). The current integrator and the current Biquad filter show their duality with voltage integrator and Biquad. In the domain of filter design, COA is proven to be applicable to MOS-C current filter as well as SC voltage filter. Thus this COA can be used to process the signals on chip.
Thomas, Rachel Lee. "Time-Scaled Stochastic Input to Biochemical Reaction Networks." Diss., 2010. http://hdl.handle.net/10161/2443.
Повний текст джерелаBiochemical reaction networks with a sufficiently large number of molecules may be represented as systems of differential equations. Many networks receive inputs that fluctuate continuously in time. These networks may never settle down to a static equilibrium and are of great interest both mathematically and biologically. Biological systems receive inputs that vary on multiple time scales. Hormonal and neural inputs vary on a scale of seconds or minutes; inputs from meals and circadian rhythms vary on a scale of hours or days; and long term environmental changes (such as diet, disease, and pollution) vary on a scale of years. In this thesis, we consider the limiting behavior of networks in which the input is on a different time scale compared to the reaction kinetics within the network.
We prove analytic results of how the variance of reaction rates within a system compares to the variance of the input when the input is on a different time scale than the reaction kinetics within the network. We consider the behavior of simple chains, single species complex networks, reversible chains, and certain classes of non-linear systems with time-scaled stochastic input, as the input speeds up and slows down. In all cases, as the input fluctuates more and more quickly, the variance of species within the system approaches to zero. As the input fluctuates more and more slowly, the variance of the species approaches the variance of the input, up to a normalization factor.
Dissertation
Cheng, Shih-Tung, and 鄭世東. "High linearity CMOS transconductors with triode-region pseudo-differential input pair." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/57313678452286286431.
Повний текст джерела國立交通大學
電機學院通訊與網路科技產業專班
98
With the evolution of the fabrication technology, the supply voltage of the electric circuit systems has become lower and lower. Since portable electronic devices are getting very popular, it is the trend to lower power supply voltage in order to decrease power consumption. For digital circuits, when the power supply reduces, the power consumption would be lower while circuit performance stays the same. However, for analog circuits, the low voltage supply might not only bring the downgrade of circuit performance, but also cause failure of some basic circuit structures. It has attracted lots of attentions to design analog circuits to work under low voltage conditions. Two circuits have been proposed to improve the linearity of the transconductors working in the triode region. High transconductance tuning range, low voltage supply, and high linearity are all achieved in the design. The first circuit is designed by biasing input transistor pair in the triode region, in parallel with another input pair working in the weak inversion region, to cancel out the third order harmonic distortion. The power supply voltage is 1.2V and the circuit consumes 0.226mW. The third order harmonic distortion of -71.3dB is achieved with the input signal of 0.4Vpp. The transconductor fabricated by TSMC 0.18um CMOS 1P6M technology occupies the area of . The second transconductor also biases the input transistor pair in the triode region. In addition, high performance mobility compensation mechanism has been implemented. It has successfully suppressed the third order harmonic distortion by 22.4dB. The supply voltage is 1.8V and the circuit consumes 427uW. The third order harmonic distortion of -79dB is achieved with the input signal of 1.2Vpp. The transconductor fabricated by TSMC 0.18um CMOS technology occupies the area of .
Liu, Kun. "Discontinuous Galerkin Methods for Parabolic Partial Differential Equations with Random Input Data." Thesis, 2013. http://hdl.handle.net/1911/71989.
Повний текст джерелаYang, Jhang-yuan, and 楊掌淵. "Light Input Load High-Speed Differential D Flip-Flop Designs and Implementations." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/00640354014296222908.
Повний текст джерела國立雲林科技大學
電子與光電工程研究所碩士班
101
The internal voltage of recent digital integrated circuit has been gradually decreased, while its operating speed continuous to grow. This makes high speed operation and signal strength maintenance a great challenge to digital integrated circuit. The most frequently used component in synchronized digital integrated circuit is D-type flip-flop. It would be an important issue if D-type flip-flop is to be designed with low voltage, high speed and working robust circuit. The special characteristic of advanced circuits, such as USB, eSATA and HDMI is that they can operate in high speed while resisting noise. The other characteristic shared by these advanced circuits is that they all adopt common-mode noise-rejectoin digital differential circuit design. This study focused on the circuit design of differential D-type flip-flop, which is expected to replace traditional single-ended D-type flip-flop in performing accurate logic computation in high-noise, high-speed and low-voltage environment. From digital logic circuit design concept we can learn that, one of the characteristics of high-speed circuit is its extremely small input capacitance. This thesis started with the design concept of minimizing load capacitance, and proposed several high-speed digital differential latch circuits based on DCVSL circuit style, according to which a differential D-type flip-flop was implemented. Only one NMOS input capacitance being triggered on both inputs of the bit line and the differential master-servant latch circuits, which equipped it with the characteristic of high speed. The study also explored the operation speed of MOS transistor under different threshold voltage in a same process technology. To compare and examine the low input capacitance differential and high speed D-type flip-flops proposed in this thesis, we designed a feedback-driven and a non-feedback driven frequency divider circuit to observe their high-speed operating performance. In 0.18um CMOS 1.8V process, eighteen D-type flip-flop circuits have been implemented with high-speed prescaler for real chip verifications. After simulation, validation and comparison, the fastest combination was found, which was the Normal VT differential NMOS diode feedback-driven type circuit. The circuit can achieve an operating frequency of 3.25GHz, which is 6% higher than traditional differential D-type flip-flop. The power consumption of the circuit was only 0.43mW under 3.25GHz in a layout area of 960um x 840um. After simulating and comparing in 90nm CMOS 1V process, we found that the combination with the fastest operating speed is the circuit configuration of PMOS and NMOS Low VT single-ended nmos diode non-feedback-driven type, for its operating frequency can achieve 4.5GHz, which is 7% higher than traditional differential D-type flip-flop. Its power consumption was only 86uW under 4.5GHz in a layout area of 463.6um x 323um.
Hung, Yi-Ting, and 洪亦廷. "The Design of Differential Multi-input XOR Circuit for High-Performance Finite-Field Multiplier Applications." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/48195444536300008378.
Повний текст джерела雲林科技大學
電子與資訊工程研究所
97
The thesis proposes a new high-performance low-cost multi-input exclusive OR gate. This new circuit adopts the known Differential Cascode Voltage Switch Pass Gate (DCVSPG) architecture which was originally modified from Differential Cascode Voltage Switch (DCVS) and combined with pass transistor gates to eliminate the floating node. In thesis, some well known multi-input XOR gates were studied and analyzed, and the results show that our new proposed XOR has lower power, shorter delay, less layout area and easier design features than the traditional one. Under a TSMC 0.18µm 1.8V process technology, our new 4-input XOR gate reaches 1GHz operational speed. When compare with the known fastest traditional DCVSPG XOR, our new circuit performs even faster than 25%. The total transistor area is reduced by 29% to 93% when compare with the traditional C-CMOS at 150MHz, PTL CMOS at 350MHz, Pseudo NMOS at 800MHz, respectively. Therefore, our new multi-input XOR is the smallest one among the traditional circuits. For verifying the effectiveness of our new XOR, a reordered normal basis finite field multiplier (FFM) is chosen being a test vehicle. Before the circuit is implemented, four basic architectures of FFM have been surveyed. Inspired by their circuit topology, we then proposed a new compact full-parallel reordered normal basis FFM, and it reduced about 20% gate count. The new compact FFM implementation results, using TSMC 0.18µm 1.8V process technology, show that our new 4-input XOR has less 7% transistor count than the known traditional smallest two-stage 2-input DCVSPG XOR gates. The total power consumption of new FFM has only 306mW at 1GHz operational speed.
Webster, Clayton G. "Sparse grid stochastic collocation techniques for the numerical solution of partial differential equations with random input data." 2007. http://etd.lib.fsu.edu/theses/available/etd-03302007-154630.
Повний текст джерелаAdvisor: Max Gunzburger, Florida State University, College of Arts and Sciences, Dept. of Mathematics and School of Computational Science. Title and description from dissertation home page (viewed July 5, 2007). Document formatted into pages; contains xv, 160 pages. Includes bibliographical references.
Huang, Chun-Jen, and 黃俊仁. "Design and Implementation of Low Voltage Rail-to-Rail CMOS Operational Amplifier Using Dual Differential Input Pairs." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/98438983359573886137.
Повний текст джерела輔仁大學
電子工程學系
92
In this work, we present three low-voltage CMOS amplifiers. The first amplifier with dual P-channel differential pairs, that combines a P-channel differential input pair and a level-shift P-channel differential input pair, obtain rail-to-rail signaling. Under 1 volts supply voltage, the input common mode range is 0.15~0.93V. The second amplifier with dual P-channel differential pairs and current driven bulk (C.D.B.)skill, that apply C.D.B. skill to reduce Vt of differential pairs , obtain rail-to-rail signaling. Under 1 volts supply voltage, the input common mode range is 0.02~0.98V. The third amplifier with dual N-channel differential pairs, that combines a N-channel differential input pair and a level-shift N-channel differential input pair, obtain rail-to-rail signaling. Under 1 volts supply voltage, the input common mode range is 0.01~0.97V. These 3 amplifiers are fabricated by TSMC 0.35um. The total chip size is 1476X927um2.
Chuan-YuSun and 孫全佑. "A Fifth-Order Butterworth OTA-C Lowpass Filter with Multiple-Output Differential-Input OTA for ECG Acquisition." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/78554n.
Повний текст джерела國立成功大學
電機工程學系
105
This study proposes a fifth-order Butterworth operational transconductance amplifier-C (OTA-C) low-pass filter (LPF) with multiple-output differential-input (MODI) OTA structure and metal–insulator–metal capacitors for electrocardiography applications. The current division technology is used as an alternative output pair to provide multiple outputs and achieve high linearity. This technique reduces the number of OTAs of the fifth-order LPF from 11 to 6 as compared with the conventional structure. The design issue of linearity and noise are also considered in the implementation of LPF. In order to achieve a filter with large-time constant and low noise, linearized MODI OTA structures with reduced transconductance and impedance scaler circuits for capacitors are used. OTA-based circuits is operated in the subthreshold region and supply voltage of 1V to conserve power consumption due to the battery life of the portable device and the critical area of the digital processor required in the circuit. The proposed filter is fabricated in a 0.18 µm complementary metal–oxide–semiconductor technology with a core area of 0.135 mm2. The experimental results show that the dynamic range (DR) is 58.44 dB, achieved a total harmonic distortion (THD) of -59 dB under a bandwidth of 250 Hz and input voltage of 100 mV at a 1 V supply voltage. The total power dissipation is 390 nW.
李三益. "A fifth-order gm-C filter with large differential input signals and wide common-mode voltage ranges." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/nf6jz7.
Повний текст джерела國立交通大學
電信工程系所
94
This thesis presents a low-voltage CMOS fifth-order elliptic low-pass gm-C filter with large differential input swings and wide common-mode ranges. The Operational Transconductance Amplifier (OTA) is a low-voltage CMOS voltage-to-current (V-I) converter. The basic OTA cell with NMOS-inputs is connected in parallel with its counterpart PMOS-input OTA circuit, in conjunction with NMOS and PMOS output current mirrors, to achieve large input signal and common-mode voltage ranges. For the gm-C filter, additional tuning circuitry is required in order to compensate the process and temperature variation.. In this OTA design, two frequency tuning circuits are utilized, respectively, to adjust the control voltage of NMOS-input and PMOS-input OTAs so as to fix the filter cutoff frequency and also maintain the equivalence between the two transconductance of NMOS-input and PMOS-input OTAs. The gm-C filter operates with supply voltage of 1.8V, has cutoff frequency of 1.6MHz to 2.4MHz, dissipates 0.75mW power, and has large differential input signals and wide common-mode voltage ranges of ±0.7V.
Chia, Wee Lee Mechanical & Manufacturing Engineering Faculty of Engineering UNSW. "Multiple-Input Multiple-Output (MIMO) blind system identification for operational modal analysis using the Mean Differential Cepstrum (MDC)." 2007. http://handle.unsw.edu.au/1959.4/40738.
Повний текст джерелаOmoumi, Kevin Christopher. "Design of a High-Voltage, Differential Drive Bradbury-Nielsen Gate Amplifier with Ultra-High Slew Rate and Input Isolation." 2011. http://trace.tennessee.edu/utk_gradthes/901.
Повний текст джерелаCHEN, YUN-SHENG, and 陳雲昇. "Design consideration of multi-differential-input op-amp and its applications to low-offset and low-noise op-amps." Thesis, 1988. http://ndltd.ncl.edu.tw/handle/06214665157493990801.
Повний текст джерелаWu, Min-Kang, and 吳旻剛. "A Study of Channel Capacity of Optimal Multiple-Input Multiple-Output System Antenna Element Spacing by Applying Dynamic Differential Evolution." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/81456597174321881780.
Повний текст джерела淡江大學
電機工程學系碩士班
98
The geometrical shape of antenna arrays for maximizing the average channel capacity of the system in a multiple-input multiple-output (MIMO) link is investigated. The optimum element spacing of the transmitting antenna is also included. In this paper, channel capacity of multiple-input multiple-output narrowband system in indoor wireless channels at 5-GHz U-NII (Unlicensed-National Information Infrastructure) bands is calculated. An optimization procedure for the element spacing of the antenna transmitter in narrowband wireless communication system is presented. The frequency responses of different transceiver antenna element spacing are computed by shooting and bouncing ray/image (SBR/Image) techniques, and the channel frequency response is further used to calculate corresponding channel capacity. The transmitter is in the center of the indoor environment and the receivers are uniform intervals distribution, which 150 measurements with 0.25m intervals in the whole wooden table in indoor environment. And the inter-element separation of Receiver antennas (Rx) is 0.03m. Linear shaped array, L shaped array, T shaped array and rectangular shaped array geometries with non-uniform inter-element spacing are investigated for both line-of-sight (LOS) and non-LOS (NLOS) scenarios. The optimal element spacing of antenna for maximizing the channel capacity is searched by dynamic differential evolution (DDE). Numerical results have shown that our proposed method is effective for increasing average channel capacity. It is also found that L shaped array has the highest channel capacity and the improvement ratio for rectangular shaped array is largest.
Hsieh, Cheng-Ku, and 謝政谷. "The 10-bit 20-MS/s Fully Differential SAR ADC Chip Design Using Positive Input Signal Tracking DAC Switching Method." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/62182120701248612696.
Повний текст джерела國立臺灣科技大學
電子工程系
102
This paper presents a 1.8-V 10-bit 20MS/s successive approximation register (SAR) analog-to-digital converter (ADC) implemented in the TSMC 0.18-um CMOS process. By applying a single-sided switching method that reduces DAC switching energy, the proposed SAR ADC achieves lower power consumption. In order to avoid using an external high frequency clock to drive the ADC, asynchronous control logic is used. A pre-amplifier based comparator reduces the kickback noise from the logic circuit. A bootstrapped switch increases the sample linearity of the ADC. The SAR ADCs were simulated by HSPICE and SpectreRF. The 10-bit ADC was taped out by TSMC. The measured results for differential and integral nonlinearity of the 10-bit ADC are within 1.2/-0.4 LSB (Least Significant Bit) and -1.54~1.1LSB respectively at full sampling rate. The measurement results show an effective number of bits (ENOB) of 8.85-bits with a sampling frequency of 20 MHz at a 10 KHz input frequency. The chip area, including pads, is 0.57 mm2. Power consumption of this ADC is 910μW with a 1.8 V supply voltage.
Silva, Cristiana Malcata Antunes Alves da. "Aquisição do complemento direto preposicionado em crianças bilingues português europeu/espanhol ibérico." Master's thesis, 2017. http://hdl.handle.net/10362/22136.
Повний текст джерелаRegarding monolingual children, the acquisition of Differential Object Marking (DOM) occurs before the age of three (Rodríguez-Mondoñedo 2008). However, few studies have addressed the acquisition of this phenomenon in bilingual children. The present study focuses on the acquisition of DOM in European Portuguese-Iberian Spanish bilingual children living in Portugal. The participants performance was tested through an elicited production test that considered the animacy variable in this structure taking into account for the Aissen scale (2003). The fact that it envolves interface properties which may make it harder to acquire, was also considered, as was the relevance of certain input aspects such as the parents’ native language which may influence the acquisition of this structure. The results showed that the children under 5 years old do not yet ully master the DOM properties investigated, confirming the complexity of the phenomenon towards the interfaces involved. The scale of animacy seems relevant during the process of acquisition as 5-year-old children already appear to distinguish human and nonhuman animate objects. The children whose parents have both Spanish as their native language and communicate with the child in Spanish have better results than those parents have different native languages.
Le, Gratiet Keyrian Louis. "Differential distribution of co-transmitted cholinergic and GABAergic synaptic inputs onto substantia nigra dopaminergic neurons." Thesis, 2021. http://hdl.handle.net/1828/12887.
Повний текст джерелаGraduate
2022-04-12
Chen, Yung-Hung, and 陳永鴻. "Noise Improvement of Low Frequency and Low Power Dissipation Rail-To-Rail Differential Inpup Operational Amplifier IC Design." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/85124772732420524510.
Повний текст джерела國立清華大學
電子工程研究所
97
In this work, TSMC SiGe0.35μm technology is used to design a low noise analog integrated circuit. This work is called 「Noise Improvement of Low-frequency , Low-power Rail-To-Rail Differential Input Op-Amp」, and is simulated by H-SPICE. It uses BiCMOS technology replacing CMOS technology in the differential input stage to improve noise in Op-Amp circuits. Through simulation and comparison, the results show that noise in the BiCMOS rail-to-rail differential input Op-Amp is better than noise in CMOS rail-to-rail differential input Op-Amp. Finally, rail-to-rail instrumentation Amps are integrated by these two kinds of Op-Amp, and then they are simulated and compared again. The simulation and comparison results show that noise is significantly improved when using BiCMOS rail-to-rail differential input Op-Amps. In addition, this paper mentions the designed rail-to-rail instrumentation Amps could be applied as ECG Amplifier in the medical electronic. This paper also introduces what is ECG and ECG related electronics.
Rajan, G. Susinder. "Low Decoding Complexity Space-Time Block Codes For Point To Point MIMO Systems And Relay Networks." Thesis, 2008. http://hdl.handle.net/2005/742.
Повний текст джерелаTong, Yong Sheng, and 童詠聖. "CRF receptors regulate CART peptides to differentially modulate firing rates and synaptic inputs of DMV neurons innervating stomach and cecum in rats." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/wwser4.
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