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Статті в журналах з теми "Injection locked VCO":

1

Jiang, Longkai, Changjun Liu, Shaoyue Wang, Xueman Sun, and Jie Wu. "A Weak Reverse Coupling Cascaded Injection-Locked VCO Array for Beam Scanning in Phased Arrays." Electronics 12, no. 10 (May 19, 2023): 2301. http://dx.doi.org/10.3390/electronics12102301.

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We propose a novel phase shifter for beam scanning in phased arrays using a cascaded injection-locked voltage-controlled oscillator (VCO) array with weak reverse coupling. We analyze the phase noise performance of a multi-signal injection-locked oscillator and establish a phase output model for the array, studying the effects of forward and reverse injection ratios on phase and phase noise at each stage. By decoupling and cascade locking VCO array elements through controlled injection ratios, we design a 2.45 GHz one-dimensional linear array of four VCOs that achieves a continuous fixed phase difference between adjacent oscillators from −180∘ to 180∘, enabling electronic tuning of phase shift and beam scanning. Finally, the beam scanning of the antenna array is realized by using the VCO array. Our theoretical and experimental results demonstrate the effectiveness of our proposed approach.
2

TSURU, Masaomi, Kengo KAWASAKI, Koji TSUTSUMI, and Eiji TANIGUCHI. "Adaptively Phase-Shift Controlled Self-Injection Locked VCO." IEICE Transactions on Electronics E98.C, no. 7 (2015): 677–84. http://dx.doi.org/10.1587/transele.e98.c.677.

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3

JANG, S. L., C. W. CHANG, S. C. WU, C. F. LEE, L. y. TSAI, and J. F. HUANG. "Quadrature Hartley VCO and Injection-Locked Frequency Divider." IEICE Transactions on Electronics E91-C, no. 8 (August 1, 2008): 1371–74. http://dx.doi.org/10.1093/ietele/e91-c.8.1371.

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4

Hao, Yuan, Li Cai Wang, Qing Lei Du, and Fei Cheng Wang. "Theory and Experiments of Injection-Locked Oscillator." Applied Mechanics and Materials 602-605 (August 2014): 2522–25. http://dx.doi.org/10.4028/www.scientific.net/amm.602-605.2522.

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Injection-locking technique is receiving increasing interest in industrial applications, which is especially suitable for smart antenna array, but relative experiments are complicated. The article focuses on the theory and experiment of the technique. Firstly, section 2 reviews the theory of injection-locking technique, and summarizes two useful conclusions on injection-locking bandwidth and phase difference adjusting bound of the phenomena. Secondly, section 3 describes experiments using commercial microwave integrated circuit (MMIC) voltage controlled oscillator (VCO), which is reduces the experimental conditions. Experiments results perform very well.
5

Lee, Shuenn-Yuh, Liang-Hung Wang, and Yu-Heng Lin. "A CMOS Quadrature VCO With Subharmonic and Injection-Locked Techniques." IEEE Transactions on Circuits and Systems II: Express Briefs 57, no. 11 (November 2010): 843–47. http://dx.doi.org/10.1109/tcsii.2010.2082990.

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6

Xue, Quan. "A subharmonically injection-locked dual-gate FET VCO frequency synthesizer." Microwave and Optical Technology Letters 26, no. 5 (2000): 294–96. http://dx.doi.org/10.1002/1098-2760(20000905)26:5<294::aid-mop6>3.0.co;2-z.

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7

Jang, S. L., Y. H. Chuang, S. H. Lee, L. R. Chi, and C. F. Lee. "An Integrated 5–2.5-GHz Direct-Injection Locked Quadrature $LC$ VCO." IEEE Microwave and Wireless Components Letters 17, no. 2 (February 2007): 142–44. http://dx.doi.org/10.1109/lmwc.2006.890343.

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8

Jang, Sheng-Lyang, S. S. Huang, Chien-Feng Lee, and M. H. Juang. "CMOS Quadrature VCO Implemented With Two First-Harmonic Injection-Locked Oscillators." IEEE Microwave and Wireless Components Letters 18, no. 10 (October 2008): 695–97. http://dx.doi.org/10.1109/lmwc.2008.2003476.

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9

Jang, S. L., S. H. Huang, C. C. Liu, and M. H. Juang. "CMOS Colpitts Quadrature VCO Using the Body Injection-Locked Coupling Technique." IEEE Microwave and Wireless Components Letters 19, no. 4 (April 2009): 230–32. http://dx.doi.org/10.1109/lmwc.2009.2015506.

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10

Jang, Sheng-Lyang, Cheng-Chen Liu, Shin-Hsin Huang, and Miin-Horng Juang. "Quadrature cross-coupled VCO implemented with body injection-locked frequency dividers." Microwave and Optical Technology Letters 51, no. 8 (May 13, 2009): 1918–21. http://dx.doi.org/10.1002/mop.24495.

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Дисертації з теми "Injection locked VCO":

1

Shin, Dongseok. "Frequency Locking Techniques Based on Envelope Detection for Injection-Locked Signal Sources." Diss., Virginia Tech, 2017. http://hdl.handle.net/10919/86673.

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Signal generation at high frequency has become increasingly important in numerous wireline and wireless applications. In many gigahertz and millimeter-wave frequency ranges, conventional frequency generation techniques have encountered several design challenges in terms of frequency tuning range, phase noise, and power consumption. Recently, injection locking has been a popular technique to solve these design challenges for frequency generation. However, the narrow locking range of the injection locking techniques limits their use. Furthermore, they suffer from significant reference spur issues. This dissertation presents novel frequency generation techniques based on envelope detection for low-phase-noise signal generation using injection-locked frequency multipliers (ILFMs). Several calibration techniques using envelope detection are introduced to solve conventional problems in injection locking. The proposed topologies are demonstrated with 0.13um CMOS technology for the following injection-locked frequency generators. First, a mixed-mode injection-frequency locked loop (IFLL) is presented for calibrating locking range and phase noise of an injection-locked oscillator (ILO). The IFLL autonomously tracks the injection frequency by processing the AM modulated envelope signal bearing a frequency difference between injection frequency and ILO free-running frequency in digital feedback. Second, a quadrature injection-locked frequency tripler using third-harmonic phase shifters is proposed. Two capacitively-degenerated differential pairs are utilized for quadrature injection signals, thereby increasing injection-locking range and reducing phase error. Next, an injection-locked clock multiplier using an envelope-based frequency tracking loop is presented for a low phase noise signal and low reference spur. In the proposed technique, an envelope detector constantly monitors the VCO's output waveform distortion caused by frequency difference between the VCO frequency and reference frequency. Therefore, the proposed techniques can compensate for frequency variation of the VCO due to PVT variations. Finally, this dissertation presents a subharmonically injection-locked PLL (SILPLL), which is cascaded with a quadrature ILO. The proposed SILPLL adopts an envelope-detection based injection-timing calibration for synchronous reference pulse injection into a VCO. With one of the largest frequency division ratios (N=80) reported so far, the SILPLL can achieve low RMS jitter and reference spur.
Ph. D.
2

Muhammad, Nuraddeen Ado. "Analysis and design of an innovative 19.5 GHz active phase-shifter architecture, implemented in a 0.13 μm BiCMOS SiGe process, for beamforming in 5G applications". Electronic Thesis or Diss., Poitiers, 2024. http://www.theses.fr/2024POIT2257.

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Pour différentes raisons, la 5G domine actuellement l'actualité technologique. Les capacités de la 5G en termes de largeur de bande et de temps réel constitues un énorme potentiel sociétal en permettant pléthore d'applications nouvelles et inattendues. En effet, la bande de fréquence des ondes millimétriques se caractérise par une largeur de bande disponible qui peut prendre en charge des systèmes sans fil à haut débit pour les futurs systèmes de radiocommunication, y compris les systèmes cellulaires de cinquième génération et au-delà. Les fréquences d'exploitation des ondes millimétriques nécessitent généralement une plus grande ouverture d'antenne pour améliorer le bilan de liaison. Ces antennes se présentent généralement sous la forme de réseaux phasés, permettant la formation de faisceaux. Dans ce contexte, ce travail présente la conception et la mise en œuvre d'un déphaseur actif à 19,5 GHz pour la formation de faisceaux. Le circuit proposé est basé sur une architecture originale utilisant un oscillateur commandé en tension verrouillé par injection (ILVCO en Anglais) associé à un filtre polyphase suivi d'un circuit de sélection de phase et de son signe. La phase souhaitée dans la plage de ± 45° est synthétisée avec le circuit proposé en modifiant la tension de commande Vcntr de l’ILVCO pour un réglage fin et en modifiant les deux signaux de commandes du sélecteur de phase et de signe (S0, S2) pour un réglage grossier, ce qui engendre une variation de phase linéaire de 360°. D'après les résultats de la simulation post-layout, la plage de réglage de la fréquence d’oscillation libre du VCO varie de 17,89 GHz à 20,16 GHz. En outre, avec une puissance injectée de -8,5 dBm et une fréquence de 19,5 GHz, le déphaseur proposé consomme 20,47 mA sous une tension d'alimentation de 1,3 V. De plus, la puissance de sortie moyenne sur 50 Ω est de -15,58 dBm. Le circuit complet a une taille de 1,58 mm2, y compris les pads, et il est intégré sur un process BiCMOS SiGe:C 0,13 μm. Enfin, les résultats obtenus montrent que le déphaseur actif proposé s’avère un candidat potentiel pour les systèmes à réseau phasé utilisés pour la formation de faisceaux dans les applications 5G
For good reasons, 5G dominates technological news. The high-bandwidth and real-time capabilities of 5G have huge societal potential by enabling a plethora of new and unanticipated application cases. Indeed, the millimeter-wave frequency band is characterized by an available bandwidth that can support high-speed wireless systems for future radio communications systems, including 5th Generation cellular systems and beyond. The frequencies of operation at mm-wave generally requires larger antenna aperture to improve the channel budget at useful distances. These antennas are usually in the form of phased arrays, allowing beamforming to be performed. This work presents the design and implementation of a 19.5 GHz active phase shifter for beamforming in 5G applications. The proposed circuit is based on an original architecture using an injection-locked voltage-controlled oscillator (ILVCO) associated with a polyphase filter followed by a phase selection circuit and its sign. The desired phase in the range of ± 45° is synthesised with the proposed circuit by altering the control voltage Vcntr of an ILVCO for fine-tuning and modifying the two control signals of phase and sign selectors (S0, S2) for coarse tuning, resulting in a 360° linear phase variation. According to the post-layout simulation results, the frequency tuning range of the VCO varies from 17.89 GHz to 20.16 GHz in free-running mode. In addition, with an injected power of -8.5 dBm and a frequency of 19.5 GHz, the proposed phase shifter draws 20.47 mA from a 1.3 V supply voltage. Furthermore, the mean output power on 50 Ω load is found to be -15.58 dBm. The whole circuit has a chip size of 1.58 mm2 including the pads and it is integrated in a BiCMOS SiGe:C 0.13 μm process. Finally, the obtained results justify that the proposed active phase shifter is a relevant design for phased-array systems used for beamforming in 5G applications
3

Liu, Cheng-Chen, and 劉丞斌. "Quadrature Injection-Locked Frequency Divider and Novel Self-Injection Eight-phase VCO." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/66480860503550621292.

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Анотація:
碩士
國立臺灣科技大學
電子工程系
96
Chapter 4 in this thesis presents a new divide-by-2 and -4 injection-locked frequency divider (ILFD). The ILFD consists of a new 3.5 GHz quadrature voltage controlled oscillator (QVCO) and two NMOS switches, which are in parallel with the QVCO resonators for signal injection. The proposed CMOS ILFD has been implemented with the TSMC 0.18-μm CMOS technology and the core power consumption is 10.95 mW at the supply voltage of 1.5 V. The free-running frequency of the QILFD is tunable from 3.02 GHz to 3.53 GHz. At the input power of 0 dBm, the total divide-by-2 locking range is from 5.96 GHz to 7.68 GHz as the tuning voltage is varied from 0 V to 1.5 V. The phase noise of the locked output spectrum is lower than that of free running ILFD in the 2 mode. The phase deviation of quadrature output is about 0.14o . Chapter 5 presents a new technique for designing multi-phase VCOs, which were implemented in the standard TSMC 0.35 μm SiGe 3P3M BiCMOS process. The quadrature voltage-controlled oscillator (QVCO) consists of two direct- injection locked frequency dividers (ILFDs) with a tail MOSFET. The 2nd harmonic frequency component at the drain node of tail transistor in one ILFD is injected to the gate of injection MOSFET in the other ILFD to couple the two independent ILFDs. The eight- phase VCO is also designed with similar technique to couple four differential VCOs. At the supply voltage of 3.0 V, the output phase noise of the QVCO is -118.22 dBc/Hz at 1MHz offset frequency from the carrier frequency of 2.28 GHz, and the figure of merit is -173.25 dBc/Hz. At the supply voltage of 3.0 V, the total power consumption is 14.4 mW. At the supply voltage of 3.0 V, the output phase noise of the eight-phase VCO is -116.14 dBc/Hz at 1MHz offset frequency from the carrier frequency of 2.92 GHz, and the figure of merit is -171.3 dBc/Hz. Chapter 6 presents an integrated VCO injection-locked frequency divider (ILFD) circuit. The divide-by-4 injection locked frequency divider consists of a 2.8GHz nMOS-core VCO with a direct-injection MOSFET and the VCO is a 5.6GHz cross-coupled p-core CMOS VCO. The ILFD divides down the injection signal frequency by 4, while the VCO outputs a second harmonic using the tail inductor, and the harmonic is applied to the gate of injection in the ILFD. The ILFD outputs a signal with half of the fundamental frequency while the VCO outputs a signal with the fundamental frequency. The circuit is implemented in a standard 0.18-μm CMOS process. At the supply voltage of 1.5V, the ILFD can be tunable from 2.772GHZ to 2.928GHZ with a corresponding VCO frequency from 5.529GHZ~5.848GHZ.
4

Kalusalingam, Shriram. "Superharmonic Injection Locked Quadrature LC VCO Using Current Recycling Architecture." 2010. http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8602.

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Quadrature LO signal is a key element in many of the RF transceivers which tend to dominate today’s wireless communication technology. The design of a quadrature LC VCO with better phase noise and lower power consumption forms the core of this work. This thesis investigates a coupling mechanism to implement a quadrature voltage controlled oscillator using indirect injection method. The coupling network in this QVCO couples the two LC cores with their super-harmonic and it recycles its bias current back into the LC tank such that the power consumed by the coupling network is insignificant. This recycled current enables the oscillator to achieve higher amplitude of oscillation for the same power consumption compared to conventional design, hence assuring better phase noise. Mathematical analysis has been done to study the mechanism of quadrature operation and mismatch effects of devices on the quadrature phase error of the proposed QVCO. The proposed quadrature LC VCO is designed in TSMC 0.18 μm technology. It is tunable from 2.61 GHz - 2.85 GHz with sensitivity of 240 MHz/V. Its worst case phase noise is -120 dBc/Hz at 1 MHz offset. The total layout area is 1.41 mm^2 and the QVCO core totally draws 3 mA current from 1.8 V supply.
5

Yang, Su-Jhen, and 楊肅振. "Design of 2.45GHz Passive RFID Transponder with Injection-Locked VCO." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/51902385810370503579.

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Анотація:
碩士
國立暨南國際大學
電機工程學系
98
In this thesis, a 2.45GHz passive RFID transponder with injection-locked VCO is presented. The RFID transponder contains five parts: the RF-to-DC converter, the mode selector, the injection-locked voltage-controlled oscillator(ILO), the digital control circuit and the digital modulator. The injection-locked VCO uses direct-injection to lock at 2.45GHz with a locking range of 206MHz for a 2.45GHz 250mV incident signal. The chip contains a 128 bits ROM and the data rate is 153Mb/s. The chip designed is using TSMC 0.18 mm 1P6M CMOS process provided by Chip Implementation Center(CIC). The chip area is 479μm × 627μm. The chip works at 1V with 3.82mW power consumption.
6

Chiu, Yao-Ting, and 邱耀庭. "Implementation of CMOS Quadrature VCO and Clapp Injection-Locked Frequency Divider." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/buu6n3.

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Анотація:
碩士
國立臺灣科技大學
電子工程系
99
In wireless communication system, frequency synthesizers are used to implement the frequency up/down converting of signal. In a frequency synthesizer, voltage-controlled oscillator (VCO) and divider are the key blocks. For VCOs, low phase-noise output is required to avoid corrupting the mixer-converted signal by close interfering tones. The frequency of output signal of VCO is divided down to the level of reference signal, and is compared with reference signal by a phase frequency detector (PFD) to adjust the output of VCO. Therefore the dividers must have the ability of high frequency operation. Because of wireless application, both of them should operate at low power consumption. This thesis proposes VCO ,QVCO and frequency dividers by 2. A Cross-Coupled Complementary Colpitts CMOS Tuned with Gated MOSFET Varactors, CMOS Quadrature VCO Using the Injection MOSFET Coupling, A Wide-locking Range Differential Clapp Injection-Locked Frequency Divider .The above circuits are fabricated in the TSMC 0.18 μm CMOS process. Another one is a Differential Clapp ILFD implemented in the UMC 90 nm process. Firstly, MOSFET Body adjust the bias voltage point has been used to design a voltage-controlled oscillator (VCO), which consists of n-core and p-core VCOs. The oscillating frequency of the VCO can be tuned from 5.88 GHz to 6.74 GHz, while the tuning voltage varies from 0.1 V to 2 V. The phase noise of the oscillation frequency 6.38 GHz is -121.56 dBc/Hz at 1 MHz frequency offset. Secondly, The LC-tank QVCO consists of two first-harmonic injection-locked oscillators (ILOs), The outputs of one ILO are injected to the gates of the MOS transistors on the other ILO and vice versa so as to force the two ILOs operate in quadrature. The oscillating frequency of the QVCO can be tuned from 5.44 GHz to 5.95 GHz, while the tuning voltage varies from 0.2 V to 2 V. The phase noise of the oscillation frequency 5.91 GHz is -121.52 dBc/Hz at 1 MHz frequency offset. Finally, The designed circuit topology is an all nMOS LC-tank Clapp ILFD using a series-tuned resonator.In this circuit,we will use an NMOSFET device used as signal injection. At the supply voltage of 1.1 V. Tuning range is about 1.916 GHz, from 20.247 to 18.331 GHz, while the control voltage was tuned from 0 to 1.0 V. The operation range is about 6.6 GHz, from 35.9 GHz to 42.5 GHz.
7

Chiu, Chung-Ching, and 邱仲慶. "The Study of Differential Complementary Colpitts VCO and Injection Locked Frequency Divider." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/44bsb8.

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Анотація:
碩士
國立臺灣科技大學
電子工程系
94
ABSTRACT This thesis is mainly composed of two topics. First, we present a 0.35-μm CMOS frequency divider realized with a ring oscillator and a direct injection-locking technique. The divide-by-2 FD circuit consists of a 2-stage differential CMOS ring oscillator with n-MOS switches directly coupled to its differential outputs, the measured phase noise of the divide-by-2 divider is -98dBc/Hz at 1MHz offset from the free running frequency of 939MHz. The low-voltage CMOS divide-by-2 FD has been implemented with the TSMC 0.35 μm CMOS technology and the power consumption is 27 mW at the supply voltage of 3.3 V. At the input power of -5dbm, the divider-by-2 FD can function properly with about 1640MHz locking range from 1.28GHz to 2.92GHz, featuring a 87% locking range. And finally this thesis presents a new differential CMOS voltage controlled oscillator (VCO). The topology of the proposed differential VCO is a combination of Colpitts VCO and cross-coupled VCO. A symmetric transformer and differential differentially tuned MOS varactors are used to reduce phase noise. The VCO has been fabricated with the 0.18-μm CMOS process. At the 1.2-V supply voltage, the output frequency of VCO is from 5.99GHz to 6.43GHz with 441MHz tuning range and a phase noise of -118.5dBc/Hz at a 1MHz offset from the center frequency of 6.43GHz. Its core current consumption is 2.8 mA and the core power consumption is 3.36mW. The total power consumption of this VCO is 9.12mW. The figure of merit (FoM) of this differential VCO is -189.4 dBc.
8

li-Jen, Chi, and 錡利仁. "A Study of A 3D Helical Inductors Low Voltage VCO and A 5/2.5G Injection Locked Quadrature VCO." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/27pu9b.

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Анотація:
碩士
國立臺灣科技大學
電子工程系
94
This thesis is mainly composed of two topics, the first one is the 2.4-GHz low-voltage voltage controlled oscillator (VCO) with 3D helical inductors. The LC resonator consists of two tapped 3D helical inductors and varactors. The balanced VCO has two differential outputs and the frequency is tuned by varactors. It effectively makes use of 3D helical inductors to reduce the area of the whole chip, and to decrease the phase noise by center tapped inductors. The second one is the 5/2.5GHz injection locked quadrature VCO circuit, using a 5GHz Colpitts VCO to inject signals into two complementary type CMOS VCOs to produce the quadrature outputs. It makes use of PMOS to reduce flicker noise in order to get better phase noise.
9

Tsai, Meng-Hsiu, and 蔡孟修. "Microwave/Millimeter-wave VCO with Wide Tuning Range and Subharmonic Injection-Locked Oscillators." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/39604299045227622427.

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Анотація:
碩士
國立中央大學
電機工程研究所
98
The communication circuits applied in microwave and millimeter-wave frequency ranges have being gradually popularized in our life. Among the circuits, the oscillator constitutes an important circuit in the communication system. The injection-locked oscillator can improves the phase noise of the output signal by means of additionally injecting signals. This thesis explores the process and principle of the injection-locked oscillator and the deductions on the injection-locked oscillator models based on the relevant literatures. This thesis is mainly divided into two parts. In the first part, it explores how to make voltage-controlled oscillator at K-band by using SiGe BiCMOS technology and ADS simulation software. The variable capacitor is implemented by connecting the heterojunction bipolar transistor (HBT) and the metal-oxide-semiconductor field-effect transistor (MOSFET) in parallel.Thus, this oscillator shows a wide tuning range. The adjustable frequency range is from16.5 GHz to 19.85 GHz. In the second part of thesis, 50 GHz and 75 GHz subharmonic injection-locked oscillators are designed and manufactured in BiFET and GaAs pHEMT technologies. The measured oscillator shows low phase noise, wide-band locking range, low power consumption and high output power. Finally, this thesis explores how to use voltage-controlled oscillator to realize the modulation for the frequency-shift keying (FSK) signals and to demonstrate the demodulating the FSK signals using the injection-locked oscillator.
10

Li, Guan-Zhang, and 李冠樟. "Divide-by-5 and 8 Injection-Locked Frequency Dividers and GaN dual LC Resonator VCO." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/v6vq8t.

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Анотація:
碩士
國立臺灣科技大學
電子工程系
106
In the RF transceiver, PLL is very important, PLL components include Phase Frequency Detector (PFD), Charge Pump (CP), Loop Filter (LF), Voltage Controlled Oscillator (VCO), and Frequency Divider (FD). The most important characteristics of divider performance are low-power, low phase noise, wide locking range. This thesis presents the design of Injection-Locked Frequency Dividers and VCO. Firstly, we study the locking range of an LC tank divide by five injection locked frequency divider that uses a pair of varactors and tests the characteristic about connecting an small inductor between the two injection MOS, this circuit designed in the tsmc 0.18 μm CMOS process. We use four inductors in this circuit and the chip area is 1.02 × 0.93 mm2. We observed the sensitivity of locking range to get an information that this circuit has three locking range frequency at the incident power of 0 dBm to -20 dBm, the resonant frequencies are 2.6GHz, 2.7GHz and 3.4GHz respectively. At the supply voltage of 0.9 V, the power consumption is 4.95mW, at the incident power of 0 dBm the locking range is 4.5 GHz(30.1%), from the incident frequency 12.7 GHz to 17.2 GHz. The free-running oscillation frequency is 2.877 GHz. We also find a characteristic about divide by three at lower frequency band. At the supply of 0.58 V, the power consumption is 3.25mW, at the incident power of 0 dBm the locking range is 3.7 GHz(45.4%), from the incident frequency 6.3 GHz to 10 GHz. The free-running oscillation frequency is 2.956 GHz. Secondly, a current-reused LC tank divide by eight injection locked frequency divider designed in the tsmc 0.18 μm CMOS process. The proposed current-reused ILFD is based on a divide by two p-core LC ILFD stacking on a divide by four n-core capacitive cross-coupled LC ILFD. In the divide by four we use a circle mutual inductance to get better coupling coefficient and Q factor. At the supply of 1.6 V and at the incident power of 0 dBm, the locking range is 4 GHz(38.83%), from the incident frequency 8.3 GHz to 12.3 GHz, and the chip area is 1.2 × 1.2 mm2. Finally, we presented a GaN HEMT oscillator with switching active cores in 0.25 μm GAN HEMT process. The proposed voltage controlled oscillator is based on a multipath transformer connect two resonant respectively, the free-running oscillation frequency is 1.7GHz, 1.9GHz and 2.1GHz. We use the gate and drain biases to control the resonant on and off, through these we can tune the oscillation frequency. At the supply of 0.6 V, the phase noise is -123.3 dBc/Hz at the offset frequency of 1 MHz from the carrier at 2.1 GHz at the power consumption 1.8mW.

Тези доповідей конференцій з теми "Injection locked VCO":

1

Ponnambalam, Maran, and Premanand Chandramani. "Injection locked differential ring VCO." In 2013 IEEE Conference on Information & Communication Technologies (ICT). IEEE, 2013. http://dx.doi.org/10.1109/cict.2013.6558133.

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2

Beraud-Sudreau, Q., O. Mazouffre, M. Pignol, L. Baguena, C. Neveu, J.-B. Begueret, and T. Taris. "VHDL-AMS model of an injection locked VCO." In 2012 IEEE 10th International New Circuits and Systems Conference (NEWCAS). IEEE, 2012. http://dx.doi.org/10.1109/newcas.2012.6328947.

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3

Kawasaki, Kengo, Koji Tsutsumi, Masaomi Tsuru, and Eiji Taniguchi. "A self-injection locked VCO with adaptive control of injection phase." In 2014 44th European Microwave Conference (EuMC). IEEE, 2014. http://dx.doi.org/10.1109/eumc.2014.6986610.

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4

Chen Lian, Wei Li, Haipeng Fu, Ning Li, and Junyan Ren. "Low phase noise injection-locked doubler-based quadrature CMOS VCO." In 2011 IEEE 9th International Conference on ASIC (ASICON 2011). IEEE, 2011. http://dx.doi.org/10.1109/asicon.2011.6157280.

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5

Lamberg, John R. "Ka-band hybrid integrated circuit mutually injection locked power combined VCO." In 1987 Twelth International Conference on Infrared and Millimeter Waves. IEEE, 1987. http://dx.doi.org/10.1109/irmm.1987.9126884.

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6

Zhao, Fei, Yong Xu, and Yuanliang Wu. "A Novel Design of 100GHz Silicon-Based CMOS Injection Locked VCO." In RCAE 2018: 2018 International Conference on Robotics, Control and Automation Engineering. New York, NY, USA: ACM, 2018. http://dx.doi.org/10.1145/3303714.3303733.

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7

Ikeda, S., S. Lee, T. Kamimura, H. Ito, N. Ishihara, and K. Masu. "Fractionally Injection-Locked Frequency Multiplication Technique with Multi-Phase Ring VCO." In 2012 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2012. http://dx.doi.org/10.7567/ssdm.2012.j-7-1.

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8

Zhongxia He, Dan Kuykenstierna, Szhau Lai, and Herbert Zirath. "A 12 Gbps analog QPSK baseband receiver based on injection-locked VCO." In 2015 IEEE MTT-S International Microwave Symposium (IMS2015). IEEE, 2015. http://dx.doi.org/10.1109/mwsym.2015.7166905.

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9

Lee, Sanghun, Sunhwan Jang, and Cam Nguyen. "Dual-injection-locked ½ divider with optimized VCO loaded Q and current." In 2013 National Conference on Communications (NCC). IEEE, 2013. http://dx.doi.org/10.1109/ncc.2013.6487921.

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10

Seow, Boon-Eu, Wei-Cheng Lai, Tzuen-Hsi Huang, and Huey-Ru Chuang. "Fully integrated 24 GHz CMOS injection-locked VCO with folded Marchand balun." In TENCON 2016 - 2016 IEEE Region 10 Conference. IEEE, 2016. http://dx.doi.org/10.1109/tencon.2016.7848490.

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