Дисертації: "In-memory compute"

1

Scrbak, Marko. "Methodical Evaluation of Processing-in-Memory Alternatives." Thesis, University of North Texas, 2019. https://digital.library.unt.edu/ark:/67531/metadc1505199/.

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In this work, I characterized a series of potential application kernels using a set of architectural and non-architectural metrics, and performed a comparison of four different alternatives for processing-in-memory cores (PIMs): ARM cores, GPGPUs, coarse-grained reconfigurable dataflow (DF-PIM), and a domain specific architecture using SIMD PIM engine consisting of a series of multiply-accumulate circuits (MACs). For each PIM alternative I investigated how performance and energy efficiency changes with respect to a series of system parameters, such as memory bandwidth and latency, number of PIM cores, DVFS states, cache architecture, etc. In addition, I compared the PIM core choices for a subset of applications and discussed how the application characteristics correlate to the achieved performance and energy efficiency. Furthermore, I compared the PIM alternatives to a host-centric solution that uses a traditional server-class CPU core or PIM-like cores acting as host-side accelerators instead of being part of 3D-stacked memories. Such insights can expose the achievable performance limits and shortcomings of certain PIM designs and show sensitivity to a series of system parameters (available memory bandwidth, application latency and bandwidth sensitivity, etc.). In addition, identifying the common application characteristics for PIM kernels provides opportunity to identify similar types of computation patterns in other applications and allows us to create a set of applications which can then be used as benchmarks for evaluating future PIM design alternatives.

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2

Thomas, Jonathan. "Asynchronous Validity Resolution in Sequentially Consistent Shared Virtual Memory." Fogler Library, University of Maine, 2001. http://www.library.umaine.edu/theses/pdf/Thomas.pdf.

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3

Jiang, Song. "Efficient caching algorithms for memory management in computer systems." W&M ScholarWorks, 2004. https://scholarworks.wm.edu/etd/1539623446.

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As disk performance continues to lag behind that of memory systems and processors, fully utilizing memory to reduce disk accesses is a highly effective effort to improve the entire system performance. Furthermore, to serve the applications running on a computer in distributed systems, not only the local memory but also the memory on remote servers must be effectively managed to minimize I/O operations. The critical challenges in an effective memory cache management include: (1) Insightfully understanding and quantifying the locality inherent in the memory access requests; (2) Effectively utilizing the locality information in replacement algorithms; (3) Intelligently placing and replacing data in the multi-level caches of a distributed system; (4) Ensuring that the overheads of the proposed schemes are acceptable.;This dissertation provides solutions and makes unique and novel contributions in application locality quantification, general replacement algorithms, low-cost replacement policy, thrashing protection, as well as multi-level cache management in a distributed system. First, the dissertation proposes a new method to quantify locality strength, and accurately to identify the data with strong locality. It also provides a new replacement algorithm, which significantly outperforms existing algorithms. Second, considering the extremely low-cost requirements on replacement policies in virtual memory management, the dissertation proposes a policy meeting the requirements, and considerably exceeding the performance existing policies. Third, the dissertation provides an effective scheme to protect the system from thrashing for running memory-intensive applications. Finally, the dissertation provides a multi-level block placement and replacement protocol in a distributed client-server environment, exploiting non-uniform locality strengths in the I/O access requests.;The methodology used in this study include careful application behavior characterization, system requirement analysis, algorithm designs, trace-driven simulation, and system implementations. A main conclusion of the work is that there is still much room for innovation and significant performance improvement for the seemingly mature and stable policies that have been broadly used in the current operating system design.

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4

Squillante, Mark S. "Issues in shared-memory multiprocessor scheduling : a performance evaluation /." Thesis, Connect to this title online; UW restricted, 1990. http://hdl.handle.net/1773/6858.

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5

Sperens, Martin. "Dynamic Memory Managment in C++." Thesis, Luleå tekniska universitet, Datavetenskap, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-76611.

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Memory allocation is an important part of program optimization as well as of computer architecture. This thesis examines some of the concepts of memory allocation and tries to implement overrides for the standard new and delete functions in the c++ library using memory pools combined with other techniques. The overrides are tested against the standard new and delete as well as a custom memory pool with perfect size for the allocations. The study finds that the overrides are slightly faster on a single thread but not on multiple. The study also finds that the biggest gain on performance is to create custom memory pools specific to the programs needs. Lastly, the study also lists a number of ways that the library could be improved

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6

Chan, Chun Keung. "A study on non-volatile memory scaling in the sub-100nm regime /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20CHAN.

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7

Zeffer, Håkan. "Hardware–Software Tradeoffs in Shared-Memory Implementations." Licentiate thesis, Uppsala universitet, Avdelningen för datorteknik, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-86369.

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Shared-memory architectures represent a class of parallel computer systems commonly used in the commercial and technical market. While shared-memory servers typically come in a large variety of configurations and sizes, the advance in semiconductor technology have set the trend towards multiple cores per die and multiple threads per core. Software-based distributed shared-memory proposals were given much attention in the 90s. But their promise of short time to market and low cost could not make up for their unstable performance. Hence, these systems seldom made it to the market. However, with the trend towards chip multiprocessors, multiple hardware threads per core and increased cost of connecting multiple chips together to form large-scale machines, software coherence in one form or another might be a good intra-chip coherence solution. This thesis shows that data locality, software flexibility and minimal processor support for read and write coherence traps can offer good performance, while removing the hard limit of scalability. Our aggressive fine-grained software-only distributed shared-memory system exploits key application properties, such as locality and sharing patterns, to outperform a hardware-only machine on some benchmarks. On average, the software system is 11 percent slower than the hardware system when run on identical node and interconnect hardware. A detailed full-system simulation study of dual core CMPs, with multiple hardware threads per core and minimal processor support for coherence traps is on average one percent slower than its hardware-only counterpart when some flexibility is taken into account. Finally, a functional full-system simulation study of an adaptive coherence-batching scheme shows that the number of coherence misses can be reduced with up to 60 percent and bandwidth consumption reduced with up to 22 percent for both commercial and scientific applications.

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8

McDonald, Ian Lindsay. "Memory management in a distributed system of single address space operating systems supporting quality of service." Thesis, University of Glasgow, 2001. http://theses.gla.ac.uk/5427/.

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The choices provided by an operating system to the application developer for managing memory came in two forms: no choice at all, with the operating system making all decisions about managing memory; or the choice to implement virtual memory management specific to the individual application. The second of these choices is, for all intents and purposes, the same as the first: no choice at all. For many application developers, the cost of implementing a customised virtual memory management system is just too high. The results is that, regardless of the level of flexibility available, the developer ends up using the system-provided default. Further exacerbating the problem is the tendency for operating system developers to be extremely unimaginative when providing that same default. Advancements in virtual memory techniques such as prefetching, remote paging, compressed caching, and user-level page replacement coupled with the provision of user-level virtual memory management should have heralded a new era of choice and an application-centric approach to memory management. Unfortunately, this has failed to materialise. This dissertation describes the design and implementation of the Heracles virtual memory management system. The Heracles approach is one of inclusion rather than exclusion. The main goal of Heracles is to provide an extensible environment that is configurable to the extent of providing application-centric memory management without the need for application developers to implement their own. However, should the application developer wish to provide a more specialised implementation for all or any part of Heracles, the system is constructed around well-defined interfaces that allow new implementations to be "plugged in" where required. The result is a virtual memory management hierarchy that is highly configurable, highly flexible, and can be adapted at run-time to meet new phases in the application's behaviour. Furthermore, different parts of an application's address space can have different hierarchies associated with managing its memory.

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9

Bearpark, Keith. "Learning and memory in genetic programming." Thesis, University of Southampton, 2000. https://eprints.soton.ac.uk/45930/.

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Genetic Programming is a form of Evolutionary Computation in which computer programs are evolved by methods based on simulating the natural evolution of biological species. A new generation of a species acquires the characteristics of previous generations through the inheritance of genes by sexual reproduction and through random changes in alleles by random mutation. The new generation may enhance its ability to survive by the acquisition of cultural knowledge through learning processes. This thesis combines the transfer of knowledge by genetic means with the transfer of knowledge by cultural means. In particular, it introduces a new evolutionary operator, memory operator. In conventional genetic programming systems, a new generation is formed from a mating pool whose members are selected from the fittest members of previous generation. The new generation is produced by the exchange of genes between members of the mating pool and the random replacement of genes in the offspring. The new generation may or may not be able to survive better than its predecessor in a given environment. The memory operator augments the evolutionary process by inserting into new chromosomes genetic material known to often result in fitness improvements. This material is acquired through a learning process in which the system is required to evolve generations that survive in a less demanding environment. The cultural knowledge acquired in this learning process is applied as an intelligent form of mutation to aid survival in a more demanding environment.

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10

Olson, Julius, and Emma Södergren. "Long Term Memory in Conversational Robots." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-260316.

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This study discusses an implementation of a long term memory in the robot Furhat. The idea was to find a way to prevent identical and very similar questions from being asked several times and to store the information of which questions have already been asked in a document database. The project encompasses tf-idf, as well as a small-scale test with Word2Vec, to find a vector representation of all questions from Furhat’s database and then clustering these questions with the k-means method. The tests resulted in high scores on all the evaluation metrics used, which is promising for implementation into the actual Furhat robot, as well as further research on similar implementations of long term memory functions in chatbots.
I denna rapport behandlas implementeringen av ett långtidsminne i roboten Furhat. Idén bakom detta minne var att hindra roboten från att vara repetitiv och ställa allt för likartade eller identiska frågor till en konversationspartner. Projektet inkluderar användandet av tf-idf, samt inledande försök med word2vec i skapandet av vektorrepresentationer av dialogsystemets frågor, samt klustring av dessa representationer med algoritmen k-means. De genomförda testerna renderade goda resultat, vilket är lovande för implementering av en liknande mekanism i Furhats dialogsystem samt för framtida forskning inom långtidsminnesfunktionalitet i chatbots i allmänhet.

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11

Mao, Yandong. "Fast in-memory storage systems : two aspects." Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/93819.

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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 109-114).
This dissertation addresses two challenges relating to in-memory storage systems. The first challenge is storing and retrieving data at a rate close to the capabilities of the underlying memory system, particularly in the face of parallel accesses from multiple cores. We present Masstree, a high performance in-memory key-value store that runs on a single multi-core server. Masstree is derived from a concurrent B+tree. It provides lock-free reads for good multi-core performance, which requires special care to avoid writes interfering with concurrent reads. To reduce time spent waiting for memory for workloads with long common key prefixes, Masstree arranges a set of B+trees into a Trie. Masstree uses software prefetch to further hide DRAM latency. Several optimizations improve concurrency. Masstree achieves millions of queries per second on a 16-core server, which is more than 30x as fast as MongoDB [6] or VoltDB [17]. The second challenge is replicating storage for fault-tolerance without being limited by slow writes to stable disk storage. Lazy VSR is a quorum-based replication protocol that is fast and can recover from simultaneous crashes of all the replicas as long as a majority revive with intact disks. The main idea is to acknowledge requests after recording them in memory, and to write updates to disk in the background, allowing large batched writes and thus good performance. A simultaneous crash of all replicas may leave the replicas with significantly different on-disk states; much of the design of Lazy VSR is concerned with reconciling these states efficiently during recovery. Lazy VSR's client-visible semantics are unusual in that the service may discard recent acknowledged updates if a majority of replicas crash. To demonstrate that clients can nevertheless make good use of Lazy VSR, we built a file system backend on it. Evaluation shows that Lazy VSR achieves much better performance than a version of itself with traditional group commit. Lazy VSR achieves 1.7 x the performance of ZooKeeper [42] and 3.6 x the performance of MongoDB [6].
by Yandong Mao.
Ph. D.

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12

Zhao, Anthony Dong. "Modeling image-to-image confusions in memory." Thesis, Massachusetts Institute of Technology, 2015. http://hdl.handle.net/1721.1/100611.

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Thesis: M. Eng. in Computer Science and Engineering, Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Title as it appears in MIT Commencement Exercises program, June 5, 2015: Metamers in memory: predicting pairwise image confusions with deep learning. Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 81-83).
Previous experiments have examined what causes images to be remembered or forgotten. In these experiments, participants sometimes create false positives when identifying images they have seen before, but the precise cause of these false positives has remained unclear. We examine confusions between individual images as a possible cause of these false positives. We first introduce a new experimental task for examining measuring the rates at which participants confuse one image for another and show that the images prone to false positives are also ones that people tend to confuse. Second, we show that there is a correlation between how often people confuse pairs of images and how similar they find those pairs. Finally, we train a Siamese neural network to predict confusions between pairs of images. By studying the mechanisms behind the failures of memory, we hope to increase our understanding of memory as a whole and move closer to a computational model of memory.
by Anthony Dong Zhao.
M. Eng. in Computer Science and Engineering

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13

Malviya, Nirmesh. "Recovery algorithms for in-memory OLTP databases." Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/75716.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 63-66).
Fine-grained, record-oriented write-ahead logging, as exemplified by systems like ARIES, has been the gold standard for relational database recovery. In this thesis, we show that in modern high-throughput transaction processing systems, this is no longer the optimal way to recover a database system. In particular, as transaction throughputs get higher, ARIES-style logging starts to represent a non-trivial fraction of the overall transaction execution time. We propose a lighter weight, coarse-grained command logging technique which only records the transactions that were executed on the database. It then does recovery by starting from a transactionally consistent checkpoint and replaying the commands in the log as if they were new transactions. By avoiding the overhead of fine-grained, page-level logging of before and after images (and substantial associated I/O), command logging can yield significantly higher throughput at run-time. Recovery times for command logging are higher compared to ARIES, but especially with the advent of high-availability techniques that can mask the outage of a recovering node, recovery speeds have become secondary in importance to run-time performance for most applications. We evaluated our approach on an implementation of TPC-C in a main memory database system (VoltDB), and found that command logging can offer 1.5x higher throughput than a main-memory optimized implementation of ARIES.
by Nirmesh Malviya.
S.M.

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14

Tu, Stephen Lyle. "Fast transactions for multicore in-memory databases." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/82375.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 55-57).
Though modern multicore machines have sufficient RAM and processors to manage very large in-memory databases, it is not clear what the best strategy for dividing work among cores is. Should each core handle a data partition, avoiding the overhead of concurrency control for most transactions (at the cost of increasing it for cross-partition transactions)? Or should cores access a shared data structure instead? We investigate this question in the context of a fast in-memory database. We describe a new transactionally consistent database storage engine called MAFLINGO. Its cache-centered data structure design provides excellent base key-value store performance, to which we add a new, cache-friendly serializable protocol and support for running large, read-only transactions on a recent snapshot. On a key-value workload, the resulting system introduces negligible performance overhead as compared to a version of our system with transactional support stripped out, while achieving linear scalability versus the number of cores. It also exhibits linear scalability on TPC-C, a popular transactional benchmark. In addition, we show that a partitioning-based approach ceases to be beneficial if the database cannot be partitioned such that only a small fraction of transactions access multiple partitions, making our shared-everything approach more relevant. Finally, based on a survey of results from the literature, we argue that our implementation substantially outperforms previous main-memory databases on TPC-C benchmarks.
by Stephen Lyle Tu.
S.M.

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15

Sevcik, Jaroslav. "Program transformations in weak memory models." Thesis, University of Edinburgh, 2009. http://hdl.handle.net/1842/3132.

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We analyse the validity of common optimisations on multi-threaded programs in two memory models—the DRF guarantee and the Java Memory Model. Unlike in the single-threaded world, even simple program transformations, such as common subexpression elimination, can introduce new behaviours in shared-memory multi-threading with an interleaved semantics. To validate such optimisations, most current programming languages define weaker semantics, called memory models, that aim to allow such transformations while providing reasonable guarantees. In this thesis, we consider common program transformations and analyse their safety in the two most widely used language memory models: (i) the DRF guarantee, which promises sequentially consistent behaviours for data race free programs, and (ii) the Java Memory Model, which is the semantics of multithreaded Java. The DRF guarantee is the semantics of Ada and it has been proposed as the semantics of the upcoming revision of C++. Our key results are: (i) we prove that a large class of elimination and reordering transformations satisfies the DRF guarantee; (ii) we find that the Java language is more restrictive—despite the claims in the specification, the Java Memory Model does not allow some important program transformations, such as common subexpression elimination. To establish the safety results, we develop a trace semantic framework and describe important program optimisations as relations on sets of traces. We prove that all our elimination and reordering transformations satisfy the DRF guarantee, i.e., the semantic transformations cannot introduce new behaviours for data race free programs. Moreover, we prove that all the transformations preserve data race freedom. This ensures safety of transformations composed from eliminations and reorderings. In addition to the DRF guarantee, we prove that for arbitrary programs, our transformations prevent values appearing “outof- thin-air”—if a program does not contain constant c and does not perform any operation that could create c, then no transformation of the program can output c. We give an application of the semantic framework to a concrete language and prove safety of several simple syntactic transformations. We employ similar semantic techniques to prove validity of several classes of transformations, such as the elimination of an overwritten write or reordering of independent memory accesses, in the Java Memory Model. To establish the iii negative results for the Java Memory Model, we provide counterexamples showing that several common optimisations can introduce new behaviours and thus are not safe.

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16

Shelor, Charles F. "Dataflow Processing in Memory Achieves Significant Energy Efficiency." Thesis, University of North Texas, 2018. https://digital.library.unt.edu/ark:/67531/metadc1248478/.

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The large difference between processor CPU cycle time and memory access time, often referred to as the memory wall, severely limits the performance of streaming applications. Some data centers have shown servers being idle three out of four clocks. High performance instruction sequenced systems are not energy efficient. The execute stage of even simple pipeline processors only use 9% of the pipeline's total energy. A hybrid dataflow system within a memory module is shown to have 7.2 times the performance with 368 times better energy efficiency than an Intel Xeon server processor on the analyzed benchmarks. The dataflow implementation exploits the inherent parallelism and pipelining of the application to improve performance without the overhead functions of caching, instruction fetch, instruction decode, instruction scheduling, reorder buffers, and speculative execution used by high performance out-of-order processors. Coarse grain reconfigurable logic in an energy efficient silicon process provides flexibility to implement multiple algorithms in a low energy solution. Integrating the logic within a 3D stacked memory module provides lower latency and higher bandwidth access to memory while operating independently from the host system processor.

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17

Hedberg, Charlie Forsberg, and Alexander Pedersen. "Artificial Intelligence : Memory-driven decisions in games." Thesis, Blekinge Tekniska Högskola, Institutionen för teknik och estetik, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-3640.

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Developing AI (Artificial Intelligence) for games can be a hard and challenging task. It is sometimes desired to create behaviors that follow some sort of logical pattern. In order to do this, information must be gathered and processed. This bachelor thesis presents an algorithm that could assist current AI technologies to collect and memorize environmental data. The thesis also covers practical implementation guidelines, established through research and testing.
Att utveckla AI (Artificiell Intelligence) i spel kan vara en hård och utmanande uppgift. Ibland är det önskvärt att skapa beteenden som följer något sorts logiskt mönster. För att kunna göra detta måste information samlas in och processas. I detta kandidatarbete presenteras en algoritm som kan assistera nuvarande AI-teknologier för att samla in och memorera omgivningsinformation. Denna uppsats täcker också riktlinjer för praktisk implementering fastställda genom undersökning och tester.
Detta är en reflekstionsdel till en digital medieproduktion.

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18

Vrljicak, Tomislav. "Reinforcement learning in stochastic games against bounded memory opponents." Thesis, McGill University, 2005. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=98512.

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Learning to play in the presence of independent and self-motivated opponents is a difficult task, because the dynamics of the environment appear to be non-stationary. In recent years there has been considerable amount of research in the field of Multi-Agent Learning, and some of this work has been in the context of Reinforcement Learning. One commonly used approach has been to restrict the opponent to a class of computationally bounded players, creating a parametrized model of it, and then search the model that can best explain the observed opponent behavior. In this thesis we study the problem of Reinforcement Learning in Stochastic Games, and propose two models for the opponent and two search algorithms, one based on Tests of Significance and the other on Maximum a Posteriori probabilities. We integrate the modeled opponent into a Markovian environment, and present an algorithm for solving the resulting MDP. Finally, we perform experiments on the effectiveness of the search algorithms.

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19

Schwiebert, Loren. "A comprehensive study of communication in distributed memory multiprocessors /." The Ohio State University, 1995. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487864986609059.

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20

Laing, C. D. "A reflective process memory in decision making." Thesis, University of Bristol, 1998. http://hdl.handle.net/1983/eb6a9ded-1e28-454e-baea-286bfe75f9bf.

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21

Kearney, Garrett Donough Anthony. "Design of a memory based expert system for interpreting facial expressions in terms of signalled emotions." Thesis, University of Greenwich, 1991. http://gala.gre.ac.uk/6376/.

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A memory based expert system(JANUS) has been designed to interpret facial expression in terms of the signalled emotion. Janus accepts a geometric description of the face obtained from measurements on a digitised full face photograph and returns the appropriate emotion label. An intermediate representation in terms of verbal face actions(eg. . mouth open,eyes closed)is also used. A production rule system converts the geometric description to verbal form, while a dynamic memory interprets the face actions in terms of emotions. Following the work of Schank(1982)and Kolodner (1984),the dynamic memory is structured as a tree of packets, storing, in Janus, typical facial expressions connected by links to atypical but related face expressions previously encountered. This enables new input to be channelled along the appropriate path to an interpretation based on previous experience. The system is capable of learning new emotion labels and associated face actions for use in subsequent interpretations. A prototype system has been developed on a SUN 2/MJN/120 system using POPLOG.V alidation studies suggest that the interpretations offered by Janus are generally consistent with those of human expert.

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22

Doudalis, Ioannis. "Hardware assisted memory checkpointing and applications in debugging and reliability." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/42700.

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The problems of software debugging and system reliability/availability are among the most challenging problems the computing industry is facing today, with direct impact on the development and operating costs of computing systems. A promising debugging technique that assists programmers identify and fix the causes of software bugs a lot more efficiently is bidirectional debugging, which enables the user to execute the program in "reverse", and a typical method used to recover a system after a fault is backwards error recovery, which restores the system to the last error-free state. Both reverse execution and backwards error recovery are enabled by creating memory checkpoints, which are used to restore the program/system to a prior point in time and re-execute until the point of interest. The checkpointing frequency is the primary factor that affects both the latency of reverse execution and the recovery time of the system; more frequent checkpoints reduce the necessary re-execution time. Frequent creation of checkpoints poses performance challenges, because of the increased number of memory reads and writes necessary for copying the modified system/program memory, and also because of software interventions, additional synchronization and I/O, etc., needed for creating a checkpoint. In this thesis I examine a number of different hardware accelerators, whose role is to create frequent memory checkpoints in the background, at minimal performance overheads. For the purpose of reverse execution, I propose the HARE and Euripus hardware checkpoint accelerators. HARE and Euripus create different types of checkpoints, and employ different methods for keeping track of the modified memory. As a result, HARE and Euripus have different hardware costs and provide different functionality which directly affects the latency of reverse execution. For improving the availability of the system, I propose the Kyma hardware accelerator. Kyma enables simultaneous creation of checkpoints at different frequencies, which allows the system to recover from multiple types of errors and tolerate variable error-detection latencies. The Kyma and Euripus hardware engines have similar architectures, but the functionality of the Kyma engine is optimized for further reducing the performance overheads and improving the reliability of the system. The functionality of the Kyma and Euripus engines can be combined into a unified accelerator that can serve the needs of both bidirectional debugging and system recovery.

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23

Ghosh, Mrinmoy. "Microarchitectural techniques to reduce energy consumption in the memory hierarchy." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/28265.

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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.
Committee Chair: Lee, Hsien-Hsin S.; Committee Member: Cahtterjee,Abhijit; Committee Member: Mukhopadhyay, Saibal; Committee Member: Pande, Santosh; Committee Member: Yalamanchili, Sudhakar.

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24

Barrie, Anne. "An exploratory study of computer-assisted memory training in head injury and schizophrenia /." Title page, contents and abstract only, 1989. http://web4.library.adelaide.edu.au/theses/09ARPS/09arpsb275.pdf.

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25

Fagrell, Per, and Richard Eklycke. "Implementing Memory Protection in a Minimal OS." Thesis, Linköping University, Department of Computer and Information Science, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-17355.

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The car industry has created a series of standards called AutoSAR as a response to the increasing number of processors in modern vehicles. Among these specifications is one for real-time operating systems (RTOS). This RTOS standard includes requirements for memory protection. This thesis outlines the work involved in introducing the memory protection outlined in this specification in the OSEck operating system. The work consisted of updating the operating system, implementing the AutoSAR OS API, and updating the suite of toolsused to build the finished system.The AutoSAR specifications were found to be very thorough and well thoughtout. The OS API was successfully implemented, and the data-structures needed to permit its functionality. The existing software tools were updated to conformwith the new requirements from AutoSAR, and additional software was createdto ease the configuration process.Memory protection was successfully implemented in the OSEck operating system, including two implementations of the trap interface. The memory protection functionality adds yet another layer of user-configuration to the operating system. Also, additional overhead for system calls, context switches and message passing is expected. A general evaluation of how OSEck application performance is aff ected is beyond the scope of this thesis, but preliminary studies of additional instruction counts on certain system calls have been performed.

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26

Hsieh, Wilson Cheng-Yi. "Dynamic computation migration in distributed shared memory systems." Thesis, Massachusetts Institute of Technology, 1995. http://hdl.handle.net/1721.1/36635.

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Анотація:

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.
Vita.
Includes bibliographical references (p. 123-131).
by Wilson Cheng-Yi Hsieh.
Ph.D.

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27

Ezell, Novice M. J. (Novice Marie Johnson) 1976. "Analysis of memory usage in a LaserJet printer." Thesis, Massachusetts Institute of Technology, 1999. http://hdl.handle.net/1721.1/80062.

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Анотація:

Thesis (S.B. and M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.
Includes bibliographical references (leaf 56).
by Novice M.J. Ezell.
S.B.and M.Eng.

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28

Shai, Yee-man. "Effects of computer presentation formats on learning among elderly and younger adults the role of cognitive abilities /." Click to view the E-thesis via HKUTO, 2006. http://sunzi.lib.hku.hk/hkuto/record/B35804440.

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29

Yuki, Tomofumi. "Dissertation beyond shared memory loop parallelism in the polyhedral model." Thesis, Colorado State University, 2013. http://pqdtopen.proquest.com/#viewpdf?dispub=3565471.

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Анотація:

With the introduction of multi-core processors, motivated by power and energy concerns, parallel processing has become main-stream. Parallel programming is much more difficult due to its non-deterministic nature, and because of parallel programming bugs that arise from non-determinacy. One solution is automatic parallelization, where it is entirely up to the compiler to efficiently parallelize sequential programs. However, automatic parallelization is very difficult, and only a handful of successful techniques are available, even after decades of research.

Automatic parallelization for distributed memory architectures is even more problematic in that it requires explicit handling of data partitioning and communication. Since data must be partitioned among multiple nodes that do not share memory, the original memory allocation of sequential programs cannot be directly used. One of the main contributions of this dissertation is the development of techniques for generating distributed memory parallel code with parametric tiling.

Our approach builds on important contributions to the polyhedral model, a mathematical framework for reasoning about program transformations. We show that many affine control programs can be uniformized only with simple techniques. Being able to assume uniform dependences significantly simplifies distributed memory code generation, and also enables parametric tiling. Our approach implemented in the AlphaZ system, a system for prototyping analyses, transformations, and code generators in the polyhedral model. The key features of AlphaZ are memory re-allocation, and explicit representation of reductions.

We evaluate our approach on a collection of polyhedral kernels from the PolyBench suite, and show that our approach scales as well as PLuTo, a state-of-the-art shared memory automatic parallelizer using the polyhedral model.

Automatic parallelization is only one approach to dealing with the non-deterministic nature of parallel programming that leaves the difficulty entirely to the compiler. Another approach is to develop novel parallel programming languages. These languages, such as X10, aim to provide highly productive parallel programming environment by including parallelism into the language design. However, even in these languages, parallel bugs remain to be an important issue that hinders programmer productivity.

Another contribution of this dissertation is to extend the array dataflow analysis to handle a subset of X10 programs. We apply the result of dataflow analysis to statically guarantee determinism. Providing static guarantees can significantly increase programmer productivity by catching questionable implementations at compile-time, or even while programming.

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30

Demaine, Erik. "Effcient Simulation of Message-Passing in Distributed-Memory Architectures." Thesis, University of Waterloo, 1996. http://hdl.handle.net/10012/1069.

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Анотація:

In this thesis we propose a distributed-memory parallel-computer simulation system called PUPPET (Performance Under a Pseudo-Parallel EnvironmenT). It allows the evaluation of parallel programs run in a pseudo-parallel system, where a single processor is used to multitask the program's processes, as if they were run on the simulated system. This allows development of applications and teaching of parallel programming without the use of valuable supercomputing resources. We use a standard message-passing language, MPI, so that when desired (e. g. , development is complete) the program can be run on a truly parallel system without any changes. There are several features in PUPPET that do not exist in any other simulation system. Support for all deterministic MPI features is available, including collective and non-blocking communication. Multitasking (more processes than processors) can be simulated, allowing the evaluation of load-balancing schemes. PUPPET is very loosely coupled with the program, so that a program can be run once and then evaluated on many simulated systems with multiple process-to-processor mappings. Finally, we propose a new model of direct networks that ignores network traffic, greatly improving simulation speed and often not signficantly affecting accuracy.

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31

Sandblom, Johan. "Episodic memory in the human prefrontal cortex /." Stockholm, 2007. http://diss.kib.ki.se/2007/978-91-7357-136-4/.

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32

Olsson, Markus. "Design and Implementation of Transactions in a Column-Oriented In-Memory Database System." Thesis, Umeå University, Department of Computing Science, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:umu:diva-32705.

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Анотація:

Coldbase is a column-oriented in-memory database implemented in Java that is used with a specific workload in mind. Coldbase is optimized to receive large streams of timestamped trading data arriving at a fast pace while allowing simple but frequent queries that analyse the data concurrently. By limiting the functionality, Coldbase is able to reach a high performance while the memory consumption is low. This thesis presents ColdbaseTX which is an extension to Coldbase that adds support for transactions. It uses an optimistic approach by storing all writes of a transaction locally and applying them when the transaction commits. Readers are separated from writers by using two versions of the data which makes it possible to guarantee that readers are never blocked.Benchmarks compare Coldbase to ColdbaseTX regarding both performance andmemory efficiency. The results show that ColdbaseTX introduces a small overhead in both memory and performance which however is deemed acceptable since the gain is support for transactions.

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33

Das, Jayita. "Auxiliary Roles in STT-MRAM Memory." Scholar Commons, 2014. https://scholarcommons.usf.edu/etd/5613.

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Анотація:

Computer memories now play a key role in our everyday life given the increase in the number of connected smart devices and wearables. Recently post-CMOS memory technologies are gaining significant research attention along with the regular ones. Spin Transfer Torque Magnetoresistive RAM (STT-MRAM) is one such post-CMOS memory technology with a rapidly growing commercial interest and potential across diverse application platforms. Research has shown the ability of STT-MRAM to replace different levels of memory hierarchy as well. In brief, STT-MRAM possesses all the favorable properties of a universal memory technology. In this dissertation we have explored the roles of this emerging memory technology beyond traditional storage. The purpose is to enhance the overall performance of the application platform that STT-MRAM is a part of. The roles that we explored are computation and security. We have discussed how the intrinsic properties of STT-MRAM can be used for computation and authentication. The two properties that we are interested in are the dipolar coupling between the magnetic memory cells and the variations in the geometries of the memory cell. Our contributions here are a 22nm CMOS integrated STT-MRAM based logic-in-memory architecture and a geometric variation based STT-MRAM signature generation. In addition we have explored the device physics and the dynamics of STT-MRAM cells to propose a STT based clocking mechanism that is friendlier with the logic-in-memory setup. By investigating the logic layouts and propagation style in the architecture, we have also proposed different techniques that can improve the logic density and performance of the architecture.

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34

Åslin, Fredrik. "Evaluation of Hierarchical Temporal Memory in algorithmic trading." Thesis, Linköping University, Department of Computer and Information Science, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-54235.

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This thesis looks into how one could use Hierarchal Temporal Memory (HTM) networks to generate models that could be used as trading algorithms. The thesis begins with a brief introduction to algorithmic trading and commonly used concepts when developing trading algorithms. The thesis then proceeds to explain what an HTM is and how it works. To explore whether an HTM could be used to generate models that could be used as trading algorithms, the thesis conducts a series of experiments. The goal of the experiments is to iteratively optimize the settings for an HTM and try to generate a model that when used as a trading algorithm would have more profitable trades than losing trades. The setup of the experiments is to train an HTM to predict if it is a good time to buy some shares in a security and hold them for a fixed time before selling them again. A fair amount of the models generated during the experiments was profitable on data the model have never seen before, therefore the author concludes that it is possible to train an HTM so it can be used as a profitable trading algorithm.

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35

Lundgren, Björn, and Anders Ödlund. "Exposure of Patterns in Parallel Memory Acces." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-9795.

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The concept and advantages of a Parallel Memory Architecture (PMA) in computer systems have been known for long but it’s only in recent time it has become interesting to implement modular parallel memories even in handheld embedded systems. This thesis presents a method to analyse source code to expose possible parallel memory accesses. Memory access Patterns may be found, categorized and the corresponding code marked for optimization. As a result a PMA compatible with found pattern(s) and code optimization may be specified.

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36

Mills, Richard Tran. "Dynamic adaptation to CPU and memory load in scientific applications." W&M ScholarWorks, 2004. https://scholarworks.wm.edu/etd/1539623457.

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Анотація:

As commodity computers and networking technologies have become faster and more affordable, fairly capable machines have become nearly ubiquitous while the effective "distance" between them has decreased as network connectivity and capacity has multiplied. There is considerable interest in developing means to readily access such vast amounts of computing power to solve scientific problems, but the complexity of these modern computing environments pose problems for conventional computer codes designed to run on a static, homogeneous set of resources. One source of problems is the heterogeneity that is naturally present in these settings. More problematic is the competition that arises between programs for shared resources in these semi-autonomous environments. Fluctuations in the availability of CPU, memory, and other resources can cripple application performance. Contention for CPU time between jobs may introduce significant load imbalance in parallel applications. Contention for limited memory resources may cause even more severe performance problems, as thrashing may increase execution times by an order of magnitude or more.;Our goal is to develop techniques that enable scientific applications to achieve good performance in non-dedicated environments by monitoring system conditions and adapting their behavior accordingly. We focus on two important shared resources, CPU and memory, and pursue our goal on two distinct but complementary fronts: First, we present some simple algorithmic modifications that can significantly improve load balance in a class of iterative methods that form the computational core of many scientific and engineering applications. Second, we introduce a framework for enabling scientific applications to dynamically adapt their memory usage according to current availability of main memory. An application-specific caching policy is used to keep as much of the data set as possible in main memory, while the remainder of the data are accessed in an out-of-core fashion.;We have developed modular code libraries to facilitate implementation of our techniques, and have deployed them in a variety of scientific application kernels. Experimental evaluation of their performance indicates that our techniques provide some important classes of scientific applications with robust and low-overhead means for mitigating the effects of fluctuations in CPU and memory availability.

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37

Ho, Yuk. "Application of minimal perfect hashing in main memory indexing." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/36445.

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38

Atmaca, Eralp 1976. "Hysteresis and memory effects in nanocrystal embedded MOS capacitors." Thesis, Massachusetts Institute of Technology, 2000. http://hdl.handle.net/1721.1/58686.

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Анотація:

Thesis (M. Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.
Issued separately by degree.
Includes bibliographical references (p. 103-106).
Nanocrystal Memory is a promising new memory type which utilizes silicon nanocrystals and quantum mechanical direct tunneling current for charge storage. This thesis presents the work done to characterize the memory effect in nanocrystal embedded metal-oxide-semiconductor (NC-MOS) capacitors, the fundamental components of the nanocrystal memory. Various properties of the NC-MOS capacitors including gate stack composition, oxide charge storage and interface traps are studied by making high frequency and quasi-static capacitance voltage and current voltage measurements. High frequency and quasi-static capacitance characteristics reveal hysteresis which is evidence for the memory effect. A hysteresis of 2 V is demonstrated which is large enough to enable the use of nanocrystal embedded devices as memory devices. Measurement results suggest that the tunneling in the accumulation bias regime is mostly electron tunneling from the channel into the nanocrystals, and the tunneling in the inversion bias regime is hole tunneling from the channel into the nanocrystals. Charge is stored in the nanocrystals either in the discrete quantum dot states or in the interface traps that surround the nanocrystals. The oxide thickness is varied to control the tunneling rate and the retention time. A thinner tunnel oxide is necessary for achieving a higher tunneling rate which provides a faster write/erase. However, when the barrier thickness is lower, the charge confined in the nanocrystals can leak back into the channel more easily. Measurement conditions such as bias schemes, hold times, sweep rates and illumination can significantly influence the memory effect. It is demonstrated that the memory effect is enhanced by longer hold times, wider sweep regimes and light.
by Eralp Atmaca.
M.Eng.and S.B.

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39

Stamatoiu, Oana L. (Oana Liana) 1981. "Learning commonsense categorical knowledge in a thread memory system." Thesis, Massachusetts Institute of Technology, 2004. http://hdl.handle.net/1721.1/17988.

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Анотація:

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.
Includes bibliographical references (p. 89-92).
If we are to understand how we can build machines capable of broad purpose learning and reasoning, we must first aim to build systems that can represent, acquire, and reason about the kinds of commonsense knowledge that we humans have about the world. This endeavor suggests steps such as identifying the kinds of knowledge people commonly have about the world, constructing suitable knowledge representations, and exploring the mechanisms that people use to make judgments about the everyday world. In this work, I contribute to these goals by proposing an architecture for a system that can learn commonsense knowledge about the properties and behavior of objects in the world. The architecture described here augments previous machine learning systems in four ways: (1) it relies on a seven dimensional notion of context, built from information recently given to the system, to learn and reason about objects' properties; (2) it has multiple methods that it can use to reason about objects, so that when one method fails, it can fall back on others; (3) it illustrates the usefulness of reasoning about objects by thinking about their similarity to other, better known objects, and by inferring properties of objects from the categories that they belong to; and (4) it represents an attempt to build a autonomous learner and reasoner, that sets its own goals for learning about the world and deduces new facts by reflecting on its acquired knowledge. This thesis describes this architecture, as well as a first implementation, that can learn from sentences such as "A blue bird flew to the tree" and "The small bird flew to the cage" that birds can fly. One of the main contributions of this work lies in suggesting a further set of salient ideas about how we can
(cont.) build broader purpose commonsense artificial learners and reasoners.
by Oana L. Stamatoiu.
M.Eng.

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40

Zhang, Guowei Ph D. Massachusetts Institute of Technology. "Architectural support to exploit commutativity in shared-memory systems." Thesis, Massachusetts Institute of Technology, 2016. http://hdl.handle.net/1721.1/106073.

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Анотація:

Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2016.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 57-64).
Parallel systems are limited by the high costs of communication and synchronization. Exploiting commutativity has historically been a fruitful avenue to reduce traffic and serialization. This is because commutative operations produce the same final result regardless of the order they are performed in, and therefore can be processed concurrently and without communication. Unfortunately, software techniques that exploit commutativity, such as privatization and semantic locking, incur high runtime overheads. These overheads offset the benefit and thereby limit the applicability of software techniques. To avoid high overheads, it would be ideal to exploit commutativity in hardware. In fact, hardware already provides much of the functionality that is required to support commutativity For instance, private caches can buffer and coalesce multiple updates. However, current memory hierarchies can understand only reads and writes, which prevents hardware from recognizing and accelerating commutative operations. The key insight this thesis develops is that, with minor hardware modifications and minimal extra complexity, cache coherence protocols, the key component of communication and synchronization in shared-memory systems, can be extended to allow local and concurrent commutative operations. This thesis presents two techniques that leverage this insight to exploit commutativity in hardware. First, Coup provides architectural support for a limited number of single-instruction commutative updates, such as addition and bitwise logical operations. CouP allows multiple private caches to simultaneously hold update-only permission to the same cache line. Caches with update-only permission can locally buffer and coalesce updates to the line, but cannot satisfy read requests. Upon a read request, Coup reduces the partial updates buffered in private caches to produce the final value. Second, CoMMTM is a commutativity-aware hardware transactional memory (HTM) that supports an even broader range of multi-instruction, semantically commutative operations, such as set insertions and ordered puts. COMMTM extends the coherence protocol with a reducible state tagged with a user-defined label. Multiple caches can hold a given line in the reducible state with the same label, and transactions can implement arbitrary user-defined commutative operations through labeled loads and stores. These commutative operations proceed concurrently, without triggering conflicts or incurring any communication. A non-commutative operation (e.g., a conventional load or store) triggers a user-defined reduction that merges the different cache lines and may abort transactions with outstanding reducible updates. CouP and CoMMTM reduce communication and synchronization in many challenging parallel workloads. At 128 cores, CouP accelerates state-of-the-art implementations of update-heavy algorithms by up to 2.4x, and COMMTM outperforms a conventional eager-lazy HTM by up to 3.4x and reduces or eliminates wasted work due to transactional aborts.
by Guowei Zhang.
S.M.

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41

Beane, Glen L. "The Effects of Microprocessor Architecture on Speedup in Distrbuted Memory Supercomputers." Fogler Library, University of Maine, 2004. http://www.library.umaine.edu/theses/pdf/BeaneGL2004.pdf.

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42

Abbas, Gulfam, and Naveed Asif. "Performance Tradeoffs in Software Transactional Memory." Thesis, Blekinge Tekniska Högskola, Sektionen för datavetenskap och kommunikation, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-6059.

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Анотація:

Transactional memory (TM), a new programming paradigm, is one of the latest approaches to write programs for next generation multicore and multiprocessor systems. TM is an alternative to lock-based programming. It is a promising solution to a hefty and mounting problem that programmers are facing in developing programs for Chip Multi-Processor (CMP) architectures by simplifying synchronization to shared data structures in a way that is scalable and compos-able. Software Transactional Memory (STM) a full software approach of TM systems can be defined as non-blocking synchronization mechanism where sequential objects are automatically converted into concurrent objects. In this thesis, we present performance comparison of four different STM implementations – RSTM of V. J. Marathe, et al., TL2 of D. Dice, et al., TinySTM of P. Felber, et al. and SwissTM of A. Dragojevic, et al. It helps us in deep understanding of potential tradeoffs involved. It further helps us in assessing, what are the design choices and configuration parameters that may provide better ways to build better and efficient STMs. In particular, suitability of an STM is analyzed against another STM. A literature study is carried out to sort out STM implementations for experimentation. An experiment is performed to measure performance tradeoffs between these STM implementations. The empirical evaluations done as part of this thesis conclude that SwissTM has significantly higher throughput than state-of-the-art STM implementations, namely RSTM, TL2, and TinySTM, as it outperforms consistently well while measuring execution time and aborts per commit parameters on STAMP benchmarks. The results taken in transaction retry rate measurements show that the performance of TL2 is better than RSTM, TinySTM and SwissTM.

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43

McNamee, Dylan James. "Virtual memory alternatives for transaction buffer management in a single-level store /." Thesis, Connect to this title online; UW restricted, 1996. http://hdl.handle.net/1773/6961.

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44

Johnson, Gregory. "Beliefs of Graduate Students About Unstructured Computer Use in Face-to-Face Classes with Internet Access and its Influence on Student Recall." Doctoral diss., University of Central Florida, 2009. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/2089.

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Анотація:

The use of computers equipped with Internet access by students during face-to-face (F2F) class sessions is perceived as academically beneficial by a growing number of students and faculty members in universities across the United States. Nevertheless, some researchers suggest unstructured computer use detached from the immediate class content may negatively influence student participation, increase distraction levels, minimize recall of recently presented information, and decrease student engagement. This study investigates graduate students' beliefs about computer use with Internet access during graduate face-to-face lecture classes in which computer use is neither mandated nor integrated in the class and the effect of such use on student recall. Methods include a 44-item questionnaire to investigate graduate students' beliefs about computers and two experiments to investigate the influence of computer use during a lecture on students' memory recall. One experimental group (open laptop) used computers during a lecture while the other (closed laptop) did not. Both groups were given the same memory recall test after the lectures, and the resulting scores were analyzed. Two weeks later, a second phase of the experiment was implemented in which laptop groups were reversed. Results from the first experiment indicated no statistically significant difference in recall scores between the open laptop group (M = 54.90, SD = 19.65) and the closed laptop group (M = 42.86, SD = 16.68); t (29) = -1.82, p = .08 (two tailed). Conversely, the second experiment revealed statistically significant differences in scores between the open laptop (M = 39.67, SD = 15.97) and the closed laptop group (M = 59.29, SD = 26.88); t (20.89) = 2.37, p = .03 (two tailed). The magnitude of the difference in mean scores (mean difference = 19.62, 95% CI: 2.39 to 36.85) was large (eta squared = 0.17). Multiple regression analysis suggests two factors accounted for 10% of the variance in recall scores: (1) students' beliefs about distractions from computer use, and (2) beliefs about the influence of computer use on memory recall. Based on survey findings, participants (N=116) viewed computers and Internet access in graduate classes as helpful academic tools, but distractions from computer use were major sources of concern for students who used computers in graduate classes and those who did not. Additionally, participants believed academic productivity would increase if instructors integrated computer use appropriately in the curricula. Results of the survey and experiments suggest unstructured computer use with Internet access in the graduate classroom is strongly correlated with increased student distractions and decreased memory recall. Thus, restricting unstructured computer use is likely to increase existing memory recall levels, and increasing unstructured computer use is likely to reduce memory recall. Recommendations include changes in the way students use computers, pedagogical shifts, computer integration strategies, modified seating arrangements, increased accountability, and improved interaction between instructors and students.
Ph.D.
Department of Educational Research, Technology and Leadership
Education
Education PhD

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45

Balasubramaniam, Mahadevan. "Performance analysis and evaluation of dynamic loop scheduling techniques in a competitive runtime environment for distributed memory architectures." Master's thesis, Mississippi State : Mississippi State University, 2003. http://library.msstate.edu/etd/show.asp?etd=etd-04022003-154254.

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46

Muñiz, Navarro José Alberto. "A hybrid data structure for dense keys in in-memory database systems." Thesis, Massachusetts Institute of Technology, 2010. http://hdl.handle.net/1721.1/62662.

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Анотація:

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 71-72).
This thesis presents a data structure which performs well for in-memory indexing of keys that are unevenly distributed into clusters with a high density of keys. This pattern is prevalent, for example, in systems that use tables with keys where one field is auto-incremented. These types of tables are widely used. The proposed data structure consists of a B+ Tree with intervals as keys, and arrays as values. Each array holds a cluster of values, while the clusters themselves are managed by the B+ Tree for space and cache efficiency. Using the H-Tree as an in-memory indexing structure for an implementation of the TPC-C benchmark sped up the transaction processing time by up to 50% compared to an implementation based on B+Trees, and showed even more dramatic performance gains in the presence of few and large clusters of data.
by José Alberto Muñiz Navarro.
M.Eng.

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47

Gul, Saba. "Novelty in goal-oriented machines using a thread memory structure." Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/53143.

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Анотація:

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.
Includes bibliographical references (leaves 55-56).
Resourcefulness and creativity are desirable properties for an intelligent machine. The incredible adeptness of the human mind at seeing situations from diverse viewpoints allows it to conjure many techniques to accomplish the same goal, and hence recover elegantly when one method fails. In the context of goal-oriented machines, this thesis presents a system that finds substitutes for the typical physical resource used to accomplish a goal, by finding novel uses for other, available resources-uses that these resources were not originally meant or designed for. In a domain where an object can serve multiple functions, this requires: (1) understanding the functional context the object is operating in; (2) building a realistic representation of the given objects, which often do not fall neatly into tightly-structured categorizations, but instead share properties with other 'boundary' objects. The system does this by learning from examples, and using the average member, or 'stereotype' as the class representative; (3) allowing imperfection: identifying properties that are not crucial for goal satisfaction, and selectively ignoring them; and (4) measuring similarity between objects to find the best substitute. The system bootstraps with knowledge about the properties of the objects and is given positive and negative examples for the goal. It can infer, for example, that two objects such as an orange (the typical resource) and a ball (the positive example) are related in the context of finding a throwable object on account of their similarity in shape and size, but unrelated in the context of finding an ingredient for a fruit salad, because one is a fruit and the other is not.
(cont.) It then finds a substitute that shares shape and size features with the orange. If, on the other hand, we need an ingredient for a fruit salad, we can supply it another edible fruit as a positive example. The system is implemented in Java; its performance is illustrated with 7 examples in the domain of everyday objects.
by Saba Gul.
M.Eng.

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48

Qazi, Masood. "Circuit design for embedded memory in low-power integrated circuits." Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/75645.

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Анотація:

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 141-152).
This thesis explores the challenges for integrating embedded static random access memory (SRAM) and non-volatile memory-based on ferroelectric capacitor technology-into lowpower integrated circuits. First considered is the impact of process variation in deep-submicron technologies on SRAM, which must exhibit higher density and performance at increased levels of integration with every new semiconductor generation. Techniques to speed up the statistical analysis of physical memory designs by a factor of 100 to 10,000 relative to the conventional Monte Carlo Method are developed. The proposed methods build upon the Importance Sampling simulation algorithm and efficiently explore the sample space of transistor parameter fluctuation. Process variation in SRAM at low-voltage is further investigated experimentally with a 512kb 8T SRAM test chip in 45nm SOI CMOS technology. For active operation, an AC coupled sense amplifier and regenerative global bitline scheme are designed to operate at the limit of on current and off current separation on a single-ended SRAM bitline. The SRAM operates from 1.2 V down to 0.57 V with access times from 400ps to 3.4ns. For standby power, a data retention voltage sensor predicts the mismatch-limited minimum supply voltage without corrupting the contents of the memory. The leakage power of SRAM forces the chip designer to seek non-volatile memory in applications such as portable electronics that retain significant quantities of data over long durations. In this scenario, the energy cost of accessing data must be minimized. This thesis presents a ferroelectric random access memory (FRAM) prototype that addresses the challenges of sensing diminishingly small charge under conditions favorable to low access energy with a time-to-digital sensing scheme. The 1 Mb IT1C FRAM fabricated in 130 nm CMOS operates from 1.5 V to 1.0 V with corresponding access energy from 19.2 pJ to 9.8 pJ per bit. Finally, the computational state of sequential elements interspersed in CMOS logic, also restricts the ability to power gate. To enable simple and fast turn-on, ferroelectric capacitors are integrated into the design of a standard cell register, whose non-volatile operation is made compatible with the digital design flow. A test-case circuit containing ferroelectric registers exhibits non-volatile operation and consumes less than 1.3 pJ per bit of state information and less than 10 clock cycles to save or restore with no minimum standby power requirement in-between active periods.
by Masood Qazi.
Ph.D.

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49

Zheng, Wenting. "Fast checkpoint and recovery techniques for an in-memory database." Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/91701.

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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 61-62).
Multicore in-memory databases for modern machines can support extraordinarily high transaction rates for online transaction processing workloads. A potential weakness of such databases, however, is recovery from crash failures. We show that techniques for disk-based persistence can be ecient enough to keep up with current systems' huge memory sizes and fast transaction rates, be smart enough to avoid additional contention, and provide fast recovery. This thesis presents SiloR, a persistence system built for a very fast multicore database system called Silo. We show that naive logging and checkpoints make normal-case execution slower, but that careful design of the persistence system allows us to keep up with many workloads without negative impact on runtime performance. We design the checkpoint and logging system to utilize multicore's resources to its fullest extent, both during runtime and during recovery. Parallelism allows the system to recover fast. Experiments show that a large database (~~ 50 GB) can be recovered in under five minutes.
by Wenting Zheng.
M. Eng.

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50

Kjelso, Morten. "A quantitative evaluation of data compression in the memory hierarchy." Thesis, Loughborough University, 1997. https://dspace.lboro.ac.uk/2134/10596.

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This thesis explores the use of lossless data compression in the memory hierarchy of contemporary computer systems. Data compression may realise performance benefits by increasing the capacity of a level in the memory hierarchy and by improving the bandwidth between two levels in the memory hierarchy. Lossless data compression is already widely used in parts ofthe memory hierarchy. However, most of these applications are characterised by targeting inexpensive and relatively low performance devices such as magnetic disk and tape devices. The consequences of this are that the benefits of data compression are not realised to their full potential. This research aims to understand how the benefits of data compression can be realised for levels of the memory hierarchy which have a greater impact on system performance and system cost. This thesis presents a review of data compression in the memory hierarchy and argues that main memory compression has the greatest potential to improve system performance. The review also identifies three key issues relating to the use of data compression in the memory hierarchy. Quantitative investigations are presented to address these issues for main memory data compression. The first investigation is into memory data, and shows that memory data from a range of Unix applications typically compresses to half its original size. The second investigation develops three memory compression architectures, taking into account the results of the previous investigation. Furthermore, the management of compressed data is addressed and management methods are developed which achieve storage efficiencies in excess of 90% and typically complete allocation and de allocation operations with only a few memory accesses. The experimental work then culminates in a performance investigation. This shows that when memory resources are strecthed, hardware based memory compression can improve system performance by up to an order of magnitude. Furthermore, software based memory compression can improve system performance by up to a factor of 2. Finally, the performance models and quantitative results contained in this thesis enable us to identify under what conditions memory compression offers performance benefits. This may help designers incorporate memory compression into future computer systems.

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Дисертації з теми "In-memory compute"

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