Увійти

Готові списки джерел за темами / High level Synthesi / Статті в журналах

Статті в журналах з теми "High level Synthesi"

Щоб переглянути інші типи публікацій з цієї теми, перейдіть за посиланням: High level Synthesi.

Автор: Grafiati

Опубліковано: 14 березня 2023

Оформте джерело за APA, MLA, Chicago, Harvard та іншими стилями

Оберіть тип джерела:

Ознайомтеся з топ-50 статей у журналах для дослідження на тему "High level Synthesi".

Біля кожної праці в переліку літератури доступна кнопка «Додати до бібліографії». Скористайтеся нею – і ми автоматично оформимо бібліографічне посилання на обрану працю в потрібному вам стилі цитування: APA, MLA, «Гарвард», «Чикаго», «Ванкувер» тощо.

Також ви можете завантажити повний текст наукової публікації у форматі «.pdf» та прочитати онлайн анотацію до роботи, якщо відповідні параметри наявні в метаданих.

Переглядайте статті в журналах для різних дисциплін та оформлюйте правильно вашу бібліографію.

1

Rajan, S. P., M. Fujita, K. Yuan, and M. T.-C. Lee. "ATM switch design by high-level modeling, formal verification and high-level synthesi." ACM Transactions on Design Automation of Electronic Systems 3, no. 4 (October 1998): 554–62. http://dx.doi.org/10.1145/296333.296342.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

2

Yang, Hae-Chan, Sang-Jun Park, Kwoan-Young Park, Jae-Hyun Sa, and Tae-Hwan Kim. "High-level Synthesis Design and Implementation of an Efficient Capsule Network Inference System in an FPGA." Journal of the Institute of Electronics and Information Engineers 58, no. 11 (November 30, 2021): 39–47. http://dx.doi.org/10.5573/ieie.2021.58.11.39.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

3

Bolton, Martin. "High-level synthesis." Microprocessors and Microsystems 18, no. 8 (October 1994): 489. http://dx.doi.org/10.1016/0141-9331(94)90097-3.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

4

Pawlak, Adam. "High-level synthesis." Microprocessing and Microprogramming 35, no. 1-5 (September 1992): 261. http://dx.doi.org/10.1016/0165-6074(92)90325-2.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

5

YAMAMOTO, Takahiro. "Safety assessment of high-level nuclear waste disposal in Japan from the standpoint of geology." Synthesiology English edition 4, no. 4 (2012): 202–11. http://dx.doi.org/10.5571/syntheng.4.202.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

6

Ravi, Selvaraj, and M. Joseph. "High-Level Test Synthesis." ACM Transactions on Design Automation of Electronic Systems 19, no. 4 (August 2014): 1–27. http://dx.doi.org/10.1145/2627754.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

7

Ewering, Christian, and Gunter Gerhardt. "PASS: High level synthesis." Microprocessing and Microprogramming 30, no. 1-5 (August 1990): 103–8. http://dx.doi.org/10.1016/0165-6074(90)90225-x.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

8

Xing, Xianwu, and Ching Chuen Jong. "Floorplan-Driven Multivoltage High-Level Synthesis." VLSI Design 2009 (September 6, 2009): 1–10. http://dx.doi.org/10.1155/2009/156751.

Повний текст джерела

Анотація:

As the semiconductor technology advances, interconnect plays a more and more important role in power consumption in VLSI systems. This also imposes a challenge in high-level synthesis, in which physical information is limited and conventionally considered after high-level synthesis. To close the gap between high-level synthesis and physical implementation, integration of physical synthesis and high-level synthesis is essential. In this paper, a technique named FloM is proposed for integrating floorplanning into high-level synthesis of VLSI system with multivoltage datapath. Experimental results obtained show that the proposed technique is effective and the energy consumed by both the datapath and the wires can be reduced by more than 40%.

Стилі APA, Harvard, Vancouver, ISO та ін.

9

Dossis, M. "High-level Synthesis Integrated Verification." Engineering, Technology & Applied Science Research 5, no. 5 (October 4, 2015): 864–70. http://dx.doi.org/10.48084/etasr.596.

Повний текст джерела

Анотація:

It is widely known in the engineering community that more than 60% of the IC design project time is spent on verification. For the very complex contemporary chips, this may prove prohibitive for the IC to arrive at the correct time in the market and therefore, valuable sales share may be lost by the developing industry. This problem is deteriorated by the fact that most of conventional verification flows are highly repetitive and a great proportion of the project time is spent on last-moment simulations. In this paper we present an integrated approach to rapid, high-level verification, exploiting the advantages of a formal High-level Synthesis tool, developed by the author. Verification in this work is supported at 3 levels: high-level program code, RTL simulation and rapid, generated C testbench execution. This paper is supported by strong experimental work with 3-4 popular design synthesis and verification that proves the principles of our methodology.

Стилі APA, Harvard, Vancouver, ISO та ін.

10

Gajski, D. D., and L. Ramachandran. "Introduction to high-level synthesis." IEEE Design & Test of Computers 11, no. 4 (1994): 44–54. http://dx.doi.org/10.1109/54.329454.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

11

Paulin, P. G., and J. P. Knight. "Algorithms for high-level synthesis." IEEE Design & Test of Computers 6, no. 6 (December 1989): 18–31. http://dx.doi.org/10.1109/54.41671.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

12

Rosenstiel, Wolfgang. "Optimizations in high level synthesis." Microprocessing and Microprogramming 18, no. 1-5 (December 1986): 347–52. http://dx.doi.org/10.1016/0165-6074(86)90063-3.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

13

Zhenyu Gu, Jia Wang, R. P. Dick, and Hai Zhou. "Unified Incremental Physical-Level and High-Level Synthesis." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26, no. 9 (September 2007): 1576–88. http://dx.doi.org/10.1109/tcad.2007.895780.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

14

Van Meerbergen, J. L., P. E. R. Lippens, W. F. J. Verhaegh, and A. Van Der Werf. "PHIDEO: High-level synthesis for high throughput applications." Journal of VLSI signal processing systems for signal, image and video technology 9, no. 1-2 (January 1995): 89–104. http://dx.doi.org/10.1007/bf02406472.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

15

Nishikawa, Hiroki, Kenta Shirane, Ryohei Nozaki, Ittetsu Taniguchi, and Hiroyuki Tomiyama. "Function‐level module sharing techniques in high‐level synthesis." ETRI Journal 42, no. 4 (August 2020): 527–33. http://dx.doi.org/10.4218/etrij.2020-0107.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

16

Zheng, Hongbin, Swathi T. Gurumani, Liwei Yang, Deming Chen, and Kyle Rupnow. "High-Level Synthesis With Behavioral-Level Multicycle Path Analysis." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 33, no. 12 (December 2014): 1832–45. http://dx.doi.org/10.1109/tcad.2014.2361661.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

17

Herklotz, Yann, James D. Pollard, Nadesh Ramanathan, and John Wickerson. "Formal verification of high-level synthesis." Proceedings of the ACM on Programming Languages 5, OOPSLA (October 20, 2021): 1–30. http://dx.doi.org/10.1145/3485494.

Повний текст джерела

Анотація:

High-level synthesis (HLS), which refers to the automatic compilation of software into hardware, is rapidly gaining popularity. In a world increasingly reliant on application-specific hardware accelerators, HLS promises hardware designs of comparable performance and energy efficiency to those coded by hand in a hardware description language such as Verilog, while maintaining the convenience and the rich ecosystem of software development. However, current HLS tools cannot always guarantee that the hardware designs they produce are equivalent to the software they were given, thus undermining any reasoning conducted at the software level. Furthermore, there is mounting evidence that existing HLS tools are quite unreliable, sometimes generating wrong hardware or crashing when given valid inputs. To address this problem, we present the first HLS tool that is mechanically verified to preserve the behaviour of its input software. Our tool, called Vericert, extends the CompCert verified C compiler with a new hardware-oriented intermediate language and a Verilog back end, and has been proven correct in Coq. Vericert supports most C constructs, including all integer operations, function calls, local arrays, structs, unions, and general control-flow statements. An evaluation on the PolyBench/C benchmark suite indicates that Vericert generates hardware that is around an order of magnitude slower (only around 2× slower in the absence of division) and about the same size as hardware generated by an existing, optimising (but unverified) HLS tool.

Стилі APA, Harvard, Vancouver, ISO та ін.

18

Lyuh, C. G., T. Kim, and K. W. Kim. "Coupling-Aware High-Level Interconnect Synthesis." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23, no. 1 (January 2004): 157–64. http://dx.doi.org/10.1109/tcad.2003.819892.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

19

Kundu, Sudipta, Sorin Lerner, and Rajesh K. Gupta. "Translation Validation of High-Level Synthesis." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29, no. 4 (April 2010): 566–79. http://dx.doi.org/10.1109/tcad.2010.2042889.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

20

Coussy, Philippe, and Andres Takach. "Special Issue on High-Level Synthesis." IEEE Design & Test of Computers 25, no. 5 (September 2008): 393. http://dx.doi.org/10.1109/mdt.2008.147.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

21

Coussy, P., D. D. Gajski, M. Meredith, and A. Takach. "An Introduction to High-Level Synthesis." IEEE Design & Test of Computers 26, no. 4 (July 2009): 8–17. http://dx.doi.org/10.1109/mdt.2009.69.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

22

Coussy, Philippe, Ghizlane Lhairech-Lebreton, and Dominique Heller. "Multiple Word-Length High-Level Synthesis." EURASIP Journal on Embedded Systems 2008, no. 1 (2008): 916867. http://dx.doi.org/10.1155/2008/916867.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

23

Georgakakis, Spyridon, and John Evans. "Overview of high level synthesis tools." Journal of Instrumentation 6, no. 02 (February 18, 2011): C02005. http://dx.doi.org/10.1088/1748-0221/6/02/c02005.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

24

Prihozhy, A. "Net scheduling in high-level synthesis." IEEE Design & Test of Computers 13, no. 1 (1996): 26–35. http://dx.doi.org/10.1109/54.485780.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

25

Lin, Colin Yu, Zhenghong Jiang, Cheng Fu, Hayden Kwok-Hay So, and Haigang Yang. "FPGA High-level Synthesis versus Overlay." ACM SIGARCH Computer Architecture News 44, no. 4 (January 11, 2017): 92–97. http://dx.doi.org/10.1145/3039902.3039919.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

26

Ghosh, Indradeep, and Niraj K. Jha. "High-level test synthesis: a survey." Integration 26, no. 1-2 (December 1998): 79–99. http://dx.doi.org/10.1016/s0167-9260(98)00022-4.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

27

Ismaeel, A. A., R. Bhatnagar, and R. Mathew. "Concurrent testing in high level synthesis." Microelectronics Reliability 40, no. 12 (December 2000): 2095–106. http://dx.doi.org/10.1016/s0026-2714(00)00028-7.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

28

Lakshminarayana, G., A. Raghunathan, N. K. Jha, and S. Dey. "Power management in high-level synthesis." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 7, no. 1 (March 1999): 7–15. http://dx.doi.org/10.1109/92.748195.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

29

Winterstein, Felix J., Samuel R. Bayliss, and George A. Constantinides. "Separation Logic for High-Level Synthesis." ACM Transactions on Reconfigurable Technology and Systems 9, no. 2 (February 3, 2016): 1–23. http://dx.doi.org/10.1145/2836169.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

30

Lin, Youn-Long. "Recent developments in high-level synthesis." ACM Transactions on Design Automation of Electronic Systems 2, no. 1 (January 1997): 2–21. http://dx.doi.org/10.1145/250243.250245.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

31

Keinprasit, Rachaporn, and Prabhas Chongstitvatana. "High-level synthesis by dynamic ant." International Journal of Intelligent Systems 19, no. 1-2 (January 2004): 25–38. http://dx.doi.org/10.1002/int.10148.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

32

TATSUOKA, Masato, and Mineo KANEKO. "High Level Congestion Detection from C/C++ Source Code for High Level Synthesis." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E103.A, no. 12 (December 1, 2020): 1437–46. http://dx.doi.org/10.1587/transfun.2020vlp0012.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

33

Verdier, François S., and Bertrand Zavidovique. "A High Level Synthesis System for VLSI Image Processing Applications." VLSI Design 7, no. 4 (January 1, 1998): 321–36. http://dx.doi.org/10.1155/1998/95421.

Повний текст джерела

Анотація:

We present a VLSI synthesis environment dedicated to the design of image processing architectures. The environment includes a “front-end” data-flow emulator for validation of the algorithms and the RTL-synthesis system called ALPHA. The latter implements a stochastic search in the design space and produces efficient solutions considering the “restricted” domain of concerned applications. Two simulated Annealing (SA) algorithms run in sequence for data-path synthesis (scheduling and module selection) and then for control synthesis and data-path completion (binding). An interesting feature of the first optimization is the use of the data-flow graph regularity to predict the control influence in terms of the future design. A few designs have already been compiled under this environment including a default detector presented here.

Стилі APA, Harvard, Vancouver, ISO та ін.

34

Aytekin, Metin, Suzy A. A. Comhair, Carol de la Motte, Sudip K. Bandyopadhyay, Carol F. Farver, Vincent C. Hascall, Serpil C. Erzurum, and Raed A. Dweik. "High levels of hyaluronan in idiopathic pulmonary arterial hypertension." American Journal of Physiology-Lung Cellular and Molecular Physiology 295, no. 5 (November 2008): L789—L799. http://dx.doi.org/10.1152/ajplung.90306.2008.

Повний текст джерела

Анотація:

Hyaluronan (HA), a large glycosaminoglycan found in the ECM, has major roles in lung and vascular biology and disease. However, its role in idiopathic pulmonary arterial hypertension (IPAH) is unknown. We hypothesized that HA metabolism is abnormal in IPAH. We measured the plasma levels of HA in IPAH and healthy individuals. We also evaluated HA synthesis and the expression of HA synthases and hyaluronidases in pulmonary artery smooth muscle cells (PASMCs) from explanted lungs. Plasma HA levels were markedly elevated in IPAH compared with controls [HA (ng/ml, mean ± SD): IPAH 325 ± 80, control 28 ± 9; P = 0.02]. In vitro, unstimulated IPAH PASMCs produced high levels of HA compared with control cells [HA in supernatant (μg/ml, mean ± SD): IPAH 12 ± 2, controls 6 ± 0.9; P = 0.04]. HA levels were also higher in IPAH PASMC lysates. The increased HA was biologically relevant as shown by tissue staining and increased HA-specific binding of mononuclear cells to IPAH compared with control PASMCs [number of bound cells × 104 (mean ± SD): IPAH 9.5 ± 3, control 3.0 ± 1; P = 0.01]. This binding was abrogated by the addition of hyaluronidase. HA synthase-2 and hyaluronidase-2 were predominant in control and IPAH PASMCs. Interestingly, the expressions of HA synthase-2 and hyaluronidase-2 were ∼2-fold lower in IPAH compared with controls [HA synthase-2 (relative expression mean ± SE): IPAH 4.3 ± 0.02, control 7.8 ± 0.1; P = 0.0004; hyaluronidase-2 (relative expression mean ± SE): IPAH 4.2 ± 0.06, control 7.6 ± 0.07; P = 0.008]. Thus patients with IPAH have higher circulating levels of HA, and PASMCs derived from IPAH lungs produce more HA compared with controls. This is associated with increased tissue levels and increased binding of inflammatory cells suggesting a role for HA in remodeling and inflammation in IPAH.

Стилі APA, Harvard, Vancouver, ISO та ін.

35

Pilászy, György, György Rácz, and Péter Arató. "Communication Time Estimation in High Level Synthesis." Periodica Polytechnica Electrical Engineering 57, no. 4 (2013): 99. http://dx.doi.org/10.3311/ppee.7413.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

36

Zhang, Zhiru, Deming Chen, Steve Dai, and Keith Campbell. "High-level Synthesis for Low-power Design." IPSJ Transactions on System LSI Design Methodology 8 (2015): 12–25. http://dx.doi.org/10.2197/ipsjtsldm.8.12.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

37

Su, Fei, and Krishnendu Chakrabarty. "High-level synthesis of digital microfluidic biochips." ACM Journal on Emerging Technologies in Computing Systems 3, no. 4 (January 2008): 1–32. http://dx.doi.org/10.1145/1324177.1324178.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

38

Wang, W., A. Raghunathan, N. K. Jha, and S. Dey. "Resource Budgeting for Multiprocess High-Level Synthesis." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23, no. 7 (July 2004): 1010–19. http://dx.doi.org/10.1109/tcad.2004.829806.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

39

Lin Zhong and N. K. Jha. "Interconnect-aware low-power high-level synthesis." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24, no. 3 (March 2005): 336–51. http://dx.doi.org/10.1109/tcad.2004.842820.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

40

Andriamisaina, Caaliph, Philippe Coussy, Emmanuel Casseau, and Cyrille Chavet. "High-Level Synthesis for Designing Multimode Architectures." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29, no. 11 (November 2010): 1736–49. http://dx.doi.org/10.1109/tcad.2010.2062751.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

41

Ly, T. A., and J. T. Mowchenko. "Applying simulated evolution to high level synthesis." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 12, no. 3 (March 1993): 389–409. http://dx.doi.org/10.1109/43.215002.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

42

Martin, G., and G. Smith. "High-Level Synthesis: Past, Present, and Future." IEEE Design & Test of Computers 26, no. 4 (July 2009): 18–25. http://dx.doi.org/10.1109/mdt.2009.83.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

43

Sarkar, S., S. Dabral, P. K. Tiwari, and R. S. Mitra. "Lessons and Experiences with High-Level Synthesis." IEEE Design & Test of Computers 26, no. 4 (July 2009): 34–45. http://dx.doi.org/10.1109/mdt.2009.84.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

44

Yuan Xie and Yibo Chen. "Statistical High-Level Synthesis under Process Variability." IEEE Design & Test of Computers 26, no. 4 (July 2009): 78–87. http://dx.doi.org/10.1109/mdt.2009.85.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

45

Roy, J., N. Kumar, R. Dutta, and R. Vemuri. "DSS: a distributed high-level synthesis system." IEEE Design & Test of Computers 9, no. 2 (June 1992): 18–32. http://dx.doi.org/10.1109/54.143143.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

46

Camposano, R. "From behavior to structure: high-level synthesis." IEEE Design & Test of Computers 7, no. 5 (October 1990): 8–19. http://dx.doi.org/10.1109/54.60603.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

47

Ernst, R., and J. Bhasker. "Simulation-based verification for high-level synthesis." IEEE Design & Test of Computers 8, no. 1 (March 1991): 14–20. http://dx.doi.org/10.1109/54.75659.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

48

Camposano, R., L. F. Saunders, and R. M. Tabet. "VHDL as input for high-level synthesis." IEEE Design & Test of Computers 8, no. 1 (March 1991): 43–49. http://dx.doi.org/10.1109/54.75662.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

49

Lavagno, Luciano. "What is ECO for high-level synthesis?" ACM SIGDA Newsletter 39, no. 12 (December 2009): 1. http://dx.doi.org/10.1145/1862885.1862886.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

50

Bergamaschi, R. A., R. A. O'Connor, L. Stok, M. Z. Moricz, S. Prakash, A. Kuehlmann, and D. S. Rao. "High-level synthesis in an industrial environment." IBM Journal of Research and Development 39, no. 1.2 (January 1995): 131–48. http://dx.doi.org/10.1147/rd.391.0131.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

Ми пропонуємо знижки на всі преміум-плани для авторів, чиї праці увійшли до тематичних добірок літератури. Зв'яжіться з нами, щоб отримати унікальний промокод!