Дисертації з теми "High level Synthesi"
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1
Amarasinghe, V. Kosala I. "Distributed high-level synthesis." Thesis, University of Southampton, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.438696.
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2
Langer, Jan. "High-Level-Synthese von Operationseigenschaften." Doctoral thesis, Universitätsbibliothek Chemnitz, 2011. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-79059.
Повний текст джерелаАнотація:
In der formalen Verifikation digitaler Schaltkreise hat sich die Methodik der vollständigen Verifikation anhand spezieller Operationseigenschaften bewährt. Operationseigenschaften beschreiben das Verhalten einer Schaltung in einem festen Zeitintervall und können sequentiell miteinander verknüpft werden, um so das Gesamtverhalten zu spezifizieren. Zusätzlich beweist eine formale Vollständigkeitsprüfung, dass die Menge der Eigenschaften für jede Folge von Eingangssignalwerten die Ausgänge der zu verifizierenden Schaltung eindeutig und lückenlos determiniert. In dieser Arbeit wird untersucht, wie aus Operationseigenschaften, deren Vollständigkeit erfolgreich bewiesen wurde, automatisiert eine Schaltungsbeschreibung abgeleitet werden kann. Gegenüber der traditionellen Entwurfsmethodik auf Register-Transfer-Ebene (RTL) bietet dieses Verfahren zwei Vorteile. Zum einen vermeidet der Vollständigkeitsbeweis viele Arten von Entwurfsfehlern, zum anderen ähnelt eine Beschreibung mit Hilfe von Operationseigenschaften den in Spezifikationen häufig genutzten Zeitdiagrammen, sodass die Entwurfsebene der Spezifikationsebene angenähert wird und Fehler durch manuelle Verfeinerungsschritte vermieden werden. Das Entwurfswerkzeug vhisyn führt die High-Level-Synthese (HLS) einer vollständigen Menge von Operationseigenschaften zu einer Beschreibung auf RTL durch. Die Ergebnisse zeigen, dass sowohl die verwendeten Synthesealgorithmen, als auch die erzeugten Schaltungen effizient sind und somit die Realisierung größerer Beispiele zulassen. Anhand zweier Fallstudien kann dies praktisch nachgewiesen werdenThe complete verification approach using special operation properties is an accepted methodology for the formal verification of digital circuits. Operation properties describe the behavior of a circuit during a certain time interval. They can be sequentially concatenated in order to specify the overall behavior. Additionally, a formal completeness check proves that the sequence of properties consistently determines the exact value of the output signals for every valid sequence of input signal values. This work examines how a circuit description can be automatically derived from a set of operation properties whose completeness has been proven. In contrast to the traditional design flow at register-transfer level (RTL), this method offers two advantages. First, the prove of completeness helps to avoid many design errors. Second, the design of operation properties resembles the design of timing diagrams often used in textual specifications. Therefore, the design level is closer to the specification level and errors caused by refinement steps are avoided. The design tool vhisyn performs the high-level synthesis from a complete set of operation properties to a description at RTL. The results show that both the synthesis algorithms and the generated circuit descriptions are efficient and allow the design of larger applications. This is demonstrated by means of two case studies
3
Baidas, Zaher Abdulkarim. "High-level floating-point synthesis." Thesis, University of Southampton, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.325049.
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4
Abbas, Naeem. "Acceleration of a bioinformatics application using high-level synthesis." Phd thesis, École normale supérieure de Cachan - ENS Cachan, 2012. http://tel.archives-ouvertes.fr/tel-00847076.
Повний текст джерелаАнотація:
The revolutionary advancements in the field of bioinformatics have opened new horizons in biological and pharmaceutical research. However, the existing bioinformatics tools are unable to meet the computational demands, due to the recent exponential growth in biological data. So there is a dire need to build future bioinformatics platforms incorporating modern parallel computation techniques. In this work, we investigate FPGA based acceleration of these applications, using High-Level Synthesis. High-Level Synthesis tools enable automatic translation of abstract specifications to the hardware design, considerably reducing the design efforts. However, the generation of an efficient hardware using these tools is often a challenge for the designers. Our research effort encompasses an exploration of the techniques and practices, that can lead to the generation of an efficient design from these high-level synthesis tools. We illustrate our methodology by accelerating a widely used application -- HMMER -- in bioinformatics community. HMMER is well-known for its compute-intensive kernels and data dependencies that lead to a sequential execution. We propose an original parallelization scheme based on rewriting of its mathematical formulation, followed by an in-depth exploration of hardware mapping techniques of these kernels, and finally show on-board acceleration results. Our research work demonstrates designing flexible hardware accelerators for bioinformatics applications, using design methodologies which are more efficient than the traditional ones, and where resulting designs are scalable enough to meet the future requirements.
5
Lawrence, Bleddyn Idris. "High level synthesis with interconnect prediction." Thesis, University of Southampton, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.437114.
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6
Yeung, Ping F. "High-level synthesis of VLSI circuits." Thesis, University of Edinburgh, 1992. http://hdl.handle.net/1842/11647.
Повний текст джерелаАнотація:
Following the widespread acceptance and application of logic synthesis, we are on the way to establishing synthesis methodologies which can handle higher levels of abstraction. High-level synthesis is the focal point. It should be able to take a behavioural description of the design, a set of constraints and goals, then construct a structural implementation that performs the circuit function while satisfying the constraints. In order to ensure a smooth transformation and mapping of high-level description onto hardware, a new strategy for high-level synthesis, flexibility damping, is introduced. It allows a large design space to be explored progressively and systematically. It facilitates the propagation of constraints and helps the introduction of user-specified information. To carry out the strategy, two algorithms, resource restricted scheduling and integrated concurrent mapping are developed. Resource restricted scheduling handles complex control structures and schedules operations across basic blocks in order to utilise all the available resources. After the scheduling has established the flexibility of the abstract elements, concurrent mapping is performed to bind operations, storage, and communications onto functional units, register files and buses concurrently. By considering all the resources at the same time, this mapping process ensures an overall minimum cost of implementation.
7
Fallside, Hamish. "High level synthesis of memory architectures." Thesis, University of Edinburgh, 1995. http://hdl.handle.net/1842/10882.
Повний текст джерелаАнотація:
The development of high level tools for electronic design has been driven by the increasing demands of an ever more complex design process. The diversification in the use of electronic circuitry requires design tools tailored to application specific domains. Intelligent synthesis requires domain specific knowledge in addition to general synthesis techniques. The preponderance of synthesis systems in domains such as Digital Signal Processing is indicative of this need. Methods are presented here for the synthesis of memory architectures in one such domain: image processing. The research concentrates on performance synthesis. The techniques presented aim to optimise the design so as to minimise the memory access bottleneck of the eventual hardware implementation. The development of a synthesis system is described which serves to support the research. Algorithmic descriptions, coded in C, are processed by the tool in order to produce a structural description of a memory architecture able to implement the presented algorithms in hardware. Data flow and dependence analysis techniques are employed, these address the "high levelness" of the input algorithm, an important task if the designer is to be relieved of low level design detail. Methods for organising the algorithm's data in, and it's access from memory are presented, and experimental results are included. The organisation of data in memory is accomplished as part of the scheduling process for the user algorithm. The methods aim to optimise the hardware implementation by maximising the utilisation of the memory resources allocated during synthesis. In dealing with the access of data from memory, methods are presented for the automatic detection of memory inefficient structures in the user description, and their transformation into a representation yielding synthesised designs with greater memory throughput. Such designs are better able to support the user's algorithms within desired performance limitations. Examples are included which provide an evaluation of the techniques' efficacy.
8
Finlay, Iain William. "High-level synthesis using structural input." Thesis, University of Edinburgh, 1992. http://hdl.handle.net/1842/14849.
Повний текст джерелаАнотація:
The task of a high-level behavioural synthesis system is to create a structure to implement a given abstract specification of behaviour. The behaviour is specified at the algorithmic level, typically in the form of a high-level programming language. The synthesized structure is described at the register-transfer level. In such systems the synthesis task is guided only by the behaviour and some physical design constraints such as speed and area. This approach frequently leads to difficulties in synthesizing a suitable architecture. The synthesis system reported in this thesis tackles this problem by enabling the designer to specify structural input alongside the behaviour. The structural input is described at the register-transfer level and need not define a complete structure. The synthesis tool makes use of this input structure by incorporating it into the design where appropriate or as instructed. This structurally directed approach is shown to give the designer greater control over structural aspects of the design in addition to enabling greater exploration of possible structural solutions.
9
Schmidt, Marco, Ulrich Möhrke, and Paul Herrmann. "Verhaltensbeschreibung in der High-Level Synthese." Universität Leipzig, 1996. https://ul.qucosa.de/id/qucosa%3A34506.
Повний текст джерелаАнотація:
Was versteht man unter High-Level Synthese? Wie beschreibt man das Verhalten einer Schaltung in VHDL? Diese zwei Fragen sollen hier
erörtert werden. Zuerst wird kurz das High-Level Synthese Programm Caddy vorgestellt und die internen Verarbeitungsschritte kurz aufgezeigt. Dann werden die verschiedenen Stufen der Schaltungsbeschreibbung mit ihren jeweiligen Vor- und Nachteilen diskutiert. Zum Schluss wird noch auf die Grenzen von VHDL-Verhaltensbeschreibungen eingegangen und mögliche Lösungsvorschläge gemacht, um diese Grenzen zu erweitern. Es wird im Grossen und Ganzen nur die momentane Entwicklung zusammengefasst. Dabei soll dieser Bericht auch als Anleitung zur VHDL-Verhaltensbeschreibung dienen.
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Uguen, Yohann. "High-level synthesis and arithmetic optimizations." Thesis, Lyon, 2019. http://www.theses.fr/2019LYSEI099.
Повний текст джерелаАнотація:
À cause de la nature relativement jeune des outils de synthèse de haut-niveau (HLS), de nombreuses optimisations arithmétiques n'y sont pas encore implémentées. Cette thèse propose des optimisations arithmétiques se servant du contexte spécifique dans lequel les opérateurs sont instanciés. Certaines optimisations sont de simples spécialisations d'opérateurs, respectant la sémantique du C. D'autres nécessitent de s'éloigner de cette sémantique pour améliorer le compromis précision/coût/performance. Cette proposition est démontrée sur des sommes de produits de nombres flottants. La somme est réalisée dans un format en virgule-fixe défini par son contexte. Quand trop peu d’informations sont disponibles pour définir ce format en virgule-fixe, une stratégie est de générer un accumulateur couvrant l'intégralité du format flottant. Cette thèse explore plusieurs implémentations d'un tel accumulateur. L'utilisation d'une représentation en complément à deux permet de réduire le chemin critique de la boucle d'accumulation, ainsi que la quantité de ressources utilisées. Un format alternatif aux nombres flottants, appelé posit, propose d'utiliser un encodage à précision variable. De plus, ce format est augmenté par un accumulateur exact. Pour évaluer précisément le coût matériel de ce format, cette thèse présente des architectures d'opérateurs posits, implémentés avec le même degré d'optimisation que celui de l'état de l'art des opérateurs flottants. Une analyse détaillée montre que le coût des opérateurs posits est malgré tout bien plus élevé que celui de leurs équivalents flottants. Enfin, cette thèse présente une couche de compatibilité entre outils de HLS, permettant de viser plusieurs outils avec un seul code. Cette bibliothèque implémente un type d'entiers de taille variable, avec de plus une sémantique strictement typée, ainsi qu'un ensemble d'opérateurs ad-hoc optimisésHigh-level synthesis (HLS) tools offer increased productivity regarding FPGA programming. However, due to their relatively young nature, they still lack many arithmetic optimizations. This thesis proposes safe arithmetic optimizations that should always be applied. These optimizations are simple operator specializations, following the C semantic. Other require to a lift the semantic embedded in high-level input program languages, which are inherited from software programming, for an improved accuracy/cost/performance ratio. To demonstrate this claim, the sum-of-product of floating-point numbers is used as a case study. The sum is performed on a fixed-point format, which is tailored to the application, according to the context in which the operator is instantiated. In some cases, there is not enough information about the input data to tailor the fixed-point accumulator. The fall-back strategy used in this thesis is to generate an accumulator covering the entire floating-point range. This thesis explores different strategies for implementing such a large accumulator, including new ones. The use of a 2's complement representation instead of a sign+magnitude is demonstrated to save resources and to reduce the accumulation loop delay. Based on a tapered precision scheme and an exact accumulator, the posit number systems claims to be a candidate to replace the IEEE floating-point format. A throughout analysis of posit operators is performed, using the same level of hardware optimization as state-of-the-art floating-point operators. Their cost remains much higher that their floating-point counterparts in terms of resource usage and performance. Finally, this thesis presents a compatibility layer for HLS tools that allows one code to be deployed on multiple tools. This library implements a strongly typed custom size integer type along side a set of optimized custom operators
11
Winterstein, Felix. "Separation logic for high-level synthesis." Thesis, Imperial College London, 2016. http://hdl.handle.net/10044/1/33371.
Повний текст джерелаАнотація:
High-level synthesis (HLS) promises a significant shortening of the digital hardware design cycle by raising the abstraction level of the design entry to high-level languages such as C/C++. However, applications using dynamic, pointer-based data structures remain difficult to implement well, yet such constructs are widely used in software. Automated optimisations that leverage the memory bandwidth of dedicated hardware implementations by distributing the application data over separate on-chip memories and parallelise the implementation are often ineffective in the presence of dynamic data structures, due to the lack of an automated analysis that disambiguates pointer-based memory accesses. This thesis takes a step towards closing this gap. We explore recent advances in separation logic, a rigorous mathematical framework that enables formal reasoning about the memory access of heap-manipulating programs. We develop a static analysis that automatically splits heap-allocated data structures into provably disjoint regions. Our algorithm focuses on dynamic data structures accessed in loops and is accompanied by automated source-to-source transformations which enable loop parallelisation and physical memory partitioning by off-the-shelf HLS tools. We then extend the scope of our technique to pointer-based memory-intensive implementations that require access to an off-chip memory. The extended HLS design aid generates parallel on-chip multi-cache architectures. It uses the disjointness property of memory accesses to support non-overlapping memory regions by private caches. It also identifies regions which are shared after parallelisation and which are supported by parallel caches with a coherency mechanism and synchronisation, resulting in automatically specialised memory systems. We show up to 15x acceleration from heap partitioning, parallelisation and the insertion of the custom cache system in demonstrably practical applications.
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Gremzow, Carsten. "High-Level-Synthese aus flachen Kontroll-/Datenflussgraphen." [S.l.] : [s.n.], 2004. http://deposit.ddb.de/cgi-bin/dokserv?idn=970644744.
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TOMIYAMA, Hiroyuki, Hiroyuki KANBARA, Yoshiyuki ISHIMORI, Nagisa ISHIURA, and Masanari NISHIMURA. "High-Level Synthesis of Software Function Calls." Institute of Electronics, Information and Communication Engineers, 2008. http://hdl.handle.net/2237/15044.
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14
Wang, Xiaojun. "An interactive, high-level logic synthesis system." Thesis, Staffordshire University, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.387386.
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15
Patterson, Isaac. "Trustworthy system development through high-level synthesis." Thesis, Monterey, California: Naval Postgraduate School, 2014. http://hdl.handle.net/10945/43974.
Повний текст джерелаАнотація:
Approved for public release; distribution is unlimitedMajor processor manufacturers have embraced the high-level synthesis (HLS) design philosophy. HLS offers the potential to explore the design space of electronic circuits and systems more efficiently than traditional methods. In this thesis, we investigate the ap-plication of HLS to hardware-oriented security and trust by developing a model of a simple 16-bit Central Processing Unit in the SystemC modeling language. We enhanced our processor with a simple security mechanism that enforces a memory integrity policy. The integrity policy allows a region of the program labeled as trustworthy to modify any address in data memory, but another region of the program labeled as untrustworthy is restricted to only being able to modify a specific region of data memory. Our timing results show that adding the integrity policy enforcement mechanism has a negligible effect on overall system performance.
16
Collis, G. V. "A prototype high level hardware synthesis system." Thesis, University of Manchester, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.234891.
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17
Oikonomakos, Petros. "High-level synthesis for on-line testability." Thesis, University of Southampton, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.414359.
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Liu, Junyi. "Parametric polyhedral optimisation for high-level synthesis." Thesis, Imperial College London, 2017. http://hdl.handle.net/10044/1/64814.
Повний текст джерелаАнотація:
High-level synthesis (HLS) improves hardware design productivity by using high-level programming languages for design entry. Although various automatic optimisations have been supported in modern HLS tools, manual effort is still required to achieve sufficient hardware acceleration. Loop pipelining is one of the most important opti- mization methods in HLS for increasing loop parallelism. In this thesis, we extend the capability of loop pipelining in HLS to handle loops with uncertain dependencies (i.e., parameterised by an undetermined variable) and/or non-uniform dependencies (i.e., varying between loop iterations). Our optimisations allow a pipeline to be scheduled without the aforementioned memory dependencies at compile time, but an associated controller will change the execution speed of loop iterations at runtime. A parametric polyhedral analysis is developed to generate the control logic and is integrated in an automated source-to-source code transformation framework. Experiments over a suite of benchmarks show that transformed pipelines can achieve 3.7-11× faster acceleration with a reasonable resource overhead. To tackle the challenge of memory and communication bottlenecks, we have also developed a tile size selection for loop tiling to improve data locality. The size of the tiles, which can significantly affect the memory requirement, is usually determined by partial enumeration. We propose an analytical methodology in this thesis to automate the selection of a tile size for optimised memory reuse in HLS. A new parametric polyhedral analysis for memory mapping is introduced to capture memory usage analytically for arbitrary tile sizes. To determine the tile size for data reuse in constrained on-chip memory, an algorithm is then developed to optimize over this model, using non-linear solvers to minimize communication overhead. We show experimentally that our tile size selection can quickly produce high-quality solutions associated with an efficient memory mapping.
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Mahmood, Hassan. "Crest Factor Reduction using High Level Synthesis." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-229437.
Повний текст джерелаАнотація:
Modern wireless mobile communication technology has made noticeable improvements from the technologies in the past but is still plagued by poor power efficiency of power amplifiers found in today’s base stations. One of the factors that affect the power efficiency adversely comes from modern modulation techniques like orthogonal frequency division multiplexing which result in signals with high peak to average power ratio, also known as the crest factor. Crest factor reduction algorithms are used to solve this problem. However, the dominant method of hardware description for synthesis has been to start with writing register transfer level code which gives a very fixed implementation that may not be the optimal solution. This thesis project is focused on developing a peak cancellation crest factor reduction system, using a high-level language as the system design language, and synthesizing it using high-level synthesis. The aim is to find out if highlevel synthesis design methodology can yield increased productivity and improved quality of results for such designs as compared to the design methodology that requires the system to be implemented at the register transfer level. Design space exploration is performed to find an optimal design with respect to area. Finally, a few parameters are presented to measure the performance of the system, which helps in tuning it. The results of design space exploration helped in choosing the best possible implementation out of four different configurations. The final implementation that resulted from high-level synthesis had an area comparable to the previous register transfer level implementation. It was also concluded that, for this design, the high-level synthesis design methodology increased productivity and decreased design time.Användning av högnivåsyntes för reduktion av toppfaktor Det har gjorts noterbara framsteg inom modern trådlös kommunikationsteknik för mobiltelefoni, men tekniken plågas fortfarande av dålig energieffektivitet hos förstärkarna i dagens basstationer. En faktor som påverkar energieffektiviteten negativt är om signaler har en stor skillnad mellan maximal effekt och medeleffekt. Kvoten mellan maximal effekt och medeleffekt kallas för toppfaktor, och en egenskap hos moderna moduleringstekniker, såsom ortogonal frekvensdelningsmodulering, är att de har en hög toppfaktor. Algoritmer för reducering av toppfaktor kan lösa det problemet. Den dominerande metoden för design av hårdvara är att skriva kod i ett hårdvarubeskrivande språk med abstraktionsnivån Register Transfer Level och sedan använda verktyg för att syntetisera hårdvara från koden. Resultatet är en specifik implementation som inte nödvändigtvis är den optimala lösningen. Det här examensarbetet är inriktat på att utveckla ett system för reducering av toppfaktor, baserat på algoritmen Peak Cancellation, genom att skriva kod i ett högnivåspråk och använda verktyg för högnivåsyntes för att syntetisera designen. Syftet är att ta reda på om högnivåsyntes som designmetod kan ge ökad produktivitet och ökad kvalitet, för den här typen av design, jämfört med den klassiska designmetoden med abstraktionsnivån Register Transfer Level. Verktyget för högnivåsyntes användes för att på ett effektivt sätt undersöka olika designalternativ för att optimera kretsytan. I rapporten presenteras ett antal parametrar för att mäta prestandan hos systemet, vilket ger information som kan användas för finjustering. Resultatet av undersökningen av designalternativ gjorde det möjligt att välja den bästa implementationen bland fyra olika konfigurationer. Den slutgiltiga implementationen hade en kretsyta som är jämförbar med en tidigare design som implementerats med hårdvarubeskrivande språk med abstraktionsnivån Register Transfer Level. En annan slutsats är att, för den här designen, så gav designmetoden med högnivåsyntes ökad produktivitet och minskad designtid.
20
Xiao, Chenglong. "Custom operator identification for high-level synthesis." Rennes 1, 2012. http://www.theses.fr/2012REN1E005.
Повний текст джерелаАнотація:
Il est de plus en plus fréquent de faire appel à des opérateurs spécifiques en conception de circuits. Les opérateurs spécifiques peuvent être mis en œuvre par des unités matérielles dédiées, en vue de réduire la taille du code, d’améliorer les performances et de réduire la surface du circuit. Dans cette thèse, nous proposons un flot de conception basé sur l’identification d’opérateurs spécifiques pour la synthèse de haut niveau. Les points clés de ce flot de conception sont l’énumération automatique et la sélection des opérateurs spécifiques à partir d'un code de l'application de haut niveau et la re-génération du code source intégrant les opérateurs spécifiques sélectionnés. Contrairement aux approches proposées précédemment, notre flot de conception est adaptable et est indépendant des outils de synthèse de haut niveau (il ne nécessite pas d’intervenir sur les algorithmes d’ordonnancement et de projection des outils de synthèse de haut niveau). Les résultats expérimentaux montrent que notre approche permet de réduire la surface du circuit de 19% en moyenne, et jusqu'à 37% dans certains cas, par rapport à une synthèse de haut niveau traditionnelle. La latence du circuit est réduite en moyenne de 22%, et atteint jusqu'à 59%. De plus, la taille du code est réduite de 74% en moyenneIt is increasingly common to see custom operators appear in various fields of circuit design. Custom operators that can be implemented in special hardware units make it possible to reduce code size, improve performance and reduce area. In this thesis, we propose a design flow based on custom operator identification for high-level synthesis. The key issues involved in the design flow are: automatic enumeration and selection of custom operators from a given high-level application code and re-generation of the source code incorporating the selected custom operators. Unlike the previously proposed approaches, our design flow is quite adaptable and is independent of high-level synthesis tools (i. E. , without modifying the scheduling and binding algorithms in high-level synthesis tools). Experimental results show that our approach achieves on average 19%, and up to 37% area reduction, compared to a traditional high-level synthesis. Meanwhile, the latency is reduced on average by 22%, and up to 59%. Furthermore, on average 74% and up to 81% code size reduction can be achieved
21
Hänninen, T. (Tony). "Intelin High Level Synthesis Compiler -ohjelman ominaisuudet." Bachelor's thesis, University of Oulu, 2019. http://jultika.oulu.fi/Record/nbnfioulu-201905141748.
Повний текст джерелаАнотація:
Abstract. The increasing complexity of systems and applications increases workload and makes development cycles longer. High-Level Synthesis (HLS) tools have been developed to alleviate this by raising the level of abstraction from Register Transfer Level (RTL). This work introduces the basics of Field Programmable Gate Arrays (FPGA) and HLS. The Intel HLS Compiler and its features are studied in more detail. Intel HLS compiler is a commercial HLS tool, which takes in untimed C++ as input and generates production-quality RTL that is optimized for Intel FPGAs.Intelin High Level Synthesis Compiler -ohjelman ominaisuudet. Tiivistelmä. Laitteistojen ja systeemien kasvava kompleksisuus kasvattaa työmäärää ja pidentää suunnitteluvuohon kuluvaa aikaa. Korkean tason synteesin (HLS) työkalut ovat kehitetty automatisoimaan ja nopeuttamaan digitaalisuunnittelua nostamalla abstraktiotasoa korkeammalle rekisterinsiirtotasolta (RTL). Tässä työssä kuvataan FPGA-piirien ja HLS:n perusperiaatteet, jonka jälkeen Intel HLS Compiler -työkalua tutkitaan tarkemmin. Intel HLS Compiler on työkalu, joka generoi RTL-koodia C++-kielellä kirjoitetuista algoritmeista.
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Joshi, Manasi. "On Reverse Engineering of Encrypted High Level Synthesis Designs." University of Cincinnati / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1535466997060049.
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HUANG, RENQIU. "PHYSICAL AWARE HIGH LEVEL SYNTHESIS AND INTERCONNECT FOR FPGAs." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1147616884.
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Nourani-Dargiri, Mehrdad. "Area and delay estimation for constraint-driven high-level synthesis." Case Western Reserve University School of Graduate Studies / OhioLINK, 1994. http://rave.ohiolink.edu/etdc/view?acc_num=case1057603424.
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Tran, Mai-Thanh. "Towards hardware synthesis of a flexible radio from a high-level language." Thesis, Rennes 1, 2018. http://www.theses.fr/2018REN1S072/document.
Повний текст джерелаАнотація:
La radio logicielle est une technologie prometteuse pour répondre aux exigences de flexibilité des nouvelles générations de standards de communication. Elle peut être facilement reprogrammée au niveau logiciel pour implémenter différentes formes d'onde. En s'appuyant sur une technologie dite logicielle telle que les microprocesseurs, cette approche est particulièrement flexible et assez facile à mettre en œuvre. Cependant, ce type de technologie conduit généralement à une faible capacité de calcul et, par conséquent, à des débit faibles. Pour résoudre ce problème, la technologie FPGA s'avère être une bonne alternative pour la mise en œuvre de la radio logicielle. En effet, les FPGAs offrent une puissance de calcul élevée et peuvent être reconfigurés. Ainsi, inclure des FPGAs dans le concept de radio logicielle peut permettre de prendre en charge plus de formes d'onde avec des exigences plus strictes qu'une approche basée sur la technologie logicielle. Cependant, les principaux inconvénients d’une conception à base de FPGAs sont le niveau du langage de description d'entrée qui doit typiquement être le niveau matériel, et le temps de reconfiguration qui peut dépasser les exigences d'exécution si le FPGA est entièrement reconfiguré. Pour surmonter ces problèmes, cette thèse propose une méthodologie de conception qui exploite à la fois la synthèse de haut niveau et la reconfiguration dynamique. La méthodologie proposée donne un cadre pour construire une radio flexible pour la radio logicielle à base de FPGAs et qui peut être reconfigurée pendant l'exécutionSoftware defined radio (SDR) is a promising technology to tackle flexibility requirements of new generations of communication standards. It can be easily reprogrammed at a software level to implement different waveforms. When relying on a software-based technology such as microprocessors, this approach is clearly flexible and quite easy to design. However, it usually provides low computing capability and therefore low throughput performance. To tackle this issue, FPGA technology turns out to be a good alternative for implementing SDRs. Indeed, FPGAs have both high computing power and reconfiguration capacity. Thus, including FPGAs into the SDR concept may allow to support more waveforms with more strict requirements than a processor-based approach. However, main drawbacks of FPGA design are the level of the input description language that basically needs to be the hardware level, and, the reconfiguration time that may exceed run-time requirements if the complete FPGA is reconfigured. To overcome these issues, this PhD thesis proposes a design methodology that leverages both high-level synthesis tools and dynamic reconfiguration. The proposed methodology is a guideline to completely build a flexible radio for FPGA-based SDR, which can be reconfigured at run-time
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Namvar, Gharehshiran Amir. "High Level Synthesis Evaluation of Tools and Methodology." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-177362.
Повний текст джерелаАнотація:
The advances in silicon technology, as well as competitive time to market, in the recent decade have forced the design tools and methodologies to progress towards higher levels of abstraction. Raising the level of abstraction shortens the design cycle via elimination of details in design specification. One such new methodology is High Level Synthesis (HLS). HLS tools accept the behavioral design in the abstract level as the input and generate the detailed Register Transfer Level (RTL) code. In this thesis project, the HLS methodology is introduced in the design flow and its advantages are outlined. We then evaluate and compare three HLS tools developed by market leading vendors, namely, C-to-Silicon, CatapultC and Synphonycc. To compare the HLS tools, an HLS input is developed for one of the Ericsson’s designs and the generated RTL is compared with the hand-written RTL based on several performance criteria. Thereof, we discuss the choice of the best tool so as to facilitate adoption of HLS in Ericsson’s design flow. At last, capability of the HLS tools in the synthesis of designs with pure control flow is investigated.
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Ghatraju, Lakshmikanth. "Frontiers for high-level synthesis of digital circuits." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/nq24073.pdf.
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Hettiaratchi, Sambuddhi Sinha Bandara. "Power optimized memory access in high-level synthesis." Thesis, Imperial College London, 2003. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.407906.
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Baguma, Gerald. "High Level Synthesis of FPGA-Based Digital Filters." Thesis, Uppsala universitet, Institutionen för informationsteknologi, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-232414.
Повний текст джерелаАнотація:
This thesis work is aimed at the high level synthesis of FPGA based IIR digital filters using Vivado HLS produced by Xilinx and HDL coder produced by MathWorks. The Higher Layer Model of the filter was designed in Vivado HLS, MATLAB and Simulink. Simulations, verification and Synthesis of the RTL code was done for both tools. Further optimizations were done so that the final design could meet the area, timing and throughput requirements. The resulting designs were later evaluated to see which of them satisfies the design objectives specified. This thesis work has revealed that Vivado HLS is able to generate more efficient designs than the HDL coder. Vivado provides the designer with more granularity to control scheduling and binding, the two processes at the heart of HLS. In addition, both tools provide the designer with transparency from modeling up to verification of the RTL code. HDL coder did not meet timing. Vivado HLS on the other hand met the timing requirements. The limitations of each design flow are also discussed in this report. A review of the tools available on the market today was also done and recommendations about them made. Finally, this thesis work recommends that ABB HVDC should adopt the HLS methodology using Vivado in order to achieve accelerated development. More work should be done to evaluate the possibility of auto C/C++ code generation for RTL synthesis in Vivado. Lastly, an evaluation on the LabVIEW environment should be done as an alternative to the HLS methodology.
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Ziyuan, Jiang. "Synthesis of GPU Programs from High-Level Models." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-230163.
Повний текст джерелаАнотація:
Modern graphics processing units (GPUs) provide high-performance general purpose computation abilities. They have massive parallel architectures that are suitable for executing parallel algorithms and operations. They are also throughput-oriented devices that are optimized to achieve high throughput for stream processing. Designing efficient GPU programs is a notoriously difficult task. The ForSyDe methodology is suitable to ease the difficulties of GPU programming. The methodology encourages software development from a high level of abstraction and then transforming the abstract model to an implementation through a series of formal methods. The existing ForSyDe models support the synchronous data flow (SDF) model of computation (MoC) which is suitable for modeling stream computations and is good for synthesizing efficient stream processing programs. There also exists high-level design models named parallel patterns that are suitable to represent parallel algorithms and operations. The thesis studies the method of modeling parallel algorithms using parallel patterns, and explores the way to synthesize efficient OpenCL implementation on GPUs for parallel patterns. The thesis also tries to enable the integration of parallel patterns into the ForSyDe SDF model in order to model stream parallel operations. An automation library that helps designing stream programs for parallel algorithms targeting GPUs is purposed in the thesis project. Several experiments are performed to evaluate the effectiveness of the proposed library regarding implementations of the high-level model.Moderna grafikbehandlingsenheter (GPU) tillhandahåller högpresterande generella syftes-beräkningsförmågor. De har massiva parallella arkitekturer som är lämpliga för att utföra parallella algoritmer och operationer. De är också streaminriktade enheter som är optimerade för att uppnå hög streaming för streamingbehandling. Att utforma effektiva GPU-program är en notoriskt svårt uppgift. ForSyDe-metoden är lämplig för att underlätta svårigheterna med GPU-programmering. Metodiken uppmuntrar mjukvaruutveckling från en hög nivå av abstraktion för att sedan omvandla den abstrakta modellen till en implementering genom en rad formella metoder. De befintliga ForSyDe-modellerna stöder synkron dataflöde (SDF) modell av beräkning (MoC) som är lämplig för modellering av streaming-beräkningar och är bra för att syntetisera effektiv streaming-bearbetningsprogram. Det finns också högkvalitativa designmodeller som kallas parallella mönster vilka är lämpliga för att representera parallella algoritmer och operationer. Avhandlingen analyserar metoden för modellering av parallella algoritmer med parallella mönster, och utforskar sättet att syntetisera effektiv OpenCL-implementering för GPU för parallella mönster. Avhandlingen försöker även att möjliggöra integration av parallella mönster i ForSyDe SDF-modellen för att modellera streaming parallella operationer. Ett automationsbibliotek som hjälper till att designa stream-program för parallella algoritmer som riktar sig mot GPU:er är avsedda för avhandlingsprojektet. Flera experiment utförs för att utvärdera effektiviteten hos det föreslagna biblioteket avseende implementering av högnivåmodellen.
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Lim, Stephen E. L. "A high-level methodology for VHDL-based synthesis." Thesis, University of Aberdeen, 1992. http://digitool.abdn.ac.uk/R?func=search-advanced-go&find_code1=WSN&request1=AAIU047338.
Повний текст джерелаАнотація:
A language-based design methodology for the design of digital electronic circuits has been developed and implemented. The methodology is suitable for the high-level synthesis of Very Large Scale Integrated (VLSI) circuits, which are specified behaviourally in an IEEE standard hardware description language, VHDL. The output is a register-transfer level specification of the same circuit, with a bound hardware structure that meets the designer's area and speed requirements. We believe that this work is the first high-level synthesis research to preserve VHDL simulation semantics. To this end, we have developed a process model based on the VHDL process statement onto which all behavioural descriptions can be mapped. The synthesis methodology is based on two major sets of transformations: behavioural transformations and control/data flow graph (CDFG) transformations. The first employs several known language compiler optimisation techniques with a goal to minimising data path and controller area, or making user-directed tradeoffs between data path and controller area for an improved speed. CDFG transformations are the workhorse of data path and control synthesis. A graph notation and algebra are developed that support efficient algebraic graph transformations. Data path and control synthesis algorithms that operate on our CDFG model, the VHDL Intermediate Graph (VIG), are presented. Examples from the High-Level Synthesis Workshop benchmark suite are synthesised and results shown. To round up the work, several problems and issues that face high level synthesis both in research and in the real world are discussed in this thesis.
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OUAISS, IYAD. "HIERARCHICAL MEMORY SYNTHESIS IN RECONFIGURABLE COMPUTERS." University of Cincinnati / OhioLINK, 2002. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1033498452.
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Hemmert, Karl S. "Source Level Debugging of Circuits Synthesized from High Level Language Descriptions." Diss., CLICK HERE for online access, 2004. http://contentdm.lib.byu.edu/ETD/image/etd405.pdf.
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Asthana, Rohit Mohan. "High-Level CSP Model Compiler for FPGAs." Thesis, Virginia Tech, 2010. http://hdl.handle.net/10919/36428.
Повний текст джерелаАнотація:
The ever-growing competition in current electronics industry has resulted in stringent time-to-market goals and reduced design time available to engineers. Lesser design time has subsequently raised a need for high-level synthesis design methodologies that raise the design to a higher level of abstraction. Higher level of abstraction helps in increasing the predictability and productivity of the design and reduce the number of bugs due to human-error. It also enables the designer to try out dierent optimization strategies early in the design stage. In-spite of all these advantages, high-level synthesis design methodologies have not gained much popularity in the mainstream design flow mainly because of the reasons like lack of readability and reliability of the generated register transfer level (RTL) code. The compiler framework presented in this thesis allows the user to draw high-level graphical models of the system. The compiler translates these models into synthesizeable RTL Verilog designs that exhibit their desired functionality following
communicating sequential processes (CSP) model of computation. CSP model of computation introduces a good handshaking mechanism between different components in the design that makes designs less prone to timing violations during implementation and bottlenecks while in actual operation.Master of Science
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Ellervee, Peeter. "High-level synthesis of control and memory intensive applications." Doctoral thesis, KTH, Electronic Systems Design, 2000. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-2929.
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Beikzadeh, Mohammad Reza. "Automatic high-level synthesis based upon artificial intelligence techniques." Thesis, University of Essex, 1992. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.315691.
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Nijhar, Tajinder Pal Kaur. "Source code optimisation in a high level synthesis system." Thesis, University of Southampton, 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.242110.
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Ahmadi, Arash. "An investigation of high level synthesis for computational hardware." Thesis, University of Southampton, 2007. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.443050.
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Gao, Xitong. "Structural optimization of numerical programs for high-level synthesis." Thesis, Imperial College London, 2016. http://hdl.handle.net/10044/1/42498.
Повний текст джерелаАнотація:
This thesis introduces a new technique, and its associated tool SOAP, to automatically perform source-to-source optimization of numerical programs, specifically targeting the trade-off among numerical accuracy, latency, and resource usage as a high-level synthesis flow for FPGA implementations. A new intermediate representation, MIR, is introduced to carry out the abstraction and optimization of numerical programs. Equivalent structures in MIRs are efficiently discovered using methods based on formal semantics by taking into account axiomatic rules from real arithmetic, such as associativity, distributivity and others, in tandem with program equivalence rules that enable control-flow restructuring and eliminate redundant array accesses. For the first time, we bring rigorous approaches from software static analysis, specifically formal semantics and abstract interpretation, to bear on program transformation for high-level synthesis. New abstract semantics are developed to generate a computable subset of equivalent MIRs from an original MIR. Using formal semantics, three objectives are calculated for each MIR representing a pipelined numerical program: the accuracy of computation and an estimate of resource utilization in FPGA and the latency of program execution. The optimization of these objectives produces a Pareto frontier consisting of a set of equivalent MIRs. We thus go beyond existing literature by not only optimizing the precision requirements of an implementation, but changing the structure of the implementation itself. Using SOAP to optimize the structure of a variety of real world and artificially generated arithmetic expressions in single precision, we improve either their accuracy or the resource utilization by up to 60%. When applied to a suite of computational intensive numerical programs from PolyBench and Livermore Loops benchmarks, SOAP has generated circuits that enjoy up to a 12x speedup, with a simultaneous 7x increase in accuracy, at a cost of up to 4x more LUTs.
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Duncan, Andrew A. "High level synthesis for an area efficient datapath architecture." Thesis, University of Aberdeen, 1994. http://digitool.abdn.ac.uk/R?func=search-advanced-go&find_code1=WSN&request1=AAIU069038.
Повний текст джерелаАнотація:
The advances in integrated circuit fabrication technology, coupled with the emergence of independent silicon foundries, has made it commercially viable to fabricate low volume Application Specific Integrated Circuits (ASICs). However, given the complexity of such systems it is becoming uneconomical to design them using conventional computer aided design (CAD) techniques. One approach to solving the so called "design crisis" has been to develop design tools which can synthesise an entire silicon architecture from an algorithmic description of its functionality. Such systems are referred to as high level synthesis systems. Interconnect is a major cost in VLSI devices and its effects are difficult to estimate in high level synthesis. As such, many existing high level synthesis systems use quite weak interconnect estimation heuristics which lead to inefficient layout when the synthesised structure is mapped into the physical domain. The presented approach defines a partitioned target architecture and bit-sliced layout style which may virtually eliminate the need for global wiring and hence obviate the problem of interconnect estimation. The structural cost of the synthesised architecture is therefore more closely associated with the real physical cost when realised on chip. This target architecture is used as the basis for the CASS high level synthesis system which performs algorithmic behavioural synthesis for digital signal processing (DSP) applications. A detailed discussion of the algorithms in the CASS tools is given and presented area estimates show that significant area savings are attainable by using the defined architecture and layout style. The development of CASS inspired a successor system which performs high level synthesis in one global optimisation. COBRA performs synthesis by optimising a mapping of variable lifetimes in a three dimensional "datapath space" using the method of simulated annealing.
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Jelodari, Mamaghani Mahdi. "High-level synthesis of elasticity : from models to circuits." Thesis, University of Manchester, 2016. https://www.research.manchester.ac.uk/portal/en/theses/highlevel-synthesis-of-elasticity-from-models-to-circuits(7d881d3e-b90a-4ec3-9caa-67524d3bd34b).html.
Повний текст джерелаАнотація:
The forward-looking design trend in Very Large Scale Integrated (VLSI) is Systems-on-Chip (SoC). SoC aims to integrate multiple computation, communication and storage components into a single chip and targets high performance systems by elimination of most on-chip communication costs. It is agreed that running SoC components under control of a single clock is not feasible and clock distribution has been revealed as a critical obstacle. Asynchronous techniques can be exploited to relax strict timing constraints of traditional design methodologies. A less radical solution is Globally Asynchronous Locally Synchronous (GALS) systems which offer potential advantages in this respect, as it preserves system modularity and concentrates on communication aspects. The problem with GALS design is the relative lack of familiarity of traditional designers with this approach. To deal with this, a methodology is proposed to allow designers implement GALS systems at a higher abstraction level which is independent of technology, protocol, data encoding or any other details of circuit design. With the recent advances in concurrent programming, Communicating Sequential Processes (CSP) has gained popularity again. The CSP-based programming languages, like Go, have emerged to allow software designers to exploit the model toward implementing scalable softwares. CSP has a long history since 90's in the hardware domain, mainly utilised by the Asynchronous community. In this thesis, a novel high level synthesis framework is proposed, called eTeak, which enables the designers to implement GALS-like systems in a CSP-based language (Balsa) without concerning about the timing issues at system level. The proposed approach in this thesis takes advantage of synchronous elasticity to introduce a common timing discipline to the circuit which transforms it into a latency-insensitive system. A latency-insensitive system is able to tolerate dynamic changes in the computation and communication delays. This feature enables eTeak to raise the level of abstraction to the data-flow representation where functionality is separated from timing details. Therefore, it is possible for a designer to specify a large scale system by only concentrating on its functionality and postpone timing complexity to when synthesis takes place. Unlike many previous systems, the proposed design flow employs data-driven synthesis style to distribute controllers through the network which contributes to its modularity and enhanced concurrency. This facilitates partitioning into elastic blocks and is supposed to pave the road for further optimisations, such retiming and re-synthesis, using commercial EDA tools.
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SIVA, SUBRAMANYAN D. "APPLICATIONS OF SATISFIABILITY IN SYNTHESIS OF RECONFIGURABLE COMPUTERS." University of Cincinnati / OhioLINK, 2002. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1022761893.
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Ali, Baraa Saeed. "HIGH LEVEL SYNTHSIS FOR A NETWORK ON CHIP TOPOLOGY." OpenSIUC, 2013. https://opensiuc.lib.siu.edu/theses/1079.
Повний текст джерелаАнотація:
Network on chips (NoCs) have emerged as a panacea to solve many intercommunication issues that are imposed by the fast growing of VLSI design. NOC have been deployed as a solution for the communication delay between cores, area overhead, power consumption, etc. One of the leading parameters of speeding up the performance of system on chips (SOCs) is the efficiency of scheduling algorithms for the applications running on a SOC. In this thesis we are arguing that a global scheduling view can significantly improve latency in NoCs. This view can be achieved by having the NoC nodes communicate with each other in a predefined application-based fashion; by calculating in advance how many clock cycles the nodes need to execute and transmit packets to the network and how many clock cycles are needed for the packets to travel all the way to the destination through routers (including queuing delay). By knowing that, we could keep some of the cores stay in "Hold-On" state until the right time comes to start transmitting. This technique could lead to reduced congestion and it may guarantee that the cores do not suffer from severe resource contention, e.g. accessing memory. This task is achieved by using a network simulator (such as OPNET) and gathering statistics, so the worst case latency can be determined. Therefore, if NoC nodes can somehow postpone sending packets in a way that does not violate the deadline of their tasks, packet dropping or livelock can be avoided. It is assumed that the NoC nodes here need buffers of their own in order to hold the ready-to-transmit packets and this can be the cost of this approach.
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Krishnan, Vyas. "Temperature and interconnect aware unified physical and high level synthesis." [Tampa, Fla] : University of South Florida, 2008. http://purl.fcla.edu/usf/dc/et/SFE0002785.
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Pinilla, Jose Pablo. "Source-level instrumentation for in-system debug of high-level synthesis designs for FPGA." Thesis, University of British Columbia, 2016. http://hdl.handle.net/2429/59380.
Повний текст джерелаАнотація:
High-Level Synthesis (HLS) has emerged as a promising technology to reduce the time and complexity that is associated with the design of digital logic circuits. HLS tools are capable of allocating resources and scheduling operations from a software-like behavioral specification. In order to maintain the productivity promised by HLS, it is important that the designer can debug the system in the context of the high-level code. Currently, software simulations offer a quick and familiar method to target logic and syntax bugs, while software/hardware co-simulations are useful for synthesis verification. However, to analyze the behaviour of the circuit as it is running, the user is forced to understand waveforms from the synthesized design. Debugging a system as it is running requires inserting instrumentation circuitry that gathers data regarding the operation of the circuit, and a database that maps the record entries to the original high-level variables. Previous work has proposed adding this instrumentation at the Register Transfer Level (RTL) or in the high-level source code. Source-level instrumentation provides advantages in portability, transparency, and customization. However, previous work using source-level transformations has focused on the ability to expose signals for observation rather than the construction of the instrumentation itself, thereby limiting these advantages by requiring lower-level code manipulation. This work shows how trace buffers and related circuitry can be inserted by automatically modifying the source-level specification of the design. The transformed code can then be synthesized using the regular HLS flow to generate the instrumented hardware description. The portability of the instrumentation is shown with synthesis results for Vivado HLS and LegUp, and compiled for Xilinx and Altera devices correspondingly. Using these HLS tools, the impact on circuit size varies from 15.3% to 52.5% and the impact on circuit speed ranges from 5.8% to 30%. We also introduce a low overhead technique named Array Duplicate Minimization (ADM) to improve trace memory efficiency. ADM improves overall debug observability by removing up to 31.7% of data duplication created between the trace memory and the circuit{'}s memory structures.Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
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MANSOURI, NAZANIN. "AUTOMATED CORRECTNESS CONDITION GENERATION FOR FORMAL VERIFICATION OF SYNTHESIZED RTL DESIGNS." University of Cincinnati / OhioLINK, 2001. http://rave.ohiolink.edu/etdc/view?acc_num=ucin982064542.
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Farahini, Nasim. "SiLago: Enabling System Level Automation Methodology to Design Custom High-Performance Computing Platforms : Toward Next Generation Hardware Synthesis Methodologies." Doctoral thesis, KTH, Elektronik och Inbyggda System, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-185787.
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Araujo, Barrientos Antonio. "Implementation of a High Performance Embedded MPC on FPGA using High-Level Synthesis." Master's thesis, Pontificia Universidad Católica del Perú, 2017. http://tesis.pucp.edu.pe/repositorio/handle/123456789/8899.
Повний текст джерелаАнотація:
Model predictive control(MPC) has been, since its introduction in the late 70’s, a well accepted control technique, especially for industrial processes, which are typically slow and allow for on-line calculation of the control inputs. Its greatest advantage is its ability to consider constraints, on both inputs and states, directly and naturally. More recently, the improvements in processor speed have allowed its use in a wider range of problems, many involving faster dynamics. Nevertheless, implementation of MPC algorithms on embedded systems with resources, size, power consumption and cost constraints remains a challenge. In this thesis, High-Level Synthesis (HLS) is used to implement implicit MPC algo-rithms for linear (LMPC) and nonlinear (NMPC) plant models, considering constraints on both control inputs and states of the system. The algorithms are implemented in the Zynqr -7000 All Programmable System-on-a-Chip(AP SoC) ZC706 Evaluation Kit, targetingXilinx’sZynqr-7000 AP SoC which contains a general purpose Field Programmable GateArray(FPGA). In order to solve the optimization problema teach sampling instant, an Interior-PointMethod(IPM) isused. The main computation cost of this method is the solution of a system of linear equations. A minimum residual (MINRES) algorithm is used for the solution of this system of equations taking into consideration its special structure in order to make it computationally efficient. A library was created for the linear algebra operations required for the IPM and MINRES algorithms. The implementation is tested on trajectory tracking case studies. Results for the linear cases how good performance and implementation metrics, as well as computation times within the considered sampling periods. For the nonlinear case, although a high computation time was needed, the algorithm performed well on the case study presented. Because of resources constraints, implementation of the nonlinear algorithm on higher order systems was precluded.Tesis
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Isaksson, Johan. "FPGA-Accelerated Image Processing Using High Level Synthesis with OpenCL." Thesis, Linköpings universitet, Datorteknik, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-143213.
Повний текст джерелаАнотація:
High Level Synthesis (HLS) is a new method for developing applications for use on FPGAs. Instead of the classic approach using a Hardware Descriptive Language (HDL), a high level programming language can be used. HLS has many perks, including high level debugging and simulation of the system being developed. This shortens the development time which in turn lowers the development cost. In this thesis an evaluation is made regarding the feasibility of using SDAccel as the HLS tool in the OpenCL environment. Two image processing algorithms are implemented using OpenCL C and then synthesized to run on a Kintex Ultrascale FPGA. The implementation focuses both on low latency and throughput as the target environment is a video distribution network used in vehicles. The network provides the driver with video feeds from cameras mounted on the vehicle. Finally the test result of the algorithm runs are presented, displaying how well the HLS tool has preformed in terms of system performance and FPGA resource utilization.
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Mansour, Omar. "High level synthesis for non-manifest digital signal processing applications." Enschede : University of Twente [Host], 2006. http://doc.utwente.nl/51107.
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