Статті в журналах: "Heterogeneous embedded system"

1

Valente, Giacomo, Tiziana Fanni, Carlo Sau, Tania Di Mascio, Luigi Pomante, and Francesca Palumbo. "A Composable Monitoring System for Heterogeneous Embedded Platforms." ACM Transactions on Embedded Computing Systems 20, no. 5 (July 2021): 1–34. http://dx.doi.org/10.1145/3461647.

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Advanced computations on embedded devices are nowadays a must in any application field. Often, to cope with such a need, embedded systems designers leverage on complex heterogeneous reconfigurable platforms that offer high performance, thanks to the possibility of specializing/customizing some computing elements on board, and are usually flexible enough to be optimized at runtime. In this context, monitoring the system has gained increasing interest. Ideally, monitoring systems should be non-intrusive, serve several purposes, and provide aggregated information about the behavior of the different system components. However, current literature is not close to such ideality: For example, existing monitoring systems lack in being applicable to modern heterogeneous platforms. This work presents a hardware monitoring system that is intended to be minimally invasive on system performance and resources, composable, and capable of providing to the user homogeneous observability and transparent access to the different components of a heterogeneous computing platform, so system metrics can be easily computed from the aggregation of the collected information. Building on a previous work, this article is primarily focused on the extension of an existing hardware monitoring system to cover also specialized coprocessing units, and the assessment is done on a Xilinx FPGA-based System on Programmable Chip. Different explorations are presented to explain the level of customizability of the proposed hardware monitoring system, the tradeoffs available to the user, and the benefits with respect to standard de facto monitoring support made available by the targeted FPGA vendor.

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2

Jammalamadaka, Sastry Kodanda Rama, Valluru Sai Kumar Reddy, and Smt J Sasi Bhanu. "Networking Heterogeneous Microcontroller based Systems through Universal Serial Bus." International Journal of Electrical and Computer Engineering (IJECE) 5, no. 5 (October 1, 2015): 992. http://dx.doi.org/10.11591/ijece.v5i5.pp992-1002.

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Networking heterogeneous embedded systems is a challenge. Every distributed embedded systems requires that the network is designed specifically considering the heterogeneity that exits among different Microcontroller based systems that are used in developing a distributed embedded system. Communication architecture, which considers the addressing of the individual systems, arbitration, synchronisation, error detection and control etc., needs to be designed considering a specific application. The issue of configuring the slaves has to be addressed. It is also important that the messages, flow of the messages across the individual ES systems must be designed. Every distributed embedded system is different and needs to be dealt with separately. This paper presents an approach that addresses various issues related to networking distributed embedded systems through use of universal serial bus communication protocol (USB). The approach has been applied to design a distributed embedded that monitors and controls temperatures within a Nuclear reactor system.

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3

Zhang, Huafeng, Hehua Zhang, Ming Gu, and Jiaguang Sun. "Modeling a Heterogeneous Embedded System in Coloured Petri Nets." Journal of Applied Mathematics 2014 (2014): 1–8. http://dx.doi.org/10.1155/2014/943094.

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Embedded devices are everywhere now and, unlike personal computers, their systems differ in implementation languages and behaviors. Interactions of different devices require programmers to master programming paradigms in all related languages. So, a defect may occur if differences in systems' behaviors are ignored. In this paper, a heterogeneous system which is composed of two subsystems is introduced and we point out a potential defect in this system caused by an interface mismatch. Then, a state based approach is applied to verify our analysis of the system.

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4

Syschikov, Alexey, Yuriy Sheynin, Boris Sedov, and Vera Ivanova. "Domain-Specific Programming Environment for Heterogeneous Multicore Embedded Systems." International Journal of Embedded and Real-Time Communication Systems 5, no. 4 (October 2014): 1–23. http://dx.doi.org/10.4018/ijertcs.2014100101.

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Nowadays embedded systems are used in a broad range of domains such as avionics, space, automotive, mobile, domestic appliances etc. Sophisticated software determines the quality of embedded systems and requires high-qualified experts for software development. Software becomes the main assert of embedded systems that is valuable to retain in changing computing platforms in embedded systems evolution. Computing platforms for embedded systems became multicore processors and SoC, they can change in the embedded system lifetime that could be long (dozen of years for an automobile and airplane). It requires software porting to new platforms as a regular process. Many tools and approaches allow developing of software for domain area experts, but mainly for general-purpose computing systems. In this paper the authors present the complex technology and tools that allows involving domain experts in software development for embedded systems. The proposed technology has various aspects and abilities that can be used to build verifiable and portable software for a wide range of embedded platforms.

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5

Wu, Dian Hong. "Task Optimization Scheduling Algorithm in Embedded System Based on Internet of Things." Applied Mechanics and Materials 513-517 (February 2014): 2398–402. http://dx.doi.org/10.4028/www.scientific.net/amm.513-517.2398.

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Embedded system has been widely used in the network, server, etc., and it has a good application prospect with the development of Internet of things. In the embedded heterogeneous computing system, task scheduling is the key to deciding the system performance. For multi-task scheduling, the current scheduling algorithm is mostly based on task duplication, without a full consideration of the correlation between the predecessor task and its subsequent tasks. Based on modeling the multi-frame task scheduling problem in the heterogeneous embedded system, this paper analyzes the availability of tasks through the design of genetic algorithm, so as to verify the algorithm's feasibility, which is of important guiding significance for the multi-task scheduling in the embedded heterogeneous computing system.

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6

Pervan, Branimir, Josip Knezović, and Emanuel Guberović. "Energy-efficient distributed password hash computation on heterogeneous embedded system." Automatika 63, no. 3 (February 28, 2022): 399–417. http://dx.doi.org/10.1080/00051144.2022.2042115.

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7

Rath, A. K., and S. N. Dehuri. "Non-dominated Sorting Genetic Algorithms for Heterogeneous Embedded System Design." Journal of Computer Science 2, no. 3 (March 1, 2006): 288–91. http://dx.doi.org/10.3844/jcssp.2006.288.291.

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E, Mounika. "A Hybridised Heterogeneous Embedded System Networking through Multi-Master Interface." International Journal of Emerging Trends in Engineering Research 8, no. 3 (March 15, 2020): 885–93. http://dx.doi.org/10.30534/ijeter/2020/45832020.

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9

Majumdar, Abhinandan, Srihari Cadambi, and Srimat T. Chakradhar. "An Energy-Efficient Heterogeneous System for Embedded Learning and Classification." IEEE Embedded Systems Letters 3, no. 1 (March 2011): 42–45. http://dx.doi.org/10.1109/les.2010.2100802.

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10

Campeanu, Gabriel, and Mehrdad Saadatmand. "A Two-Layer Component-Based Allocation for Embedded Systems with GPUs." Designs 3, no. 1 (January 19, 2019): 6. http://dx.doi.org/10.3390/designs3010006.

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Component-based development is a software engineering paradigm that can facilitate the construction of embedded systems and tackle its complexities. The modern embedded systems have more and more demanding requirements. One way to cope with such a versatile and growing set of requirements is to employ heterogeneous processing power, i.e., CPU–GPU architectures. The new CPU–GPU embedded boards deliver an increased performance but also introduce additional complexity and challenges. In this work, we address the component-to-hardware allocation for CPU–GPU embedded systems. The allocation for such systems is much complex due to the increased amount of GPU-related information. For example, while in traditional embedded systems the allocation mechanism may consider only the CPU memory usage of components to find an appropriate allocation scheme, in heterogeneous systems, the GPU memory usage needs also to be taken into account in the allocation process. This paper aims at decreasing the component-to-hardware allocation complexity by introducing a two-layer component-based architecture for heterogeneous embedded systems. The detailed CPU–GPU information of the system is abstracted at a high-layer by compacting connected components into single units that behave as regular components. The allocator, based on the compacted information received from the high-level layer, computes, with a decreased complexity, feasible allocation schemes. In the last part of the paper, the two-layer allocation method is evaluated using an existing embedded system demonstrator; namely, an underwater robot.

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11

Attarzadeh-Niaki, Seyed-Hosein, and Ingo Sander. "Heterogeneous co-simulation for embedded and cyber-physical systems design." SIMULATION 96, no. 9 (June 1, 2020): 753–65. http://dx.doi.org/10.1177/0037549720921945.

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The growing complexity of embedded and cyber-physical systems makes the design of all system components from scratch increasingly impractical. Consequently, already from early stages of a design flow, designers rely on prior experience, which comes in the form of legacy code or third-party intellectual property (IP) blocks. Current approaches partly address the co-simulation problem for specific scenarios in an ad hoc style. This work suggests a general method for co-simulation of heterogeneous IPs with a system modeling and simulation framework. The external IPs can be integrated as high-level models running in an external simulator or as software- and hardware-in-the-loop simulation with minimal effort. Examples of co-simulation scenarios for wrapping models with different semantics are presented together with their practical usage in two case studies. The presented method is also used to formulate a refinement-by-replacement workflow for IP-based system design.

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12

Woychik, Charles, Robert Mundella, Keith Kunard, Victor Vilar, Justin Borski, and Robert Nead. "Heterogeneous System-In-Package (HSIP) Technology." International Symposium on Microelectronics 2020, no. 1 (September 1, 2020): 000034–41. http://dx.doi.org/10.4071/2380-4505-2020.1.000034.

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Abstract A stitched test vehicle has been designed using molded wafer technology to characterize the assembly yield and reliability of a 4-layered topside Buildup (BU) and 4 layered bottom side BU package. In this design, the individual module uses 20 1mm square Si die elements, and one 10mmm square Si die and 8 through substrate vias (TSVs) arrayed on a 14mm square module size to produce a Reliability Test Vehicle (RTV) using Fan-out Wafer-Level (FOWL) technology. 17 individual RTV modules are molded on a 100mm wafer to create a reconstituted wafer. On the 1mm square Si die are two dog bone structures that allows for the design of a stitched net for each build layer with the embedded Si die. Therefore one can generate a stitched net between the first BU layer with the embedded Si die, the second BU layer with the embedded die layer, and so on. The layered stitched design feature, allows one to characterize the integrity of the individual BU layers during the sequential BU processing of the layers on both sides of the molded core. The TSVs allow for signal communication between the top 4 BU layers with the 4 backside BU layers. On top of each 4th layer is a ball grid array (BGA) pad on a 0.8mm pitch that can be used to stack this module using conventional soldering methods. This approach to embed die in a molded wafer and then BU layers on each side is referred to as Heterogeneous System-in-Package (HSIP) technology. Another feature to be included in this work is the use of Current Induced Thermal Cycle (CITC) testing. This is a fast and accurate test method developed by i3 Electronics in Endicott, NY to assess the reliability of vias in a BU package. It is widely used in the industry for circuit boards and build up organic substrates, and is now be applied to the finer via dimension (25um diameter) used for HSIP technology. As was discussed above for the RTV design, the same BU and TSV features will be tested in this CITC module design. The BU layers are exactly the same as that used in the above RTV design. For this wafer build, the die will be molded to create a reconstituted wafer. The first goal is to develop a molding process that has less than 20um die shift and produces a molded substrate with the acceptable amount of bow to accommodate the topside build up layers. For each BU layer, the assembly yield can be characterized by probing the stitched nets for the first, second, and so on BU layers for both sides. This data will provide assembly yield. The individual RTV and CITC modules can then be diced from the wafer, solder balls are attached to the topside BGA pads, and then tested using a conventional clam shell socket test fixture. The first set of reliability tests will be thermal cycling and temperature humidity. In this paper we will discuss the challenges with building HSIP modules, their yield and the first phase of reliability testing.

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13

Dey, Soumyajit, Dipankar Sarkar, and Anupam Basu. "A Kleene Algebra of Tagged System Actors for Reasoning about Heterogeneous Embedded Systems." IEEE Transactions on Computers 62, no. 10 (October 2013): 1917–31. http://dx.doi.org/10.1109/tc.2012.134.

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14

Xu, Xingwen. "Material database management system based on heterogeneous multi-processor and computer embedded system." Microprocessors and Microsystems 82 (April 2021): 103926. http://dx.doi.org/10.1016/j.micpro.2021.103926.

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15

Liang, Quanyi, and Zhikun She. "Constraint consensus of heterogeneous multi-agent systems." International Journal of Modern Physics C 29, no. 05 (May 2018): 1840005. http://dx.doi.org/10.1142/s0129183118400053.

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In this brief paper, we study the constraint consensus problem of heterogeneous multi-agent systems. First, we provide an invariant set, which can be exactly obtained by solving linear equations. Then, a virtual system is defined on this invariant set such that it is the largest common embedded system of all the individual agents. Afterwards, a linear consensus protocol is proposed with the corresponding constraint consensus criterion. In particular, the above virtual system can reveal all the asymptotic dynamical behaviors if heterogeneous multi-agent systems achieve consensus. Finally, an example with numerical simulations is given to illustrate the validity of our criterion.

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RADOJEVIC, IVAN, ZORAN SALCIC, and PARTHA ROOP. "A NEW MODEL FOR HETEROGENEOUS EMBEDDED SYSTEMS — What Esterel and SyncCharts Need to Become a Suitable Specification Platform." International Journal of Software Engineering and Knowledge Engineering 15, no. 02 (April 2005): 405–10. http://dx.doi.org/10.1142/s0218194005001963.

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Specification of embedded systems based on formal models of computation is gaining importance. The behavior of an increasing number of embedded systems is heterogeneous, consisting of a mixture of control-dominated and data-dominated parts. While models of computations suitable to control-dominated systems and data-dominated systems are well developed, there are only a limited number of models catering to both systems. In this paper, we present informally a new model for heterogeneous embedded systems, called HEMOC, which combines three common models of computation, synchronous reactive, hierarchical finite state machines and synchronous data flow. Then, the languages Esterel and SyncCharts are used for system specification following the new model in order to determine what they need to become suitable specification platform.

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17

Chaudhary, Pooja, Brij B. Gupta, and A. K. Singh. "Securing heterogeneous embedded devices against XSS attack in intelligent IoT system." Computers & Security 118 (July 2022): 102710. http://dx.doi.org/10.1016/j.cose.2022.102710.

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18

Kwak, Jaeheon, and Jinkyu Lee. "Minimizing Capacity Degradation of Heterogeneous Batteries in a Mobile Embedded System." IEEE Embedded Systems Letters 12, no. 1 (March 2020): 25–28. http://dx.doi.org/10.1109/les.2019.2929069.

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19

Deluno Garcia, Fernando, Wesley Angelino de Souza, and Fernando Pinhabel Marafao. "Embedded NILM as Home Energy Management System: A Heterogeneous Computing Approach." IEEE Latin America Transactions 18, no. 02 (February 2019): 360–67. http://dx.doi.org/10.1109/tla.2019.9082249.

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Deluno Garcia, Fernando, Wesley Angelino de Souza, and Fernando Pinhabel Marafao. "Embedded NILM as Home Energy Management System: A Heterogeneous Computing Approach." IEEE Latin America Transactions 18, no. 02 (February 2020): 360–67. http://dx.doi.org/10.1109/tla.2020.9085291.

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21

Wang, Zi Ting, and Yan Ping Lin. "The Research and Application of Pork Traceability System Based on RFID." Advanced Materials Research 846-847 (November 2013): 1724–28. http://dx.doi.org/10.4028/www.scientific.net/amr.846-847.1724.

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The author analyzes and researches the heterogeneous data of the food traceability system,then propose the template-based adaptive heterogeneous data processing algorithms. According to the algorithm, the middle-ware ,with the design of embedded RFID achieves the processing and integration of heterogeneous data . The middle-war it work with the back-end server online, but also possess high practicality when the network off-line works alone.Copyright © 2013 IFSA.

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22

Faye, Fatou, and Mbaye Sene. "Reliability and Availability of Embedded Software Architectures: A Survey." Applied Mechanics and Materials 373-375 (August 2013): 1612–17. http://dx.doi.org/10.4028/www.scientific.net/amm.373-375.1612.

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This paper summarizes works based on the reliability and the availability of embedded software architectures. Nowadays, the advent of the embedded systems has pulled the development of different domains (aeronautics, automobile, industry, medicines, telecommunications, household electrical appliances, so one so far). Indeed, the embedded system includes hardware and software that must collaborate to carry out well defined complex tasks. An embedded system is an integration of heterogeneous components (components of the computing and the electronics). Indeed, the implementation of the embedded systems presents some constraints which can be, for example the system cost, energy consummation, speed of execution, reliability, availability, security ...However, among these constraints enumerated briefly, the reliability and the availability of the software architecture of these systems are the object of complete study in this article.

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23

Kilaru, Chaitanya, Dr JKR Sastry, and Dr K RajaSekhara Rao. "Testing distributed embedded systems through logic analyzer." International Journal of Engineering & Technology 7, no. 2.7 (March 18, 2018): 297. http://dx.doi.org/10.14419/ijet.v7i2.7.10601.

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Testing distributed embedded systems is complex as the individual systems connected on to the network are heterogeneous in nature.The communication system that is used for establishing the networking also varies greatly leading to different testing requirements. Testing of embedded systems can be carried using different methods that include Scaffolding, assert macros, instruction set simulators. In-circuit emulators, logic analyzers each requiring establishment of different testing environment required for undertaking actual testing. Testing of any embedded systems involves testing hardware, testing hardware dependent code, and testing hardware independent code. Logic analyzers are generally used for testing proper working of the Hardware.In this paper, a framework is presented using which testing of hardware distributed across the distributed embedded system using logic analyzer is presented.

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24

Rajasekhar, J., and Dr JKR Sastry. "An approach to hybridisation of embedded system networks." International Journal of Engineering & Technology 7, no. 2.7 (March 18, 2018): 384. http://dx.doi.org/10.14419/ijet.v7i2.7.10748.

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Embedded systems can be networked using either wired or wireless technologies. ES systems when networked using wires can communicate serially over a bus using the technologies such as CAN, I2C, USB, RS485, and Fire wire. These standards differ in many ways which include arbitration, synchronization, address resolution, timing, type of communication etc. Embedded systems can also be network using wireless technologies which exits in many versions.Several applications these days are requiring more than one communication technology. Several sub-systems are developed using a networking method and it requires that the subsystems that are networked using different technologies are to be networked further for realizing entire application. Such a network needs to deal with many of the heterogeneous communication system leading to an issue of hybridisation. In this paper various issues/approaches that need to be addressed for hybridising of the ES networks have been presented.

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25

Spagnolo, Fanny, Stefania Perri, Fabio Frustaci, and Pasquale Corsonello. "Energy-Efficient Architecture for CNNs Inference on Heterogeneous FPGA." Journal of Low Power Electronics and Applications 10, no. 1 (December 24, 2019): 1. http://dx.doi.org/10.3390/jlpea10010001.

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Due to the huge requirements in terms of both computational and memory capabilities, implementing energy-efficient and high-performance Convolutional Neural Networks (CNNs) by exploiting embedded systems still represents a major challenge for hardware designers. This paper presents the complete design of a heterogeneous embedded system realized by using a Field-Programmable Gate Array Systems-on-Chip (SoC) and suitable to accelerate the inference of Convolutional Neural Networks in power-constrained environments, such as those related to IoT applications. The proposed architecture is validated through its exploitation in large-scale CNNs on low-cost devices. The prototype realized on a Zynq XC7Z045 device achieves a power efficiency up to 135 Gops/W. When the VGG-16 model is inferred, a frame rate up to 11.8 fps is reached.

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26

Li, Chunqiang, Ren Guo, Xianting Tian, and Huibin Wang. "KHV: KVM-Based Heterogeneous Virtualization." Electronics 11, no. 16 (August 22, 2022): 2631. http://dx.doi.org/10.3390/electronics11162631.

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A KVM (Kernel-based Virtual Machine) is subject to the complexity of the Linux kernel and the difficulty and cost of safety certification; thus, it is not popularized in embedded high-reliability scenarios. This paper proposes a KVM-based Heterogeneous Virtualization (KHV), which is independent of hardware virtualization (KVM mandatory virtualization), follows the principle of static partitioning, localizes the hypervisor, and inherits the KVM software ecosystem. KHV balances the demands of static partitioning and flexible sharing in the embedded system. The paper implemented KHV on the RISC-V Xuantie C910 CPU-based SoC and conducted a performance comparison with KVM. The experiment shows that KHV is 50% smaller than KVM in terms of fluctuation, and KHV makes the guest OS have the same performance as the bare-metal OS in scheduler benchmarks, whereas KVM dropped an average of 28%.

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27

Leu, Jenq-Shiou, Wei-Hsiang Lin, Wen-Bin Hsieh, and Chien-Chih Lo. "Design and Implementation of a VoIP Broadcasting Service over Embedded Systems in a Heterogeneous Network Environment." Scientific World Journal 2014 (2014): 1–10. http://dx.doi.org/10.1155/2014/917060.

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As the digitization is integrated into daily life, media including video and audio are heavily transferred over the Internet nowadays. Voice-over-Internet Protocol (VoIP), the most popular and mature technology, becomes the focus attracting many researches and investments. However, most of the existing studies focused on a one-to-one communication model in a homogeneous network, instead of one-to-many broadcasting model among diverse embedded devices in a heterogeneous network. In this paper, we present the implementation of a VoIP broadcasting service on the open source—Linphone—in a heterogeneous network environment, including WiFi, 3G, and LAN networks. The proposed system featuring VoIP broadcasting over heterogeneous networks can be integrated with heterogeneous agile devices, such as embedded devices or mobile phones. VoIP broadcasting over heterogeneous networks can be integrated into modern smartphones or other embedded devices; thus when users run in a traditional AM/FM signal unreachable area, they still can receive the broadcast voice through the IP network. Also, comprehensive evaluations are conducted to verify the effectiveness of the proposed implementation.

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JIANG, Jian-chun, Su-hua ZENG, and Ming CEN. "Architecture design of embedded operating system based on heterogeneous dual-core processor." Journal of Computer Applications 28, no. 10 (September 30, 2009): 2686–89. http://dx.doi.org/10.3724/sp.j.1087.2008.02686.

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29

MAN, Meng-hua, Liang YUAN, Guo-liang DING, Zheng-quan JU, and Liang SONG. "Embedded dual-computer redundant system design with-high reliability and heterogeneous structure." Journal of Computer Applications 29, no. 8 (October 9, 2009): 2143–45. http://dx.doi.org/10.3724/sp.j.1087.2009.02143.

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30

Son, Hyun-Seung, Woo-Yeol Kim, and R. Young-Chul Kim. "MDA(Model Driven Architecture) based Design for Multitasking of Heterogeneous Embedded System." KIPS Transactions:PartD 15D, no. 3 (June 30, 2008): 355–60. http://dx.doi.org/10.3745/kipstd.2008.15-d.3.355.

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31

Gao, Fang, Zhangqin Huang, Shulong Wang, and Xinrong Ji. "Optimized Parallel Implementation of Face Detection Based on Embedded Heterogeneous Many-Core Architecture." International Journal of Pattern Recognition and Artificial Intelligence 31, no. 07 (April 10, 2017): 1756011. http://dx.doi.org/10.1142/s0218001417560110.

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Computing performance is one of the key problems in embedded systems for high-resolution face detection applications. To improve the computing performance of embedded high-resolution face detection systems, a novel parallel implementation of embedded face detection system was established based on a low power CPU-Accelerator heterogeneous many-core architecture. First, a basic CPU version of face detection prototype was implemented based on the cascade classifier and Local Binary Patterns operator. Second, the prototype was extended to a specified embedded parallel computing platform that is called Parallella and consists of Xilinx Zynq and Adapteva Epiphany. Third, the face detection algorithm was optimized to adapt to the Parallella architecture to improve the detection speed and the utilization of computing resources. Finally, a face detection experiment was conducted to evaluate the computing performance of the proposal in this paper. The experimental results show that the proposed implementation obtained a very consistent accuracy as that of the dual-core ARM, and achieved 7.8 times speedup than that of the dual-core ARM. Experiment results prove that the proposed implementation has significant advantages on computing performance.

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32

Pérez, Ignacio, and Miguel Figueroa. "A Heterogeneous Hardware Accelerator for Image Classification in Embedded Systems." Sensors 21, no. 8 (April 9, 2021): 2637. http://dx.doi.org/10.3390/s21082637.

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Convolutional neural networks (CNN) have been extensively employed for image classification due to their high accuracy. However, inference is a computationally-intensive process that often requires hardware acceleration to operate in real time. For mobile devices, the power consumption of graphics processors (GPUs) is frequently prohibitive, and field-programmable gate arrays (FPGA) become a solution to perform inference at high speed. Although previous works have implemented CNN inference on FPGAs, their high utilization of on-chip memory and arithmetic resources complicate their application on resource-constrained edge devices. In this paper, we present a scalable, low power, low resource-utilization accelerator architecture for inference on the MobileNet V2 CNN. The architecture uses a heterogeneous system with an embedded processor as the main controller, external memory to store network data, and dedicated hardware implemented on reconfigurable logic with a scalable number of processing elements (PE). Implemented on a XCZU7EV FPGA running at 200 MHz and using four PEs, the accelerator infers with 87% top-5 accuracy and processes an image of 224×224 pixels in 220 ms. It consumes 7.35 W of power and uses less than 30% of the logic and arithmetic resources used by other MobileNet FPGA accelerators.

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Moody, Kevin, and Nick Stukan. "Embedded SIP Modules for next-GEN Heterogeneous “POWER-Devices”." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (January 1, 2019): 000383–407. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_tp1_073.

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In this paper will focus on the comprehension of System-in-Package (SiP) with embedded active and passive components integration will be described. Embedding of semiconductor chips into substrates provides many advantages that have been noted. It allows the smallest package form-factor with high degree of miniaturization through sequentially stacking of multiple layers containing embedded devices that are optimized for electrical performance with short and geometrically well controlled copper interconnects. In addition, the embedding gives a homogeneous mechanical environment of the chips, resulting in good reliability at system level. Furthermore, embedded technology is an excellent resolution to Power management challenges dealing with new device technologies (Si, GaS, GaN) and optimization on the thermal dissipation with improved efficiency. Embedded technology comes with many challenges in 2019, primarily design for manufacturability (DFM) and maturity. Customers are looking for better-performance capability and pricing normally that means same or lower than die free package cost (DFPC) comparison. This paper will discuss the challenges bring to market the Embedded SIP Modules for next-GEN Heterogeneous “POWER-Devices” Today, the embedded process is being developed by printed circuit board (PCB) manufacturers creating a new supply chain, bringing new players into the semiconductor industry. This new supply chain comes along with new business models. As a result of the increasing interest in implementing embedding technologies, ACCESS Semiconductors in China is committed to be a leader in the adaptation of embedding technologies, with over 10-yrs mature coreless technology and proved design rules for low profile dimensions with seamless Ti/Cu sputtering and Cu pillar interconnect giving advantages in both electrical & power performance. ACCESS Patented “Via-in-Frame” technology provides High Reliability (MSL1, PCT, BHAST) at Cost Effective in high panel utilization for HVM, using standard substrate/PCB known material sets, no need for wafer bumping/RDL, over-mold or under-fill cost adders. ACCESS Semiconductors is currently in HVM on single die 2L, and LVM on multi-devices actives/passives 4L SiP construction both platforms are driven from the power market segment. In-development on Die Last & Frameless (MeSiP) platforms utilizing hybrid technology (mSAP) and Photo Imageable Dielectric (PID) materials for cost down solutions in HVM by Q1FY2020. Also, ACCESS Semiconductors total turn-key solutions will include front-of-line (FOL) and end-of-line (EOL) capability from wafer handling, back-grinding, and dicing with KGD traceability thru the embedded chip process, frame/strip singulation, FT, marking pack & ship providing additional 30% cost reduction in the future. Here's an illustration of Embedded Technology Roadmap and Product Platforms.

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Edahiro, Masato, and Masaki Gondo. "Research on highly parallel embedded control system design and implementation method." Impact 2019, no. 10 (December 30, 2019): 44–46. http://dx.doi.org/10.21820/23987073.2019.10.44.

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The pace of technology's advancements is ever-increasing and intelligent systems, such as those found in robots and vehicles, have become larger and more complex. These intelligent systems have a heterogeneous structure, comprising a mixture of modules such as artificial intelligence (AI) and powertrain control modules that facilitate large-scale numerical calculation and real-time periodic processing functions. Information technology expert Professor Masato Edahiro, from the Graduate School of Informatics at the Nagoya University in Japan, explains that concurrent advances in semiconductor research have led to the miniaturisation of semiconductors, allowing a greater number of processors to be mounted on a single chip, increasing potential processing power. 'In addition to general-purpose processors such as CPUs, a mixture of multiple types of accelerators such as GPGPU and FPGA has evolved, producing a more complex and heterogeneous computer architecture,' he says. Edahiro and his partners have been working on the eMBP, a model-based parallelizer (MBP) that offers a mapping system as an efficient way of automatically generating parallel code for multi- and many-core systems. This ensures that once the hardware description is written, eMBP can bridge the gap between software and hardware to ensure that not only is an efficient ecosystem achieved for hardware vendors, but the need for different software vendors to adapt code for their particular platforms is also eliminated.

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Mamri, Ayoub, Mohamed Abouzahir, Mustapha Ramzi, and Rachid Latif. "ORB-SLAM accelerated on heterogeneous parallel architectures." E3S Web of Conferences 229 (2021): 01055. http://dx.doi.org/10.1051/e3sconf/202122901055.

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SLAM algorithm permits the robot to cartography the desired environment while positioning it in space. It is a more efficient system and more accredited by autonomous vehicle navigation and robotic application in the ongoing research. Except it did not adopt any complete end-to-end hardware implementation yet. Our work aims to a hardware/software optimization of an expensive computational time functional block of monocular ORB-SLAM2. Through this, we attempt to implement the proposed optimization in FPGA-based heterogeneous embedded architecture that shows attractive results. Toward this, we adopt a comparative study with other heterogeneous architecture including powerful embedded GPGPU (NVIDIA Tegra TX1) and high-end GPU (NVIDIA GeForce 920MX). The implementation is achieved using high-level synthesis-based OpenCL for FPGA and CUDA for NVIDIA targeted boards.

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Selvarajah, K., C. Shooter, L. Liotti, and A. Tully. "Heterogeneous Wireless Sensor Network for Transportation System Applications." International Journal of Vehicular Technology 2011 (May 17, 2011): 1–14. http://dx.doi.org/10.1155/2011/853948.

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The important innovations in wireless and digital electronics will support many applications in the areas of safety, environmental and emissions control, driving assistance, diagnostics, and maintenance in the transport domain. The last few years have seen the emergence of many new technologies that can potentially have major impacts on transportation systems. One of these technologies is Wireless Sensor Networks. A wireless sensor device is typically composed of a processing unit, memory, and a radio chip which allows it to communicate wirelessly with other devices within range. The Embedded Middleware in Mobility Applications (EMMA) project delivers a middleware that aims to facilitate the interaction between sensing technologies in transportation systems. This paper outlines our experience in the EMMA project and provides an illustration of the important role that wireless sensor technology can play in future transportation system. The paper discusses our experience of using heterogeneous sensors to develop transportation system applications in the EMMA project and focuses on how cooperation between vehicle and infrastructure can be addressed. It also presents encouraging results obtained from the experiments in investigating the feasibility of utilising wireless sensor in vehicle and vehicle-to-infrastructure communication in real transportation applications.

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CAI, XIA, MICHAEL R. LYU, and KAM-FAI WONG. "COMPONENT-BASED EMBEDDED SOFTWARE ENGINEERING: DEVELOPMENT FRAMEWORK, QUALITY ASSURANCE AND A GENERIC ASSESSMENT ENVIRONMENT." International Journal of Software Engineering and Knowledge Engineering 12, no. 02 (April 2002): 107–33. http://dx.doi.org/10.1142/s0218194002000846.

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Embedded software is used to control the functions of mechanical and physical devices by dedicated digital signal processor and computers. Nowadays, heterogeneous and collaborative embedded software systems are widely adopted to engage the physical world. To make such software extremely reliable, very efficient and highly flexible, component-based embedded software development can be employed for the complex embedded systems, especially those based on object-oriented (OO) approaches. In this paper, we introduce a component-based embedded software framework and the features it inherits. We propose a quality assurance (QA) model for component-based embedded software development, which covers both the component QA and the system QA as well as their interactions. Furthermore, we propose a generic quality assessment environment for component-based embedded systems: ComPARE. ComPARE can be used to assess real-life off-the-shelf components and to evaluate and validate the models selected for their evaluation. The overall component-based embedded systems can then be composed and analyzed seamlessly.

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Shrikrishna Parab, Jivan, Rupesh Sadanand Paliekar Porob, Kottanal Roy Francis Joseph, Kunal Vishwanath Naik, Rajanish K. Kamat, and Gourish M. Naik. "Heterogeneous embedded system with “microcontroller‐CPLD” based shared memory interface for sensor applications." Sensor Review 25, no. 4 (December 2005): 287–91. http://dx.doi.org/10.1108/02602280510620132.

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Yamada, Hiroshi, Yutaka Onozuka, Atsuko Iida, Kazuhiko Itaya, and Hideyuki Funaki. "A Wafer-level System Integration Technology Incorporates Heterogeneous Devices." International Symposium on Microelectronics 2012, no. 1 (January 1, 2012): 000793–800. http://dx.doi.org/10.4071/isom-2012-wp16.

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A pseudo-SoC technology incorporating heterogeneous devices has been developed by applying a wafer-level system integration technology. The pseudo-SoC is set up to realize one microchip with heterogeneous devices made by using individual processes for epoxy resin, insulating layer and redistribution layer, respectively. The individual heterogeneous devices are embedded in the epoxy resin to reconfigure the integration wafer. As the insulating layer and redistribution layer are formed by semiconductor wafer process without interposer substrate, the pseudo-SoC enables integration density and signal transmission speed as identical to that of SoC. Also, as the commercial LSI devices and peripheral passive components are able to use for the system integration, the pseudo-SoC enables reduction of time-to-market as identical that of SiP. This paper describes the heterogeneous devices integration technologies and focuses on the pseudo-SoC that overcomes the limitation of system integration and provides the complementary advantages of SiP and SoC with various applications.

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Guajo, Joaquín, Cristian Alzate-Anzola, Luis Castaño-Londoño, and David Márquez-Viloria. "Performance Evaluation of Convolutional Networks on Heterogeneous Architectures for Applications in Autonomous Robotics." TecnoLógicas 25, no. 53 (April 29, 2022): e2170. http://dx.doi.org/10.22430/22565337.2170.

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Humanoid robots find application in human-robot interaction tasks. However, despite their capabilities, their sequential computing system limits the execution of computationally expensive algorithms such as convolutional neural networks, which have demonstrated good performance in recognition tasks. As an alternative to sequential computing units, Field-Programmable Gate Arrays and Graphics Processing Units have a high degree of parallelism and low power consumption. This study aims to improve the visual perception of a humanoid robot called NAO using these embedded systems running a convolutional neural network. The methodology adopted here is based on image acquisition and transmission using simulation software: Webots and Choreographe. In each embedded system, an object recognition stage is performed using commercial convolutional neural network acceleration frameworks. Xilinx® Ultra96™, Intel® Cyclone® V-SoC and NVIDIA® Jetson™ TX2 cards were used, and Tinier-YOLO, AlexNet, Inception-V1 and Inception V3 transfer-learning networks were executed. Real-time metrics were obtained when Inception V1, Inception V3 transfer-learning and AlexNet were run on the Ultra96 and Jetson TX2 cards, with frame rates between 28 and 30 frames per second. The results demonstrated that the use of these embedded systems and convolutional neural networks can provide humanoid robots such as NAO with greater visual recognition in tasks that require high accuracy and autonomy.

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Sahlabadi, Mahdi, Ravie Chandren Muniyandi, Zarina Shukor, and Amirhossein Sahlabadi. "Heterogeneous Hierarchical Coloured Petri Net Software/Hardware Architectural View of Embedded System based on System Behaviours." Procedia Technology 11 (2013): 925–32. http://dx.doi.org/10.1016/j.protcy.2013.12.277.

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Hu, Nan, Chao Wang, and Xuehai Zhou. "FLIA: Architecture of Collaborated Mobile GPU and FPGA Heterogeneous Computing." Electronics 11, no. 22 (November 16, 2022): 3756. http://dx.doi.org/10.3390/electronics11223756.

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Accelerators, such as GPUs (Graphics Processing Unit) that is suitable for handling highly parallel data, and FPGA (Field Programmable Gate Array) with algorithms customized architectures, are widely adopted. The motivation is that algorithms with various parallel characteristics can efficiently map to the heterogeneous computing architecture by collaborated GPU and FPGA. However, current applications always utilize only one type of accelerator because the traditional development approaches need more support for heterogeneous processor collaboration. Therefore, a comprehensible architecture facilitates developers to employ heterogeneous computing applications. This paper proposes FLIA (Flow-Lead-In Architecture) for abstracting heterogeneous computing. FLIA implementation based on OpenCL extension supports task partition, communication, and synchronization. An embedded system of a three-dimensional waveform oscilloscope is selected as a case study. The experimental results show that the embedded heterogeneous computing achieves 21× speedup than the OpenCV baseline. Heterogeneous computing also consumes fewer FPGA resources than the pure FPGA accelerator, but their performance and energy consumption are approximate.

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Mohamed, Abouzahir, Elouardi Abdelhafid, Bouaziz Samir, Latif Rachid, and Tajer Abdelouahed. "Implementation of FastSLAM2.0 on an Embedded System and HIL Validation using Different Sensors Data." International Journal of Adaptive, Resilient and Autonomic Systems 6, no. 2 (July 2015): 88–116. http://dx.doi.org/10.4018/ijaras.2015070105.

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The improved particle filter based simultaneous localization and mapping (SLAM) has been developed for many robotic applications. The main purpose of this article is to demonstrate that recent heterogeneous architectures can be used to implement the FastSLAM2.0 and can greatly help to design embedded systems based robot applications and autonomous navigation. The algorithm is studied, optimized and evaluated with a real dataset using different sensors data and a hardware in the loop (HIL) method. Authors have implemented the algorithm on a system based embedded applications. Results demonstrate that an optimized FastSLAM2.0 algorithm provides a consistent localization according to a reference. Such systems are suitable for real time SLAM applications.

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Bouyahya, Ali, Yassine Manai, and Joseph Haggège. "Application of New Approach of design flow for Hardware/Software Embedded System with the Use of Design Patterns in Fuzzy control system." International Journal of Reconfigurable and Embedded Systems (IJRES) 4, no. 2 (July 1, 2015): 142. http://dx.doi.org/10.11591/ijres.v4.i2.pp142-160.

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<p>This paper present a new method of conception of hardware/software embedded system design methodology based on use of design pattern approach called Abstract_factory. We called this new design tool “smart cell”. The main idea of the conception of embedded systems design is based on the used of object-oriented design ULM2.0. When the smart-cell is implemented, we justify their uses as a design tool that allows, first, to develop a specified application of fuzzy controller called PDC (parallel distributed conpensation). Second, the specification of the generation phases of the system architecture design, and eventually partitioning the application on heterogeneous platform based on hardware resource DSP and FPGA software to illustrate the proposed approach.</p>

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Perri, Stefania, Cristian Sestito, Fanny Spagnolo, and Pasquale Corsonello. "Efficient Deconvolution Architecture for Heterogeneous Systems-on-Chip." Journal of Imaging 6, no. 9 (August 25, 2020): 85. http://dx.doi.org/10.3390/jimaging6090085.

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Today, convolutional and deconvolutional neural network models are exceptionally popular thanks to the impressive accuracies they have been proven in several computer-vision applications. To speed up the overall tasks of these neural networks, purpose-designed accelerators are highly desirable. Unfortunately, the high computational complexity and the huge memory demand make the design of efficient hardware architectures, as well as their deployment in resource- and power-constrained embedded systems, still quite challenging. This paper presents a novel purpose-designed hardware accelerator to perform 2D deconvolutions. The proposed structure applies a hardware-oriented computational approach that overcomes the issues of traditional deconvolution methods, and it is suitable for being implemented within any virtually system-on-chip based on field-programmable gate array devices. In fact, the novel accelerator is simply scalable to comply with resources available within both high- and low-end devices by adequately scaling the adopted parallelism. As an example, when exploited to accelerate the Deep Convolutional Generative Adversarial Network model, the novel accelerator, running as a standalone unit implemented within the Xilinx Zynq XC7Z020 System-on-Chip (SoC) device, performs up to 72 GOPs. Moreover, it dissipates less than 500mW@200MHz and occupies 5.6%, 4.1%, 17%, and 96%, respectively, of the look-up tables, flip-flops, random access memory, and digital signal processors available on-chip. When accommodated within the same device, the whole embedded system equipped with the novel accelerator performs up to 54 GOPs and dissipates less than 1.8W@150MHz. Thanks to the increased parallelism exploitable, more than 900 GOPs can be executed when the high-end Virtex-7 XC7VX690T device is used as the implementation platform. Moreover, in comparison with state-of-the-art competitors implemented within the Zynq XC7Z045 device, the system proposed here reaches a computational capability up to 20% higher, and saves more than 60% and 80% of power consumption and logic resources requirement, respectively, using 5.7× fewer on-chip memory resources.

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Mingallon, Maria, and Sakthivel Ramaswamy. "Thigmo-Morphogenetic Fiber Composites Embedded with Shape Memory Alloys." Advances in Science and Technology 80 (September 2012): 102–11. http://dx.doi.org/10.4028/www.scientific.net/ast.80.102.

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The premise of this research is to integrate sensing and actuation functions into a fibre composite material system. Fibre composites, which are anisotropic and heterogeneous, offer the possibility for local variations in their material properties. Embedded fibre optics are herein used to sense, while shape memory alloys provide actuation capabilities to the resulting composite. The definition of the geometry, inspired by the organization strategies found in biological composites, complements the functioning of the adaptive material system at both local and global levels, allowing it to display integrated functionality.

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Saddik, Amine, Rachid Latif, Mohamed Elhoseny, and Abdelhafid El Ouardi. "Real-time evaluation of different indexes in precision agriculture using a heterogeneous embedded system." Sustainable Computing: Informatics and Systems 30 (June 2021): 100506. http://dx.doi.org/10.1016/j.suscom.2020.100506.

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Sinaei, Sima, and Omid Fatemi. "Multi-objective algorithms for the application mapping problem in heterogeneous multiprocessor embedded system design." Journal of Supercomputing 75, no. 8 (May 29, 2018): 4150–76. http://dx.doi.org/10.1007/s11227-018-2442-2.

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Feldkaemper, H. T., H. Blume, and T. G. Noll. "Study of heterogeneous and reconfigurable architectures in the communication domain." Advances in Radio Science 1 (May 5, 2003): 165–69. http://dx.doi.org/10.5194/ars-1-165-2003.

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Abstract. One of the most challenging design issues for next generations of (mobile) communication systems is fulfilling the computational demands while finding an appropriate trade-off between flexibility and implementation aspects, especially power consumption. Flexibility of modern architectures is desirable, e.g. concerning adaptation to new standards and reduction of time-to-market of a new product. Typical target architectures for future communication systems include embedded FPGAs, dedicated macros as well as programmable digital signal and control oriented processor cores as each of these has its specific advantages. These will be integrated as a System-on-Chip (SoC). For such a heterogeneous architecture a design space exploration and an appropriate partitioning plays a crucial role. On the exemplary vehicle of a Viterbi decoder as frequently used in communication systems we show which costs in terms of ATE complexity arise implementing typical components on different types of architecture blocks. A factor of about seven orders of magnitude spans between a physically optimised implementation and an implementation on a programmable DSP kernel. An implementation on an embedded FPGA kernel is in between these two representing an attractive compromise with high flexibility and low power consumption. Extending this comparison to further components, it is shown quantitatively that the cost ratio between different implementation alternatives is closely related to the operation to be performed. This information is essential for the appropriate partitioning of heterogeneous systems.

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Chakraborty, Bidesh, Mamata Dalui, and Biplab K. Sikdar. "Design of a Reliable Cache System for Heterogeneous CMPs." Journal of Circuits, Systems and Computers 27, no. 14 (August 23, 2018): 1850219. http://dx.doi.org/10.1142/s0218126618502195.

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The embedded system-on-a-chip (SoC), that integrates heterogeneous processors with variation in coherence protocol, adds complexity in maintaining coherency in the data caches. It further complicates the task of coherence verification in such systems. This work targets effective solution for coherence verification in heterogeneous chip multiprocessors (CMPs) through introduction of highly efficient verification unit. It is developed around the modeling tool of cellular automaton (CA) invented by von Neumann in 1950s. The modular and cascadable structure of CA ensures high scalability and robustness in the proposed design. A CA segment is employed to analyze the states of a data block in different private caches of a heterogeneous processor cluster and to verify inconsistencies, if any, within the cluster. The outcomes of coherence verification for clusters are analyzed by the CA resulted out of augmentation of the CA segments. On the other hand, in this work, we further propose a CA-based coherence protocol processor (PP), which caters the need for determining the state of a data block with high accuracy. The PP designed for the heterogeneous CMPs, while computing the states of za block on every transaction (read/write), can capture defects, if any, and thereby realizes a fault-tolerant PP without introduction of additional hardware logic.

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