Статті в журналах: "Hardware Under Test"

1

Pomeranz, Irith. "Test Compaction by Test Removal Under Transparent Scan." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27, no. 2 (February 2019): 496–500. http://dx.doi.org/10.1109/tvlsi.2018.2878067.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

2

Yin, Jiao, Hu Liu, Jun Wang, and Ke Li. "Control System Design of Pneumatic Conveying in Sand/Dust Environment Simulation Test." Applied Mechanics and Materials 442 (October 2013): 424–29. http://dx.doi.org/10.4028/www.scientific.net/amm.442.424.

Повний текст джерела

Анотація:

This paper focuses on the design of pneumatic conveying control system, including the design of both hardware and software part. The hardware part is mainly about building a test bed. Under certain wind conditions, by controlling the rotary feed valve to achieve the control of sand/dust concentration. The software part is to make the use of LabVIEW to develop a screen display program, which can achieve real-time data acquisition and control. The paper consists of three parts, the pneumatic control system hardware design, the pneumatic conveying control system software design and then Origin is used to linear fit the wind speed parameters collected back.

Стилі APA, Harvard, Vancouver, ISO та ін.

3

Wan Jamaludin, Wan Shahmisufi, Tan Wei Ren, Bakhtiar Affendi Rosdi, Dahaman Ishak, Noor Hafizi Hanafi, and Muhammad Nasiruddin Mahyuddin. "Adopting Hardware-In-the-Loop for Testing Vehicle Instrument Panel using Economical Approach." Indonesian Journal of Electrical Engineering and Computer Science 10, no. 1 (April 1, 2018): 50. http://dx.doi.org/10.11591/ijeecs.v10.i1.pp50-58.

Повний текст джерела

Анотація:

An economical approach for testing Vehicle Instrument Panel is proposed in this paper due to high expenditure of purchasing the available Commercial Off-The-Shelf Hardware-In-The-Loop. Vehicle Instrument Panel is designated as the Device-Under-Test in this paper. The Hardware-In-The-Loop, designated as the test equipment, will simulate the assigned input signals controllable via designed Graphical User Interface. The resulting display is shown on the Graphical User Interface and the Device-Under-Test. The speedometer gauge measurement showed the highest disparity of 4 km/h which is within the tolerance of the pre-determined specification of the Device-Under-Test.

Стилі APA, Harvard, Vancouver, ISO та ін.

4

Zhang, Peng, Hou Jun Wang, Li Li, and Ping Wang. "Design and Implementation of Intermediate Frequency Generation and Analysis Module for Avionics Test." Advanced Materials Research 1049-1050 (October 2014): 1147–53. http://dx.doi.org/10.4028/www.scientific.net/amr.1049-1050.1147.

Повний текст джерела

Анотація:

To test airborne avionics device, it is necessary to provide signal stimulus for the device under test (DUT) to simulate the real work environment. This paper proposes a hardware module which used to signal generate and analyze. The hardware structure and diagram of logic design are described. The generated waveforms and measurement results are presented. This test module combined with other necessary modules can achieve the test of L band airborne avionics such as ATC, TCAS and TACAN.

Стилі APA, Harvard, Vancouver, ISO та ін.

5

Tian, Zeng Hao. "MIMO Channel Research and Hardware Implementation." Applied Mechanics and Materials 543-547 (March 2014): 2581–84. http://dx.doi.org/10.4028/www.scientific.net/amm.543-547.2581.

Повний текст джерела

Анотація:

The MIMO technology, namely through many antenna clear signal transmission and the receive, in does not increase the extra band width under the premise, enhanced the channel capacity greatly. Understood the MIMO channel the characteristic, studies the channel modelling method, unified the FPGA parallel characteristic, the design has manufactured one kind based on XILINX FPGA the platform MIMO channel analog meter, through the massive test confirmation, and did with the theoretically simulation performance compares, has confirmed the accuracy.

Стилі APA, Harvard, Vancouver, ISO та ін.

6

Larsson, E., and S. Edbom. "Test data truncation for test quality maximisation under ATE memory depth constraint." IET Computers & Digital Techniques 1, no. 1 (2007): 27. http://dx.doi.org/10.1049/iet-cdt:20050209.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

7

Shi, Zhendong, Haocheng Ma, Qizhi Zhang, Yanjiang Liu, Yiqiang Zhao, and Jiaji He. "Test Generation for Hardware Trojan Detection Using Correlation Analysis and Genetic Algorithm." ACM Transactions on Embedded Computing Systems 20, no. 4 (June 2021): 1–20. http://dx.doi.org/10.1145/3446837.

Повний текст джерела

Анотація:

Hardware Trojan (HT) is a major threat to the security of integrated circuits (ICs). Among various HT detection approaches, side channel analysis (SCA)-based methods have been extensively studied. SCA-based methods try to detect HTs by comparing side channel signatures from circuits under test with those from trusted golden references. The pre-condition for SCA-based HT detection to work is that the testers can collect extra signatures/anomalies introduced by activated HTs. Thus, activation of HTs and amplification of the differences between circuits under test and golden references are the keys to SCA-based HT detection methods. Test vectors are of great importance to the activation of HTs, but existing test generation methods have two major limitations. First, the number of test vectors required to trigger HTs is quite large. Second, the HT circuit’s activities are marginal compared with the whole circuit’s activities. In this article, we propose an optimized test generation methodology to assist SCA-based HT detection. Considering the HTs’ inherent surreptitious nature, inactive nodes with low transition probability are more likely to be selected as HT trigger nodes. Therefore, the correlations between circuit inputs and inactive nodes are first exploited to activate HTs. Then a test reordering process based on the genetic algorithm (GA) is implemented to increase the proportion of the HT circuit’s activities to the whole circuit’s activities. Experiments on 10 selected ISCAS benchmarks, wb_conmax benchmark, and b17 benchmark demonstrate that the number of test vectors required to trigger HTs reduces 28.8% on average compared with the result of MERO and MERS methods. After the test vector reordering process, the proportion of the HT circuit’s activities to the whole circuit’s activities is improved by 95% on average, compared with the result of MERS method.

Стилі APA, Harvard, Vancouver, ISO та ін.

8

Han, Gu Jing, Meng Zou, and Wu Zhi Min. "Research on Deadbeat Control for Three-Phase Grid-Connected Inverter in Model Based Design." Applied Mechanics and Materials 241-244 (December 2012): 1159–63. http://dx.doi.org/10.4028/www.scientific.net/amm.241-244.1159.

Повний текст джерела

Анотація:

Using model based design(MBD) method, deadbeat control algorithm for three-phase grid-connected inverter was designed in optimization and realized in hardware. According to the advanced idea of MBD and its basic procedure, the software-in-loop(SIL) test, processor-in-loop(PIL) test and hardware-in-loop(HIL) test for deadbeat control algorithm were mainly researched under MATLAB/Simulink environment choosing TMS320F2812 as object hardware board. In such method, embedded codes could be produced automatically and the errors brought in through algorithm model could be tested and corrected earlier. Meanwhile, simply changing the PIL related modules, the self-defined deadbeat algorithm module could be flexibly applied in other hardware platforms. At last, the correctness and efficiency of deadbeat control algorithm were verified in three-phase grid-connected inverter experiment platform.

Стилі APA, Harvard, Vancouver, ISO та ін.

9

Alymova, E. V., and O. V. Khachkinaev. "Automation of Software and Hardware Systems Acceptance Testing in the Paradigm of Behavior-Driven Development." Informacionnye Tehnologii 29, no. 4 (April 18, 2023): 186–96. http://dx.doi.org/10.17587/it.29.189-196.

Повний текст джерела

Анотація:

The paper is devoted to the problem of software and hardware systems acceptance testing according to the Agile Testing methodology. The Agile approach is widely used by software developers, however, developers of software and hardware solutions rarely use this approach, not believing in its effectiveness. The paper assumes that for software and hardware complexes, the practice of continuous integration should be applicable and, as a result, test interaction with hardware at the level ofphysical interfaces performs automatically. The article's authors presented Accepta, a system for automating acceptance testing of software and hardware complexes, explicitly designed for the Agile Testing methodology in the context of continuous integration. The main component of Accepta is an interface block based on the Nucleo-F767ZI debug board manufactured by ST. Test actions that run within the framework of Accepta supplement by expanding the command system of the interface block. The software part, which implements the functions of test describing and execution, is based on the Cucumber framework for automating software systems acceptance testing. The requirements for the object under test and the scenarios for checking the requirements are described in the Gherkin language, which is close to the natural description. The test script steps are described programmatically in the Ruby language. The actual execution of test actions is provided by sending commands through the COM port to the interface unit and analyzing the received responses. As the practice of using Accepta in working projects has shown, this approach allows us to successfully apply the Agile development methodology for software and hardware systems. Due to the automotive interaction with the device under the test interface, high intensity of testing in the development process, including regression, is ensured. The regular testing consequence is fast feedback: as soon as any functionality stops working correctly, developers find out about it fast. At the same time, due to the use of test automation tools, the reproducibility of test action sequences led to the detection of a defect is ensured.

Стилі APA, Harvard, Vancouver, ISO та ін.

10

Wang, Zhi Shen, and Gang Yan Li. "Compensation Control Network and Test of Bus Air Brake System in Under-Pressure State." Applied Mechanics and Materials 711 (December 2014): 342–46. http://dx.doi.org/10.4028/www.scientific.net/amm.711.342.

Повний текст джерела

Анотація:

The paper aims at pressure compensation control of bus air brake system in under-pressure state, based on SAE J1939 protocol, using CAN bus technology, the nodes such as vehicle status data acquisition node, brake system pressure information collection node, brake pressure compensation controller node, brake actuator system node, test and diagnostic node were defined, hardware and software of communication interface were designed, under-pressure compensation control network of bus air brake system was built and test, the test results show reliability, stability, real-time of the network meet the requirements of brake control.

Стилі APA, Harvard, Vancouver, ISO та ін.

11

Pikuza, M. O., and S. Yu Mikhnevich. "Testing a hardware random number generator using NIST statistical test suite." Doklady BGUIR 19, no. 4 (July 1, 2021): 37–42. http://dx.doi.org/10.35596/1729-7648-2021-19-4-37-42.

Повний текст джерела

Анотація:

Random number generators are required for the operation of cryptographic information protection systems. For а correct application of the generator in the field of information security, it is necessary that its output sequence to be indistinguishable from a uniformly distributed random sequence. To verify this, it is necessary to test the generator output sequence using various statistical test suites such as Dihard and NIST. The purpose of this work is to test a prototype hardware random number generator. The generator is built on the basis of the ND103L noise diode and has a random digital sequence of binary numbers at the output. In the prototype there is a possibility of regulating the amount of reverse current through the noise diode, as well as setting the data acquisition period, i.e. data generation frequency. In the course of operation, a number of sequences of random numbers were removed from the generator at various values of the reverse current through the noise diode, the period of data acquisition and the ambient temperature. The resulting sequences were tested using the NIST statistical test suite. After analyzing the test results, it was concluded that the generator operates relatively stably in a certain range of initial parameters, while the deterioration in the quality of the generator's operation outside this range is associated with the technical characteristics of the noise diode. It was also concluded that the generator under study is applicable in certain applications and to improve the stability of its operation, it can be improved both in hardware and software. The results of this work can be useful to developers of hardware random number generators built according to a similar scheme.

Стилі APA, Harvard, Vancouver, ISO та ін.

12

Pomeranz, I., and S. M. Reddy. "Test compaction methods for transition faults under transparent-scan." IET Computers & Digital Techniques 3, no. 4 (2009): 315. http://dx.doi.org/10.1049/iet-cdt.2008.0115.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

13

Pomeranz, Irith. "Reducing the input test data volume under transparent scan." IET Computers & Digital Techniques 8, no. 1 (January 2014): 1–10. http://dx.doi.org/10.1049/iet-cdt.2013.0067.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

14

Li Jiang, Qiang Xu, K. Chakrabarty, and T. M. Mak. "Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20, no. 9 (September 2012): 1621–33. http://dx.doi.org/10.1109/tvlsi.2011.2160410.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

15

CHEN, CHENG-HSIEN, and CHEN-YI LEE. "REDUCE THE MEMORY BANDWIDTH OF 3D GRAPHICS HARDWARE WITH A NOVEL RASTERIZER." Journal of Circuits, Systems and Computers 11, no. 04 (August 2002): 377–91. http://dx.doi.org/10.1142/s0218126602000525.

Повний текст джерела

Анотація:

Currently, memory bandwidth has become the main bottleneck in graphics system. Reducing the memory access can reduce the power consumption and boost overall system performance. Low power technique is more important for graphics applications on hand-held or mobile device. In this paper, we propose a novel visibility driven rasterizer to reduce the memory access and operations on invisible pixels. It integrates with two-level hierarchical Z-buffer to do visibility driven rasterization. The rasterization scheme is tile-order scan-line based, and the rasterizer can smartly change the tile-size depending on the triangle size. This technique can balance the rasterization loading under different triangles. Moreover, we propose a fast visibility test algorithm to quickly reject a group of pixels within the tile. Simulation results show that the overall bandwidth reduction can be up to 60% under our test images.

Стилі APA, Harvard, Vancouver, ISO та ін.

16

Vannahme, Anna, Jonas Busch, Mathias Ehrenwirth, and Tobias Schrag. "Experimental Study of District Heating Substations in a Hardware-in-the-Loop Test Rig." Resources 12, no. 4 (March 26, 2023): 43. http://dx.doi.org/10.3390/resources12040043.

Повний текст джерела

Анотація:

This study compares two district heating substation systems for implementation in rural district heating networks with non-retrofitted single- and two-family houses. The aim is to determine which system has the potential to provide lower return temperatures and/or lower power peak demand. A hardware-in-the-loop-test rig was utilized to measure the two district heating substations under real operation conditions. This experimental study demonstrates that load balancing of the district heating network is attainable with the district heating substation with storage. This is especially advantageous when there is a high demand for domestic hot water. Overall, both systems yield comparable return temperatures.

Стилі APA, Harvard, Vancouver, ISO та ін.

17

Parlato, Aldo, Elio Tomarchio, Cristiano Calligaro, and Calogero Pace. "The methodology for active testing of electronic devices under the radiations." Nuclear Technology and Radiation Protection 33, no. 1 (2018): 53–60. http://dx.doi.org/10.2298/ntrp1801053p.

Повний текст джерела

Анотація:

The methodology, developed for active testing of electronic devices under the radiations, is presented. The test set-up includes a gamma-ray facility, the hardware board/fixtures and the software tools purposely designed and realized. The methodology is so wide-ranging to allow us the verification of different classes of electronic devices, even if only application examples for static random access memory modules are reported.

Стилі APA, Harvard, Vancouver, ISO та ін.

18

Kerzérho, V., P. Cauvet, S. Bernard, F. Azaïs, M. Renovell, M. Comte, and O. Chakib. "ADC Production Test Technique Using Low-Resolution Arbitrary Waveform Generator." VLSI Design 2008 (April 30, 2008): 1–8. http://dx.doi.org/10.1155/2008/482159.

Повний текст джерела

Анотація:

Standard production test techniques for ADC require an ATE with an arbitrary waveform generator (AWG) with a resolution at least 2 bits higher than the ADC under test resolution. This requirement is a real issue for the new high-performance ADCs. This paper proposes a test solution that relaxes this constraint. The technique allows the test of ADC harmonic distortions using only low-cost ATE. The method involves two steps. The first step, called the learning phase, consists in extracting the harmonic contributions from the AWG. These characteristics are then used during the second step, called the production test, to discriminate the harmonic distortions induced by the ADC under test from the ones created by the generator. Hardware experimentations are presented to validate the proposed approach.

Стилі APA, Harvard, Vancouver, ISO та ін.

19

Qian, Zheng Xiang, and Yong Xin Shi. "Design and Realization of Test System for UAV Aeronautic Electronic Equipment." Applied Mechanics and Materials 644-650 (September 2014): 1158–61. http://dx.doi.org/10.4028/www.scientific.net/amm.644-650.1158.

Повний текст джерела

Анотація:

A portable test system of aeronautic electronic equipment used for UAV is researched and designed in this paper, according to the computer test and control technology. The structure of hardware and software of test system is explained in detail. The system can meet the needs that UAV units test for these devices quickly and efficiently under field-war conditions. The application results indicate that the precision of this test system is up to the demand of UAV weapon system.

Стилі APA, Harvard, Vancouver, ISO та ін.

20

Niu, Ruibin. "Mechanical Vibration Test Based on the Wireless Vibration Monitoring System." Security and Communication Networks 2022 (August 25, 2022): 1–8. http://dx.doi.org/10.1155/2022/9022128.

Повний текст джерела

Анотація:

In order to apply wireless sensor networks to mechanical vibration monitoring, the author proposes a wireless network topology with multiple data collection points for mechanical vibration monitoring. This structure reduces the transmission load of the data collection point, increases the data transmission rate of the network, balances the energy dissipation in the network, and utilizes the general wireless sensor network hardware platform. The network transmission protocol and related auxiliary mechanisms are designed and implemented, and a wireless vibration monitoring test platform is constructed. The transmission performance of the network structure with multiple data collection points is evaluated through the actual test. The experimental results show that by using the wireless sensor network topology with multiple data collection points, it can meet the requirements of continuous transmission of vibration data obtained by 1 kHz sampling. Conclusion. The system performance of the wireless sensor network based on this network structure has been improved under the condition of general hardware, and the network structure of multiple data collection points shows good performance in the process of high-speed data transmission.

Стилі APA, Harvard, Vancouver, ISO та ін.

21

Lv, Zhao, Shuming Chen, and Yaohua Wang. "Simulation-Based Hardware Verification with a Graph-Based Specification." Mathematical Problems in Engineering 2018 (2018): 1–10. http://dx.doi.org/10.1155/2018/6398616.

Повний текст джерела

Анотація:

Simulation-based verification continues to be the primary technique for hardware verification due to its scalability and ease of use; however, it lacks exhaustiveness. Although formal verification techniques can exhaustively prove functional correctness, they are limited in terms of the scale of their design due to the state-explosion problem. Alternatively, semiformal approaches can involve a compromise between scalability, exhaustiveness, and resource costs. Therefore, we propose an event-driven flow graph-based specification, which can describe the cycle-accurate functional behaviors without the exploration of whole state space. To efficiently generate input sequences according to the proposed specification, we introduce a functional automatic test pattern generation (ATPG) approach, which involves the proposed intelligent redundancy-reduction strategy to solve problems of random test vectors. We also proposed functional coverage criterion based on the formal specification to support a more reliable measure of verification. We implement a verification platform based on the proposed semiformal approach and compare the proposed semiformal approach with the constrained randomized test (CRT) approach. The experiment results show that the proposed semiformal verification method ensures a more exhaustive and effective exploration of the functional correctness of designs under verification (DUVs).

Стилі APA, Harvard, Vancouver, ISO та ін.

22

Hazen, John, and L. Scorsone. "Infrared Sensor Calibration Facility." Journal of the IEST 35, no. 1 (January 1, 1992): 33–40. http://dx.doi.org/10.17764/jiet.2.35.1.d536816582691754.

Повний текст джерела

Анотація:

The Boeing Infrared Sensor (BIRS) Calibration Facility represents a major capital investment by The Boeing Company in optical and infrared technology. The facility was designed and built for calibrating and testing new generation large aperture long wave infrared (LWIR) sensors, seekers, and related technologies. The capability exists to perform both radiometric and goniometric calibrations of large infrared sensors under simulated environmental operating conditions. The system is presently configured for endoatmospheric calibrations with a uniform background field that can be set to simulate the expected mission background levels. During calibration, the sensor under test is also exposed to expected mission temperatures and pressures within the test chamber. The facility could be converted for exoatmospheric testing. The first major test runs in the facility were completed during 1989 with very satisfactory results. This paper will describe system configuration and hardware elements, and will address the modifications made to date. Pitt-Des Moines. Inc. (PDM) of Pittsburgh, Pennsylvania, was the contractor for the turnkey design and construction of the test chambers and thermal vacuum systems. Hughes Danbury Optical Systems (formerly Perkin Elmer Optical Systems) was the hardware supplier for the optical hardware. The Boeing Company performed all optical assembly, integration, testing, and alignment on-site.

Стилі APA, Harvard, Vancouver, ISO та ін.

23

Zhi, Chuan. "Research on the Physical Training under the Internet Environment." Applied Mechanics and Materials 687-691 (November 2014): 2875–78. http://dx.doi.org/10.4028/www.scientific.net/amm.687-691.2875.

Повний текст джерела

Анотація:

The Web-Based Physical Education is an assistant physical education mode that in the use of computer technology, multimedia technology and Internet technology physical education, aid physical educators and student to learn sports knowledge, access to sports information, learn sports skills, watch sports game, study sports theory, test knowledge and ability, operate distance learning and so on online, and achieve the information exchange between people and computer or among people, with the hardware software facilities and campus Internet especially developed for the education.

Стилі APA, Harvard, Vancouver, ISO та ін.

24

Salman, Muhammad, Antoine Ligot, and Mauro Birattari. "Concurrent design of control software and configuration of hardware for robot swarms under economic constraints." PeerJ Computer Science 5 (September 30, 2019): e221. http://dx.doi.org/10.7717/peerj-cs.221.

Повний текст джерела

Анотація:

Designing a robot swarm is challenging due to its self-organized and distributed nature: complex relations exist between the behavior of the individual robots and the collective behavior that results from their interactions. In this paper, we study the concurrent automatic design of control software and the automatic configuration of the hardware of robot swarms. We introduce Waffle, a new instance of the AutoMoDe family of automatic design methods that produces control software in the form of a probabilistic finite state machine, configures the robot hardware, and selects the number of robots in the swarm. We test Waffle under economic constraints on the total monetary budget available and on the battery capacity of each individual robot comprised in the swarm. Experimental results obtained via realistic computer-based simulation on three collective missions indicate that different missions require different hardware and software configuration, and that Waffle is able to produce effective and meaningful solutions under all the experimental conditions considered.

Стилі APA, Harvard, Vancouver, ISO та ін.

25

Siddiqui, Atif, Muhammad Yousuf Irfan Zia, and Pablo Otero. "A Universal Machine-Learning-Based Automated Testing System for Consumer Electronic Products." Electronics 10, no. 2 (January 10, 2021): 136. http://dx.doi.org/10.3390/electronics10020136.

Повний текст джерела

Анотація:

Consumer electronic manufacturing (CEM) companies face a constant challenge to maintain quality standards during frequent product launches. A manufacturing test verifies product functionality and identifies manufacturing defects. Failure to complete testing can even result in product recalls. In this research, a universal automated testing system has been proposed for CEM companies to streamline their test process in reduced test cost and time. A universal hardware interface is designed for connecting commercial off-the-shelf (COTS) test equipment and unit under test (UUT). A software application, based on machine learning, is developed in LabVIEW. The test site data for around 100 test sites have been collected. The application automatically selects COTS test equipment drivers and interfaces on UUT and test measurements for test sites through a universal hardware interface. Further, it collects real-time test measurement data, performs analysis, generates reports and key performance indicators (KPIs), and provides recommendations using machine learning. It also maintains a database for historical data to improve manufacturing processes. The proposed system can be deployed standalone as well as a replacement for the test department module of enterprise resource planning (ERP) systems providing direct access to test site hardware. Finally, the system is validated through an experimental setup in a CEM company.

Стилі APA, Harvard, Vancouver, ISO та ін.

26

Siddiqui, Atif, Muhammad Yousuf Irfan Zia, and Pablo Otero. "A Universal Machine-Learning-Based Automated Testing System for Consumer Electronic Products." Electronics 10, no. 2 (January 10, 2021): 136. http://dx.doi.org/10.3390/electronics10020136.

Повний текст джерела

Анотація:

Consumer electronic manufacturing (CEM) companies face a constant challenge to maintain quality standards during frequent product launches. A manufacturing test verifies product functionality and identifies manufacturing defects. Failure to complete testing can even result in product recalls. In this research, a universal automated testing system has been proposed for CEM companies to streamline their test process in reduced test cost and time. A universal hardware interface is designed for connecting commercial off-the-shelf (COTS) test equipment and unit under test (UUT). A software application, based on machine learning, is developed in LabVIEW. The test site data for around 100 test sites have been collected. The application automatically selects COTS test equipment drivers and interfaces on UUT and test measurements for test sites through a universal hardware interface. Further, it collects real-time test measurement data, performs analysis, generates reports and key performance indicators (KPIs), and provides recommendations using machine learning. It also maintains a database for historical data to improve manufacturing processes. The proposed system can be deployed standalone as well as a replacement for the test department module of enterprise resource planning (ERP) systems providing direct access to test site hardware. Finally, the system is validated through an experimental setup in a CEM company.

Стилі APA, Harvard, Vancouver, ISO та ін.

27

Tang, Yan Kun, Kun Yang, Yan Nan Zhai, and Hui Zhang. "A Design of Safety Lock Testing Instrument Based on 89S52 Singlechip and LabVIEW." Applied Mechanics and Materials 347-350 (August 2013): 1549–52. http://dx.doi.org/10.4028/www.scientific.net/amm.347-350.1549.

Повний текст джерела

Анотація:

A design method of safety lock test based on 89S52 Singlechip is put forward and hardware structure and circuit scheme is introduced. Through the modularized design method of software, parameters of safety lock under different conditions are measured and quality test of safety lock is achieved.

Стилі APA, Harvard, Vancouver, ISO та ін.

28

Bai, Yang, Xin Zhang, Qiang Yang, Yong Yang, Weibo Deng, and Di Yao. "Multi-Channel Data Acquisition Card under New Acquisition and Transmission Architecture of High Frequency Ground Wave Radar." Sensors 21, no. 4 (February 5, 2021): 1128. http://dx.doi.org/10.3390/s21041128.

Повний текст джерела

Анотація:

It is known that the data acquisition and processing system plays an important role in radar target detection system. In order to meet the requirements of real-time processing and accurate transmission of echo signals in high-frequency ground-wave radar (HFGWR) systems, a new acquisition and transmission framework utilizing the designed acquisition card based on the PCIe (peripheral component interconnect express) has been designed and is presented in this paper. The Xilinx FPGA (Field-Programmable Gate Array) chip Kintex7-XC7K325T is adopted as a hardware carrier in acquisition card. The hardware’s composition, analog front-end circuit, the DMA (Direct Memory Access) transmission, FPGA structure, ADC (Analog-to-Digital Converter) chip, and performance test of this card are showed and discussed. Currently, the acquisition card has been accomplished and applied in the practical system of HFGWR.

Стилі APA, Harvard, Vancouver, ISO та ін.

29

Testori, Marcello, Olivier Lamquet, and Giuliano Matli. "Real-Time hardware-in-the-loop grid simulator to test generating units’ speed governors under islanding operating conditions." IFAC-PapersOnLine 49, no. 27 (2016): 188–94. http://dx.doi.org/10.1016/j.ifacol.2016.10.681.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

30

Edemsky, Dmitry, Alexei Popov, Igor Prokopovich, and Vladimir Garbatsevich. "Airborne Ground Penetrating Radar, Field Test." Remote Sensing 13, no. 4 (February 12, 2021): 667. http://dx.doi.org/10.3390/rs13040667.

Повний текст джерела

Анотація:

Deployment of a ground penetrating radar (GPR) on a flying machine allows one to substantially extend the application area of this geophysical method and to simplify carrying out large surveys of dangerous and hard-to-reach terrain, where usual ground-based methods are hardly applied. There is a necessity to promote investigations in this direction by modifying hardware characteristics and developing specific proceeding algorithms. For this purpose, we upgraded commercial ground-based subsurface sounding hardware and performed corresponding computer simulation and real experiments. Finally, the first experimental flights were done with the constructed GPR prototype mounted on a helicopter. Using our experience in the development of ground-based GPR and the results of numerical simulations, an appropriate configuration of antennas and their placing on the flying machine were chosen. Computer modeling allowed us to select an optimal resistive loading of transmitter and receiver dipoles; calculate radiation patterns on fixed frequencies; analyze the efficiency of different conductor diameters in antenna circuit; calculate cross-coupling of transmitting and receiving antennas with the helicopter. Preliminary laboratory experiments to check the efficiency of the designed system were performed on an urban building site, using a tower crane with the horizontal jib to operate the measuring system in the air above the ground area to be sounded. Both signals from the surface and subsurface objects were recorded. To interpret the results, numerical modeling was carried out. A two-dimensional model of our experiment was simulated, it matches well the experimental data. Laboratory experiments provided an opportunity to estimate the level of spurious reflections from the external objects, which helps to recognize weak signals from subsurface objects in GPR surveys under live conditions.

Стилі APA, Harvard, Vancouver, ISO та ін.

31

Schoberer, Thomas, Jan Weyr, Gernot Steindl, Gregor Görtler, and Werner Stutterecker. "Comparison of the Energy Performance of a Heat Pump under Various Conditions by Using a Hardware-in-the-Loop (HIL) Test Method." Applied Mechanics and Materials 887 (January 2019): 622–32. http://dx.doi.org/10.4028/www.scientific.net/amm.887.622.

Повний текст джерела

Анотація:

For nearly Zero Energy Buildings, it is a challenge to optimize the heat supply of the building based on technologies like heat pumps. Within the project “energy4buildings” a test bench has been realized to create an interface between hardware, located in a laboratory, and a building simulation software. This integrated test bench with a focus on electrical driven heat pumps and chillers can be used to simulate realistic conditions like part load behavior, stand-by-losses, on/off behavior or user-/weather conditions by using different kind of building models. The requirements of the test rig have been realized by using a hardware-in-the loop (HIL) method, which allows real-time tests of embedded devices within a virtual environment under reproducible laboratory conditions. By using the HIL-method, early statements according performance with a reduction of costs under realistic conditions can be made for various devices. This paper describes the implementation of the HIL-interface consisting of hardware, simulation software and data acquisition including an optimization of the behaviour of the control system as well as HIL experiments at varying steady state conditions like temperature tolerance or holding time. Based on the tests both, a comparison of the performance and analyses of deviations between real and simulated value have been made, to make an accurate statement of the behaviour of the system. The knowledge gained in this paper indicates a potential for optimization of the control strategy of some components as well as the improvement of the communication process to make an early estimation regarding performance of the installed device.

Стилі APA, Harvard, Vancouver, ISO та ін.

32

Horen, Y., A. Kuperman, Z. Vainer, S. Tapuchi, and M. Averbukh. "Emulating time varying nonlinear uncertainties and disturbances in linear time invariant systems." SIMULATION 88, no. 12 (September 26, 2012): 1499–507. http://dx.doi.org/10.1177/0037549712459788.

Повний текст джерела

Анотація:

An approach allowing the creation of parameter uncertainties and external disturbances without any hardware parts supplementary to the nominal system is proposed in this manuscript. The emulating signal, reflecting the plant variations, essential for testing of controllers, is created in software and added to the plant input, forcing the nominal system output to resemble the output of a system with actual uncertainties and disturbances, thus allowing us to test the controller’s robustness prior to an actual field test. In addition, the full state vector of the emulated system may be reconstructed and fed back to the controller, if necessary. The proposed methods allow simultaneous emulation of any combination of time-varying parameter variations and external disturbances. The method can be related to a class of enhanced hardware-in-the-loop simulations, since the nominal hardware is present in the setup in addition to the controller under test. The proposed techniques can be used to test the performance of advanced control algorithms before their mass production. Extended simulation results are reported to confirm the feasibility of the proposed approaches.

Стилі APA, Harvard, Vancouver, ISO та ін.

33

Weyr, Jan, Thomas Schoberer, and Werner Stutterecker. "Communication Analysis of Hardware-in-the-Loop Test Method for Heat Pumps and Chillers." Applied Mechanics and Materials 887 (January 2019): 587–96. http://dx.doi.org/10.4028/www.scientific.net/amm.887.587.

Повний текст джерела

Анотація:

There are many modelling and simulation methods and techniques, which may be used for prediction or reproduction of heat pumps and chillers behaviour. The hardware-in-the-loop method (HIL) is a technique developed to test a system and its elements working real-time to validate simulated values and to determine the actual performance of heating and cooling capability and performance of the whole system under specific conditions. The HIL can also serve as an intermediate step before testing a system in its actual environment providing opportunity to change boundary conditions or use different control mechanisms. This paper deals with the analysis complexity and possible inaccuracies due to communication difficulties between the test rig and simulation software and due to the test rig hydraulic character. We test and compare several simulation and communication variants such as different time step or different steady-state detection methods in order to achieve the most realistic behaviour of the heat pump and the whole system. The main result of this research is enhancement of communication and simulation accuracy and speedup of the whole process.

Стилі APA, Harvard, Vancouver, ISO та ін.

34

Marinissen, E. J., B. Vermeulen, H. Hollmann, and R. G. Bennetts. "Minimizing pattern count for interconnect test under a ground bounce constraint." IEEE Design & Test of Computers 20, no. 2 (March 2003): 8–18. http://dx.doi.org/10.1109/mdt.2003.1188257.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

35

Porobic, Vlado, Evgenije Adzic, and Milan Rapaic. "HIL evaluation of control unit in grid-tied coverters." Thermal Science 20, suppl. 2 (2016): 393–406. http://dx.doi.org/10.2298/tsci150928025p.

Повний текст джерела

Анотація:

Hardware-in-the-Loop (HIL) emulation is poised to become unsurpassed design tool for development, testing, and optimization of real-time control algorithms for grid connected power electronics converters for distributed generation, active filters and smart grid applications. It is strongly important to examine and test how grid connected converters perform under different operating conditions including grid disturbances and faults. In that sense, converter?s controller is a key component responsible for ensuring safe and high-performance operation. This paper demonstrates an example how ultra-low latency and high fidelity HIL emulator is used to easily, rapidly and exhaustively test and validate standard control strategy for grid connected power electronics converters, without need for expensive hardware prototyping and laboratory test equipment.

Стилі APA, Harvard, Vancouver, ISO та ін.

36

Wang, Weizheng, Zhuo Deng, and Jin Wang. "Enhancing Sensor Network Security with Improved Internal Hardware Design." Sensors 19, no. 8 (April 12, 2019): 1752. http://dx.doi.org/10.3390/s19081752.

Повний текст джерела

Анотація:

With the rapid development of the Internet-of-Things (IoT), sensors are being widely applied in industry and human life. Sensor networks based on IoT have strong Information transmission and processing capabilities. The security of sensor networks is progressively crucial. Cryptographic algorithms are widely used in sensor networks to guarantee security. Hardware implementations are preferred, since software implementations offer lower throughout and require more computational resources. Cryptographic chips should be tested in a manufacturing process and in the field to ensure their quality. As a widely used design-for-testability (DFT) technique, scan design can enhance the testability of the chips by improving the controllability and observability of the internal flip-flops. However, it may become a backdoor to leaking sensitive information related to the cipher key, and thus, threaten the security of a cryptographic chip. In this paper, a secure scan test architecture was proposed to resist scan-based noninvasive attacks on cryptographic chips with boundary scan design. Firstly, the proposed DFT architecture provides the scan chain reset mechanism by gating a mode-switching detection signal into reset input of scan cells. The contents of scan chains will be erased when the working mode is switched between test mode and functional mode, and thus, it can deter mode-switching based noninvasive attacks. Secondly, loading the secret key into scan chains of cryptographic chips is prohibited in the test mode. As a result, the test-mode-only scan attack can also be thwarted. On the other hand, shift operation under functional mode is disabled to overcome scan attack in the functional mode. The proposed secure scheme ensures the security of cryptographic chips for sensor networks with extremely low area penalty.

Стилі APA, Harvard, Vancouver, ISO та ін.

37

Wang, Jun, and Xiao Lu Li. "Dynamic Temperature Test for PTC Material Used to Heat Diesel." Applied Mechanics and Materials 321-324 (June 2013): 158–62. http://dx.doi.org/10.4028/www.scientific.net/amm.321-324.158.

Повний текст джерела

Анотація:

This paper gives a way which utilizes the PTC (positive temperature coefficient) materials to preheat diesel in the injector in order to improve the cold start performance and emissions of engine. Combining high performance data acquisition system based on MSP430F149, a dynamic temperature testing system was developed to test fuel temperature heated by PTC in injector. The software and hardware electrocircuit were expounded in detail. The temperature varying law of diesel fuel heated with PTC ceramics was measured under different voltage. A conclusion can be draw that diesel fuel may be heated to self-defined temperature around Curie point when diesel fuel was heated with PTC material.

Стилі APA, Harvard, Vancouver, ISO та ін.

38

Pomeranz, I., and S. M. Reddy. "Test generation for embedded circuits under the transparent-scan approach." IEE Proceedings - Computers and Digital Techniques 152, no. 6 (2005): 713. http://dx.doi.org/10.1049/ip-cdt:20045151.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

39

Liu, Mengnan, Chuiquan Wei, and Liyou Xu. "Development of Cooperative Controller for Dual-Motor Independent Drive Electric Tractor." Mathematical Problems in Engineering 2020 (November 11, 2020): 1–12. http://dx.doi.org/10.1155/2020/4826904.

Повний текст джерела

Анотація:

This paper proposes a control strategy of dual-motor independent drive electric tractor with cooperative control power take-off (PTO) and driving systems by investigating its structural characteristics to meet the field operation requirements. In the following operation mode, the vehicle speed is taken as the input signal, and the PTO motor speed is followed by the vehicle speed at a proportional ratio. Four different principles of collaborative control strategy-based stability control, namely, general closed-loop, conventional PID, adaptive fuzzy PID, and fuzzy neural network adaptive PID controls, are proposed to meet the requirements during speed change. Hardware design is divided into modules in accordance with circuit function. Software design is divided into application layer and underlying software, where the application software realizes the control strategy of the entire machine. The underlying software is based on the hardware driver of MC9S12XEP100 that connects the application layer software and hardware. A hardware-in-the-loop test platform based on dSPACE/DS1007 is built to test the function of the collaborative controller. Results show that the stabilization time of fuzzy neural network adaptive PID control is 0.024 s. Compared with the three other control modes, the settling time decreases by 0.256, 0.034, and 0.028, respectively, and the overshoot decreases to 1.6%. Root locus analysis results show that the stability of the system is the best. Under the entire machine cooperative operation mode hardware in the loop test, the PTO motor maintains the fixed target speed under the fixed speed output mode, and the PTO speed in the following mode has a good follow-up to the vehicle speed. The controller realizes the control of the power output shaft to cut between the following and standard speeds. It also meets the requirement of cooperative control in the operation of dual-motor independent drive electric tractor.

Стилі APA, Harvard, Vancouver, ISO та ін.

40

Abdurakhmanov, Sh, Zh Chyngysheva, B. Musaliev, and E. Tilekov. "Results of the Controlled Clinical Test of Intraoperative Blood Reinfusion Hardware, Assembled From the Abdominal Cavity in Conditions of Slow and Fast Modes." Bulletin of Science and Practice 6, no. 2 (February 15, 2020): 111–17. http://dx.doi.org/10.33619/2414-2948/51/08.

Повний текст джерела

Анотація:

Conducting parallel clinical and experimental control on the basis of controlled clinical trials was necessitated by, on the whole, a more thorough assessment of the effectiveness of intraoperative blood reinfusion hardware with the establishment of the possibility of ‘transfer’ of experimental data on modeling cavity blood loss to a clinical platform. Objective: a comparative description of the results of the following studies performed in the context of controlled clinical trials: 1) experimental control — a study of blood collected from the pleural and abdominal cavities before and after intraoperative blood reinfusion hardware under simulation conditions in animal injuries of the abdomen and chest with the formation, respectively, of hemothorax and hemoperitoneum; 2) clinical control — a study of blood collected from the abdominal and thoracic cavities before and after intraoperative blood reinfusion hardware in patients with injuries and injuries of the chest and abdomen with the corresponding formation of hemothorax and hemoperitoneum.

Стилі APA, Harvard, Vancouver, ISO та ін.

41

Zhang, Wei Xin, Wei Bing Bai, Chao Xu, Wei Yuan Chen, and Rui Jiang. "A Facial Recognition System Based on Integral Image." Applied Mechanics and Materials 687-691 (November 2014): 3905–8. http://dx.doi.org/10.4028/www.scientific.net/amm.687-691.3905.

Повний текст джерела

Анотація:

This article made a in-depth research of the face detection with the method of integral image, which is based on image capture and recognition technology, and designed the hardware circuit and software program development framework. Designed hardware circuit platform around the Cortex-A8 core processor in hardware, which was exclusively for the camera driver, face recognition and image capture. Prorammed face detection code with QT, and finally transplanted the face detection program to ARM board. Results show that the system has a high identification rate correctly and a good real-time performance under normal lighting conditions after a certain sample size of the test.

Стилі APA, Harvard, Vancouver, ISO та ін.

42

Kladovščikov, Leonid, Marijan Jurgo, and Romualdas Navickas. "Design of an Oscillation-Based BIST System for Active Analog Integrated Filters in 0.18 µm CMOS." Electronics 8, no. 7 (July 20, 2019): 813. http://dx.doi.org/10.3390/electronics8070813.

Повний текст джерела

Анотація:

In this paper, an oscillation-based built-in self-test system for active an analog integrated circuit is presented. This built-in self-test system was used to detect catastrophic and parametric faults, introduced during chip manufacturing. As circuits under test (CUT), second-order Sallen-Key, Akerberg-Mossberg and Tow-Thomas biquad filters were designed. The proposed test hardware detects parametric and catastrophic faults on changeable limits. The influence of both oscillation and test hardware on fault detection limits were investigated and analyzed. The proposed oscillation based self-test system was designed and simulated in 0.18 µm complementary metal-oxide semiconductor (CMOS) technology. Due to the easiness of implementation and configuration for testing of different active analog filters, such self-test systems can be effectively used in modern integrated circuits, made of a large number of devices and circuits, such as the multi-standard transceivers used in the core hardware of software-defined radios. Using the proposed test strategy, the fault tolerance limits for catastrophic faults varied from 96% to 100% for all injected faults in different structures of low pass filters (LPF). The detection range of parametric faults of passive components’ nominal value, depending on the used structure of the filter, did not exceed –0.74% – 0.72% in case of Sallen-Key, –3.31% – 1.00% in case of Akerberg-Mossberg and –2.39% – 1.44% in case of Tow-Thomas LPF.

Стилі APA, Harvard, Vancouver, ISO та ін.

43

Leibfritz, M. M., M. D. Blech, F. M. Landstorfer, and T. F. Eibert. "A comparison of software- and hardware-gating techniques applied to near-field antenna measurements." Advances in Radio Science 5 (June 12, 2007): 43–48. http://dx.doi.org/10.5194/ars-5-43-2007.

Повний текст джерела

Анотація:

Abstract. It is well-known that antenna measurements are error prone with respect to reflections within an antenna measurements test facility. The influence on near-field (NF) measurements with subsequent NF to far-field (FF) transformation can be significantly reduced applying soft- or hard-gating techniques. Hard-gating systems are often used in compact range facilities employing fast PIN-diode switches (Hartmann, 2000) whereas soft-gating systems utilize a network analyzer to gather frequency samples and eliminate objectionable distortions in the time-domain by means of Fourier-transformation techniques. Near-field (NF) antenna measurements are known to be sensitive to various errors concerning the measurement setup as there have to be mentioned the accuracy of the positioner, the measurement instruments or the quality of the anechoic chamber itself. Two different approaches employing soft- and hard-gating techniques are discussed with respect to practical applications. Signal generation for the antenna under test (AUT) is implemented using a newly developed hard-gating system based on digital signal synthesis allowing gate-widths of 250 ps to 10 ns. Measurement results obtained from a Yagi-Uda antenna under test (AUT) and a dual polarized open-ended waveguide used as probe antenna are presented for the GSM 1800 frequency range.

Стилі APA, Harvard, Vancouver, ISO та ін.

44

Liu, Yanjiang, Yiqiang Zhao, Jiaji He, and Ruishan Xin. "A Statistical Test Generation Based on Mutation Analysis for Improving the Hardware Trojan Detection." Journal of Circuits, Systems and Computers 29, no. 03 (June 3, 2019): 2050049. http://dx.doi.org/10.1142/s0218126620500498.

Повний текст джерела

Анотація:

Hardware Trojan has become a major threat to the security and trustworthiness of integrated circuit (IC) employed in critical applications. Due to the presence of process variations and measurement noises, all existing side-channel Trojan detection approaches suffer from low detection sensitivity or even false negatives with increasing circuit size and decreasing Trojan size. In this paper, we propose a statistical test generation approach based on mutation analysis, which generates a set of test vectors aiming at activating the hardware Trojan inserted into the low activity nodes. Such approach not only enhances the controllability of low activity nodes through increasing the switching activity of it, but also improves the observability by propagating the artificial designed errors introduced by the mutant to the outputs. Simulation results of a set of ISCAS’85 and ISCAS’89 benchmark circuits show that the proposed approach improves the activity of low activity nodes 463% at most compared with the Multiple Excitation of Rare Occurrence (MERO) approach and increases the Trojan coverage with 84.08% reduction in test length. Moreover, the test vectors generated by the proposed approach and the MERO approach, respectively, are exerted to the circuit under test. Experimental results demonstrate that the Mahalanobis distance margin of the proposed approach is much greater than the MERO approach, and thus provide a comparable robustness with decreasing Trojan size.

Стилі APA, Harvard, Vancouver, ISO та ін.

45

HIGAMI, Yoshinobu, Hiroshi TAKAHASHI, Shin-ya KOBAYASHI, and Kewal K. SALUJA. "Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment." IEICE Transactions on Information and Systems E96.D, no. 6 (2013): 1323–31. http://dx.doi.org/10.1587/transinf.e96.d.1323.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

46

Balike, M., S. Rakheja, and S. V. Hoa. "STUDY OF AN ENERGY DISSIPATING UNDER-RIDE GUARD USING HARDWARE-IN-THE-LOOP SIMULATION." Transactions of the Canadian Society for Mechanical Engineering 23, no. 2 (June 1999): 307–20. http://dx.doi.org/10.1139/tcsme-1999-0021.

Повний текст джерела

Анотація:

Hardware-in-the-Loop (HIL) simulation technique is implemented to analyze the performance characteristics of an energy dissipative under-ride guard system for enhancement of crashworthiness of lightweight vehicles involved in coillisions with heavy freight vehicles. The experimental setup, software and hardware interface, and the test methodology used to perform the HIL simulation are briefly described. The energy dissipating under-ride guard, while impacted by a car body, is analytically modeled incorporating nonlinearities due to asymmetric damping in compression and rebound, restoring properties and kinematics of linkages, using the principles of conservation of momentum and Lagrangian dynamics. The performance characteristics of the under-ride guard are evaluated under direct impact at different speeds, and the results obtained from the HIL simulation are compared with those derived from the nonlinear analytical model. The study revealed very good correlation between the analytical and experimental findings in terms of the amount of energy dissipated, acceleration level, rebound velocity and the magnitude of intrusion. An analysis of the results showed that significant portion of the kinetic energy can be dissipated by the under-ride guard.

Стилі APA, Harvard, Vancouver, ISO та ін.

47

Muhammad, Moiz, Holger Behrends, Stefan Geißendörfer, Karsten von Maydell, and Carsten Agert. "Power Hardware-in-the-Loop: Response of Power Components in Real-Time Grid Simulation Environment." Energies 14, no. 3 (January 25, 2021): 593. http://dx.doi.org/10.3390/en14030593.

Повний текст джерела

Анотація:

With increasing changes in the contemporary energy system, it becomes essential to test the autonomous control strategies for distributed energy resources in a controlled environment to investigate power grid stability. Power hardware-in-the-loop (PHIL) concept is an efficient approach for such evaluations in which a virtually simulated power grid is interfaced to a real hardware device. This strongly coupled software-hardware system introduces obstacles that need attention for smooth operation of the laboratory setup to validate robust control algorithms for decentralized grids. This paper presents a novel methodology and its implementation to develop a test-bench for a real-time PHIL simulation of a typical power distribution grid to study the dynamic behavior of the real power components in connection with the simulated grid. The application of hybrid simulation in a single software environment is realized to model the power grid which obviates the need to simulate the complete grid with a lower discretized sample-time. As an outcome, an environment is established interconnecting the virtual model to the real-world devices. The inaccuracies linked to the power components are examined at length and consequently a suitable compensation strategy is devised to improve the performance of the hardware under test (HUT). Finally, the compensation strategy is also validated through a simulation scenario.

Стилі APA, Harvard, Vancouver, ISO та ін.

48

Delgado, María Luisa, Jorge E. Jiménez-Hornero, and Francisco Vázquez. "Design, Implementation and Validation of a Hardware-in-the-Loop Test Bench for Heating Systems in Conventional Coaches." Applied Sciences 13, no. 4 (February 9, 2023): 2212. http://dx.doi.org/10.3390/app13042212.

Повний текст джерела

Анотація:

Experimental work with heating systems installed in public transport vehicles, particularly for optimisation and control design, is a challenging task due to cost and space limitations, primarily imposed by the heating hardware and the need to have a real vehicle available. In this work, a hybrid hardware-in-the-loop (HIL) test bench for heating systems in conventional coaches is introduced. This approach consists of a hardware system made up of the main heating components, assembled as a lab experimental plant, along with a simulation component including a cabin thermal model, both exchanging real-time data using a standard communication protocol. This scheme presents great flexibility regarding data logging for further analysis and easily changing the experimental operational conditions and disturbances under different scenarios (i.e., solar irradiance, outside temperature, water temperature from the engine cooling circuit, number of passengers, etc.). Comparisons between the hybrid system’s transient and steady-state responses and those from selected experiments conducted on an actual coach allowed us to conclude that the proposed system is a suitable test bed to aid in optimisation and design tasks. In this context, several closed-loop test experiments using the test bench were additionally carried out to assess the performance of the proposed control system.

Стилі APA, Harvard, Vancouver, ISO та ін.

49

Iman-Eini, Hossein, and Sarath B. Tennakoon. "Investigation of a cascaded H-bridge photovoltaic inverter under non-uniform insolation conditions by hardware-in-the-loop test." International Journal of Electrical Power & Energy Systems 105 (February 2019): 330–40. http://dx.doi.org/10.1016/j.ijepes.2018.08.017.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

50

Garzia, Fabio, Johannes Rossouw van der Merwe, Alexander Rügamer, Santiago Urquijo, and Wolfgang Felber. "HDDM Hardware Evaluation for Robust Interference Mitigation." Sensors 20, no. 22 (November 13, 2020): 6492. http://dx.doi.org/10.3390/s20226492.

Повний текст джерела

Анотація:

Interference can significantly degrade the performance of global navigation satellite system (GNSS) receivers. Therefore, mitigation methods are required to ensure reliable operations. However, as there are different types of interference, robust, multi-purpose mitigation algorithms are needed. This paper describes the most popular state-of-the-art interference mitigation techniques. The high-rate DFT-based data manipulator (HDDM) is proposed as a possible solution to overcome their limitations. This paper presents a hardware implementation of the HDDM algorithm. The hardware HDDM module is integrated in three different receivers equipped with analog radio-frequency (RF) front-ends supporting signals with different dynamic range. The resource utilization and power consumption is evaluated for the three cases. The algorithm is compared to a low-end mass-market receiver and a high-end professional receiver with basic and sophisticated interference mitigation capabilities, respectively. Different type of interference are used to compare the mitigation capabilities of the receivers under test. Results of the HDDM hardware implementation achieve the similar or improved performance to the state of the art. With more complex interferences, like frequency hopping or pulsed, the HDDM shows even better performance.

Стилі APA, Harvard, Vancouver, ISO та ін.

Статті в журналах з теми "Hardware Under Test"

Оформте джерело за APA, MLA, Chicago, Harvard та іншими стилями