Готові списки джерел за темами / Hardware Model Checking

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Опубліковано: 14 березня 2023

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Статті в журналах з теми "Hardware Model Checking"

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Pixley, Carl, and Vigyan Singhal. "Model checking: a hardware design perspective." International Journal on Software Tools for Technology Transfer (STTT) 2, no. 3 (November 1, 1999): 288–306. http://dx.doi.org/10.1007/s100090050036.

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Gong, Wei, and Jun Wei Jia. "Comparison of Model Checking Tools." Advanced Materials Research 659 (January 2013): 181–85. http://dx.doi.org/10.4028/www.scientific.net/amr.659.181.

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Анотація:
Model Checking is a method for verification. The model will be checked until the specification of it is proved or disproved. With the rising complexity of big models, there are non-checkable cases, in which cases the problem can be analyzed by some models, for example, bounded Model Checking means to analyze the model until a defined time or depth. The verification happens automatically. The programs for doing this are called Model Checking Tools or Model Checker. Model Checking are used in both software and hardware verification. It is an inherent part of hardware verification, whereas it is less used in the software verification.
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Vasudevan, Shobha, E. Allen Emerson, and Jacob A. Abraham. "Efficient Model Checking of Hardware Using Conditioned Slicing." Electronic Notes in Theoretical Computer Science 128, no. 6 (May 2005): 279–94. http://dx.doi.org/10.1016/j.entcs.2005.04.017.

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Moiseenko, Evgenii, Michalis Kokologiannakis, and Viktor Vafeiadis. "Model checking for a multi-execution memory model." Proceedings of the ACM on Programming Languages 6, OOPSLA2 (October 31, 2022): 758–85. http://dx.doi.org/10.1145/3563315.

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Multi-execution memory models, such as Promising and Weakestmo, are an advanced class of weak memory consistency models that justify certain outcomes of a concurrent program by considering multiple candidate executions collectively. While this key characteristic allows them to support effective compilation to hardware models and a wide range of compiler optimizations, it makes reasoning about them substantially more difficult. In particular, we observe that Promising and Weakestmo inhibit effective model checking because they allow some suprisingly weak behaviors that cannot be generated by examining one execution at a time. We therefore introduce Weakestmo2, a strengthening of Weakestmo by constraining its multi-execution nature, while preserving the important properties of Weakestmo: DRF theorems, compilation to hardware models, and correctness of local program transformations. Our strengthening rules out a class of surprisingly weak program behaviors, which we attempt to characterize with the help of two novel properties: load buffering race freedom and certification locality. In addition, we develop WMC, a model checker for Weakestmo2 with performance close to that of the best tools for per-execution models.
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Li, Dejian, Qizhi Zhang, Dongyan Zhao, Lei Li, Jiaji He, Yidong Yuan, and Yiqiang Zhao. "Hardware Trojan Detection Using Effective Property-Checking Method." Electronics 11, no. 17 (August 24, 2022): 2649. http://dx.doi.org/10.3390/electronics11172649.

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Hardware Trojans refer to additional logic maliciously implanted by attackers in integrated circuits (ICs). Because of the potential security threat of hardware Trojans, they have attracted extensive attention to security issues. As a formal verification method, property checking has been proved to be a powerful solution for hardware Trojan detection. However, existing property-checking methods are limited by the unity of security properties and the model explosion problem of formal models. The limitations above hinder the practical applications of these methods. To alleviate these challenges, we propose an effective property-checking method for hardware Trojan detection. Specifically, we establish the formal model based on the principle of finite state machine (FSM), and the method can alleviate the model explosion problem. For property writing, we extract the core behavior characteristics of hardware Trojans and then generate properties for the verification of certain types of hardware Trojans. Experimental results demonstrate that our approach is applicable to detect information leakage and denial of service (DoS) hardware Trojans by verifying security properties.
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McMillan, K. L. "A methodology for hardware verification using compositional model checking." Science of Computer Programming 37, no. 1-3 (May 2000): 279–309. http://dx.doi.org/10.1016/s0167-6423(99)00030-1.

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Bjesse, Per. "Word level bitwidth reduction for unbounded hardware model checking." Formal Methods in System Design 35, no. 1 (July 7, 2009): 56–72. http://dx.doi.org/10.1007/s10703-009-0080-2.

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Zhang, Jie, Jian Qi, and Yong Guan. "Research on Hardware Design Verification Methods." Advanced Materials Research 588-589 (November 2012): 1208–13. http://dx.doi.org/10.4028/www.scientific.net/amr.588-589.1208.

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This paper first summarizes the existing basic theories and methods of hardware design verification. Then it analyzes and compares the simulation-based verification and formal methods-based verification, and discusses Equivalence Checking, Model Checking and Theorem Proving in detail. Finally, it points out the existing problems and the future directions in the field.
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Cooke, John. "Symbolic Model Checking." Microprocessors and Microsystems 18, no. 5 (June 1994): 297. http://dx.doi.org/10.1016/0141-9331(94)90007-8.

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Ben-David, Shoham, Cindy Eisner, Daniel Geist, and Yaron Wolfsthal. "Model Checking at IBM." Formal Methods in System Design 22, no. 2 (March 2003): 101–8. http://dx.doi.org/10.1023/a:1022905120346.

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Дисертації з теми "Hardware Model Checking"

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Ford, Gregory Fick. "Hardware Emulation of Sequential ATPG-Based Bounded Model Checking." Case Western Reserve University School of Graduate Studies / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=case1384265165.

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Raju, Akhilesh. "Trojan Detection in Hardware Designs." University of Cincinnati / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1504781162418081.

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VENDRAMINETTO, DANILO. "Advanced Techniques for Bit-Level Model Checking." Doctoral thesis, Politecnico di Torino, 2016. http://hdl.handle.net/11583/2643478.

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With increasing design complexity, verification becomes a more and more important aspect of the design flow: modern circuits contain up to several million transistors, causing verification to be the major bottleneck and the most expensive stage. This is one of the reasons why Formal Verification techniques are gaining large attention, since they allow to prove correctness of a circuit (ensuring a total functional correctness) compared to classical simulation, which cannot guarantee sufficient coverage of the design, due to its intrinsic not complete nature. Being Formal Verification a complete technique, its natural application can be found in all those critical systems where the absence of bugs is mandatory. In particular, hardware design can be considered as one of the most critical areas, due to the difficulties (and costs) involved in solving a fault introduced at the design stage, but exposed only after its manufacturing. On the other hand, generally speaking, a software system could be patched easily, just releasing a newer version of the software itself. Nevertheless recently also software applications are becoming a relevant area of application for Formal Verification techniques, especially concerning safety critical applications, software security aspects and firmware of embedded systems. Nowadays the most widely used approach to Formal Verification is Model Checking, which consists of a systematically exhaustive exploration of the mathematical model of the system under analysis. The great advantage of Model Checking is that, provided the model of the system and the property to check, it is fully automatic; while its primary disadvantage relies on the difficulty to scale to large systems. The main goal of this Ph.D. dissertation is to present improvements to Model Checking algorithms for hardware design, focused on scalability and efficiency aspects. Every contribution is provided with exhaustive experimental data, performed on industrial test-cases. This dissertation studies also a recent but equally relevant (and critical) area of application for Model Checking algorithms: the verification of security properties in embedded systems. In this context, due to the novelty of this topic, efforts were oriented to study the applicability of the Model Checking approach, leaving the scalability aspects to further works.
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Marques, Luis Gustavo Perpetuo Costa. "Metodologia de desenvolvimento de VHDL sintetizável com uso de model checking." reponame:Repositório Institucional da UFSC, 2016. https://repositorio.ufsc.br/xmlui/handle/123456789/168246.

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Анотація:
Dissertação (mestrado) - Universidade Federal de Santa Catarina, Centro Tecnológico, Programa de Pós-Graduação em Engenharia de Automação e Sistemas, Florianópolis, 2016.
Made available in DSpace on 2016-09-20T05:06:37Z (GMT). No. of bitstreams: 1 340508.pdf: 1748559 bytes, checksum: 4657b6761e65d66a2334a312d9f91477 (MD5) Previous issue date: 2016
Essa dissertação foi elaborada em uma companhia que desenvolve equipamentos para proteção e automação de subestações, sendo que a maior parte deles possui um FPGA programado em VHDL como unidade principal de processamento. O código VHDL sintetizável e validado através de simulação e testes em equipamento, método bastante comum mas que não e suficiente para garantir a satisfação de propriedades tanto gerais quanto orientadas a aplicação, devido ao fato de não ser exaustivo. Na direção de aumentar a confiabilidade do circuito projetado para o FPGA, o objetivo principal da dissertação e apresentar uma metodologia de desenvolvimento de codigo VHDL sintetizável que aprimore as atuais técnicas utilizadas, ao incorporar métodos formais para verificação de propriedades, sendo que o método formal utilizado e o model checking. A metodologia e construída de um modo que o uso do model checking seja transparente ao desenvolvedor VHDL, mantendo a interface com o processo de verificação formal em linguagem de usuário,evitando a necessidade de aprendizado de novas linguagens. Para atingir esse objetivo específico, e proposto que as propriedades sejam representadas através de padrões orientados a VHDL que são baseados na biblioteca OVL. Alem disso, os contraexemplos gerados no processo de model checking retornam como test bench VHDL, permitindo ao usuário identificar o comportamento indesejado através de simulação. O ambiente de verificação adotado utiliza modelos em linguagem intermediaria FIACRE como front-end e por isso são propostas regras de tradução VHDL-FIACRE para que a transformação possa ocorrer no contexto de engenharia dirigida a modelos e assim evitar erros no processo de tradução. O uso da linguagem intermediaria e vantajoso, pois permite a utilização das ferramentas de verificação, as quais são de código aberto,sem que seja necessária a tradução direta do VHDL para os formalismos matemáticos em que essas ferramentas se baseiam. A metodologia e validada com a aplicação em quatro exemplos de código VHDL, sendo dois deles utilizados em projetos desenvolvidos na empresa: uma função de proteção e um controlador de acesso a um barramento de transferência de dados. Os resultados da aplicação indicam que a proposta e viável,pois foi possível fazer a verificação dos exemplos, sendo que em um deles foi identificado um erro que havia passado despercebido por simulação, sinalizando que a proposta contribui no aumento da confiabilidade do código desenvolvido.

Abstract: This dissertation was elaborated in a company that develops equipment for substation protection and automation, most of them having an FPGA programmed in VHDL as the main processing unit. The synthesizable VHDL code is validated through simulation and tests on equipment, a fairly common method that is not enough to ensure the satisfaction of both general and application-oriented properties, due tothe fact of being non exhaustive. In the direction of increasing the reliability of the designed FPGA circuit, the main objective of thiswork is to present a synthesizable VHDL code development methodology that enhances the current techniques by incorporating formal methods for verication of properties, with model checking being theselected method. The methodology is constructed in such a way thatthe use of model checking procedure should be transparent to VHDL designers, keeping the interface with the formal verication process inuser language, avoiding the need to learn new languages. To achievethis specic objective, it is proposed that the properties are represented by VHDL oriented patterns based on OVL library. In addition, the counter examples generated in the model checking process for properties that failed, return as VHDL test bench, allowing the user to identify theundesired behavior through simulation. The verication environment used in the methodology requires models described with the intermediatelanguage FIACRE as front-end and so VHDL-FIACRE translation rules are proposed to allow the transformation to occur in the context of model driven engineering, and thus prevent errors in the translation process. The use of an intermediate language is advantageous because it allows the use of the verication tools, which are open source, withoutthe need of translating VHDL directly to the mathematical formalismin which these tools are based. The methodology is validated by the application in four examples of VHDL code, two of them are used in designs developed by the company: a protection function and a controller to access a data transfer bus. The application results indicate that the proposal is viable because it was possible to verify the examples,and for one of them was identied an error that had passed unnoticed by simulation, showing that the proposal contributes to increase the reliability of the created code.
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Dharmadhikari, Pranav Hemant. "Hardware Trojan Detection in Sequential Logic Designs." University of Cincinnati / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1543919236213844.

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Bingham, Brad. "Leveraging distributed explicit-state model checking for practical verification of liveness in hardware protocols." Thesis, University of British Columbia, 2015. http://hdl.handle.net/2429/52670.

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Protocol verification is a key component to hardware and software design. The proliferation of concurrency in modern designs stresses the need for accurate protocol models and scalable verification tools. Model checking is an approach for automatically verifying properties of designs, the main limitation of which is state-space explosion. As such, automatic verification of these designs can quickly exhaust the memory of a single computer. This thesis presents PReach, a distributed explicit-state model checker, designed to robustly harness the aggregate computing power of large clusters. The initial version verified safety properties, which hold if no error states can be reached. PReach has been demonstrated to run on hundreds of machines and explore state space sizes up to 90 billion, the largest published to date. Liveness is an important class of properties for hardware system correctness which, unlike safety, expresses more elaborate temporal reasoning. However, model checking of liveness is more computationally complex, and exacerbates scalability issues as compared with safety. The main thesis contribution is the extension of PReach to verify two key liveness-like properties of practical interest: deadlock-freedom and response. Our methods leverage the scalability and robustness of PReach and strike a balance between tractable verification for large models and catching liveness violations. Deadlock-freedom holds if from all reachable system states, there exists a sequence of actions that will complete all pending transactions. We find that checking this property is only a small overhead as compared to safety checking. We also provide a technique for establishing that deadlock-freedom holds of a parameterized system -- a system with a variable number of entities. Response is a stronger property than deadlock-freedom and is the most common liveness property of interest. In practical cases, fairness must be imposed on system models when model checking response to exclude those execution traces deemed inconsistent with the expected underlying hardware. We implemented a novel twist on established model checking algorithms, to target response properties with action-based fairness. This implementation vastly out-performs competing tools. This thesis shows that tractable verification of interesting liveness properties in large protocol models is possible.
Science, Faculty of
Computer Science, Department of
Graduate
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Ou, Jen-Chieh. "HARDWARE DESCRIPTION LANGUAGE PROGRAM SLICING AND WAY TO REDUCE BOUNDED MODEL CHECKING SEARCH OVERHEAD." Case Western Reserve University School of Graduate Studies / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=case1159738055.

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Adams, Sara Elisabeth. "Abstraction discovery and refinement for model checking by symbolic trajectory evaluation." Thesis, University of Oxford, 2014. http://ora.ox.ac.uk/objects/uuid:27276f9c-eba5-42a9-985d-1812097773f8.

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This dissertation documents two contributions to automating the formal verification of hardware – particularly memory-intensive circuits – by Symbolic Trajectory Evaluation (STE), a model checking technique based on symbolic simulation over abstract sets of states. The contributions focus on improvements to the use of BDD-based STE, which uses binary decision diagrams internally. We introduce a solution to one of the major hurdles in using STE: finding suitable abstractions. Our work has produced the first known algorithm that addresses this problem by automatically discovering good, non-trivial abstractions. These abstractions are computed from the specification, and essentially encode partial input combinations sufficient for determining the specification’s output value. They can then be used to verify whether the hardware model meets its specification using a technique based on and significantly extending previous work by Melham and Jones [2]. Moreover, we prove that our algorithm delivers correct results by construction. We demonstrate that the abstractions received by our algorithm can greatly reduce verification costs with three example hardware designs, typical of the kind of problems faced by the semiconductor design industry. We further propose a refinement method for abstraction schemes when over- abstraction occurs, i.e., when the abstraction hides too much information of the original design to determine whether it meets its specification. The refinement algorithm we present is based on previous work by Chockler et al. [3], which selects refinement candidates by approximating which abstracted input is likely the biggest cause of the abstraction being unsuitable. We extend this work substantially, concentrating on three aspects. First, we suggest how the approach can also work for much more general abstraction schemes. This enables refining any abstraction allowed in STE, rather than just a subset. Second, Chockler et al. describe how to refine an abstraction once a refinement candidate has been identified. We present three additional variants of refining the abstraction. Third, the refinement at its core depends on evaluating circuit logic gates. The previous work offered solutions for NOT- and AND-gates. We propose a general approach to evaluating arbitrary logic gates, which improves the selection process of refinement candidates. We show the effectiveness of our work by automatically refining an abstraction for a content-addressable memory that exhibits over-abstraction, and by evaluating some common logic gates. These two contributions can be used independently to help automate the hard- ware verification by STE, but they also complement each other. To show this, we combine both algorithms to create a fully automatic abstraction discovery and refinement loop. The only inputs required are the hardware design and the specification, which the design should meet. While only small circuits could be verified completely automatically, it clearly shows that our two contributions allow the construction of a verification framework that does not require any user interaction.
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Jafri, Nisrine. "Formal fault injection vulnerability detection in binaries : a software process and hardware validation." Thesis, Rennes 1, 2019. http://www.theses.fr/2019REN1S014/document.

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L'injection de faute est une méthode bien connue pour évaluer la robustesse et détecter les vulnérabilités des systèmes. La détection des vulnérabilités créées par injection de fautes a été approchée par différentes méthodes. Dans la littérature deux approches existent: les approches logicielles et les approches matérielles. Les approches logicielles peuvent fournir une large et rapide couverture, mais ne garantissent pas la présence de vulnérabilité dans le système. Les approches matérielles sont incontestables dans leurs résultats, mais nécessitent l’utilisation de matériaux assez coûteux et un savoir-faire approfondi, qui ne permet tout de même pas dans la majorité des cas de confirmer le modèle de faute représentant l'effet créé. Dans un premier lieu, cette thèse se concentre sur l'approche logicielle et propose une approche automatisée qui emploie les techniques de la vérification formelle pour détecter des vulnérabilités créées par injection de faute au niveau binaire. L'efficacité de cette approche est montrée en l'appliquant à des algorithmes de cryptographie implémentés dans les systèmes embarqués. Dans un second lieu, cette thèse établit un rapprochement entre les deux approches logicielles et matérielles sur la détection de vulnérabilité d'injection de faute en comparant les résultats des expériences des deux approches. Ce rapprochement des deux approches démontre que: toutes les vulnérabilités détectées par l'approche logicielle ne peuvent pas être reproduites dans le matériel; les conjectures antérieures sur le modèle de faute par des attaques d'impulsion électromagnétique ne sont pas précises ; et qu’il y a un lien entre les résultats de l’approche logicielle et l'approche matérielle. De plus, la combinaison des deux approches peut rapporter une approche plus précise et plus efficace pour détecter les vulnérabilités qui peuvent être créées par injection de faute
Fault injection is a well known method to test the robustness and security vulnerabilities of systems. Detecting fault injection vulnerabilities has been approached with a variety of different but limited methods. Software-based and hardware-based approaches have both been used to detect fault injection vulnerabilities. Software-based approaches can provide broad and rapid coverage, but may not correlate with genuine hardware vulnerabilities. Hardware-based approaches are indisputable in their results, but rely upon expensive expert knowledge, manual testing, and can not confirm what fault model represent the created effect. First, this thesis focuses on the software-based approach and proposes a general process that uses model checking to detect fault injection vulnerabilities in binaries. The efficacy and scalability of this process is demonstrated by detecting vulnerabilities in different cryptographic real-world implementations. Then, this thesis bridges software-based and hardware-based fault injection vulnerability detection by contrasting results of the two approaches. This demonstrates that: not all software-based vulnerabilities can be reproduced in hardware; prior conjectures on the fault model for electromagnetic pulse attacks may not be accurate; and that there is a relationship between software-based and hardware-based approaches. Further, combining both software-based and hardware-based approaches can yield a vastly more accurate and efficient approach to detect genuine fault injection vulnerabilities
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PASINI, PAOLO. "Improving bit-level model checking algorithms for scalability through circuit-based reasoning." Doctoral thesis, Politecnico di Torino, 2017. http://hdl.handle.net/11583/2680998.

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In the last few years real-life designs have become more and more complex, thus proper circuit management, simplification and transformation proved as important as the actual verification procedure. On the other hand, given the impossibility to determine a priori the best algorithm to use for each benchmark, portfolio approaches have become the de-facto standard in model checking. Tuning parameterization and behavior of the various algorithms in play is nowadays a must. This dissertation describes the activities conducted during the whole PhD course span, concerning model checking algorithms and preprocessing techniques in the context of industrial-derived hardware designs. More in details, some studies addressed during these years focused on appropriate property management, efficient model preprocessing techniques, proper SAT solver management and the introduction of a novel model checking algorithm.
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Книги з теми "Hardware Model Checking"

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Hana, Chockler, and Hu, Alan J. (Alan John), eds. Hardware and software: Verification and testing : 4th International Haifa Verification Conference, HVC 2008, Haifa, Israel, October 27-30, 2008 : proceedings. Berlin: Springer, 2009.

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Namjoshi, Kedar S. Hardware and Software: Verification and Testing: 5th International Haifa Verification Conference, HVC 2009, Haifa, Israel, October 19-22, 2009, Revised Selected Papers. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011.

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3

Dominique, Borrione, Paul Wolfgang J. 1951-, and IFIP WG 10 5, eds. Correct hardware design and verification methods: 13th IFIP WG 10.5 advanced research working conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005 ; proceedings. Berlin: Springer, 2005.

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Частини книг з теми "Hardware Model Checking"

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Eisner, Cindy, and Dana Fisman. "Functional Specification of Hardware via Temporal Logic." In Handbook of Model Checking, 795–829. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-10575-8_24.

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Roman, Carlos M., Gary De Palma, and Robert Kurshan. "Model Checking without Hardware Drivers." In Advances in Hardware Design and Verification, 127. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-0-387-35190-2_8.

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Yu, Zhengqi, Armin Biere, and Keijo Heljanko. "Certifying Hardware Model Checking Results." In Formal Methods and Software Engineering, 498–502. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-32409-4_32.

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Vardi, Moshe Y. "Automata-Theoretic Model Checking Revisited." In Hardware and Software: Verification and Testing, 2. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-01702-5_2.

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Henzinger, Thomas A. "Model Checking: From Hardware to Software." In Programming Languages and Systems, 176–77. Berlin, Heidelberg: Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-40018-9_12.

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Leucker, Martin. "On Model Checking Synchronised Hardware Circuits." In Advances in Computing Science — ASIAN 2000, 182–98. Berlin, Heidelberg: Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/3-540-44464-5_14.

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Beyer, Dirk, and Thomas Lemberger. "Software Verification: Testing vs. Model Checking." In Hardware and Software: Verification and Testing, 99–114. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-70389-3_7.

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Yu, Emily, Armin Biere, and Keijo Heljanko. "Progress in Certifying Hardware Model Checking Results." In Computer Aided Verification, 363–86. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-81688-9_17.

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AbstractWe present a formal framework to certify k-induction-based model checking results. The key idea is the notion of a k-witness circuit which simulates the given circuit and has a simple inductive invariant serving as proof certificate. Our approach allows to check proofs with an independent proof checker by reducing the certification problem to pure SAT checks and checking a simple QBF with one quantifier alternation. We also present Certifaiger, the resulting certification toolkit, and evaluate it on instances from the hardware model checking competition. Our experiments show the practical use of our certification method.
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Bloemen, Vincent, and Jaco van de Pol. "Multi-core SCC-Based LTL Model Checking." In Hardware and Software: Verification and Testing, 18–33. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-49052-6_2.

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Andrés, Miguel E., Pedro D’Argenio, and Peter van Rossum. "Significant Diagnostic Counterexamples in Probabilistic Model Checking." In Hardware and Software: Verification and Testing, 129–48. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-01702-5_15.

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Тези доповідей конференцій з теми "Hardware Model Checking"

1

Biere, Armin, Tom van Dijk, and Keijo Heljanko. "Hardware model checking competition 2017." In 2017 Formal Methods in Computer Aided Design (FMCAD). IEEE, 2017. http://dx.doi.org/10.23919/fmcad.2017.8102233.

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2

Singh, Gaurav, and Sandeep K. Shukla. "Model Checking Bluespec Specified Hardware Designs." In 2007 IEEE International Workshop on Microprocessor Test and Verification (MTV). IEEE, 2007. http://dx.doi.org/10.1109/mtv.2007.9.

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3

Bormann, Jörg, Jörg Lohse, Michael Payer, and Gerd Venzl. "Model checking in industrial hardware design." In the 32nd ACM/IEEE conference. New York, New York, USA: ACM Press, 1995. http://dx.doi.org/10.1145/217474.217545.

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4

Jorg Bormann. "Model Checking in Industrial Hardware Design." In 32nd Design Automation Conference. ACM, 1995. http://dx.doi.org/10.1109/dac.1995.249963.

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5

Cruz, Jonathan, Farimah Farahmandi, Alif Ahmed, and Prabhat Mishra. "Hardware Trojan Detection Using ATPG and Model Checking." In 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID). IEEE, 2018. http://dx.doi.org/10.1109/vlsid.2018.43.

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6

Kumar, Binod, Akshay Kumar Jaiswal, V. S. Vineesh, and Rushikesh Shinde. "Analyzing Hardware Security Properties of Processors through Model Checking." In 2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID). IEEE, 2020. http://dx.doi.org/10.1109/vlsid49098.2020.00036.

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Berryhill, Ryan, and Andreas Veneris. "Chasing Minimal Inductive Validity Cores in Hardware Model Checking." In 2019 Formal Methods in Computer Aided Design (FMCAD). IEEE, 2019. http://dx.doi.org/10.23919/fmcad.2019.8894268.

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Seufert, Tobias, and Christoph Scholl. "Combining PDR and reverse PDR for hardware model checking." In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2018. http://dx.doi.org/10.23919/date.2018.8341978.

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9

Bradfield, Chris, and Cynthia Sturton. "Model checking to find vulnerabilities in an instruction set architecture." In 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST). IEEE, 2016. http://dx.doi.org/10.1109/hst.2016.7495566.

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Iwasaki, Naoki, and Katsumi Wasaki. "A Meta Hardware Description Language Melasy for Model-Checking Systems." In 2008 Fifth International Conference on Information Technology: New Generations (ITNG). IEEE, 2008. http://dx.doi.org/10.1109/itng.2008.135.

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