Дисертації з теми "Hardware Emulator"
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Persson, Robert. "PPS5000 Thruster Emulator Architecture Development & Hardware Design." Thesis, Luleå tekniska universitet, Rymdteknik, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-72827.
Повний текст джерелаStanley, Berdenia Walker. "Hierarchical multiway partitioning strategy with hardware emulator architecture intelligence." Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/13360.
Повний текст джерелаWitkowsky, Jason. "A hardware emulator testbed for a software-defined radio." Thesis, Peninsula Technikon, 2003. http://hdl.handle.net/20.500.11838/1170.
Повний текст джерелаContemporary software-defined radio (SDR) is continuously changing and challenging the way traditional RF systems operate. Having more of a radio system’s operation in software enables further flexibility through the use of software manipulation. Due to practical limitations, however, it is not always feasible to have the entire radio system’s operations performed using software. Practical limitations, therefore, require that a SDR employs some form of RF front-end in order to interface the antenna signals and the signals prior to the data converters. As technology grows in support of SDR development, this hardware interface is becoming increasingly smaller. The problem with the rapid rate at which SDR developments are occurring is that RF hardware needs to change accordingly. Therefore, the RF hardware front-end can be seen as a non-standardised piece of equipment. To the designer, this means having to prototype in hardware in order to experiment with various types of SDR hardware front-ends. One of a SDR’s main attractions is the inherent property of software testability. Taking this fact into account, this thesis investigates the design and operation of a basic softwaredriven RF front-end emulator for a SDR. Basic prototype software models are identified and developed in order to test their performance within the emulator. The focus of the thesis, however, is geared toward the development of a software architecture that enables a high degree of interchangeability amongst the underlying modelled components. In the case of a SDR, the advantage of prototyping in software is in predicting the behaviour of a system prior to having to perform any physical developments. This property of software testability in the emulator can only fully be appreciated if a bench-mark system is used to evaluate the overall performance of the emulator. Therefore, a physical hardware setup is performed in order to test the basic aspects of the emulators operation. This evaluation is not meant as an exhaustive analysis of the emulator, but aims to highlight the overall performance of the emulated system against a typical physical system setup.
Daniil, Nickolaos. "Battery emulator operating in a power hardware-in-the-loop simulation : the concept of hybrid battery emulator." Thesis, University of Bristol, 2017. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.723517.
Повний текст джерелаO'Rourke, Colm Joseph. "Design of a hardware solar emulator for an experimental microgrid." Thesis, Massachusetts Institute of Technology, 2015. http://hdl.handle.net/1721.1/99852.
Повний текст джерелаCataloged from PDF version of thesis.
Includes bibliographical references (pages 67-68).
Microgrids are regions where local generation and loads are clustered together. Students from the LEES group at MIT are currently developing an experimental microgrid. This will enable various studies in the area of microgrid dynamics. The setup consists of a variety of modules that emulate both conventional and renewable sources. In this thesis, we focus on the design of one of these modules: the solar PV emulator. The complete design of a solar PV emulator will be described. Firstly, AC and DC models of a solar cell are introduced. These models specify design constraints for the power electronic circuitry. They also indicate a desired performance for the feedback control system. The controller design is discussed and the effect of load type on the closed-loop dynamics are considered. This is especially interesting for the grid-connected case. The design methodology culminates in the construction of an experimental prototype of the hardware solar PV emulator. The modular design approach is outlined as are its benefits to the overall construction of the microgrid. A Generic Controller board that can be used for all future power electronic modules in the microgrid is also designed and fabricated. The results of simulations and experiments are discussed and it is shown that it is possible for a buck converter to emulate the steady state dynamics associated with solar PV panels.
by Colm Joseph O'Rourke.
S.M.
Petucco, Andrea. "Hardware in the loop, all-electronic wind turbine emulator for grid compliance testing." Doctoral thesis, Università degli studi di Padova, 2017. http://hdl.handle.net/11577/3422321.
Повний текст джерелаDuring the last years the distribution of renewable energy sources is continuously increasing and their influence on the distribution grid is becoming every year more relevant. As the increasing integration of renewable resources is radically changing the grid scenario, grid code technical requirements as are needed to ensure the grid correct behavior. To be standard compliant wind turbines need to be submitted to certification tests which usually must be performed on the field. One of the most difficult tests to be performed on the field is the low voltage ride through (LVRT) certitication due to the following resons: • The standards specify it must be performed ad different power levels. For this reasons it is necessary to wait for the right atmospheric conditions. • It requires a voltage sag generator which is usually expensive and bulky. • The voltage sag generator needs to be cabled between the grid and the wind turbine. • The voltage sag generator causes disturbances and perturbation on the power grid, for this reasons agreements with the distributor operator are needed. For all these reasons a laboratory test bench to perform the LVRT certification tests on wind turbines would be a more controlled and inexpensive alternative to the classic testing methodology. The research presented in this thesis is focused on the design and the realization of a test bench to perform certification tests on energy converters for wind turbines in laboratory. More specifically, the possibility of performing LVRT certification tests directly in laboratory over controlled conditions would allow faster testing procedures and less certification overall costs. The solution presented in this thesis is based on a power hardware in the loop implementing a digitally-controlled, power electronics-based emulation of a wind turbine. This emulator is used to drive the electronic wind energy converter (WEC) under test. A grid emulator is used to apply voltage sags to the wind turbine converter and perform LVRT certification tests. In this solution AC power supplies are used to emulate both the wind turbine and the grid emulator. For this reason the test bench power rating is limited to the AC supplies one. Two working versions of the test bench has been realized and successfully tested. The work here presented has evolved through the following phases: • Study of the grid code requirements and the state of the art. • Modeling of the parts of a wind turbine and complete system simulations.
Adnan, Muhammad Wasif. "Implementation of an FPGA based Emulator for High Speed Power Electronic Systems." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-175752.
Повний текст джерелаBeckert, René. "Untersuchungen zur Kostenoptimierung für Hardware-Emulatoren durch Anwendung von Methoden der partiellen Laufzeitrekonfiguration." Dresden TUDpress, 2008. http://d-nb.info/991847423/04.
Повний текст джерелаShadab, Rakin Muhammad. "Statistical Analysis of a Channel Emulator for Noisy Gradient Descent Low Density Parity Check Decoder." DigitalCommons@USU, 2019. https://digitalcommons.usu.edu/etd/7582.
Повний текст джерелаOliveira, José Rodrigo de. "Emulador de turbina eólica : uma ferramenta para o estudo experimental e computacional /." Bauru, 2019. http://hdl.handle.net/11449/191354.
Повний текст джерелаResumo: As fontes renováveis de energia apresentam-se como solução para problemas relacionados ao aumento da demanda por energia elétrica e crescimento dos níveis de emissão de gás carbônico, uma vez que são não poluentes, limpas e abundantes. Aproveitamentos eólicos se mostram como uma das mais promissoras fontes de energia renovável, e por essa razão as pesquisas envolvendo este tipo de aproveitamento têm despertado grande interesse na comunidade científica. Este trabalho apresenta o desenvolvimento de um emulador de turbina eólica (ETE), uma ferramenta de apoio às investigações experimentais capaz de reproduzir o comportamento mecânico dinâmico de uma turbina eólica através de uma malha de controle digital em configuração de hardware-in-the-loop atuando sobre um acionamento eletrônico de uma máquina de indução Operando como fonte de força motriz, o ETE torna mais fácil a avaliação dinâmica de geradores e seus sistemas de controle associados voltados às aplicações envolvendo energia eólica. A pesquisa apresenta uma revisão bibliográfica sobre o estado da arte, a modelagem e a implementação experimental de um emulador de turbina eólica utilizando um motor de indução trifásico (MIT) acionado por um inversor de frequência. Para isso, é implementado um controle em malha fechada de conjugado e velocidade. Este controle faz com que o acionamento eletromecânico representado pelo MIT e inversor de frequência apresente em seu eixo o comportamento de uma turbina eólica conforme os parâmetros... (Resumo completo, clicar acesso eletrônico abaixo)
Mestre
Tomaro, Emiliano. "Simulations and automated tests of battery management system control strategies and diagnosis on hardware in the loop system." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2019. http://amslaurea.unibo.it/19241/.
Повний текст джерелаThornes, Tobias. "Investigating the potential for improving the accuracy of weather and climate forecasts by varying numerical precision in computer models." Thesis, University of Oxford, 2018. http://ora.ox.ac.uk/objects/uuid:038874a3-710a-476d-a9f7-e94ef1036648.
Повний текст джерелаNagaonkar, Yajuvendra. "FPGA-based Experiment Platform for Hardware-Software Codesign and Hardware Emulation." Diss., CLICK HERE for online access, 2006. http://contentdm.lib.byu.edu/ETD/image/etd1294.pdf.
Повний текст джерелаWilliams, Steve. "Advanced Hardware-in-the-Loop Testing Assures RF Communication System Success." International Foundation for Telemetering, 2010. http://hdl.handle.net/10150/604299.
Повний текст джерелаRF Communication (COMMS) systems where receivers and transmitters are in motion must be proven rigorously over an array of natural RF link perturbations such as Carrier Doppler shift, Signal Doppler shift, delay, path loss and noise. These perturbations play significant roles in COMMS systems involving satellites, aircraft, UAVs, missiles, targets and ground stations. In these applications, COMMS system devices must also be tested against increasingly sophisticated intentional and unintentional interference, which must result in negligible impact on quality of service. Field testing and use of traditional test and measurement equipment will need to be substantially augmented with physics-compliant channel emulation equipment that broadens the scope, depth and coverage of such tests, while decreasing R&D and test costs and driving in quality. This paper describes dynamic link emulation driven by advanced antenna and motion modeling, detailed propagation models and link budget methods for realistic, nominal and worst-case hardware-in-the-loop test and verification.
Sedaghat, Maman Reza. "Fault emulation reconfigurable hardware based fault simulation using logic emulation systems with optimized mapping /." [S.l. : s.n.], 1999. http://deposit.ddb.de/cgi-bin/dokserv?idn=95853893X.
Повний текст джерелаFord, Gregory Fick. "Hardware Emulation of Sequential ATPG-Based Bounded Model Checking." Case Western Reserve University School of Graduate Studies / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=case1384265165.
Повний текст джерелаBeckert, René. "Untersuchungen zur Kostenoptimierung für Hardware Emulatoren durch Anwendung von Methoden der partiellen Laufzeitrekonfiguration." Doctoral thesis, Universitätsbibliothek Chemnitz, 2013. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-115411.
Повний текст джерелаCurrent circuit and system designs consist a lot of gate numbers and divergent requirements. In contrast to a short development and time to market schedule, the needs for perfect test coverage and quality are rising. One approach to cover this problem is the FPGA based functional test of electronic circuits. State of the art FPGA platforms doesn't consist enough gates to support fully custom designs. The thesis catches this problem and gives some approaches to use partial dynamic reconfiguration to solve the size problem. A fully automated design flow demonstrates partial partitioning of designs, modifications to use dynamic reconfiguration and its schedule. At the end of the work, some examples demonstrates the power of the approach
Almeida, Filipe Afonso de. "Parallel software emulation of multi-processor dataflow machines on transputer networks." Thesis, University of Kent, 1992. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.315170.
Повний текст джерелаWells, George James. "Hardware emulation and real-time simulation strategies for the concurrent development of microsatellite hardware and software." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp05/MQ62899.pdf.
Повний текст джерелаBeckert, René. "Untersuchungen zur Kostenoptimierung für Hardware-Emulatoren durch Anwendung von Methoden der partiellen Laufzeitrekonfiguration." TUDpress, 2008. https://monarch.qucosa.de/id/qucosa%3A19914.
Повний текст джерелаCurrent circuit and system designs consist a lot of gate numbers and divergent requirements. In contrast to a short development and time to market schedule, the needs for perfect test coverage and quality are rising. One approach to cover this problem is the FPGA based functional test of electronic circuits. State of the art FPGA platforms doesn't consist enough gates to support fully custom designs. The thesis catches this problem and gives some approaches to use partial dynamic reconfiguration to solve the size problem. A fully automated design flow demonstrates partial partitioning of designs, modifications to use dynamic reconfiguration and its schedule. At the end of the work, some examples demonstrates the power of the approach.
Päivänsäde, V. (Ville). "Dynamic power estimation with a hardware emulation acquired switching activity model." Master's thesis, University of Oulu, 2016. http://urn.fi/URN:NBN:fi:oulu-201609082736.
Повний текст джерелаTässä työssä tutkitaan dynaamista tehonkulutuksen estimointia rekisterinsiirtotasolla laitteistoemuloinnilla tuotetulla aktiivisuusmallilla. Työ koostuu käytännön osuudesta, jossa esitellään tutkittua vuota ja siihen liittyvää testaustyötä, ja teoriaosuudesta, jonka tarkoitus on tukea käytännön osuudessa käsiteltyjä aiheita. Teoriaosuudessa käsitellään CMOS-logiikkaan perustuvien mikropiiritekniikoiden yleisimpiä tehonkulutusmekanismeja ja lyhyesti niiden vähennystekniikoita. Lisäksi osiossa käsitellään elektroniikan suunnittelun automaatiotyökalujen yleisimpiä tehonkulutuksen estimointi- ja analyysimetodologioita. Käytännön osuudessa esitellään yhden elektroniikan automaatiotyökalun dynaaminen tehonkulutuksen estimointivuo. Vuossa suunnitelman pohjapiirros estimoidaan rekisterinsiirtotason laitteistokuvauskielisestä mallista nopean synteesin avulla ja aktiivisuusmalli tuotetaan laitteistoemuloinnilla. Tutkittu tehonkulutuksen estimointityökalu oli Joules RTL Power Solution ja laitteistoemulointijärjestelmä oli Palladium XP II Verification Computing Platform, molemmat Cadence Design Systemssiltä. Vuon lopullinen laadukkuus arvioitiin käyttäen laitteistokuvauskielistä testisuunnitelmamallia, kolmea erilaista testitapausta aktiivisuusmalleina ja olemassaolevaa porttitason dynaamista tehonkulutuksen analyysivuota referenssimallina. Esitellyn rekisterinsiirtotason vuon ja porttitason referenssivuon välinen ero oli keskimäärin 4,4 % kolmessa tutkitussa testitapauksessa. Täyden keskiarvoistetun estimointivuon ajoaika oli hieman yli tunnin, kun taas inkrementaalinen ajo ilman nopeaa synteesiä kesti noin 15 minuuttia
Driscoll, Scott Crawford. "The Design and Qualification of a Hydraulic Hardware-in-the-Loop Simulator." Thesis, Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7132.
Повний текст джерелаHanono, Silvina Zimi. "InnerView hardware debugger : a logic analysis tool for the Virtual Wires emulation system." Thesis, Massachusetts Institute of Technology, 1995. http://hdl.handle.net/1721.1/11855.
Повний текст джерелаMarko, Vekić. "Нови поступак за развој управљачких склопова енергетске електронике заснован на емулацији у стварном времену". Phd thesis, Univerzitet u Novom Sadu, Fakultet tehničkih nauka u Novom Sadu, 2014. http://dx.doi.org/10.2298/NS20131223VEKIC.
Повний текст джерелаU tezi je predložen postupak razvoja upravljačkih sklopova energetskeelektronike zasnovan na tehnologiji Hardware In the Loop. Podrobno jeopisan predloženi emulator sa naglaskom na specifičnommodelovanju pogodnom za izvršenje u stvarnom vremenu što jepreduslov verodostojnosti. Sama verodostojnost je proverenapoređenjem rezultata sa simulacijom, kao i sa izmerenim rezultatimau nekoliko stvarnih pogona. Zatim je postupak razvoja upravljačkihsklopova podrobno objašnjen na primeru razvoja i ispitivanja jednognovog kontrolnog algoritma za povezivanje sinhronog generatora naelektričnu mrežu.
This paper proposes development of Power Electronics controllers based onthe Hardware In the Loop technology. Proposed emulator is describied indetail where emphasis was set on specific methods of modeling which issuitable for real time emulations in order to obtain emulation faithfulness.Fidelity itself was checked through comparison with off-line simulations andresults of real drives. Procedure of controllers development was presentedthrough development and testing of one new control algorithm for connectionof the permanent magnet synchronous generator to the electrical grid.
Noon, John Patrick. "Development of a Power Hardware-in-the-Loop Test Bench for Electric Machine and Drive Emulation." Thesis, Virginia Tech, 2020. http://hdl.handle.net/10919/101498.
Повний текст джерелаMaster of Science
According to the International Energy Agency (IEA), electric power usage is increasing across all sectors, and particularly in the transportation sector [1]. This increase is apparent in one's daily life through the increase of electric vehicles on the road. Power electronics convert electricity in one form to electricity in another form. This conversion of power is playing an increasingly important role in society because examples of this conversion include converting the dc voltage of a battery to ac voltage in an electric car or the conversion of the ac power grid to dc to power a laptop. Additionally, even within an electric car, power converters transform the battery's electric power from a higher dc voltage into lower voltage dc power to supply the entertainment system and into ac power to drive the car's motor. The electrification of the transportation sector is leading to an increase in the amount of electric energy that is being consumed and processed through power electronics. As was illustrated in the previous examples of electric cars, the application of power electronics is very wide and thus requires different testbenches for the many different applications. While some industries are used to power electronics and testing converters, transportation electrification is increasing the number of companies and industries that are using power electronics and electric machines. As industry is shifting towards these new technologies, it is a prime opportunity to change the way that high power testing is done for electric machines and power converters. Traditional testing methods are potentially dangerous and lack the flexibility that is required to test a wide variety of machines and drives. Power hardware-in-the-loop (PHIL) testing presents a safe and adaptable solution to high power testing of electric machines. Traditionally, electric machines were primarily used in heavy industry such as milling, processing, and pumping applications. These applications, and other applications such as an electric motor in a car or plane are called motor drive systems. Regardless of the particular application of the motor drive system, there are generally three parts: a dc source, an inverter, and the electric machine. In most applications, other than cars which have a dc battery, the dc source is a power electronic converter called a rectifier which converts ac electricity from the grid to dc for the motor drive. Next, the motor drive converts the dc electricity from the first stage to a controlled ac output to drive the electric machine. Finally, the electric machine itself is the final piece of the electrical system and converts the electrical energy to mechanical energy which can drive a fan, belt, or axle. The fact that this motor drive system can be generalized and applied to a wide range of applications makes its study particularly interesting. PHIL simplifies testing of these motor drive systems by allowing the inverter to connect directly to a machine emulator which is able to replicate a variety of loads. Furthermore, this work demonstrates the capability of PHIL to emulate both the induction machine load as well as the dc source by considering several rectifier topologies without any significant adjustments from the machine emulation platform. This thesis demonstrates the capabilities of the EGSTON Power Electronics GmbH COMPISO System Unit to emulate motor drive systems to allow for safer, more flexible motor drive system testing. The main goal of this thesis is to demonstrate an accurate PHIL emulation of a induction machine and to provide validation of the emulation results through comparison with an induction machine.
Schmitt, Alexander [Verfasser]. "Hochdynamische Power Hardware-in-the-Loop Emulation hoch ausgenutzter Synchronmaschinen mit einem Modularen-Multiphasen-Multilevel Umrichter / Alexander Schmitt." Karlsruhe : KIT Scientific Publishing, 2017. http://www.ksp.kit.edu.
Повний текст джерелаSerdar, Usenmez. "Design Of An Integrated Hardware-in-the-loop Simulation System." Master's thesis, METU, 2010. http://etd.lib.metu.edu.tr/upload/2/12612051/index.pdf.
Повний текст джерелаLevrini, Giacomo. "Feasibility study and emulation of the Hough Transform algorithm on FPGA devices for ATLAS Phase-II trigger upgrade." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2020. http://amslaurea.unibo.it/22105/.
Повний текст джерелаVarais, Andy. "Modèles à échelle réduite en similitude pour l'ingénierie système et l'expérimentation simulée "temps compacté" : application à un microréseau incluant un stockage électrochimique." Thesis, Toulouse, INPT, 2019. http://www.theses.fr/2019INPT0007/document.
Повний текст джерелаThis thesis was carried out in collaboration with SCLE SFE (ENGIE Group) and the Laplacelaboratory. It focuses on the establishment of a methodology allowing the “similarity” modelsdevelopment, with reduced power and time scale. These models can be used for systems analysisbut they are particularly useful for real-time experimentation of energy systems. Indeed, theexperiments are often carried out on a small scale for issues of size, cost, … Some parts of theseexperiments can be "emulated" (physically simulated by power devices) while others consist ofphysical components: this is called the Hardware in the Loop (HIL) procedure. Although, initially,the downscaling approach is broad in scope, our main field of application is microgrids withintegration of intermittent renewable sources coupled with storage components. As a result, ourwork focuses on the implementation of power / energy / time similarity models of ENR sources andstorage facilities. The concept of time reduction, we will talk about "compacted virtual time", is oneof the key concepts of this work. Particular attention is paid to the development of a physicalemulator of electrochemical battery. Indeed, energy storage is a key point in microgrid. In addition,this element has strong nonlinearities whose scaling in similarity must imperatively take intoaccount and is not trivial. Once these models have been developed, they are tested through theimplementation of simulated experiments using physical emulators with reduced power scale andcompacted virtual time. These tests also make it possible to compare the concepts of "copymodel" emulators, for which a model is used to reproduce the behavior of the system, and "copyimage" emulators, where the behavior of the system is reproduced from of one of its realcomponents (for example a cell for the battery)
MONTEIRO, Heron Aragão. "Emulação de circuitos quânticos em Placa FPGA." Universidade Federal de Campina Grande, 2012. http://dspace.sti.ufcg.edu.br:8080/jspui/handle/riufcg/1368.
Повний текст джерелаMade available in DSpace on 2018-08-06T19:17:03Z (GMT). No. of bitstreams: 1 HERON ARAGÃO MONTEIRO - DISSERTAÇÃO PPGCC 2012..pdf: 15948168 bytes, checksum: e445512265f530700a45c3924f68aa02 (MD5) Previous issue date: 2012-05-31
Com o avanço da nanotecnologia, a computação quântica tem recebido grande destaque no meio científico. Utilizando os fundamentos da mecânica quântica, têm sido propostos diversos algoritmos quânticos. E, até então, os mesmos têm apresentado ganhos significativos com relação às suas versões clássicas. Na intenção de poder ser verificada a eficiência dos algoritmos quânticos, diversos simuladores vêm sendo desenvolvidos, visto que a confecção de um computador quântico ainda não foi possível. Há duas grandes vertentes de simuladores: os simuladores por software e os simuladores por hardware, chamados de emuladores. Na primeira classe se encontram os programas desenvolvidos em um computador clássico, procurando implementar os fundamentos da mecânica quântica, fazendo uso das linguagens de programação clássicas. Na segunda, são utilizados recursos que não estejam vinculados à plataforma do computador clássico. Dentre os emuladores, particularmente, estudos têm sido realizados fazendo uso de hardware dedicado (mais especificamente, FPGAV). O presente trabalho propõem a verificação da real utilidade da plataforma FPGA, com a intenção de se desenvolver um emulador universal, que permita a emulação de qualquer classe de circuitos, e que os mesmos possam ser implementados com um maior número de q-bits em relação aos circuitos tratados nos trabalhos anteriores.
With the progress of nanotechnology, quantum computing has received great emphasis in scientific circles. Using the basis of quantum mechanics, different quantum algorithms have been proposed. And so far, they have presented significant gains with respect to its classic versions. In order to verify the efficiency of quantum algorithms, several simulators have been developed, since the construction of a quantum computer is not yet possible. There are two major classes of simulators, simulators via software and via hardware. The latter being also called emulators. In the first class, programs are developed in a classical computer, attempting to implement the fundamentais of quantum mechanics, making use of classic programming languages. In the second, resources are used that are not related to the classic computer platform. Among the emulators, in particular, studies have been made using dedicated hardware (more specifically, FPGA's2). The present work proposes the use of the FPGA boards in emulation of quantum circuits aiming a gain scale in relation to the alternatives presented so far. The present work proposes checking the usefulness of the FPGA with the intention of developing an universal emulator that is able to emulate any type of circuit, and that they can be implemented with a larger number of q-bit in respect to the circuits treated in the previous works.
Beckert, René [Verfasser], Wolfram [Gutachter] Hardt, Ulrich [Gutachter] Heinkel, Christophe [Gutachter] Bobda, Wolfram [Akademischer Betreuer] Hardt, and Ulrich [Akademischer Betreuer] Heinkel. "Untersuchungen zur Kostenoptimierung für Hardware-Emulatoren durch Anwendung von Methoden der partiellen Laufzeitrekonfiguration / René Beckert ; Gutachter: Wolfram Hardt, Ulrich Heinkel, Christophe Bobda ; Wolfram Hardt, Ulrich Heinkel." Dresden : TUDpress, 2013. http://d-nb.info/1214245722/34.
Повний текст джерелаMehrnoosh, Behzad. "Comparing Analog and Digital Non-Linear Sonic Signatures : an Investigation on Creative Application and Subjective Perception using the Universal Audio 1176 FET Compressor." Thesis, Luleå tekniska universitet, Institutionen för ekonomi, teknik, konst och samhälle, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-84598.
Повний текст джерелаSantos, Vitor Alexandre. "Caso de estudo de sistema de emulação em hardware para aplicação com controlador lógico programável." Universidade Tecnológica Federal do Paraná, 2016. http://repositorio.utfpr.edu.br/jspui/handle/1/2720.
Повний текст джерелаThis work is a case study of an industrial plant emulator implemented in FPGA (Field Programmable Gate Array), to simulate systems together with a PLC (Programmable Logic Controller). Based in manufacturing industry, practical results of an industrial process prototype are confronted with the results of an applied model in FPGA. The objective is to assist in testing application validation levels in development, approximation of factory floor conditions, optimization of control process and training in industrial automation based on PLC. As a proposal for the models, the research use characteristics of a closed loop speed control system and from this, a discrete system process, which uses as a basis a manufacturing process. Initially the bibliographic review presents works around simulation of systems and emulators based on reconfigurable hardware. Also are reviewed topics related to the manufacturing industry with the application of PLC, beside the GRAFCET modeling technique. Next, questions will set out questions about reconfigurable logic around FPGA devices. Following the explanation of the theme, we describe the used prototypes and the developed models developed in FPGA for the emulator. Finally the obtained data are compared. With the presentation of the results is possible to verify the similarity between the two systems, physical and modeling in the FPGA. The small differences detected in the results obtained, in some points of the simulation, are discussed at the end of the work.
Souza, Igor Dias Neto de. "Controle digital com malha dupla de tensão aplicado a um conversor formador de rede." Universidade Federal de Juiz de Fora (UFJF), 2017. https://repositorio.ufjf.br/jspui/handle/ufjf/4083.
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Esta dissertação apresenta um estudo de um conversor emulador de rede (CER) que faz parte de uma estrutura Power-Hardware-in-the-Loop (PHIL). O PHIL será futuramente utilizado para verificar os impactos causados pela integração de sistemas de geração fotovoltaico (PV) à rede elétrica, assim como a operação do sistema PV frente a distúrbios na rede. O CER, composto por um conversor fonte de tensão (VSC) de dois níveis e filtro de saída LC, é responsável por alimentar cargas isoladas emulando uma rede elétrica. A modelagem do conversor emulador de rede é feita no sistema de coordenadas estacionário (αβ0), fornecendo um sistema de equações diferenciais usado para descrever o comportamento dinâmico do sistema. O conversor é controlado no modo de tensão, através da estratégia de modulação vetorial. Duas malhas de controle em cascata são projetadas. A malha interna utiliza compensadores em avanço digitais para amortecer a ressonância do filtro LC sem a necessidade de uma realimentação interna de corrente. Já a externa utiliza controladores ressonantes digitais modificados para rejeitar distúrbios harmônicos e garantir a qualidade da forma de onda da tensão no ponto de acoplamento comum. Os controladores ressonantes são conectados em série e o projeto é baseado no amortecimento dos zeros. Resultados experimentais, obtidos com o protótipo de laboratório, cujos controladores foram implementados em um processador digital de sinais TMS320F28335 da Texas Instruments, são usados para validar as estratégias de controle propostas.
This dissertation presents a study on a grid-former converter (GFC) which is a part of a Power-Hardware-in-the-Loop (PHIL) structure. The PHIL will be used to verify the impacts caused by the integration of photovoltaic (PV) generation systems into grid, as well as to study the PV operation under grid disturbances. The GFC, composed by a two-level voltage source converter with a LC output filter, is responsible to feed isolated loads emulating an electrical grid. The modeling of the grid-former converter is done in the stationary frame (αβ0), providing a set of differential equations that describes the dynamical behavior of the system. The converter is controlled in voltage mode by means of the space vector modulation (SVM) strategy. Two control loops are designed to control the static converter. At the inner loop a novel discrete-time active damping technique is proposed in order to damp the filter resonance without the need of current feedback. The method is based on an inner feedback loop with digital lead compensator on the feedback path while the external loop uses a discretetime integrator and a modified digital resonant controller to guarantee a decreasing frequency response and ensure the quality of the voltage waveform at the point of common coupling, respectively. The resonant controllers are connected in series and the design is based on its zeros damping. Experimental results obtained with the prototype, which controllers were implemented in a Texas Instruments TMS320F28335 are used to validate the proposed control strategies.
Guimarães, Marcelo Alves. "Transporte TDM em redes GPON." Universidade de São Paulo, 2011. http://www.teses.usp.br/teses/disponiveis/18/18155/tde-07042011-152547/.
Повний текст джерелаIn this work we analyze and propose the use of native channeled /structured TDM (Time Division Multiplexing) in GPON (Gigabit Passive Optical Network), with emphasis on the structure for transmission of the telephone network legacy. The main target is to achieve an increase in transmitted bandwidth efficiency by fragmenting E1 signals, thus avoiding the use of circuit emulation techniques (which reduce the bandwidth efficiency due to overhead addition). Initially, it is described in TDM transport in GPON networks, as it is performed in present commercial equipment by two techniques: CES - Circuit Emulation Service and Native TDM - unstructured. Next, we introduce the concepts of digital switching aiming its application on the transport of native and structured TDM in GPON. At this stage, we propose a transport solution, describe its protocol and functionalities. Finally, for concept proof, we present an implementation in HDL (Hardware Description Language) meant to FPGA (Field Programmable Gate Array) application.
BOUKADIDA, Yassine. "The i-motor: a system for end-of-line testing of electric drives for vehicles." Doctoral thesis, Università degli studi di Cassino, 2021. http://hdl.handle.net/11580/83957.
Повний текст джерелаLi, Ming-You, and 李明祐. "Hardware Implementation of Analog Emulator Based on Wave Digital Filters." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/46414417801929081152.
Повний текст джерела國立中央大學
電機工程學系
105
Modern System-on-Chip (SOC) designs usually contain analog and digital circuits. However, it is difficult to simulate them together because the design and verification processes are quite different for analog and digital circuits in traditional design flow. In order to provide a rapid and reliable verification method, we adopt Wave Digital Filter (WDF) theory to map resistors, capacitors, inductors and voltage source to wave domain one-by-one and connect them with serial or parallel adaptors. By this way, analog circuits can be transformed to digital circuits and verified in digital environment together. In this thesis, we focus on studying how to implement the WDF structures on FPGA. With the built-in IEEE 754 floating point circuits in the FPGA software, we can implement all computation elements of WDF rapidly. According to the emulation results, it demonstrates that the WDF theory is possible to be implemented with real hardware, and its behavior is consistent with the simulation results of HSPICE.
"Digital implementation of an upstream DOCSIS QAM modulator and channel emulator." Thesis, 2014. http://hdl.handle.net/10388/ETD-2015-06-1783.
Повний текст джерелаΠρίσκας, Θεόδωρος. "Σχεδίαση ενός 8-bit μικροεπεξεργαστή (του μP 8085) σε VHDL και υλοποίηση σε FPGAs". Thesis, 2012. http://hdl.handle.net/10889/5575.
Повний текст джерелаThe purpose of this thesis is the design of an 8085 emulator in FPGAs using VHDL. The implementation was done with the simulation environment of ALTERA Quartus v7.2, using VHDL. The project is divided into 12 chapters: The first chapter refers to the 8085 microprocessor and it’s technical features [1], [2], [4]. The second chapter is a detailed presentation of the VHDL language [3], [10]. The third chapter presents DE2 development board of Altera. Capabilities and design features of DE2 board are presented and vga video display generation using FPGAs is explained [3], [9], [14]. The fourth chapter analyzes the operation of the first large section of the microprocessor, ALU. The architecture of the circuit, the function and the detailed code is presented. The verification of the circuit is done by using the Quartus waveform editor program [5], [6], [12], [13]. The fifth chapter presents the operation of the register file. Register File is responsible for data transfer and operation of the address bus. The architecture of the circuit, the function and the detailed code is presented. The verification of the circuit is done by using the Quartus waveform editor program [5], [7], [11], [13], [14]. The sixth chapter presents microprocessor 's interrupts. The architecture of the circuit, the function and the detailed code is presented. The verification of the circuit is done by using the Quartus waveform editor program [1], [12], [13]. The seventh chapter is a first attempt to link the first three major sections of the microprocessor [12], [13]. The eighth chapter presents the operation of the control unit. The architecture of the circuit, the function and the detailed code is presented. The verification of the circuit is done by using the Quartus waveform editor program [5], [7], [12], [13]. The ninth chapter presents the circuit of the microprocessor through the connection of all individual parts. The architecture of the circuit, the function and the detailed code is presented. The verification of the circuit is done by using the Quartus waveform editor program [7], [12], [13]. The tenth chapter presents the microprogramming of microprogram ROM of the control unit. It analyzes in detail the operation of the control signals of the parts of the microprocessor to perform each of 8085 command [7], [12], [13]. The eleventh chapter presents the simulation of microprocessor through assembly programs written in RAM memory of 8085 microprocessor [1], [12], [13]. The twelfth chapter presents the implementation of microprocessor in FPGAs using DE2 development board of Altera [3], [14].
Lee, Chao-Cheng, and 李朝丞. "Emulation-Based Open-Hardware Course Design." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/by735u.
Повний текст джерела國立臺灣師範大學
資訊教育研究所
107
This study developed task-specific software to emulate the behaviors of an open-hardware. Students could test-run their programs on the emulation software before transmit it into the hardware. The Quasi-experimental design was implemented and the participants were a class of 8th graders in a class with a total of 45 students. Among them, 23 students served as the experiment group using emulation in programming, whereas the other 22 students served as the control group without using emulation. The experiment lasted for five weeks with a total of 5 hours. Data collected for analysis including students’ achievement test, International Bebras Contest, attitude questionnaire, and class observation record. The findings show that the emulation-based open-hardware activities: (1) significantly improved students’ performance in problem decomposition, (2) had no effects on students’ performance in programming and their attitudes toward the learning activities, and (3) benefited students’ computational thinking. Future studies should extend the length of experiment time and design proper computational thinking evaluation tools.
Wieler, Richard. "Emulation systems based on reconfigurable hardware devices." 1995. http://hdl.handle.net/1993/19040.
Повний текст джерелаPeng, Fei, and 彭飛. "OpenCL 2.0 Enabled HSA Hardware Platform Emulation." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/38981095842033467767.
Повний текст джерела國立清華大學
資訊工程學系
103
Heterogeneous System Architecture (HSA) is an open industry standard that tightly coupled the CPU with variety accelerators and also designed to support data-parallel programming models. Although there is a HSA-compatible machine, it is still not the HSA fully supported machine. A lot of software components using HSA is in development, so it is useful by providing an emulation environment for verifying HSA software components and tool-chains In this paper, we introduce a HSA emulation platform that can support OpenCL 2.0, which is based on HSAemu framework. HSA emulation platform provides a plat-form that combines OpenCL 2.0 with Heterogeneous System Architecture, using Shared Virtual Memory in HSA to achieve the same feature in OpenCL 2.0, and sup-ply with other new features such as Generic Address Space, Device Enqueue, Pipe, C11 atomic. Programmers can verify whether the program written in OpenCL can leverage the Heterogeneous System Architecture. In our preliminary experiments, the HSAemu has been validated by those extra features mentioned above. It can help developers to verify the program results and performances.
LI, MENG-LIN, and 李孟霖. "Resource Optimization for Hardware Generation of WDF-based Circuit Emulators." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/r29jm6.
Повний текст джерела國立中央大學
電機工程學系
107
With the advance of semiconductor technologies, the design of Very-Large-Scale Integration (VLSI) circuits becomes more complex. System-on-Chip (SOC) has become the main stream of VLSI design style . Because SOC designs usually contain both analog and digital circuits, it is important to have an Analog/Mixed-Signal (AMS) verification flow for chip development. In this thesis, we adopt Wave Digital Filter(WDF) theorem to map analog circuits into digital circuits for emulating analog circuits. This method uses incident and reflected waves to model circuit characteristics. Each analog component can be transformed into digital component in WDF framework to support the co-simulation with digital circuits. Based on the previous studies for the simulation process of WDF architectures, this thesis presents an automatic environment for converting analog circuits into WDF structures. Using the sensitivity-based method, the change of γ value at each adaptor becomes a formula related to the input voltage, This approach successfully avoids long calculation time by replacing the look-up table and interpolation method. In order to minimize hardware resource, integer linear programming algorithm is used to obtain the minimum number of required adaptors, The affine arithmetic model is also applied to calculate the minimum bit length with certain precision. As shown in the experimental results combining the proposed methods, the generated WDF circuits are greatly improve in terms of speed and area. The automation environment also improves the convenience for users to do analog emulation
Sá, José Pedro Patrício Gonçalves de. "Emulador em hardware de floppy disk drive com acesso sem fios." Master's thesis, 2011. http://hdl.handle.net/10216/63317.
Повний текст джерелаSá, José Pedro Patrício Gonçalves de. "Emulador em hardware de floppy disk drive com acesso sem fios." Dissertação, 2011. http://hdl.handle.net/10216/63317.
Повний текст джерелаLee, Tsing Gen, and 李清根. "EMPAR: An Interactive Design Environment for Hardware Emulation Applications." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/45774630746461439061.
Повний текст джерелаWu, Cheng-Chang, and 吳誠昌. "A Real-Time Emulation Hardware Platform for Channel Decoder." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/65843466950607930475.
Повний текст джерела國立清華大學
電機工程學系
91
ABSTRACT In modern communication systems, the interference of the channel noise is unavoidable when we transmit data. To overcome this problem, many theories about channel coding have been developed. Firstly, the data in the transmitter is coded, and then transmitted to the receiver via channel. Though it may be corrupted by the channel interference, the decoder can still get the decoded data that is like the original data. The most commonly used error control coding is the convolutional code in communication systems. The Viterbi algorithm is a Maximan-likelihood decoding algorithm for the convolutional code. When developing the channel decoder without hardware support, we can only use software tools such as Xilinx ISE, Synplify Pro, or ModelSim to synthesize and simulate the decoder. In this thesis, we first design a PCI-based emulation hardware and host GUI system that utilizes a Xilinx FPGA XCV1000E for fast design realization and real-time emulation for channel decoder. Users can compiler their decoder circuit and use the system to program decoder circuit into the FPGA quickly. The system can generate convolutional code continuously, add the simulated channel noise, and then transmit data to decoder circuit by PCI interface. The system can then analyze the results from the FPGA decoder to test and verify if the design is correct. Besides, a flexible IP builder is designed which enables experimenting different aspects of Viterbi decoders by changing (n,k,m) parameters. The builder can generate the VHDL code of different parameter according to our need. Afterward, the real-time hardware emulation of the decoder can be performed. The field test of the developed PCI-based FPGA hardware emulation platform illustrates the effectiveness and usefulness of the system. It can also be used as a general fast hardware emulation platform for designing other circuits and applications.
Frauenschläger, Jens. "Hardware-Debugging durch die Kombination von Emulation und Simulation." 2002. https://ul.qucosa.de/id/qucosa%3A16537.
Повний текст джерелаTodd, Michael Gordon. "Hardware Emulation of a Secure Passive Rfid Sensor System." 2010. https://scholarworks.umass.edu/theses/528.
Повний текст джерелаLin, Li-Te, and 林俐德. "Hardware Emulation and System Prototyping of Embedded Digital Signal Processor." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/90758127535700247190.
Повний текст джерела國立交通大學
電機資訊學院碩士在職專班
94
In the development procedure of embedded DSP, to verify the functionality of DSP is a very important step and it usually takes a lot of time. Designers can use software simulation, formal verification, or hardware emulation to complete the verification of DSP. Unfortunately, software simulation is a very inefficient way considering the simulation time. Formal verification could shorten verification time, but can’t handle large-scale circuitry. Although hardware emulation could emulate complex circuitry, its shortcoming is the lack of debugging ability. In this thesis, we use hardware emulation to shorten the development procedure of DSP. In order to overcome the shortcoming of hardware emulator - the lack of debugging ability, we propose a new embedded In-Circuit Emulator (ICE) architecture, in which we use DSP ready-made hardware to reduce the time demand of verification. At the same time, we use the instruction set and hardware interrupts of DSP to reduce extra debugging hardware. We integrate this emulator into a DSP – Pica DSP (Packed Instruction and Cluster Architecture). We also rely on FPGA to implement and verify the system prototype of Pica DSP. The result of implementation shows that Pica DSP integrates ICE could be easily verified and debugged. The hardware overhead of Pica DSP is 1.53% after we integrate embedded ICE.